ceph/src/spdk/dpdk/drivers/net/sfc/base/hunt_nic.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright (c) 2012-2018 Solarflare Communications Inc.
   4  * All rights reserved.
   5  */
   6
   7 #include "efx.h"
   8 #include "efx_impl.h"
   9 #if EFSYS_OPT_MON_MCDI
  10 #include "mcdi_mon.h"
  11 #endif
  12
  13 #if EFSYS_OPT_HUNTINGTON
  14
  15 #include "ef10_tlv_layout.h"
  16
  17 static  __checkReturn   efx_rc_t
  18 hunt_nic_get_required_pcie_bandwidth(
  19         __in            efx_nic_t *enp,
  20         __out           uint32_t *bandwidth_mbpsp)
  21 {
  22         uint32_t port_modes;
  23         uint32_t max_port_mode;
  24         uint32_t bandwidth;
  25         efx_rc_t rc;
  26
  27         /*
  28          * On Huntington, the firmware may not give us the current port mode, so
  29          * we need to go by the set of available port modes and assume the most
  30          * capable mode is in use.
  31          */
  32
  33         if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
  34                 /* No port mode info available */
  35                 bandwidth = 0;
  36                 goto out;
  37         }
  38
  39         if (port_modes & (1U << TLV_PORT_MODE_40G_40G)) {
  40                 /*
  41                  * This needs the full PCIe bandwidth (and could use
  42                  * more) - roughly 64 Gbit/s for 8 lanes of Gen3.
  43                  */
  44                 if ((rc = efx_nic_calculate_pcie_link_bandwidth(8,
  45                             EFX_PCIE_LINK_SPEED_GEN3, &bandwidth)) != 0)
  46                         goto fail1;
  47         } else {
  48                 if (port_modes & (1U << TLV_PORT_MODE_40G)) {
  49                         max_port_mode = TLV_PORT_MODE_40G;
  50                 } else if (port_modes & (1U << TLV_PORT_MODE_10G_10G_10G_10G)) {
  51                         max_port_mode = TLV_PORT_MODE_10G_10G_10G_10G;
  52                 } else {
  53                         /* Assume two 10G ports */
  54                         max_port_mode = TLV_PORT_MODE_10G_10G;
  55                 }
  56
  57                 if ((rc = ef10_nic_get_port_mode_bandwidth(max_port_mode,
  58                                                             &bandwidth)) != 0)
  59                         goto fail2;
  60         }
  61
  62 out:
  63         *bandwidth_mbpsp = bandwidth;
  64
  65         return (0);
  66
  67 fail2:
  68         EFSYS_PROBE(fail2);
  69 fail1:
  70         EFSYS_PROBE1(fail1, efx_rc_t, rc);
  71
  72         return (rc);
  73 }
  74
  75         __checkReturn   efx_rc_t
  76 hunt_board_cfg(
  77         __in            efx_nic_t *enp)
  78 {
  79         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
  80         efx_port_t *epp = &(enp->en_port);
  81         uint32_t flags;
  82         uint32_t sysclk, dpcpu_clk;
  83         uint32_t bandwidth;
  84         efx_rc_t rc;
  85
  86         /*
  87          * Enable firmware workarounds for hardware errata.
  88          * Expected responses are:
  89          *  - 0 (zero):
  90          *      Success: workaround enabled or disabled as requested.
  91          *  - MC_CMD_ERR_ENOSYS (reported as ENOTSUP):
  92          *      Firmware does not support the MC_CMD_WORKAROUND request.
  93          *      (assume that the workaround is not supported).
  94          *  - MC_CMD_ERR_ENOENT (reported as ENOENT):
  95          *      Firmware does not support the requested workaround.
  96          *  - MC_CMD_ERR_EPERM  (reported as EACCES):
  97          *      Unprivileged function cannot enable/disable workarounds.
  98          *
  99          * See efx_mcdi_request_errcode() for MCDI error translations.
 100          */
 101
 102         /*
 103          * If the bug35388 workaround is enabled, then use an indirect access
 104          * method to avoid unsafe EVQ writes.
 105          */
 106         rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG35388, B_TRUE,
 107             NULL);
 108         if ((rc == 0) || (rc == EACCES))
 109                 encp->enc_bug35388_workaround = B_TRUE;
 110         else if ((rc == ENOTSUP) || (rc == ENOENT))
 111                 encp->enc_bug35388_workaround = B_FALSE;
 112         else
 113                 goto fail1;
 114
 115         /*
 116          * If the bug41750 workaround is enabled, then do not test interrupts,
 117          * as the test will fail (seen with Greenport controllers).
 118          */
 119         rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG41750, B_TRUE,
 120             NULL);
 121         if (rc == 0) {
 122                 encp->enc_bug41750_workaround = B_TRUE;
 123         } else if (rc == EACCES) {
 124                 /* Assume a controller with 40G ports needs the workaround. */
 125                 if (epp->ep_default_adv_cap_mask & EFX_PHY_CAP_40000FDX)
 126                         encp->enc_bug41750_workaround = B_TRUE;
 127                 else
 128                         encp->enc_bug41750_workaround = B_FALSE;
 129         } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
 130                 encp->enc_bug41750_workaround = B_FALSE;
 131         } else {
 132                 goto fail2;
 133         }
 134         if (EFX_PCI_FUNCTION_IS_VF(encp)) {
 135                 /* Interrupt testing does not work for VFs. See bug50084. */
 136                 encp->enc_bug41750_workaround = B_TRUE;
 137         }
 138
 139         /*
 140          * If the bug26807 workaround is enabled, then firmware has enabled
 141          * support for chained multicast filters. Firmware will reset (FLR)
 142          * functions which have filters in the hardware filter table when the
 143          * workaround is enabled/disabled.
 144          *
 145          * We must recheck if the workaround is enabled after inserting the
 146          * first hardware filter, in case it has been changed since this check.
 147          */
 148         rc = efx_mcdi_set_workaround(enp, MC_CMD_WORKAROUND_BUG26807,
 149             B_TRUE, &flags);
 150         if (rc == 0) {
 151                 encp->enc_bug26807_workaround = B_TRUE;
 152                 if (flags & (1 << MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN)) {
 153                         /*
 154                          * Other functions had installed filters before the
 155                          * workaround was enabled, and they have been reset
 156                          * by firmware.
 157                          */
 158                         EFSYS_PROBE(bug26807_workaround_flr_done);
 159                         /* FIXME: bump MC warm boot count ? */
 160                 }
 161         } else if (rc == EACCES) {
 162                 /*
 163                  * Unprivileged functions cannot enable the workaround in older
 164                  * firmware.
 165                  */
 166                 encp->enc_bug26807_workaround = B_FALSE;
 167         } else if ((rc == ENOTSUP) || (rc == ENOENT)) {
 168                 encp->enc_bug26807_workaround = B_FALSE;
 169         } else {
 170                 goto fail3;
 171         }
 172
 173         /* Get clock frequencies (in MHz). */
 174         if ((rc = efx_mcdi_get_clock(enp, &sysclk, &dpcpu_clk)) != 0)
 175                 goto fail4;
 176
 177         /*
 178          * The Huntington timer quantum is 1536 sysclk cycles, documented for
 179          * the EV_TMR_VAL field of EV_TIMER_TBL. Scale for MHz and ns units.
 180          */
 181         encp->enc_evq_timer_quantum_ns = 1536000UL / sysclk; /* 1536 cycles */
 182         if (encp->enc_bug35388_workaround) {
 183                 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
 184                 ERF_DD_EVQ_IND_TIMER_VAL_WIDTH) / 1000;
 185         } else {
 186                 encp->enc_evq_timer_max_us = (encp->enc_evq_timer_quantum_ns <<
 187                 FRF_CZ_TC_TIMER_VAL_WIDTH) / 1000;
 188         }
 189
 190         encp->enc_bug61265_workaround = B_FALSE; /* Medford only */
 191
 192         /* Alignment for receive packet DMA buffers */
 193         encp->enc_rx_buf_align_start = 1;
 194         encp->enc_rx_buf_align_end = 64; /* RX DMA end padding */
 195
 196         /*
 197          * The workaround for bug35388 uses the top bit of transmit queue
 198          * descriptor writes, preventing the use of 4096 descriptor TXQs.
 199          */
 200         encp->enc_txq_max_ndescs = encp->enc_bug35388_workaround ? 2048 : 4096;
 201
 202         EFX_STATIC_ASSERT(HUNT_PIOBUF_NBUFS <= EF10_MAX_PIOBUF_NBUFS);
 203         encp->enc_piobuf_limit = HUNT_PIOBUF_NBUFS;
 204         encp->enc_piobuf_size = HUNT_PIOBUF_SIZE;
 205         encp->enc_piobuf_min_alloc_size = HUNT_MIN_PIO_ALLOC_SIZE;
 206
 207         if ((rc = hunt_nic_get_required_pcie_bandwidth(enp, &bandwidth)) != 0)
 208                 goto fail5;
 209         encp->enc_required_pcie_bandwidth_mbps = bandwidth;
 210
 211         /* All Huntington devices have a PCIe Gen3, 8 lane connector */
 212         encp->enc_max_pcie_link_gen = EFX_PCIE_LINK_SPEED_GEN3;
 213
 214         return (0);
 215
 216 fail5:
 217         EFSYS_PROBE(fail5);
 218 fail4:
 219         EFSYS_PROBE(fail4);
 220 fail3:
 221         EFSYS_PROBE(fail3);
 222 fail2:
 223         EFSYS_PROBE(fail2);
 224 fail1:
 225         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 226
 227         return (rc);
 228 }
 229
 230
 231 #endif  /* EFSYS_OPT_HUNTINGTON */