ceph/src/spdk/dpdk/drivers/net/sfc/base/siena_flash.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  *
   3  * Copyright(c) 2019-2020 Xilinx, Inc.
   4  * Copyright(c) 2007-2019 Solarflare Communications Inc.
   5  */
   6
   7 #ifndef _SYS_SIENA_FLASH_H
   8 #define _SYS_SIENA_FLASH_H
   9
  10 #pragma pack(1)
  11
  12 /* Fixed locations near the start of flash (which may be in the internal PHY
  13  * firmware header) point to the boot header.
  14  *
  15  * - parsed by MC boot ROM and firmware
  16  * - reserved (but not parsed) by PHY firmware
  17  * - opaque to driver
  18  */
  19
  20 #define SIENA_MC_BOOT_PHY_FW_HDR_LEN (0x20)
  21
  22 #define SIENA_MC_BOOT_PTR_LOCATION (0x18)      /* First thing we try to boot */
  23 #define SIENA_MC_BOOT_ALT_PTR_LOCATION (0x1c)  /* Alternative if that fails */
  24
  25 #define SIENA_MC_BOOT_HDR_LEN (0x200)
  26
  27 #define SIENA_MC_BOOT_MAGIC (0x51E4A001)
  28 #define SIENA_MC_BOOT_VERSION (1)
  29
  30
  31 /*Structures supporting an arbitrary number of binary blobs in the flash image
  32   intended to house code and tables for the satellite cpus*/
  33 /*thanks to random.org for:*/
  34 #define BLOBS_HEADER_MAGIC (0xBDA3BBD4)
  35 #define BLOB_HEADER_MAGIC  (0xA1478A91)
  36
  37 typedef struct blobs_hdr_s {                    /* GENERATED BY scripts/genfwdef */
  38         efx_dword_t     magic;
  39         efx_dword_t     no_of_blobs;
  40 } blobs_hdr_t;
  41
  42 typedef struct blob_hdr_s {                     /* GENERATED BY scripts/genfwdef */
  43         efx_dword_t     magic;
  44         efx_dword_t     cpu_type;
  45         efx_dword_t     build_variant;
  46         efx_dword_t     offset;
  47         efx_dword_t     length;
  48         efx_dword_t     checksum;
  49 } blob_hdr_t;
  50
  51 #define BLOB_CPU_TYPE_TXDI_TEXT (0)
  52 #define BLOB_CPU_TYPE_RXDI_TEXT (1)
  53 #define BLOB_CPU_TYPE_TXDP_TEXT (2)
  54 #define BLOB_CPU_TYPE_RXDP_TEXT (3)
  55 #define BLOB_CPU_TYPE_RXHRSL_HR_LUT (4)
  56 #define BLOB_CPU_TYPE_RXHRSL_HR_LUT_CFG (5)
  57 #define BLOB_CPU_TYPE_TXHRSL_HR_LUT (6)
  58 #define BLOB_CPU_TYPE_TXHRSL_HR_LUT_CFG (7)
  59 #define BLOB_CPU_TYPE_RXHRSL_HR_PGM  (8)
  60 #define BLOB_CPU_TYPE_RXHRSL_SL_PGM  (9)
  61 #define BLOB_CPU_TYPE_TXHRSL_HR_PGM  (10)
  62 #define BLOB_CPU_TYPE_TXHRSL_SL_PGM  (11)
  63 #define BLOB_CPU_TYPE_RXDI_VTBL0 (12)
  64 #define BLOB_CPU_TYPE_TXDI_VTBL0 (13)
  65 #define BLOB_CPU_TYPE_RXDI_VTBL1 (14)
  66 #define BLOB_CPU_TYPE_TXDI_VTBL1 (15)
  67 #define BLOB_CPU_TYPE_DUMPSPEC (32)
  68 #define BLOB_CPU_TYPE_MC_XIP   (33)
  69
  70 #define BLOB_CPU_TYPE_INVALID (31)
  71
  72 /*
  73  * The upper four bits of the CPU type field specify the compression
  74  * algorithm used for this blob.
  75  */
  76 #define BLOB_COMPRESSION_MASK (0xf0000000)
  77 #define BLOB_CPU_TYPE_MASK    (0x0fffffff)
  78
  79 #define BLOB_COMPRESSION_NONE (0x00000000) /* Stored as is */
  80 #define BLOB_COMPRESSION_LZ   (0x10000000) /* see lib/lzdecoder.c */
  81
  82 typedef struct siena_mc_boot_hdr_s {            /* GENERATED BY scripts/genfwdef */
  83         efx_dword_t     magic;                  /* = SIENA_MC_BOOT_MAGIC */
  84         efx_word_t      hdr_version;            /* this structure definition is version 1 */
  85         efx_byte_t      board_type;
  86         efx_byte_t      firmware_version_a;
  87         efx_byte_t      firmware_version_b;
  88         efx_byte_t      firmware_version_c;
  89         efx_word_t      checksum;               /* of whole header area + firmware image */
  90         efx_word_t      firmware_version_d;
  91         efx_byte_t      mcfw_subtype;
  92         efx_byte_t      generation;             /* MC (Medford and later): MC partition generation when */
  93                                                 /* written to NVRAM. */
  94                                                 /* MUM & SUC images: subtype. */
  95                                                 /* (Otherwise set to 0) */
  96         efx_dword_t     firmware_text_offset;   /* offset to firmware .text */
  97         efx_dword_t     firmware_text_size;     /* length of firmware .text, in bytes */
  98         efx_dword_t     firmware_data_offset;   /* offset to firmware .data */
  99         efx_dword_t     firmware_data_size;     /* length of firmware .data, in bytes */
 100         efx_byte_t      spi_rate;               /* SPI rate for reading image, 0 is BootROM default */
 101         efx_byte_t      spi_phase_adj;          /* SPI SDO/SCL phase adjustment, 0 is default (no adj) */
 102         efx_word_t      xpm_sector;             /* XPM (MEDFORD and later): The sector that contains */
 103                                                 /* the key, or 0xffff if unsigned. (Otherwise set to 0) */
 104         efx_byte_t      mumfw_subtype;          /* MUM & SUC images: subtype. (Otherwise set to 0) */
 105         efx_byte_t      reserved_b[3];          /* (set to 0) */
 106         efx_dword_t     security_level;         /* This number increases every time a serious security flaw */
 107                                                 /* is fixed. A secure NIC may not downgrade to any image */
 108                                                 /* with a lower security level than the current image. */
 109                                                 /* Note: The number in this header should only be used for */
 110                                                 /* determining the level of new images, not to determine */
 111                                                 /* the level of the current image as this header is not */
 112                                                 /* protected by a CMAC. */
 113         efx_dword_t     reserved_c[5];          /* (set to 0) */
 114 } siena_mc_boot_hdr_t;
 115
 116 #define SIENA_MC_BOOT_HDR_PADDING \
 117         (SIENA_MC_BOOT_HDR_LEN - sizeof(siena_mc_boot_hdr_t))
 118
 119 #define SIENA_MC_STATIC_CONFIG_MAGIC (0xBDCF5555)
 120 #define SIENA_MC_STATIC_CONFIG_VERSION (0)
 121
 122 typedef struct siena_mc_static_config_hdr_s {   /* GENERATED BY scripts/genfwdef */
 123         efx_dword_t     magic;                  /* = SIENA_MC_STATIC_CONFIG_MAGIC */
 124         efx_word_t      length;                 /* of header area (i.e. not including VPD) */
 125         efx_byte_t      version;
 126         efx_byte_t      csum;                   /* over header area (i.e. not including VPD) */
 127         efx_dword_t     static_vpd_offset;
 128         efx_dword_t     static_vpd_length;
 129         efx_dword_t     capabilities;
 130         efx_byte_t      mac_addr_base[6];
 131         efx_byte_t      green_mode_cal;         /* Green mode calibration result */
 132         efx_byte_t      green_mode_valid;       /* Whether cal holds a valid value */
 133         efx_word_t      mac_addr_count;
 134         efx_word_t      mac_addr_stride;
 135         efx_word_t      calibrated_vref;        /* Vref as measured during production */
 136         efx_word_t      adc_vref;               /* Vref as read by ADC */
 137         efx_dword_t     reserved2[1];           /* (write as zero) */
 138         efx_dword_t     num_dbi_items;
 139         struct {
 140                 efx_word_t      addr;
 141                 efx_word_t      byte_enables;
 142                 efx_dword_t     value;
 143         } dbi[];
 144 } siena_mc_static_config_hdr_t;
 145
 146 /* This prefixes a valid XIP partition */
 147 #define XIP_PARTITION_MAGIC (0x51DEC0DE)
 148
 149 #define SIENA_MC_DYNAMIC_CONFIG_MAGIC (0xBDCFDDDD)
 150 #define SIENA_MC_DYNAMIC_CONFIG_VERSION (0)
 151
 152 typedef struct siena_mc_fw_version_s {          /* GENERATED BY scripts/genfwdef */
 153         efx_dword_t     fw_subtype;
 154         efx_word_t      version_w;
 155         efx_word_t      version_x;
 156         efx_word_t      version_y;
 157         efx_word_t      version_z;
 158 } siena_mc_fw_version_t;
 159
 160 typedef struct siena_mc_dynamic_config_hdr_s {  /* GENERATED BY scripts/genfwdef */
 161         efx_dword_t     magic;                  /* = SIENA_MC_DYNAMIC_CONFIG_MAGIC */
 162         efx_word_t      length;                 /* of header area (i.e. not including VPD) */
 163         efx_byte_t      version;
 164         efx_byte_t      csum;                   /* over header area (i.e. not including VPD) */
 165         efx_dword_t     dynamic_vpd_offset;
 166         efx_dword_t     dynamic_vpd_length;
 167         efx_dword_t     num_fw_version_items;
 168         siena_mc_fw_version_t   fw_version[];
 169 } siena_mc_dynamic_config_hdr_t;
 170
 171 #define SIENA_MC_EXPROM_SINGLE_MAGIC (0xAA55)  /* little-endian uint16_t */
 172
 173 #define SIENA_MC_EXPROM_COMBO_MAGIC (0xB0070102)  /* little-endian uint32_t */
 174 #define SIENA_MC_EXPROM_COMBO_V2_MAGIC (0xB0070103)  /* little-endian uint32_t */
 175
 176 typedef struct siena_mc_combo_rom_hdr_s {       /* GENERATED BY scripts/genfwdef */
 177         efx_dword_t     magic;                  /* = SIENA_MC_EXPROM_COMBO_MAGIC or SIENA_MC_EXPROM_COMBO_V2_MAGIC */
 178         union           {
 179                 struct {
 180                         efx_dword_t     len1;   /* length of first image */
 181                         efx_dword_t     len2;   /* length of second image */
 182                         efx_dword_t     off1;   /* offset of first byte to edit to combine images */
 183                         efx_dword_t     off2;   /* offset of second byte to edit to combine images */
 184                         efx_word_t      infoblk0_off;/* infoblk offset */
 185                         efx_word_t      infoblk1_off;/* infoblk offset */
 186                         efx_byte_t      infoblk_len;/* length of space reserved for one infoblk structure */
 187                         efx_byte_t      reserved[7];/* (set to 0) */
 188                 } v1;
 189                 struct {
 190                         efx_dword_t     len1;   /* length of first image */
 191                         efx_dword_t     len2;   /* length of second image */
 192                         efx_dword_t     off1;   /* offset of first byte to edit to combine images */
 193                         efx_dword_t     off2;   /* offset of second byte to edit to combine images */
 194                         efx_word_t      infoblk_off;/* infoblk start offset */
 195                         efx_word_t      infoblk_count;/* infoblk count  */
 196                         efx_byte_t      infoblk_len;/* length of space reserved for one infoblk structure */
 197                         efx_byte_t      reserved[7];/* (set to 0) */
 198                 } v2;
 199         } data;
 200 } siena_mc_combo_rom_hdr_t;
 201
 202 #pragma pack()
 203
 204 #endif  /* _SYS_SIENA_FLASH_H */