ceph/src/spdk/dpdk/drivers/net/vmxnet3/base/vmxnet3_defs.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright (C) 2007 VMware, Inc. All rights reserved.
   3  */
   4
   5 /*
   6  * vmxnet3_defs.h --
   7  *
   8  *      Definitions shared by device emulation and guest drivers for
   9  *      VMXNET3 NIC
  10  */
  11
  12 #ifndef _VMXNET3_DEFS_H_
  13 #define _VMXNET3_DEFS_H_
  14
  15 #include "vmxnet3_osdep.h"
  16 #include "upt1_defs.h"
  17
  18 /* all registers are 32 bit wide */
  19 /* BAR 1 */
  20 #define VMXNET3_REG_VRRS  0x0    /* Vmxnet3 Revision Report Selection */
  21 #define VMXNET3_REG_UVRS  0x8    /* UPT Version Report Selection */
  22 #define VMXNET3_REG_DSAL  0x10   /* Driver Shared Address Low */
  23 #define VMXNET3_REG_DSAH  0x18   /* Driver Shared Address High */
  24 #define VMXNET3_REG_CMD   0x20   /* Command */
  25 #define VMXNET3_REG_MACL  0x28   /* MAC Address Low */
  26 #define VMXNET3_REG_MACH  0x30   /* MAC Address High */
  27 #define VMXNET3_REG_ICR   0x38   /* Interrupt Cause Register */
  28 #define VMXNET3_REG_ECR   0x40   /* Event Cause Register */
  29
  30 #define VMXNET3_REG_WSAL  0xF00  /* Wireless Shared Address Lo  */
  31 #define VMXNET3_REG_WSAH  0xF08  /* Wireless Shared Address Hi  */
  32 #define VMXNET3_REG_WCMD  0xF18  /* Wireless Command */
  33
  34 /* BAR 0 */
  35 #define VMXNET3_REG_IMR      0x0   /* Interrupt Mask Register */
  36 #define VMXNET3_REG_TXPROD   0x600 /* Tx Producer Index */
  37 #define VMXNET3_REG_RXPROD   0x800 /* Rx Producer Index for ring 1 */
  38 #define VMXNET3_REG_RXPROD2  0xA00 /* Rx Producer Index for ring 2 */
  39
  40 #define VMXNET3_PT_REG_SIZE     4096    /* BAR 0 */
  41 #define VMXNET3_VD_REG_SIZE     4096    /* BAR 1 */
  42
  43 /*
  44  * The two Vmxnet3 MMIO Register PCI BARs (BAR 0 at offset 10h and BAR 1 at
  45  * offset 14h)  as well as the MSI-X BAR are combined into one PhysMem region:
  46  * <-VMXNET3_PT_REG_SIZE-><-VMXNET3_VD_REG_SIZE-><-VMXNET3_MSIX_BAR_SIZE-->
  47  * -------------------------------------------------------------------------
  48  * |Pass Thru Registers  | Virtual Dev Registers | MSI-X Vector/PBA Table  |
  49  * -------------------------------------------------------------------------
  50  * VMXNET3_MSIX_BAR_SIZE is defined in "vmxnet3Int.h"
  51  */
  52 #define VMXNET3_PHYSMEM_PAGES   4
  53
  54 #define VMXNET3_REG_ALIGN       8  /* All registers are 8-byte aligned. */
  55 #define VMXNET3_REG_ALIGN_MASK  0x7
  56
  57 /* I/O Mapped access to registers */
  58 #define VMXNET3_IO_TYPE_PT              0
  59 #define VMXNET3_IO_TYPE_VD              1
  60 #define VMXNET3_IO_ADDR(type, reg)      (((type) << 24) | ((reg) & 0xFFFFFF))
  61 #define VMXNET3_IO_TYPE(addr)           ((addr) >> 24)
  62 #define VMXNET3_IO_REG(addr)            ((addr) & 0xFFFFFF)
  63
  64 #ifndef __le16
  65 #define __le16 uint16
  66 #endif
  67 #ifndef __le32
  68 #define __le32 uint32
  69 #endif
  70 #ifndef __le64
  71 #define __le64 uint64
  72 #endif
  73
  74 typedef enum {
  75    VMXNET3_CMD_FIRST_SET = 0xCAFE0000,
  76    VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
  77    VMXNET3_CMD_QUIESCE_DEV,
  78    VMXNET3_CMD_RESET_DEV,
  79    VMXNET3_CMD_UPDATE_RX_MODE,
  80    VMXNET3_CMD_UPDATE_MAC_FILTERS,
  81    VMXNET3_CMD_UPDATE_VLAN_FILTERS,
  82    VMXNET3_CMD_UPDATE_RSSIDT,
  83    VMXNET3_CMD_UPDATE_IML,
  84    VMXNET3_CMD_UPDATE_PMCFG,
  85    VMXNET3_CMD_UPDATE_FEATURE,
  86    VMXNET3_CMD_STOP_EMULATION,
  87    VMXNET3_CMD_LOAD_PLUGIN,
  88    VMXNET3_CMD_ACTIVATE_VF,
  89    VMXNET3_CMD_RESERVED3,
  90    VMXNET3_CMD_RESERVED4,
  91    VMXNET3_CMD_REGISTER_MEMREGS,
  92
  93    VMXNET3_CMD_FIRST_GET = 0xF00D0000,
  94    VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
  95    VMXNET3_CMD_GET_STATS,
  96    VMXNET3_CMD_GET_LINK,
  97    VMXNET3_CMD_GET_PERM_MAC_LO,
  98    VMXNET3_CMD_GET_PERM_MAC_HI,
  99    VMXNET3_CMD_GET_DID_LO,
 100    VMXNET3_CMD_GET_DID_HI,
 101    VMXNET3_CMD_GET_DEV_EXTRA_INFO,
 102    VMXNET3_CMD_GET_CONF_INTR,
 103    VMXNET3_CMD_GET_ADAPTIVE_RING_INFO,
 104    VMXNET3_CMD_GET_TXDATA_DESC_SIZE,
 105    VMXNET3_CMD_RESERVED5,
 106 } Vmxnet3_Cmd;
 107
 108 /* Adaptive Ring Info Flags */
 109 #define VMXNET3_DISABLE_ADAPTIVE_RING 1
 110
 111 /*
 112  *      Little Endian layout of bitfields -
 113  *      Byte 0 :        7.....len.....0
 114  *      Byte 1 :        rsvd gen 13.len.8
 115  *      Byte 2 :        5.msscof.0 ext1  dtype
 116  *      Byte 3 :        13...msscof...6
 117  *
 118  *      Big Endian layout of bitfields -
 119  *      Byte 0:         13...msscof...6
 120  *      Byte 1 :        5.msscof.0 ext1  dtype
 121  *      Byte 2 :        rsvd gen 13.len.8
 122  *      Byte 3 :        7.....len.....0
 123  *
 124  *      Thus, le32_to_cpu on the dword will allow the big endian driver to read
 125  *      the bit fields correctly. And cpu_to_le32 will convert bitfields
 126  *      bit fields written by big endian driver to format required by device.
 127  */
 128
 129 typedef
 130 #include "vmware_pack_begin.h"
 131 struct Vmxnet3_TxDesc {
 132    __le64 addr;
 133
 134 #ifdef __BIG_ENDIAN_BITFIELD
 135    uint32 msscof:14;  /* MSS, checksum offset, flags */
 136    uint32 ext1:1;
 137    uint32 dtype:1;    /* descriptor type */
 138    uint32 rsvd:1;
 139    uint32 gen:1;      /* generation bit */
 140    uint32 len:14;
 141 #else
 142    uint32 len:14;
 143    uint32 gen:1;      /* generation bit */
 144    uint32 rsvd:1;
 145    uint32 dtype:1;    /* descriptor type */
 146    uint32 ext1:1;
 147    uint32 msscof:14;  /* MSS, checksum offset, flags */
 148 #endif  /* __BIG_ENDIAN_BITFIELD */
 149
 150 #ifdef __BIG_ENDIAN_BITFIELD
 151    uint32 tci:16;     /* Tag to Insert */
 152    uint32 ti:1;       /* VLAN Tag Insertion */
 153    uint32 ext2:1;
 154    uint32 cq:1;       /* completion request */
 155    uint32 eop:1;      /* End Of Packet */
 156    uint32 om:2;       /* offload mode */
 157    uint32 hlen:10;    /* header len */
 158 #else
 159    uint32 hlen:10;    /* header len */
 160    uint32 om:2;       /* offload mode */
 161    uint32 eop:1;      /* End Of Packet */
 162    uint32 cq:1;       /* completion request */
 163    uint32 ext2:1;
 164    uint32 ti:1;       /* VLAN Tag Insertion */
 165    uint32 tci:16;     /* Tag to Insert */
 166 #endif  /* __BIG_ENDIAN_BITFIELD */
 167 }
 168 #include "vmware_pack_end.h"
 169 Vmxnet3_TxDesc;
 170
 171 /* TxDesc.OM values */
 172 #define VMXNET3_OM_NONE  0
 173 #define VMXNET3_OM_CSUM  2
 174 #define VMXNET3_OM_TSO   3
 175
 176 /* fields in TxDesc we access w/o using bit fields */
 177 #define VMXNET3_TXD_EOP_SHIFT 12
 178 #define VMXNET3_TXD_CQ_SHIFT  13
 179 #define VMXNET3_TXD_GEN_SHIFT 14
 180 #define VMXNET3_TXD_EOP_DWORD_SHIFT 3
 181 #define VMXNET3_TXD_GEN_DWORD_SHIFT 2
 182
 183 #define VMXNET3_TXD_CQ  (1 << VMXNET3_TXD_CQ_SHIFT)
 184 #define VMXNET3_TXD_EOP (1 << VMXNET3_TXD_EOP_SHIFT)
 185 #define VMXNET3_TXD_GEN (1 << VMXNET3_TXD_GEN_SHIFT)
 186
 187 #define VMXNET3_TXD_GEN_SIZE 1
 188 #define VMXNET3_TXD_EOP_SIZE 1
 189
 190 #define VMXNET3_HDR_COPY_SIZE   128
 191
 192 typedef
 193 #include "vmware_pack_begin.h"
 194 struct Vmxnet3_TxDataDesc {
 195    uint8 data[VMXNET3_HDR_COPY_SIZE];
 196 }
 197 #include "vmware_pack_end.h"
 198 Vmxnet3_TxDataDesc;
 199
 200 #define VMXNET3_TCD_GEN_SHIFT   31
 201 #define VMXNET3_TCD_GEN_SIZE    1
 202 #define VMXNET3_TCD_TXIDX_SHIFT 0
 203 #define VMXNET3_TCD_TXIDX_SIZE  12
 204 #define VMXNET3_TCD_GEN_DWORD_SHIFT     3
 205
 206 typedef
 207 #include "vmware_pack_begin.h"
 208 struct Vmxnet3_TxCompDesc {
 209    uint32 txdIdx:12;    /* Index of the EOP TxDesc */
 210    uint32 ext1:20;
 211
 212    __le32 ext2;
 213    __le32 ext3;
 214
 215    uint32 rsvd:24;
 216    uint32 type:7;       /* completion type */
 217    uint32 gen:1;        /* generation bit */
 218 }
 219 #include "vmware_pack_end.h"
 220 Vmxnet3_TxCompDesc;
 221
 222 typedef
 223 #include "vmware_pack_begin.h"
 224 struct Vmxnet3_RxDesc {
 225    __le64 addr;
 226
 227 #ifdef __BIG_ENDIAN_BITFIELD
 228    uint32 gen:1;        /* Generation bit */
 229    uint32 rsvd:15;
 230    uint32 dtype:1;      /* Descriptor type */
 231    uint32 btype:1;      /* Buffer Type */
 232    uint32 len:14;
 233 #else
 234    uint32 len:14;
 235    uint32 btype:1;      /* Buffer Type */
 236    uint32 dtype:1;      /* Descriptor type */
 237    uint32 rsvd:15;
 238    uint32 gen:1;        /* Generation bit */
 239 #endif
 240    __le32 ext1;
 241 }
 242 #include "vmware_pack_end.h"
 243 Vmxnet3_RxDesc;
 244
 245 /* values of RXD.BTYPE */
 246 #define VMXNET3_RXD_BTYPE_HEAD   0    /* head only */
 247 #define VMXNET3_RXD_BTYPE_BODY   1    /* body only */
 248
 249 /* fields in RxDesc we access w/o using bit fields */
 250 #define VMXNET3_RXD_BTYPE_SHIFT  14
 251 #define VMXNET3_RXD_GEN_SHIFT    31
 252
 253 typedef
 254 #include "vmware_pack_begin.h"
 255 struct Vmxnet3_RxCompDesc {
 256 #ifdef __BIG_ENDIAN_BITFIELD
 257    uint32 ext2:1;
 258    uint32 cnc:1;        /* Checksum Not Calculated */
 259    uint32 rssType:4;    /* RSS hash type used */
 260    uint32 rqID:10;      /* rx queue/ring ID */
 261    uint32 sop:1;        /* Start of Packet */
 262    uint32 eop:1;        /* End of Packet */
 263    uint32 ext1:2;
 264    uint32 rxdIdx:12;    /* Index of the RxDesc */
 265 #else
 266    uint32 rxdIdx:12;    /* Index of the RxDesc */
 267    uint32 ext1:2;
 268    uint32 eop:1;        /* End of Packet */
 269    uint32 sop:1;        /* Start of Packet */
 270    uint32 rqID:10;      /* rx queue/ring ID */
 271    uint32 rssType:4;    /* RSS hash type used */
 272    uint32 cnc:1;        /* Checksum Not Calculated */
 273    uint32 ext2:1;
 274 #endif  /* __BIG_ENDIAN_BITFIELD */
 275
 276    __le32 rssHash;      /* RSS hash value */
 277
 278 #ifdef __BIG_ENDIAN_BITFIELD
 279    uint32 tci:16;       /* Tag stripped */
 280    uint32 ts:1;         /* Tag is stripped */
 281    uint32 err:1;        /* Error */
 282    uint32 len:14;       /* data length */
 283 #else
 284    uint32 len:14;       /* data length */
 285    uint32 err:1;        /* Error */
 286    uint32 ts:1;         /* Tag is stripped */
 287    uint32 tci:16;       /* Tag stripped */
 288 #endif  /* __BIG_ENDIAN_BITFIELD */
 289
 290
 291 #ifdef __BIG_ENDIAN_BITFIELD
 292    uint32 gen:1;        /* generation bit */
 293    uint32 type:7;       /* completion type */
 294    uint32 fcs:1;        /* Frame CRC correct */
 295    uint32 frg:1;        /* IP Fragment */
 296    uint32 v4:1;         /* IPv4 */
 297    uint32 v6:1;         /* IPv6 */
 298    uint32 ipc:1;        /* IP Checksum Correct */
 299    uint32 tcp:1;        /* TCP packet */
 300    uint32 udp:1;        /* UDP packet */
 301    uint32 tuc:1;        /* TCP/UDP Checksum Correct */
 302    uint32 csum:16;
 303 #else
 304    uint32 csum:16;
 305    uint32 tuc:1;        /* TCP/UDP Checksum Correct */
 306    uint32 udp:1;        /* UDP packet */
 307    uint32 tcp:1;        /* TCP packet */
 308    uint32 ipc:1;        /* IP Checksum Correct */
 309    uint32 v6:1;         /* IPv6 */
 310    uint32 v4:1;         /* IPv4 */
 311    uint32 frg:1;        /* IP Fragment */
 312    uint32 fcs:1;        /* Frame CRC correct */
 313    uint32 type:7;       /* completion type */
 314    uint32 gen:1;        /* generation bit */
 315 #endif  /* __BIG_ENDIAN_BITFIELD */
 316 }
 317 #include "vmware_pack_end.h"
 318 Vmxnet3_RxCompDesc;
 319
 320 typedef
 321 #include "vmware_pack_begin.h"
 322 struct Vmxnet3_RxCompDescExt {
 323    __le32 dword1;
 324    uint8  segCnt;       /* Number of aggregated packets */
 325    uint8  dupAckCnt;    /* Number of duplicate Acks */
 326    __le16 tsDelta;      /* TCP timestamp difference */
 327         __le32 dword2;
 328 #ifdef __BIG_ENDIAN_BITFIELD
 329         uint32 gen : 1;     /* generation bit */
 330         uint32 type : 7;    /* completion type */
 331         uint32 fcs : 1;     /* Frame CRC correct */
 332         uint32 frg : 1;     /* IP Fragment */
 333         uint32 v4 : 1;      /* IPv4 */
 334         uint32 v6 : 1;      /* IPv6 */
 335         uint32 ipc : 1;     /* IP Checksum Correct */
 336         uint32 tcp : 1;     /* TCP packet */
 337         uint32 udp : 1;     /* UDP packet */
 338         uint32 tuc : 1;     /* TCP/UDP Checksum Correct */
 339         uint32 mss : 16;
 340 #else
 341         uint32 mss : 16;
 342         uint32 tuc : 1;     /* TCP/UDP Checksum Correct */
 343         uint32 udp : 1;     /* UDP packet */
 344         uint32 tcp : 1;     /* TCP packet */
 345         uint32 ipc : 1;     /* IP Checksum Correct */
 346         uint32 v6 : 1;      /* IPv6 */
 347         uint32 v4 : 1;      /* IPv4 */
 348         uint32 frg : 1;     /* IP Fragment */
 349         uint32 fcs : 1;     /* Frame CRC correct */
 350         uint32 type : 7;    /* completion type */
 351         uint32 gen : 1;     /* generation bit */
 352 #endif  /* __BIG_ENDIAN_BITFIELD */
 353 }
 354 #include "vmware_pack_end.h"
 355 Vmxnet3_RxCompDescExt;
 356
 357 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.dword[3] */
 358 #define VMXNET3_RCD_TUC_SHIFT  16
 359 #define VMXNET3_RCD_IPC_SHIFT  19
 360
 361 /* fields in RxCompDesc we access via Vmxnet3_GenericDesc.qword[1] */
 362 #define VMXNET3_RCD_TYPE_SHIFT 56
 363 #define VMXNET3_RCD_GEN_SHIFT  63
 364
 365 /* csum OK for TCP/UDP pkts over IP */
 366 #define VMXNET3_RCD_CSUM_OK (1 << VMXNET3_RCD_TUC_SHIFT | 1 << VMXNET3_RCD_IPC_SHIFT)
 367
 368 /* value of RxCompDesc.rssType */
 369 #define VMXNET3_RCD_RSS_TYPE_NONE     0
 370 #define VMXNET3_RCD_RSS_TYPE_IPV4     1
 371 #define VMXNET3_RCD_RSS_TYPE_TCPIPV4  2
 372 #define VMXNET3_RCD_RSS_TYPE_IPV6     3
 373 #define VMXNET3_RCD_RSS_TYPE_TCPIPV6  4
 374
 375 /* a union for accessing all cmd/completion descriptors */
 376 typedef union Vmxnet3_GenericDesc {
 377    __le64                qword[2];
 378    __le32                dword[4];
 379    __le16                word[8];
 380    Vmxnet3_TxDesc        txd;
 381    Vmxnet3_RxDesc        rxd;
 382    Vmxnet3_TxCompDesc    tcd;
 383    Vmxnet3_RxCompDesc    rcd;
 384    Vmxnet3_RxCompDescExt rcdExt;
 385 } Vmxnet3_GenericDesc;
 386
 387 #define VMXNET3_INIT_GEN       1
 388
 389 /* Max size of a single tx buffer */
 390 #define VMXNET3_MAX_TX_BUF_SIZE  (1 << 14)
 391
 392 /* # of tx desc needed for a tx buffer size */
 393 #define VMXNET3_TXD_NEEDED(size) (((size) + VMXNET3_MAX_TX_BUF_SIZE - 1) / VMXNET3_MAX_TX_BUF_SIZE)
 394
 395 /* max # of tx descs for a non-tso pkt */
 396 #define VMXNET3_MAX_TXD_PER_PKT 16
 397
 398 /* Max size of a single rx buffer */
 399 #define VMXNET3_MAX_RX_BUF_SIZE  ((1 << 14) - 1)
 400 /* Minimum size of a type 0 buffer */
 401 #define VMXNET3_MIN_T0_BUF_SIZE  128
 402 #define VMXNET3_MAX_CSUM_OFFSET  1024
 403
 404 /* Ring base address alignment */
 405 #define VMXNET3_RING_BA_ALIGN   512
 406 #define VMXNET3_RING_BA_MASK    (VMXNET3_RING_BA_ALIGN - 1)
 407
 408 /* Ring size must be a multiple of 32 */
 409 #define VMXNET3_RING_SIZE_ALIGN 32
 410 #define VMXNET3_RING_SIZE_MASK  (VMXNET3_RING_SIZE_ALIGN - 1)
 411
 412 /* Tx Data Ring buffer size must be a multiple of 64 */
 413 #define VMXNET3_TXDATA_DESC_SIZE_ALIGN 64
 414 #define VMXNET3_TXDATA_DESC_SIZE_MASK  (VMXNET3_TXDATA_DESC_SIZE_ALIGN - 1)
 415
 416 /* Rx Data Ring buffer size must be a multiple of 64 */
 417 #define VMXNET3_RXDATA_DESC_SIZE_ALIGN 64
 418 #define VMXNET3_RXDATA_DESC_SIZE_MASK  (VMXNET3_RXDATA_DESC_SIZE_ALIGN - 1)
 419
 420 /* Max ring size */
 421 #define VMXNET3_TX_RING_MAX_SIZE   4096
 422 #define VMXNET3_TC_RING_MAX_SIZE   4096
 423 #define VMXNET3_RX_RING_MAX_SIZE   4096
 424 #define VMXNET3_RC_RING_MAX_SIZE   8192
 425
 426 #define VMXNET3_TXDATA_DESC_MIN_SIZE 128
 427 #define VMXNET3_TXDATA_DESC_MAX_SIZE 2048
 428
 429 #define VMXNET3_RXDATA_DESC_MAX_SIZE 2048
 430
 431 /* a list of reasons for queue stop */
 432
 433 #define VMXNET3_ERR_NOEOP        0x80000000  /* cannot find the EOP desc of a pkt */
 434 #define VMXNET3_ERR_TXD_REUSE    0x80000001  /* reuse a TxDesc before tx completion */
 435 #define VMXNET3_ERR_BIG_PKT      0x80000002  /* too many TxDesc for a pkt */
 436 #define VMXNET3_ERR_DESC_NOT_SPT 0x80000003  /* descriptor type not supported */
 437 #define VMXNET3_ERR_SMALL_BUF    0x80000004  /* type 0 buffer too small */
 438 #define VMXNET3_ERR_STRESS       0x80000005  /* stress option firing in vmkernel */
 439 #define VMXNET3_ERR_SWITCH       0x80000006  /* mode switch failure */
 440 #define VMXNET3_ERR_TXD_INVALID  0x80000007  /* invalid TxDesc */
 441
 442 /* completion descriptor types */
 443 #define VMXNET3_CDTYPE_TXCOMP      0    /* Tx Completion Descriptor */
 444 #define VMXNET3_CDTYPE_RXCOMP      3    /* Rx Completion Descriptor */
 445 #define VMXNET3_CDTYPE_RXCOMP_LRO  4    /* Rx Completion Descriptor for LRO */
 446
 447 #define VMXNET3_GOS_BITS_UNK    0   /* unknown */
 448 #define VMXNET3_GOS_BITS_32     1
 449 #define VMXNET3_GOS_BITS_64     2
 450
 451 #define VMXNET3_GOS_TYPE_UNK        0 /* unknown */
 452 #define VMXNET3_GOS_TYPE_LINUX      1
 453 #define VMXNET3_GOS_TYPE_WIN        2
 454 #define VMXNET3_GOS_TYPE_SOLARIS    3
 455 #define VMXNET3_GOS_TYPE_FREEBSD    4
 456 #define VMXNET3_GOS_TYPE_PXE        5
 457
 458 /* All structures in DriverShared are padded to multiples of 8 bytes */
 459
 460 typedef
 461 #include "vmware_pack_begin.h"
 462 struct Vmxnet3_GOSInfo {
 463 #ifdef __BIG_ENDIAN_BITFIELD
 464    uint32   gosMisc: 10;    /* other info about gos */
 465    uint32   gosVer:  16;    /* gos version */
 466    uint32   gosType: 4;     /* which guest */
 467    uint32   gosBits: 2;     /* 32-bit or 64-bit? */
 468 #else
 469    uint32   gosBits: 2;     /* 32-bit or 64-bit? */
 470    uint32   gosType: 4;     /* which guest */
 471    uint32   gosVer:  16;    /* gos version */
 472    uint32   gosMisc: 10;    /* other info about gos */
 473 #endif  /* __BIG_ENDIAN_BITFIELD */
 474 }
 475 #include "vmware_pack_end.h"
 476 Vmxnet3_GOSInfo;
 477
 478 typedef
 479 #include "vmware_pack_begin.h"
 480 struct Vmxnet3_DriverInfo {
 481    __le32          version;        /* driver version */
 482    Vmxnet3_GOSInfo gos;
 483    __le32          vmxnet3RevSpt;  /* vmxnet3 revision supported */
 484    __le32          uptVerSpt;      /* upt version supported */
 485 }
 486 #include "vmware_pack_end.h"
 487 Vmxnet3_DriverInfo;
 488
 489 #define VMXNET3_REV1_MAGIC  0xbabefee1
 490
 491 /*
 492  * QueueDescPA must be 128 bytes aligned. It points to an array of
 493  * Vmxnet3_TxQueueDesc followed by an array of Vmxnet3_RxQueueDesc.
 494  * The number of Vmxnet3_TxQueueDesc/Vmxnet3_RxQueueDesc are specified by
 495  * Vmxnet3_MiscConf.numTxQueues/numRxQueues, respectively.
 496  */
 497 #define VMXNET3_QUEUE_DESC_ALIGN  128
 498
 499 typedef
 500 #include "vmware_pack_begin.h"
 501 struct Vmxnet3_MiscConf {
 502    Vmxnet3_DriverInfo driverInfo;
 503    __le64             uptFeatures;
 504    __le64             ddPA;         /* driver data PA */
 505    __le64             queueDescPA;  /* queue descriptor table PA */
 506    __le32             ddLen;        /* driver data len */
 507    __le32             queueDescLen; /* queue descriptor table len, in bytes */
 508    __le32             mtu;
 509    __le16             maxNumRxSG;
 510    uint8              numTxQueues;
 511    uint8              numRxQueues;
 512    __le32             reserved[4];
 513 }
 514 #include "vmware_pack_end.h"
 515 Vmxnet3_MiscConf;
 516
 517 typedef
 518 #include "vmware_pack_begin.h"
 519 struct Vmxnet3_TxQueueConf {
 520    __le64    txRingBasePA;
 521    __le64    dataRingBasePA;
 522    __le64    compRingBasePA;
 523    __le64    ddPA;         /* driver data */
 524    __le64    reserved;
 525    __le32    txRingSize;   /* # of tx desc */
 526    __le32    dataRingSize; /* # of data desc */
 527    __le32    compRingSize; /* # of comp desc */
 528    __le32    ddLen;        /* size of driver data */
 529    uint8     intrIdx;
 530    uint8     _pad[1];
 531    __le16    txDataRingDescSize;
 532    uint8     _pad2[4];
 533 }
 534 #include "vmware_pack_end.h"
 535 Vmxnet3_TxQueueConf;
 536
 537 typedef
 538 #include "vmware_pack_begin.h"
 539 struct Vmxnet3_RxQueueConf {
 540    __le64    rxRingBasePA[2];
 541    __le64    compRingBasePA;
 542    __le64    ddPA;            /* driver data */
 543    __le64    rxDataRingBasePA;
 544    __le32    rxRingSize[2];   /* # of rx desc */
 545    __le32    compRingSize;    /* # of rx comp desc */
 546    __le32    ddLen;           /* size of driver data */
 547    uint8     intrIdx;
 548    uint8     _pad1[1];
 549    __le16    rxDataRingDescSize;  /* size of rx data ring buffer */
 550    uint8     _pad2[4];
 551 }
 552 #include "vmware_pack_end.h"
 553 Vmxnet3_RxQueueConf;
 554
 555 enum vmxnet3_intr_mask_mode {
 556    VMXNET3_IMM_AUTO   = 0,
 557    VMXNET3_IMM_ACTIVE = 1,
 558    VMXNET3_IMM_LAZY   = 2
 559 };
 560
 561 enum vmxnet3_intr_type {
 562    VMXNET3_IT_AUTO = 0,
 563    VMXNET3_IT_INTX = 1,
 564    VMXNET3_IT_MSI  = 2,
 565    VMXNET3_IT_MSIX = 3
 566 };
 567
 568 #define VMXNET3_MAX_TX_QUEUES  8
 569 #define VMXNET3_MAX_RX_QUEUES  16
 570 /* addition 1 for events */
 571 #define VMXNET3_MAX_INTRS      25
 572
 573 /* value of intrCtrl */
 574 #define VMXNET3_IC_DISABLE_ALL  0x1   /* bit 0 */
 575
 576 typedef
 577 #include "vmware_pack_begin.h"
 578 struct Vmxnet3_IntrConf {
 579    Bool   autoMask;
 580    uint8  numIntrs;      /* # of interrupts */
 581    uint8  eventIntrIdx;
 582    uint8  modLevels[VMXNET3_MAX_INTRS]; /* moderation level for each intr */
 583    __le32 intrCtrl;
 584    __le32 reserved[2];
 585 }
 586 #include "vmware_pack_end.h"
 587 Vmxnet3_IntrConf;
 588
 589 /* one bit per VLAN ID, the size is in the units of uint32 */
 590 #define VMXNET3_VFT_SIZE  (4096 / (sizeof(uint32) * 8))
 591
 592 typedef
 593 #include "vmware_pack_begin.h"
 594 struct Vmxnet3_QueueStatus {
 595    Bool    stopped;
 596    uint8   _pad[3];
 597    __le32  error;
 598 }
 599 #include "vmware_pack_end.h"
 600 Vmxnet3_QueueStatus;
 601
 602 typedef
 603 #include "vmware_pack_begin.h"
 604 struct Vmxnet3_TxQueueCtrl {
 605    __le32  txNumDeferred;
 606    __le32  txThreshold;
 607    __le64  reserved;
 608 }
 609 #include "vmware_pack_end.h"
 610 Vmxnet3_TxQueueCtrl;
 611
 612 typedef
 613 #include "vmware_pack_begin.h"
 614 struct Vmxnet3_RxQueueCtrl {
 615    Bool    updateRxProd;
 616    uint8   _pad[7];
 617    __le64  reserved;
 618 }
 619 #include "vmware_pack_end.h"
 620 Vmxnet3_RxQueueCtrl;
 621
 622 #define VMXNET3_RXM_UCAST     0x01  /* unicast only */
 623 #define VMXNET3_RXM_MCAST     0x02  /* multicast passing the filters */
 624 #define VMXNET3_RXM_BCAST     0x04  /* broadcast only */
 625 #define VMXNET3_RXM_ALL_MULTI 0x08  /* all multicast */
 626 #define VMXNET3_RXM_PROMISC   0x10  /* promiscuous */
 627
 628 typedef
 629 #include "vmware_pack_begin.h"
 630 struct Vmxnet3_RxFilterConf {
 631    __le32   rxMode;       /* VMXNET3_RXM_xxx */
 632    __le16   mfTableLen;   /* size of the multicast filter table */
 633    __le16   _pad1;
 634    __le64   mfTablePA;    /* PA of the multicast filters table */
 635    __le32   vfTable[VMXNET3_VFT_SIZE]; /* vlan filter */
 636 }
 637 #include "vmware_pack_end.h"
 638 Vmxnet3_RxFilterConf;
 639
 640 #define VMXNET3_PM_MAX_FILTERS        6
 641 #define VMXNET3_PM_MAX_PATTERN_SIZE   128
 642 #define VMXNET3_PM_MAX_MASK_SIZE      (VMXNET3_PM_MAX_PATTERN_SIZE / 8)
 643
 644 #define VMXNET3_PM_WAKEUP_MAGIC       0x01  /* wake up on magic pkts */
 645 #define VMXNET3_PM_WAKEUP_FILTER      0x02  /* wake up on pkts matching filters */
 646
 647 typedef
 648 #include "vmware_pack_begin.h"
 649 struct Vmxnet3_PM_PktFilter {
 650    uint8 maskSize;
 651    uint8 patternSize;
 652    uint8 mask[VMXNET3_PM_MAX_MASK_SIZE];
 653    uint8 pattern[VMXNET3_PM_MAX_PATTERN_SIZE];
 654    uint8 pad[6];
 655 }
 656 #include "vmware_pack_end.h"
 657 Vmxnet3_PM_PktFilter;
 658
 659 typedef
 660 #include "vmware_pack_begin.h"
 661 struct Vmxnet3_PMConf {
 662    __le16               wakeUpEvents;  /* VMXNET3_PM_WAKEUP_xxx */
 663    uint8                numFilters;
 664    uint8                pad[5];
 665    Vmxnet3_PM_PktFilter filters[VMXNET3_PM_MAX_FILTERS];
 666 }
 667 #include "vmware_pack_end.h"
 668 Vmxnet3_PMConf;
 669
 670 typedef
 671 #include "vmware_pack_begin.h"
 672 struct Vmxnet3_VariableLenConfDesc {
 673    __le32              confVer;
 674    __le32              confLen;
 675    __le64              confPA;
 676 }
 677 #include "vmware_pack_end.h"
 678 Vmxnet3_VariableLenConfDesc;
 679
 680 typedef
 681 #include "vmware_pack_begin.h"
 682 struct Vmxnet3_DSDevRead {
 683    /* read-only region for device, read by dev in response to a SET cmd */
 684    Vmxnet3_MiscConf     misc;
 685    Vmxnet3_IntrConf     intrConf;
 686    Vmxnet3_RxFilterConf rxFilterConf;
 687    Vmxnet3_VariableLenConfDesc  rssConfDesc;
 688    Vmxnet3_VariableLenConfDesc  pmConfDesc;
 689    Vmxnet3_VariableLenConfDesc  pluginConfDesc;
 690 }
 691 #include "vmware_pack_end.h"
 692 Vmxnet3_DSDevRead;
 693
 694 typedef
 695 #include "vmware_pack_begin.h"
 696 struct Vmxnet3_TxQueueDesc {
 697    Vmxnet3_TxQueueCtrl ctrl;
 698    Vmxnet3_TxQueueConf conf;
 699    /* Driver read after a GET command */
 700    Vmxnet3_QueueStatus status;
 701    UPT1_TxStats        stats;
 702    uint8               _pad[88]; /* 128 aligned */
 703 }
 704 #include "vmware_pack_end.h"
 705 Vmxnet3_TxQueueDesc;
 706
 707 typedef
 708 #include "vmware_pack_begin.h"
 709 struct Vmxnet3_RxQueueDesc {
 710    Vmxnet3_RxQueueCtrl ctrl;
 711    Vmxnet3_RxQueueConf conf;
 712    /* Driver read after a GET command */
 713    Vmxnet3_QueueStatus status;
 714    UPT1_RxStats        stats;
 715    uint8               _pad[88]; /* 128 aligned */
 716 }
 717 #include "vmware_pack_end.h"
 718 Vmxnet3_RxQueueDesc;
 719
 720 typedef
 721 #include "vmware_pack_begin.h"
 722 struct Vmxnet3_SetPolling {
 723    uint8 enablePolling;
 724 }
 725 #include "vmware_pack_end.h"
 726 Vmxnet3_SetPolling;
 727
 728 typedef
 729 #include "vmware_pack_begin.h"
 730 struct Vmxnet3_MemoryRegion {
 731         __le64            startPA;
 732         __le32            length;
 733         __le16            txQueueBits; /* bit n corresponding to tx queue n */
 734         __le16            rxQueueBits; /* bit n corresponding to rx queue n */
 735 }
 736 #include "vmware_pack_end.h"
 737 Vmxnet3_MemoryRegion;
 738
 739 #define MAX_MEMORY_REGION_PER_QUEUE 16
 740 #define MAX_MEMORY_REGION_PER_DEVICE 256
 741
 742 typedef
 743 #include "vmware_pack_begin.h"
 744 struct Vmxnet3_MemRegs {
 745         __le16           numRegs;
 746         __le16           pad[3];
 747         Vmxnet3_MemoryRegion memRegs[1];
 748 }
 749 #include "vmware_pack_end.h"
 750 Vmxnet3_MemRegs;
 751
 752 /*
 753  * If the command data <= 16 bytes, use the shared memory direcly.
 754  * Otherwise, use the variable length configuration descriptor.
 755  */
 756 typedef
 757 #include "vmware_pack_begin.h"
 758 union Vmxnet3_CmdInfo {
 759    Vmxnet3_VariableLenConfDesc varConf;
 760    Vmxnet3_SetPolling          setPolling;
 761    __le64                      data[2];
 762 }
 763 #include "vmware_pack_end.h"
 764 Vmxnet3_CmdInfo;
 765
 766 typedef
 767 #include "vmware_pack_begin.h"
 768 struct Vmxnet3_DriverShared {
 769    __le32               magic;
 770    __le32               pad; /* make devRead start at 64-bit boundaries */
 771    Vmxnet3_DSDevRead    devRead;
 772    __le32               ecr;
 773    __le32               reserved;
 774
 775    union {
 776       __le32            reserved1[4];
 777       Vmxnet3_CmdInfo   cmdInfo; /* only valid in the context of executing the
 778                                   * relevant command
 779                                   */
 780    } cu;
 781 }
 782 #include "vmware_pack_end.h"
 783 Vmxnet3_DriverShared;
 784
 785 #define VMXNET3_ECR_RQERR       (1 << 0)
 786 #define VMXNET3_ECR_TQERR       (1 << 1)
 787 #define VMXNET3_ECR_LINK        (1 << 2)
 788 #define VMXNET3_ECR_DIC         (1 << 3)
 789 #define VMXNET3_ECR_DEBUG       (1 << 4)
 790
 791 /* flip the gen bit of a ring */
 792 #define VMXNET3_FLIP_RING_GEN(gen) ((gen) = (gen) ^ 0x1)
 793
 794 /* only use this if moving the idx won't affect the gen bit */
 795 #define VMXNET3_INC_RING_IDX_ONLY(idx, ring_size) \
 796 do {\
 797    (idx)++;\
 798    if (UNLIKELY((idx) == (ring_size))) {\
 799       (idx) = 0;\
 800    }\
 801 } while (0)
 802
 803 #define VMXNET3_SET_VFTABLE_ENTRY(vfTable, vid) \
 804    vfTable[vid >> 5] |= (1 << (vid & 31))
 805 #define VMXNET3_CLEAR_VFTABLE_ENTRY(vfTable, vid) \
 806    vfTable[vid >> 5] &= ~(1 << (vid & 31))
 807
 808 #define VMXNET3_VFTABLE_ENTRY_IS_SET(vfTable, vid) \
 809    ((vfTable[vid >> 5] & (1 << (vid & 31))) != 0)
 810
 811 #define VMXNET3_MAX_MTU     9000
 812 #define VMXNET3_MIN_MTU     60
 813
 814 #define VMXNET3_LINK_UP         (10000 << 16 | 1)    // 10 Gbps, up
 815 #define VMXNET3_LINK_DOWN       0
 816
 817 #define VMXWIFI_DRIVER_SHARED_LEN 8192
 818
 819 #define VMXNET3_DID_PASSTHRU    0xFFFF
 820
 821 #endif /* _VMXNET3_DEFS_H_ */