ceph/src/spdk/dpdk/examples/load_balancer/main.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2014 Intel Corporation
   3  */
   4
   5 #ifndef _MAIN_H_
   6 #define _MAIN_H_
   7
   8 /* Logical cores */
   9 #ifndef APP_MAX_SOCKETS
  10 #define APP_MAX_SOCKETS 2
  11 #endif
  12
  13 #ifndef APP_MAX_LCORES
  14 #define APP_MAX_LCORES       RTE_MAX_LCORE
  15 #endif
  16
  17 #ifndef APP_MAX_NIC_PORTS
  18 #define APP_MAX_NIC_PORTS    RTE_MAX_ETHPORTS
  19 #endif
  20
  21 #ifndef APP_MAX_RX_QUEUES_PER_NIC_PORT
  22 #define APP_MAX_RX_QUEUES_PER_NIC_PORT 128
  23 #endif
  24
  25 #ifndef APP_MAX_TX_QUEUES_PER_NIC_PORT
  26 #define APP_MAX_TX_QUEUES_PER_NIC_PORT 128
  27 #endif
  28
  29 #ifndef APP_MAX_IO_LCORES
  30 #if (APP_MAX_LCORES > 16)
  31 #define APP_MAX_IO_LCORES 16
  32 #else
  33 #define APP_MAX_IO_LCORES APP_MAX_LCORES
  34 #endif
  35 #endif
  36 #if (APP_MAX_IO_LCORES > APP_MAX_LCORES)
  37 #error "APP_MAX_IO_LCORES is too big"
  38 #endif
  39
  40 #ifndef APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE
  41 #define APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE 16
  42 #endif
  43
  44 #ifndef APP_MAX_NIC_TX_PORTS_PER_IO_LCORE
  45 #define APP_MAX_NIC_TX_PORTS_PER_IO_LCORE 16
  46 #endif
  47 #if (APP_MAX_NIC_TX_PORTS_PER_IO_LCORE > APP_MAX_NIC_PORTS)
  48 #error "APP_MAX_NIC_TX_PORTS_PER_IO_LCORE too big"
  49 #endif
  50
  51 #ifndef APP_MAX_WORKER_LCORES
  52 #if (APP_MAX_LCORES > 16)
  53 #define APP_MAX_WORKER_LCORES 16
  54 #else
  55 #define APP_MAX_WORKER_LCORES APP_MAX_LCORES
  56 #endif
  57 #endif
  58 #if (APP_MAX_WORKER_LCORES > APP_MAX_LCORES)
  59 #error "APP_MAX_WORKER_LCORES is too big"
  60 #endif
  61
  62
  63 /* Mempools */
  64 #ifndef APP_DEFAULT_MBUF_DATA_SIZE
  65 #define APP_DEFAULT_MBUF_DATA_SIZE  RTE_MBUF_DEFAULT_BUF_SIZE
  66 #endif
  67
  68 #ifndef APP_DEFAULT_MEMPOOL_BUFFERS
  69 #define APP_DEFAULT_MEMPOOL_BUFFERS   8192 * 4
  70 #endif
  71
  72 #ifndef APP_DEFAULT_MEMPOOL_CACHE_SIZE
  73 #define APP_DEFAULT_MEMPOOL_CACHE_SIZE  256
  74 #endif
  75
  76 /* LPM Tables */
  77 #ifndef APP_MAX_LPM_RULES
  78 #define APP_MAX_LPM_RULES 1024
  79 #endif
  80
  81 /* NIC RX */
  82 #ifndef APP_DEFAULT_NIC_RX_RING_SIZE
  83 #define APP_DEFAULT_NIC_RX_RING_SIZE 1024
  84 #endif
  85
  86 /*
  87  * RX and TX Prefetch, Host, and Write-back threshold values should be
  88  * carefully set for optimal performance. Consult the network
  89  * controller's datasheet and supporting DPDK documentation for guidance
  90  * on how these parameters should be set.
  91  */
  92 #ifndef APP_DEFAULT_NIC_RX_PTHRESH
  93 #define APP_DEFAULT_NIC_RX_PTHRESH  8
  94 #endif
  95
  96 #ifndef APP_DEFAULT_NIC_RX_HTHRESH
  97 #define APP_DEFAULT_NIC_RX_HTHRESH  8
  98 #endif
  99
 100 #ifndef APP_DEFAULT_NIC_RX_WTHRESH
 101 #define APP_DEFAULT_NIC_RX_WTHRESH  4
 102 #endif
 103
 104 #ifndef APP_DEFAULT_NIC_RX_FREE_THRESH
 105 #define APP_DEFAULT_NIC_RX_FREE_THRESH  64
 106 #endif
 107
 108 #ifndef APP_DEFAULT_NIC_RX_DROP_EN
 109 #define APP_DEFAULT_NIC_RX_DROP_EN 0
 110 #endif
 111
 112 /* NIC TX */
 113 #ifndef APP_DEFAULT_NIC_TX_RING_SIZE
 114 #define APP_DEFAULT_NIC_TX_RING_SIZE 1024
 115 #endif
 116
 117 /*
 118  * These default values are optimized for use with the Intel(R) 82599 10 GbE
 119  * Controller and the DPDK ixgbe PMD. Consider using other values for other
 120  * network controllers and/or network drivers.
 121  */
 122 #ifndef APP_DEFAULT_NIC_TX_PTHRESH
 123 #define APP_DEFAULT_NIC_TX_PTHRESH  36
 124 #endif
 125
 126 #ifndef APP_DEFAULT_NIC_TX_HTHRESH
 127 #define APP_DEFAULT_NIC_TX_HTHRESH  0
 128 #endif
 129
 130 #ifndef APP_DEFAULT_NIC_TX_WTHRESH
 131 #define APP_DEFAULT_NIC_TX_WTHRESH  0
 132 #endif
 133
 134 #ifndef APP_DEFAULT_NIC_TX_FREE_THRESH
 135 #define APP_DEFAULT_NIC_TX_FREE_THRESH  0
 136 #endif
 137
 138 #ifndef APP_DEFAULT_NIC_TX_RS_THRESH
 139 #define APP_DEFAULT_NIC_TX_RS_THRESH  0
 140 #endif
 141
 142 /* Software Rings */
 143 #ifndef APP_DEFAULT_RING_RX_SIZE
 144 #define APP_DEFAULT_RING_RX_SIZE 1024
 145 #endif
 146
 147 #ifndef APP_DEFAULT_RING_TX_SIZE
 148 #define APP_DEFAULT_RING_TX_SIZE 1024
 149 #endif
 150
 151 /* Bursts */
 152 #ifndef APP_MBUF_ARRAY_SIZE
 153 #define APP_MBUF_ARRAY_SIZE   512
 154 #endif
 155
 156 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_READ
 157 #define APP_DEFAULT_BURST_SIZE_IO_RX_READ  144
 158 #endif
 159 #if (APP_DEFAULT_BURST_SIZE_IO_RX_READ > APP_MBUF_ARRAY_SIZE)
 160 #error "APP_DEFAULT_BURST_SIZE_IO_RX_READ is too big"
 161 #endif
 162
 163 #ifndef APP_DEFAULT_BURST_SIZE_IO_RX_WRITE
 164 #define APP_DEFAULT_BURST_SIZE_IO_RX_WRITE  144
 165 #endif
 166 #if (APP_DEFAULT_BURST_SIZE_IO_RX_WRITE > APP_MBUF_ARRAY_SIZE)
 167 #error "APP_DEFAULT_BURST_SIZE_IO_RX_WRITE is too big"
 168 #endif
 169
 170 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_READ
 171 #define APP_DEFAULT_BURST_SIZE_IO_TX_READ  144
 172 #endif
 173 #if (APP_DEFAULT_BURST_SIZE_IO_TX_READ > APP_MBUF_ARRAY_SIZE)
 174 #error "APP_DEFAULT_BURST_SIZE_IO_TX_READ is too big"
 175 #endif
 176
 177 #ifndef APP_DEFAULT_BURST_SIZE_IO_TX_WRITE
 178 #define APP_DEFAULT_BURST_SIZE_IO_TX_WRITE  144
 179 #endif
 180 #if (APP_DEFAULT_BURST_SIZE_IO_TX_WRITE > APP_MBUF_ARRAY_SIZE)
 181 #error "APP_DEFAULT_BURST_SIZE_IO_TX_WRITE is too big"
 182 #endif
 183
 184 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_READ
 185 #define APP_DEFAULT_BURST_SIZE_WORKER_READ  144
 186 #endif
 187 #if ((2 * APP_DEFAULT_BURST_SIZE_WORKER_READ) > APP_MBUF_ARRAY_SIZE)
 188 #error "APP_DEFAULT_BURST_SIZE_WORKER_READ is too big"
 189 #endif
 190
 191 #ifndef APP_DEFAULT_BURST_SIZE_WORKER_WRITE
 192 #define APP_DEFAULT_BURST_SIZE_WORKER_WRITE  144
 193 #endif
 194 #if (APP_DEFAULT_BURST_SIZE_WORKER_WRITE > APP_MBUF_ARRAY_SIZE)
 195 #error "APP_DEFAULT_BURST_SIZE_WORKER_WRITE is too big"
 196 #endif
 197
 198 /* Load balancing logic */
 199 #ifndef APP_DEFAULT_IO_RX_LB_POS
 200 #define APP_DEFAULT_IO_RX_LB_POS 29
 201 #endif
 202 #if (APP_DEFAULT_IO_RX_LB_POS >= 64)
 203 #error "APP_DEFAULT_IO_RX_LB_POS is too big"
 204 #endif
 205
 206 struct app_mbuf_array {
 207         struct rte_mbuf *array[APP_MBUF_ARRAY_SIZE];
 208         uint32_t n_mbufs;
 209 };
 210
 211 enum app_lcore_type {
 212         e_APP_LCORE_DISABLED = 0,
 213         e_APP_LCORE_IO,
 214         e_APP_LCORE_WORKER
 215 };
 216
 217 struct app_lcore_params_io {
 218         /* I/O RX */
 219         struct {
 220                 /* NIC */
 221                 struct {
 222                         uint16_t port;
 223                         uint8_t queue;
 224                 } nic_queues[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
 225                 uint32_t n_nic_queues;
 226
 227                 /* Rings */
 228                 struct rte_ring *rings[APP_MAX_WORKER_LCORES];
 229                 uint32_t n_rings;
 230
 231                 /* Internal buffers */
 232                 struct app_mbuf_array mbuf_in;
 233                 struct app_mbuf_array mbuf_out[APP_MAX_WORKER_LCORES];
 234                 uint8_t mbuf_out_flush[APP_MAX_WORKER_LCORES];
 235
 236                 /* Stats */
 237                 uint32_t nic_queues_count[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
 238                 uint32_t nic_queues_iters[APP_MAX_NIC_RX_QUEUES_PER_IO_LCORE];
 239                 uint32_t rings_count[APP_MAX_WORKER_LCORES];
 240                 uint32_t rings_iters[APP_MAX_WORKER_LCORES];
 241         } rx;
 242
 243         /* I/O TX */
 244         struct {
 245                 /* Rings */
 246                 struct rte_ring *rings[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
 247
 248                 /* NIC */
 249                 uint16_t nic_ports[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
 250                 uint32_t n_nic_ports;
 251
 252                 /* Internal buffers */
 253                 struct app_mbuf_array mbuf_out[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
 254                 uint8_t mbuf_out_flush[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
 255
 256                 /* Stats */
 257                 uint32_t rings_count[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
 258                 uint32_t rings_iters[APP_MAX_NIC_PORTS][APP_MAX_WORKER_LCORES];
 259                 uint32_t nic_ports_count[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
 260                 uint32_t nic_ports_iters[APP_MAX_NIC_TX_PORTS_PER_IO_LCORE];
 261         } tx;
 262 };
 263
 264 struct app_lcore_params_worker {
 265         /* Rings */
 266         struct rte_ring *rings_in[APP_MAX_IO_LCORES];
 267         uint32_t n_rings_in;
 268         struct rte_ring *rings_out[APP_MAX_NIC_PORTS];
 269
 270         /* LPM table */
 271         struct rte_lpm *lpm_table;
 272         uint32_t worker_id;
 273
 274         /* Internal buffers */
 275         struct app_mbuf_array mbuf_in;
 276         struct app_mbuf_array mbuf_out[APP_MAX_NIC_PORTS];
 277         uint8_t mbuf_out_flush[APP_MAX_NIC_PORTS];
 278
 279         /* Stats */
 280         uint32_t rings_in_count[APP_MAX_IO_LCORES];
 281         uint32_t rings_in_iters[APP_MAX_IO_LCORES];
 282         uint32_t rings_out_count[APP_MAX_NIC_PORTS];
 283         uint32_t rings_out_iters[APP_MAX_NIC_PORTS];
 284 };
 285
 286 struct app_lcore_params {
 287         union {
 288                 struct app_lcore_params_io io;
 289                 struct app_lcore_params_worker worker;
 290         };
 291         enum app_lcore_type type;
 292         struct rte_mempool *pool;
 293 } __rte_cache_aligned;
 294
 295 struct app_lpm_rule {
 296         uint32_t ip;
 297         uint8_t depth;
 298         uint8_t if_out;
 299 };
 300
 301 struct app_params {
 302         /* lcore */
 303         struct app_lcore_params lcore_params[APP_MAX_LCORES];
 304
 305         /* NIC */
 306         uint8_t nic_rx_queue_mask[APP_MAX_NIC_PORTS][APP_MAX_RX_QUEUES_PER_NIC_PORT];
 307         uint8_t nic_tx_port_mask[APP_MAX_NIC_PORTS];
 308
 309         /* mbuf pools */
 310         struct rte_mempool *pools[APP_MAX_SOCKETS];
 311
 312         /* LPM tables */
 313         struct rte_lpm *lpm_tables[APP_MAX_SOCKETS];
 314         struct app_lpm_rule lpm_rules[APP_MAX_LPM_RULES];
 315         uint32_t n_lpm_rules;
 316
 317         /* rings */
 318         uint32_t nic_rx_ring_size;
 319         uint32_t nic_tx_ring_size;
 320         uint32_t ring_rx_size;
 321         uint32_t ring_tx_size;
 322
 323         /* burst size */
 324         uint32_t burst_size_io_rx_read;
 325         uint32_t burst_size_io_rx_write;
 326         uint32_t burst_size_io_tx_read;
 327         uint32_t burst_size_io_tx_write;
 328         uint32_t burst_size_worker_read;
 329         uint32_t burst_size_worker_write;
 330
 331         /* load balancing */
 332         uint8_t pos_lb;
 333 } __rte_cache_aligned;
 334
 335 extern struct app_params app;
 336
 337 int app_parse_args(int argc, char **argv);
 338 void app_print_usage(void);
 339 void app_init(void);
 340 int app_lcore_main_loop(void *arg);
 341
 342 int app_get_nic_rx_queues_per_port(uint16_t port);
 343 int app_get_lcore_for_nic_rx(uint16_t port, uint8_t queue,
 344                               uint32_t *lcore_out);
 345 int app_get_lcore_for_nic_tx(uint16_t port, uint32_t *lcore_out);
 346 int app_is_socket_used(uint32_t socket);
 347 uint32_t app_get_lcores_io_rx(void);
 348 uint32_t app_get_lcores_worker(void);
 349 void app_print_params(void);
 350
 351 #endif /* _MAIN_H_ */