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1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2014 Intel Corporation
16 #include <rte_lcore.h>
17 #include <rte_string_fns.h>
21 #define APP_NAME "qos_sched"
22 #define MAX_OPT_VALUES 8
23 #define SYS_CPU_DIR "/sys/devices/system/cpu/cpu%u/topology/"
25 static uint32_t app_master_core
= 1;
26 static uint32_t app_numa_mask
;
27 static uint64_t app_used_core_mask
= 0;
28 static uint64_t app_used_port_mask
= 0;
29 static uint64_t app_used_rx_port_mask
= 0;
30 static uint64_t app_used_tx_port_mask
= 0;
33 static const char usage
[] =
37 "Application mandatory parameters: \n"
38 " --pfc \"RX PORT, TX PORT, RX LCORE, WT LCORE\" : Packet flow configuration \n"
39 " multiple pfc can be configured in command line \n"
41 "Application optional parameters: \n"
42 " --i : run in interactive mode (default value is %u) \n"
43 " --mst I : master core index (default value is %u) \n"
44 " --rsz \"A, B, C\" : Ring sizes \n"
45 " A = Size (in number of buffer descriptors) of each of the NIC RX \n"
46 " rings read by the I/O RX lcores (default value is %u) \n"
47 " B = Size (in number of elements) of each of the SW rings used by the\n"
48 " I/O RX lcores to send packets to worker lcores (default value is\n"
50 " C = Size (in number of buffer descriptors) of each of the NIC TX \n"
51 " rings written by worker lcores (default value is %u) \n"
52 " --bsz \"A, B, C, D\": Burst sizes \n"
53 " A = I/O RX lcore read burst size from NIC RX (default value is %u) \n"
54 " B = I/O RX lcore write burst size to output SW rings, \n"
55 " Worker lcore read burst size from input SW rings, \n"
56 " QoS enqueue size (default value is %u) \n"
57 " C = QoS dequeue size (default value is %u) \n"
58 " D = Worker lcore write burst size to NIC TX (default value is %u) \n"
59 " --msz M : Mempool size (in number of mbufs) for each pfc (default %u) \n"
60 " --rth \"A, B, C\" : RX queue threshold parameters \n"
61 " A = RX prefetch threshold (default value is %u) \n"
62 " B = RX host threshold (default value is %u) \n"
63 " C = RX write-back threshold (default value is %u) \n"
64 " --tth \"A, B, C\" : TX queue threshold parameters \n"
65 " A = TX prefetch threshold (default value is %u) \n"
66 " B = TX host threshold (default value is %u) \n"
67 " C = TX write-back threshold (default value is %u) \n"
68 " --cfg FILE : profile configuration to load \n"
73 app_usage(const char *prgname
)
75 printf(usage
, prgname
, APP_INTERACTIVE_DEFAULT
, app_master_core
,
76 APP_RX_DESC_DEFAULT
, APP_RING_SIZE
, APP_TX_DESC_DEFAULT
,
77 MAX_PKT_RX_BURST
, PKT_ENQUEUE
, PKT_DEQUEUE
,
78 MAX_PKT_TX_BURST
, NB_MBUF
,
79 RX_PTHRESH
, RX_HTHRESH
, RX_WTHRESH
,
80 TX_PTHRESH
, TX_HTHRESH
, TX_WTHRESH
84 static inline int str_is(const char *str
, const char *is
)
86 return strcmp(str
, is
) == 0;
89 /* returns core mask used by DPDK */
91 app_eal_core_mask(void)
96 for (i
= 0; i
< APP_MAX_LCORE
; i
++) {
97 if (rte_lcore_has_role(i
, ROLE_RTE
))
101 cm
|= (1ULL << rte_get_master_lcore());
107 /* returns total number of cores presented in a system */
109 app_cpu_core_count(void)
115 for (i
= 0; i
< APP_MAX_LCORE
; i
++) {
116 len
= snprintf(path
, sizeof(path
), SYS_CPU_DIR
, i
);
117 if (len
<= 0 || (unsigned)len
>= sizeof(path
))
120 if (access(path
, F_OK
) == 0)
128 number of values parsed
132 app_parse_opt_vals(const char *conf_str
, char separator
, uint32_t n_vals
, uint32_t *opt_vals
)
136 char *tokens
[MAX_OPT_VALUES
];
138 if (conf_str
== NULL
|| opt_vals
== NULL
|| n_vals
== 0 || n_vals
> MAX_OPT_VALUES
)
141 /* duplicate configuration string before splitting it to tokens */
142 string
= strdup(conf_str
);
146 n_tokens
= rte_strsplit(string
, strnlen(string
, 32), tokens
, n_vals
, separator
);
148 if (n_tokens
> MAX_OPT_VALUES
)
151 for (i
= 0; i
< n_tokens
; i
++)
152 opt_vals
[i
] = (uint32_t)atol(tokens
[i
]);
160 app_parse_ring_conf(const char *conf_str
)
165 ret
= app_parse_opt_vals(conf_str
, ',', 3, vals
);
169 ring_conf
.rx_size
= vals
[0];
170 ring_conf
.ring_size
= vals
[1];
171 ring_conf
.tx_size
= vals
[2];
177 app_parse_rth_conf(const char *conf_str
)
182 ret
= app_parse_opt_vals(conf_str
, ',', 3, vals
);
186 rx_thresh
.pthresh
= (uint8_t)vals
[0];
187 rx_thresh
.hthresh
= (uint8_t)vals
[1];
188 rx_thresh
.wthresh
= (uint8_t)vals
[2];
194 app_parse_tth_conf(const char *conf_str
)
199 ret
= app_parse_opt_vals(conf_str
, ',', 3, vals
);
203 tx_thresh
.pthresh
= (uint8_t)vals
[0];
204 tx_thresh
.hthresh
= (uint8_t)vals
[1];
205 tx_thresh
.wthresh
= (uint8_t)vals
[2];
211 app_parse_flow_conf(const char *conf_str
)
215 struct flow_conf
*pconf
;
218 memset(vals
, 0, sizeof(vals
));
219 ret
= app_parse_opt_vals(conf_str
, ',', 6, vals
);
220 if (ret
< 4 || ret
> 5)
223 pconf
= &qos_conf
[nb_pfc
];
225 pconf
->rx_port
= vals
[0];
226 pconf
->tx_port
= vals
[1];
227 pconf
->rx_core
= (uint8_t)vals
[2];
228 pconf
->wt_core
= (uint8_t)vals
[3];
230 pconf
->tx_core
= (uint8_t)vals
[4];
232 pconf
->tx_core
= pconf
->wt_core
;
234 if (pconf
->rx_core
== pconf
->wt_core
) {
235 RTE_LOG(ERR
, APP
, "pfc %u: rx thread and worker thread cannot share same core\n", nb_pfc
);
239 if (pconf
->rx_port
>= RTE_MAX_ETHPORTS
) {
240 RTE_LOG(ERR
, APP
, "pfc %u: invalid rx port %"PRIu16
" index\n",
241 nb_pfc
, pconf
->rx_port
);
244 if (pconf
->tx_port
>= RTE_MAX_ETHPORTS
) {
245 RTE_LOG(ERR
, APP
, "pfc %u: invalid tx port %"PRIu16
" index\n",
246 nb_pfc
, pconf
->tx_port
);
250 mask
= 1lu << pconf
->rx_port
;
251 if (app_used_rx_port_mask
& mask
) {
252 RTE_LOG(ERR
, APP
, "pfc %u: rx port %"PRIu16
" is used already\n",
253 nb_pfc
, pconf
->rx_port
);
256 app_used_rx_port_mask
|= mask
;
257 app_used_port_mask
|= mask
;
259 mask
= 1lu << pconf
->tx_port
;
260 if (app_used_tx_port_mask
& mask
) {
261 RTE_LOG(ERR
, APP
, "pfc %u: port %"PRIu16
" is used already\n",
262 nb_pfc
, pconf
->tx_port
);
265 app_used_tx_port_mask
|= mask
;
266 app_used_port_mask
|= mask
;
268 mask
= 1lu << pconf
->rx_core
;
269 app_used_core_mask
|= mask
;
271 mask
= 1lu << pconf
->wt_core
;
272 app_used_core_mask
|= mask
;
274 mask
= 1lu << pconf
->tx_core
;
275 app_used_core_mask
|= mask
;
283 app_parse_burst_conf(const char *conf_str
)
288 ret
= app_parse_opt_vals(conf_str
, ',', 4, vals
);
292 burst_conf
.rx_burst
= (uint16_t)vals
[0];
293 burst_conf
.ring_burst
= (uint16_t)vals
[1];
294 burst_conf
.qos_dequeue
= (uint16_t)vals
[2];
295 burst_conf
.tx_burst
= (uint16_t)vals
[3];
301 * Parses the argument given in the command line of the application,
302 * calculates mask for used cores and initializes EAL with calculated core mask
305 app_parse_args(int argc
, char **argv
)
310 char *prgname
= argv
[0];
311 uint32_t i
, nb_lcores
;
313 static struct option lgopts
[] = {
325 /* initialize EAL first */
326 ret
= rte_eal_init(argc
, argv
);
333 /* set en_US locale to print big numbers with ',' */
334 setlocale(LC_NUMERIC
, "en_US.utf-8");
336 while ((opt
= getopt_long(argc
, argv
, "i",
337 lgopts
, &option_index
)) != EOF
) {
341 printf("Interactive-mode selected\n");
346 optname
= lgopts
[option_index
].name
;
347 if (str_is(optname
, "pfc")) {
348 ret
= app_parse_flow_conf(optarg
);
350 RTE_LOG(ERR
, APP
, "Invalid pipe configuration %s\n", optarg
);
355 if (str_is(optname
, "mst")) {
356 app_master_core
= (uint32_t)atoi(optarg
);
359 if (str_is(optname
, "rsz")) {
360 ret
= app_parse_ring_conf(optarg
);
362 RTE_LOG(ERR
, APP
, "Invalid ring configuration %s\n", optarg
);
367 if (str_is(optname
, "bsz")) {
368 ret
= app_parse_burst_conf(optarg
);
370 RTE_LOG(ERR
, APP
, "Invalid burst configuration %s\n", optarg
);
375 if (str_is(optname
, "msz")) {
376 mp_size
= atoi(optarg
);
378 RTE_LOG(ERR
, APP
, "Invalid mempool size %s\n", optarg
);
383 if (str_is(optname
, "rth")) {
384 ret
= app_parse_rth_conf(optarg
);
386 RTE_LOG(ERR
, APP
, "Invalid RX threshold configuration %s\n", optarg
);
391 if (str_is(optname
, "tth")) {
392 ret
= app_parse_tth_conf(optarg
);
394 RTE_LOG(ERR
, APP
, "Invalid TX threshold configuration %s\n", optarg
);
399 if (str_is(optname
, "cfg")) {
400 cfg_profile
= optarg
;
411 /* check master core index validity */
412 for(i
= 0; i
<= app_master_core
; i
++) {
413 if (app_used_core_mask
& (1u << app_master_core
)) {
414 RTE_LOG(ERR
, APP
, "Master core index is not configured properly\n");
419 app_used_core_mask
|= 1u << app_master_core
;
421 if ((app_used_core_mask
!= app_eal_core_mask()) ||
422 (app_master_core
!= rte_get_master_lcore())) {
423 RTE_LOG(ERR
, APP
, "EAL core mask not configured properly, must be %" PRIx64
424 " instead of %" PRIx64
"\n" , app_used_core_mask
, app_eal_core_mask());
429 RTE_LOG(ERR
, APP
, "Packet flow not configured!\n");
434 /* sanity check for cores assignment */
435 nb_lcores
= app_cpu_core_count();
437 for(i
= 0; i
< nb_pfc
; i
++) {
438 if (qos_conf
[i
].rx_core
>= nb_lcores
) {
439 RTE_LOG(ERR
, APP
, "pfc %u: invalid RX lcore index %u\n", i
+ 1,
440 qos_conf
[i
].rx_core
);
443 if (qos_conf
[i
].wt_core
>= nb_lcores
) {
444 RTE_LOG(ERR
, APP
, "pfc %u: invalid WT lcore index %u\n", i
+ 1,
445 qos_conf
[i
].wt_core
);
448 uint32_t rx_sock
= rte_lcore_to_socket_id(qos_conf
[i
].rx_core
);
449 uint32_t wt_sock
= rte_lcore_to_socket_id(qos_conf
[i
].wt_core
);
450 if (rx_sock
!= wt_sock
) {
451 RTE_LOG(ERR
, APP
, "pfc %u: RX and WT must be on the same socket\n", i
+ 1);
454 app_numa_mask
|= 1 << rte_lcore_to_socket_id(qos_conf
[i
].rx_core
);