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[ceph.git] / ceph / src / spdk / dpdk / kernel / linux / kni / ethtool / igb / e1000_82575.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*******************************************************************************
3
4 Intel(R) Gigabit Ethernet Linux driver
5 Copyright(c) 2007-2013 Intel Corporation.
6
7 Contact Information:
8 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
9 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
10
11 *******************************************************************************/
12
13 /*
14 * 82575EB Gigabit Network Connection
15 * 82575EB Gigabit Backplane Connection
16 * 82575GB Gigabit Network Connection
17 * 82576 Gigabit Network Connection
18 * 82576 Quad Port Gigabit Mezzanine Adapter
19 * 82580 Gigabit Network Connection
20 * I350 Gigabit Network Connection
21 */
22
23 #include "e1000_api.h"
24 #include "e1000_i210.h"
25
26 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw);
27 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw);
28 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw);
29 static void e1000_release_phy_82575(struct e1000_hw *hw);
30 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw);
31 static void e1000_release_nvm_82575(struct e1000_hw *hw);
32 static s32 e1000_check_for_link_82575(struct e1000_hw *hw);
33 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw);
34 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw);
35 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
36 u16 *duplex);
37 static s32 e1000_init_hw_82575(struct e1000_hw *hw);
38 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw);
39 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
40 u16 *data);
41 static s32 e1000_reset_hw_82575(struct e1000_hw *hw);
42 static s32 e1000_reset_hw_82580(struct e1000_hw *hw);
43 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw,
44 u32 offset, u16 *data);
45 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw,
46 u32 offset, u16 data);
47 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw,
48 bool active);
49 static s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw,
50 bool active);
51 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw,
52 bool active);
53 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw);
54 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw);
55 static s32 e1000_get_media_type_82575(struct e1000_hw *hw);
56 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw);
57 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data);
58 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw,
59 u32 offset, u16 data);
60 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw);
61 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
62 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
63 u16 *speed, u16 *duplex);
64 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw);
65 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask);
66 static bool e1000_sgmii_active_82575(struct e1000_hw *hw);
67 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw);
68 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw);
69 static void e1000_config_collision_dist_82575(struct e1000_hw *hw);
70 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw);
71 static void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw);
72 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw);
73 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw);
74 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw);
75 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw);
76 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw);
77 static s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw,
78 u16 offset);
79 static s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw,
80 u16 offset);
81 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw);
82 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw);
83 static void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value);
84 static void e1000_clear_vfta_i350(struct e1000_hw *hw);
85
86 static void e1000_i2c_start(struct e1000_hw *hw);
87 static void e1000_i2c_stop(struct e1000_hw *hw);
88 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data);
89 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data);
90 static s32 e1000_get_i2c_ack(struct e1000_hw *hw);
91 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data);
92 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data);
93 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
94 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl);
95 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data);
96 static bool e1000_get_i2c_data(u32 *i2cctl);
97
98 static const u16 e1000_82580_rxpbs_table[] = {
99 36, 72, 144, 1, 2, 4, 8, 16, 35, 70, 140 };
100 #define E1000_82580_RXPBS_TABLE_SIZE \
101 (sizeof(e1000_82580_rxpbs_table)/sizeof(u16))
102
103
104 /**
105 * e1000_sgmii_uses_mdio_82575 - Determine if I2C pins are for external MDIO
106 * @hw: pointer to the HW structure
107 *
108 * Called to determine if the I2C pins are being used for I2C or as an
109 * external MDIO interface since the two options are mutually exclusive.
110 **/
111 static bool e1000_sgmii_uses_mdio_82575(struct e1000_hw *hw)
112 {
113 u32 reg = 0;
114 bool ext_mdio = false;
115
116 DEBUGFUNC("e1000_sgmii_uses_mdio_82575");
117
118 switch (hw->mac.type) {
119 case e1000_82575:
120 case e1000_82576:
121 reg = E1000_READ_REG(hw, E1000_MDIC);
122 ext_mdio = !!(reg & E1000_MDIC_DEST);
123 break;
124 case e1000_82580:
125 case e1000_i350:
126 case e1000_i354:
127 case e1000_i210:
128 case e1000_i211:
129 reg = E1000_READ_REG(hw, E1000_MDICNFG);
130 ext_mdio = !!(reg & E1000_MDICNFG_EXT_MDIO);
131 break;
132 default:
133 break;
134 }
135 return ext_mdio;
136 }
137
138 /**
139 * e1000_init_phy_params_82575 - Init PHY func ptrs.
140 * @hw: pointer to the HW structure
141 **/
142 static s32 e1000_init_phy_params_82575(struct e1000_hw *hw)
143 {
144 struct e1000_phy_info *phy = &hw->phy;
145 s32 ret_val = E1000_SUCCESS;
146 u32 ctrl_ext;
147
148 DEBUGFUNC("e1000_init_phy_params_82575");
149
150 phy->ops.read_i2c_byte = e1000_read_i2c_byte_generic;
151 phy->ops.write_i2c_byte = e1000_write_i2c_byte_generic;
152
153 if (hw->phy.media_type != e1000_media_type_copper) {
154 phy->type = e1000_phy_none;
155 goto out;
156 }
157
158 phy->ops.power_up = e1000_power_up_phy_copper;
159 phy->ops.power_down = e1000_power_down_phy_copper_82575;
160
161 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
162 phy->reset_delay_us = 100;
163
164 phy->ops.acquire = e1000_acquire_phy_82575;
165 phy->ops.check_reset_block = e1000_check_reset_block_generic;
166 phy->ops.commit = e1000_phy_sw_reset_generic;
167 phy->ops.get_cfg_done = e1000_get_cfg_done_82575;
168 phy->ops.release = e1000_release_phy_82575;
169
170 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
171
172 if (e1000_sgmii_active_82575(hw)) {
173 phy->ops.reset = e1000_phy_hw_reset_sgmii_82575;
174 ctrl_ext |= E1000_CTRL_I2C_ENA;
175 } else {
176 phy->ops.reset = e1000_phy_hw_reset_generic;
177 ctrl_ext &= ~E1000_CTRL_I2C_ENA;
178 }
179
180 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
181 e1000_reset_mdicnfg_82580(hw);
182
183 if (e1000_sgmii_active_82575(hw) && !e1000_sgmii_uses_mdio_82575(hw)) {
184 phy->ops.read_reg = e1000_read_phy_reg_sgmii_82575;
185 phy->ops.write_reg = e1000_write_phy_reg_sgmii_82575;
186 } else {
187 switch (hw->mac.type) {
188 case e1000_82580:
189 case e1000_i350:
190 case e1000_i354:
191 phy->ops.read_reg = e1000_read_phy_reg_82580;
192 phy->ops.write_reg = e1000_write_phy_reg_82580;
193 break;
194 case e1000_i210:
195 case e1000_i211:
196 phy->ops.read_reg = e1000_read_phy_reg_gs40g;
197 phy->ops.write_reg = e1000_write_phy_reg_gs40g;
198 break;
199 default:
200 phy->ops.read_reg = e1000_read_phy_reg_igp;
201 phy->ops.write_reg = e1000_write_phy_reg_igp;
202 }
203 }
204
205 /* Set phy->phy_addr and phy->id. */
206 ret_val = e1000_get_phy_id_82575(hw);
207
208 /* Verify phy id and set remaining function pointers */
209 switch (phy->id) {
210 case M88E1543_E_PHY_ID:
211 case I347AT4_E_PHY_ID:
212 case M88E1112_E_PHY_ID:
213 case M88E1340M_E_PHY_ID:
214 case M88E1111_I_PHY_ID:
215 phy->type = e1000_phy_m88;
216 phy->ops.check_polarity = e1000_check_polarity_m88;
217 phy->ops.get_info = e1000_get_phy_info_m88;
218 if (phy->id == I347AT4_E_PHY_ID ||
219 phy->id == M88E1112_E_PHY_ID ||
220 phy->id == M88E1340M_E_PHY_ID)
221 phy->ops.get_cable_length =
222 e1000_get_cable_length_m88_gen2;
223 else if (phy->id == M88E1543_E_PHY_ID)
224 phy->ops.get_cable_length =
225 e1000_get_cable_length_m88_gen2;
226 else
227 phy->ops.get_cable_length = e1000_get_cable_length_m88;
228 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
229 /* Check if this PHY is configured for media swap. */
230 if (phy->id == M88E1112_E_PHY_ID) {
231 u16 data;
232
233 ret_val = phy->ops.write_reg(hw,
234 E1000_M88E1112_PAGE_ADDR,
235 2);
236 if (ret_val)
237 goto out;
238
239 ret_val = phy->ops.read_reg(hw,
240 E1000_M88E1112_MAC_CTRL_1,
241 &data);
242 if (ret_val)
243 goto out;
244
245 data = (data & E1000_M88E1112_MAC_CTRL_1_MODE_MASK) >>
246 E1000_M88E1112_MAC_CTRL_1_MODE_SHIFT;
247 if (data == E1000_M88E1112_AUTO_COPPER_SGMII ||
248 data == E1000_M88E1112_AUTO_COPPER_BASEX)
249 hw->mac.ops.check_for_link =
250 e1000_check_for_link_media_swap;
251 }
252 break;
253 case IGP03E1000_E_PHY_ID:
254 case IGP04E1000_E_PHY_ID:
255 phy->type = e1000_phy_igp_3;
256 phy->ops.check_polarity = e1000_check_polarity_igp;
257 phy->ops.get_info = e1000_get_phy_info_igp;
258 phy->ops.get_cable_length = e1000_get_cable_length_igp_2;
259 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_igp;
260 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82575;
261 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_generic;
262 break;
263 case I82580_I_PHY_ID:
264 case I350_I_PHY_ID:
265 phy->type = e1000_phy_82580;
266 phy->ops.check_polarity = e1000_check_polarity_82577;
267 phy->ops.force_speed_duplex =
268 e1000_phy_force_speed_duplex_82577;
269 phy->ops.get_cable_length = e1000_get_cable_length_82577;
270 phy->ops.get_info = e1000_get_phy_info_82577;
271 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
272 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
273 break;
274 case I210_I_PHY_ID:
275 phy->type = e1000_phy_i210;
276 phy->ops.check_polarity = e1000_check_polarity_m88;
277 phy->ops.get_info = e1000_get_phy_info_m88;
278 phy->ops.get_cable_length = e1000_get_cable_length_m88_gen2;
279 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82580;
280 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82580;
281 phy->ops.force_speed_duplex = e1000_phy_force_speed_duplex_m88;
282 break;
283 default:
284 ret_val = -E1000_ERR_PHY;
285 goto out;
286 }
287
288 out:
289 return ret_val;
290 }
291
292 /**
293 * e1000_init_nvm_params_82575 - Init NVM func ptrs.
294 * @hw: pointer to the HW structure
295 **/
296 s32 e1000_init_nvm_params_82575(struct e1000_hw *hw)
297 {
298 struct e1000_nvm_info *nvm = &hw->nvm;
299 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
300 u16 size;
301
302 DEBUGFUNC("e1000_init_nvm_params_82575");
303
304 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
305 E1000_EECD_SIZE_EX_SHIFT);
306 /*
307 * Added to a constant, "size" becomes the left-shift value
308 * for setting word_size.
309 */
310 size += NVM_WORD_SIZE_BASE_SHIFT;
311
312 /* Just in case size is out of range, cap it to the largest
313 * EEPROM size supported
314 */
315 if (size > 15)
316 size = 15;
317
318 nvm->word_size = 1 << size;
319 if (hw->mac.type < e1000_i210) {
320 nvm->opcode_bits = 8;
321 nvm->delay_usec = 1;
322
323 switch (nvm->override) {
324 case e1000_nvm_override_spi_large:
325 nvm->page_size = 32;
326 nvm->address_bits = 16;
327 break;
328 case e1000_nvm_override_spi_small:
329 nvm->page_size = 8;
330 nvm->address_bits = 8;
331 break;
332 default:
333 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
334 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ?
335 16 : 8;
336 break;
337 }
338 if (nvm->word_size == (1 << 15))
339 nvm->page_size = 128;
340
341 nvm->type = e1000_nvm_eeprom_spi;
342 } else {
343 nvm->type = e1000_nvm_flash_hw;
344 }
345
346 /* Function Pointers */
347 nvm->ops.acquire = e1000_acquire_nvm_82575;
348 nvm->ops.release = e1000_release_nvm_82575;
349 if (nvm->word_size < (1 << 15))
350 nvm->ops.read = e1000_read_nvm_eerd;
351 else
352 nvm->ops.read = e1000_read_nvm_spi;
353
354 nvm->ops.write = e1000_write_nvm_spi;
355 nvm->ops.validate = e1000_validate_nvm_checksum_generic;
356 nvm->ops.update = e1000_update_nvm_checksum_generic;
357 nvm->ops.valid_led_default = e1000_valid_led_default_82575;
358
359 /* override generic family function pointers for specific descendants */
360 switch (hw->mac.type) {
361 case e1000_82580:
362 nvm->ops.validate = e1000_validate_nvm_checksum_82580;
363 nvm->ops.update = e1000_update_nvm_checksum_82580;
364 break;
365 case e1000_i350:
366 //case e1000_i354:
367 nvm->ops.validate = e1000_validate_nvm_checksum_i350;
368 nvm->ops.update = e1000_update_nvm_checksum_i350;
369 break;
370 default:
371 break;
372 }
373
374 return E1000_SUCCESS;
375 }
376
377 /**
378 * e1000_init_mac_params_82575 - Init MAC func ptrs.
379 * @hw: pointer to the HW structure
380 **/
381 static s32 e1000_init_mac_params_82575(struct e1000_hw *hw)
382 {
383 struct e1000_mac_info *mac = &hw->mac;
384 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
385
386 DEBUGFUNC("e1000_init_mac_params_82575");
387
388 /* Derives media type */
389 e1000_get_media_type_82575(hw);
390 /* Set mta register count */
391 mac->mta_reg_count = 128;
392 /* Set uta register count */
393 mac->uta_reg_count = (hw->mac.type == e1000_82575) ? 0 : 128;
394 /* Set rar entry count */
395 mac->rar_entry_count = E1000_RAR_ENTRIES_82575;
396 if (mac->type == e1000_82576)
397 mac->rar_entry_count = E1000_RAR_ENTRIES_82576;
398 if (mac->type == e1000_82580)
399 mac->rar_entry_count = E1000_RAR_ENTRIES_82580;
400 if (mac->type == e1000_i350 || mac->type == e1000_i354)
401 mac->rar_entry_count = E1000_RAR_ENTRIES_I350;
402
403 /* Enable EEE default settings for EEE supported devices */
404 if (mac->type >= e1000_i350)
405 dev_spec->eee_disable = false;
406
407 /* Allow a single clear of the SW semaphore on I210 and newer */
408 if (mac->type >= e1000_i210)
409 dev_spec->clear_semaphore_once = true;
410
411 /* Set if part includes ASF firmware */
412 mac->asf_firmware_present = true;
413 /* FWSM register */
414 mac->has_fwsm = true;
415 /* ARC supported; valid only if manageability features are enabled. */
416 mac->arc_subsystem_valid =
417 !!(E1000_READ_REG(hw, E1000_FWSM) & E1000_FWSM_MODE_MASK);
418
419 /* Function pointers */
420
421 /* bus type/speed/width */
422 mac->ops.get_bus_info = e1000_get_bus_info_pcie_generic;
423 /* reset */
424 if (mac->type >= e1000_82580)
425 mac->ops.reset_hw = e1000_reset_hw_82580;
426 else
427 mac->ops.reset_hw = e1000_reset_hw_82575;
428 /* hw initialization */
429 mac->ops.init_hw = e1000_init_hw_82575;
430 /* link setup */
431 mac->ops.setup_link = e1000_setup_link_generic;
432 /* physical interface link setup */
433 mac->ops.setup_physical_interface =
434 (hw->phy.media_type == e1000_media_type_copper)
435 ? e1000_setup_copper_link_82575 : e1000_setup_serdes_link_82575;
436 /* physical interface shutdown */
437 mac->ops.shutdown_serdes = e1000_shutdown_serdes_link_82575;
438 /* physical interface power up */
439 mac->ops.power_up_serdes = e1000_power_up_serdes_link_82575;
440 /* check for link */
441 mac->ops.check_for_link = e1000_check_for_link_82575;
442 /* read mac address */
443 mac->ops.read_mac_addr = e1000_read_mac_addr_82575;
444 /* configure collision distance */
445 mac->ops.config_collision_dist = e1000_config_collision_dist_82575;
446 /* multicast address update */
447 mac->ops.update_mc_addr_list = e1000_update_mc_addr_list_generic;
448 if (hw->mac.type == e1000_i350 || mac->type == e1000_i354) {
449 /* writing VFTA */
450 mac->ops.write_vfta = e1000_write_vfta_i350;
451 /* clearing VFTA */
452 mac->ops.clear_vfta = e1000_clear_vfta_i350;
453 } else {
454 /* writing VFTA */
455 mac->ops.write_vfta = e1000_write_vfta_generic;
456 /* clearing VFTA */
457 mac->ops.clear_vfta = e1000_clear_vfta_generic;
458 }
459 if (hw->mac.type >= e1000_82580)
460 mac->ops.validate_mdi_setting =
461 e1000_validate_mdi_setting_crossover_generic;
462 /* ID LED init */
463 mac->ops.id_led_init = e1000_id_led_init_generic;
464 /* blink LED */
465 mac->ops.blink_led = e1000_blink_led_generic;
466 /* setup LED */
467 mac->ops.setup_led = e1000_setup_led_generic;
468 /* cleanup LED */
469 mac->ops.cleanup_led = e1000_cleanup_led_generic;
470 /* turn on/off LED */
471 mac->ops.led_on = e1000_led_on_generic;
472 mac->ops.led_off = e1000_led_off_generic;
473 /* clear hardware counters */
474 mac->ops.clear_hw_cntrs = e1000_clear_hw_cntrs_82575;
475 /* link info */
476 mac->ops.get_link_up_info = e1000_get_link_up_info_82575;
477 /* get thermal sensor data */
478 mac->ops.get_thermal_sensor_data =
479 e1000_get_thermal_sensor_data_generic;
480 mac->ops.init_thermal_sensor_thresh =
481 e1000_init_thermal_sensor_thresh_generic;
482 /* acquire SW_FW sync */
483 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_82575;
484 mac->ops.release_swfw_sync = e1000_release_swfw_sync_82575;
485 if (mac->type >= e1000_i210) {
486 mac->ops.acquire_swfw_sync = e1000_acquire_swfw_sync_i210;
487 mac->ops.release_swfw_sync = e1000_release_swfw_sync_i210;
488 }
489
490 /* set lan id for port to determine which phy lock to use */
491 hw->mac.ops.set_lan_id(hw);
492
493 return E1000_SUCCESS;
494 }
495
496 /**
497 * e1000_init_function_pointers_82575 - Init func ptrs.
498 * @hw: pointer to the HW structure
499 *
500 * Called to initialize all function pointers and parameters.
501 **/
502 void e1000_init_function_pointers_82575(struct e1000_hw *hw)
503 {
504 DEBUGFUNC("e1000_init_function_pointers_82575");
505
506 hw->mac.ops.init_params = e1000_init_mac_params_82575;
507 hw->nvm.ops.init_params = e1000_init_nvm_params_82575;
508 hw->phy.ops.init_params = e1000_init_phy_params_82575;
509 hw->mbx.ops.init_params = e1000_init_mbx_params_pf;
510 }
511
512 /**
513 * e1000_acquire_phy_82575 - Acquire rights to access PHY
514 * @hw: pointer to the HW structure
515 *
516 * Acquire access rights to the correct PHY.
517 **/
518 static s32 e1000_acquire_phy_82575(struct e1000_hw *hw)
519 {
520 u16 mask = E1000_SWFW_PHY0_SM;
521
522 DEBUGFUNC("e1000_acquire_phy_82575");
523
524 if (hw->bus.func == E1000_FUNC_1)
525 mask = E1000_SWFW_PHY1_SM;
526 else if (hw->bus.func == E1000_FUNC_2)
527 mask = E1000_SWFW_PHY2_SM;
528 else if (hw->bus.func == E1000_FUNC_3)
529 mask = E1000_SWFW_PHY3_SM;
530
531 return hw->mac.ops.acquire_swfw_sync(hw, mask);
532 }
533
534 /**
535 * e1000_release_phy_82575 - Release rights to access PHY
536 * @hw: pointer to the HW structure
537 *
538 * A wrapper to release access rights to the correct PHY.
539 **/
540 static void e1000_release_phy_82575(struct e1000_hw *hw)
541 {
542 u16 mask = E1000_SWFW_PHY0_SM;
543
544 DEBUGFUNC("e1000_release_phy_82575");
545
546 if (hw->bus.func == E1000_FUNC_1)
547 mask = E1000_SWFW_PHY1_SM;
548 else if (hw->bus.func == E1000_FUNC_2)
549 mask = E1000_SWFW_PHY2_SM;
550 else if (hw->bus.func == E1000_FUNC_3)
551 mask = E1000_SWFW_PHY3_SM;
552
553 hw->mac.ops.release_swfw_sync(hw, mask);
554 }
555
556 /**
557 * e1000_read_phy_reg_sgmii_82575 - Read PHY register using sgmii
558 * @hw: pointer to the HW structure
559 * @offset: register offset to be read
560 * @data: pointer to the read data
561 *
562 * Reads the PHY register at offset using the serial gigabit media independent
563 * interface and stores the retrieved information in data.
564 **/
565 static s32 e1000_read_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
566 u16 *data)
567 {
568 s32 ret_val = -E1000_ERR_PARAM;
569
570 DEBUGFUNC("e1000_read_phy_reg_sgmii_82575");
571
572 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
573 DEBUGOUT1("PHY Address %u is out of range\n", offset);
574 goto out;
575 }
576
577 ret_val = hw->phy.ops.acquire(hw);
578 if (ret_val)
579 goto out;
580
581 ret_val = e1000_read_phy_reg_i2c(hw, offset, data);
582
583 hw->phy.ops.release(hw);
584
585 out:
586 return ret_val;
587 }
588
589 /**
590 * e1000_write_phy_reg_sgmii_82575 - Write PHY register using sgmii
591 * @hw: pointer to the HW structure
592 * @offset: register offset to write to
593 * @data: data to write at register offset
594 *
595 * Writes the data to PHY register at the offset using the serial gigabit
596 * media independent interface.
597 **/
598 static s32 e1000_write_phy_reg_sgmii_82575(struct e1000_hw *hw, u32 offset,
599 u16 data)
600 {
601 s32 ret_val = -E1000_ERR_PARAM;
602
603 DEBUGFUNC("e1000_write_phy_reg_sgmii_82575");
604
605 if (offset > E1000_MAX_SGMII_PHY_REG_ADDR) {
606 DEBUGOUT1("PHY Address %d is out of range\n", offset);
607 goto out;
608 }
609
610 ret_val = hw->phy.ops.acquire(hw);
611 if (ret_val)
612 goto out;
613
614 ret_val = e1000_write_phy_reg_i2c(hw, offset, data);
615
616 hw->phy.ops.release(hw);
617
618 out:
619 return ret_val;
620 }
621
622 /**
623 * e1000_get_phy_id_82575 - Retrieve PHY addr and id
624 * @hw: pointer to the HW structure
625 *
626 * Retrieves the PHY address and ID for both PHY's which do and do not use
627 * sgmi interface.
628 **/
629 static s32 e1000_get_phy_id_82575(struct e1000_hw *hw)
630 {
631 struct e1000_phy_info *phy = &hw->phy;
632 s32 ret_val = E1000_SUCCESS;
633 u16 phy_id;
634 u32 ctrl_ext;
635 u32 mdic;
636
637 DEBUGFUNC("e1000_get_phy_id_82575");
638
639 /* i354 devices can have a PHY that needs an extra read for id */
640 if (hw->mac.type == e1000_i354)
641 e1000_get_phy_id(hw);
642
643
644 /*
645 * For SGMII PHYs, we try the list of possible addresses until
646 * we find one that works. For non-SGMII PHYs
647 * (e.g. integrated copper PHYs), an address of 1 should
648 * work. The result of this function should mean phy->phy_addr
649 * and phy->id are set correctly.
650 */
651 if (!e1000_sgmii_active_82575(hw)) {
652 phy->addr = 1;
653 ret_val = e1000_get_phy_id(hw);
654 goto out;
655 }
656
657 if (e1000_sgmii_uses_mdio_82575(hw)) {
658 switch (hw->mac.type) {
659 case e1000_82575:
660 case e1000_82576:
661 mdic = E1000_READ_REG(hw, E1000_MDIC);
662 mdic &= E1000_MDIC_PHY_MASK;
663 phy->addr = mdic >> E1000_MDIC_PHY_SHIFT;
664 break;
665 case e1000_82580:
666 case e1000_i350:
667 case e1000_i354:
668 case e1000_i210:
669 case e1000_i211:
670 mdic = E1000_READ_REG(hw, E1000_MDICNFG);
671 mdic &= E1000_MDICNFG_PHY_MASK;
672 phy->addr = mdic >> E1000_MDICNFG_PHY_SHIFT;
673 break;
674 default:
675 ret_val = -E1000_ERR_PHY;
676 goto out;
677 break;
678 }
679 ret_val = e1000_get_phy_id(hw);
680 goto out;
681 }
682
683 /* Power on sgmii phy if it is disabled */
684 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
685 E1000_WRITE_REG(hw, E1000_CTRL_EXT,
686 ctrl_ext & ~E1000_CTRL_EXT_SDP3_DATA);
687 E1000_WRITE_FLUSH(hw);
688 msec_delay(300);
689
690 /*
691 * The address field in the I2CCMD register is 3 bits and 0 is invalid.
692 * Therefore, we need to test 1-7
693 */
694 for (phy->addr = 1; phy->addr < 8; phy->addr++) {
695 ret_val = e1000_read_phy_reg_sgmii_82575(hw, PHY_ID1, &phy_id);
696 if (ret_val == E1000_SUCCESS) {
697 DEBUGOUT2("Vendor ID 0x%08X read at address %u\n",
698 phy_id, phy->addr);
699 /*
700 * At the time of this writing, The M88 part is
701 * the only supported SGMII PHY product.
702 */
703 if (phy_id == M88_VENDOR)
704 break;
705 } else {
706 DEBUGOUT1("PHY address %u was unreadable\n",
707 phy->addr);
708 }
709 }
710
711 /* A valid PHY type couldn't be found. */
712 if (phy->addr == 8) {
713 phy->addr = 0;
714 ret_val = -E1000_ERR_PHY;
715 } else {
716 ret_val = e1000_get_phy_id(hw);
717 }
718
719 /* restore previous sfp cage power state */
720 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
721
722 out:
723 return ret_val;
724 }
725
726 /**
727 * e1000_phy_hw_reset_sgmii_82575 - Performs a PHY reset
728 * @hw: pointer to the HW structure
729 *
730 * Resets the PHY using the serial gigabit media independent interface.
731 **/
732 static s32 e1000_phy_hw_reset_sgmii_82575(struct e1000_hw *hw)
733 {
734 s32 ret_val = E1000_SUCCESS;
735
736 DEBUGFUNC("e1000_phy_hw_reset_sgmii_82575");
737
738 /*
739 * This isn't a true "hard" reset, but is the only reset
740 * available to us at this time.
741 */
742
743 DEBUGOUT("Soft resetting SGMII attached PHY...\n");
744
745 if (!(hw->phy.ops.write_reg))
746 goto out;
747
748 /*
749 * SFP documentation requires the following to configure the SPF module
750 * to work on SGMII. No further documentation is given.
751 */
752 ret_val = hw->phy.ops.write_reg(hw, 0x1B, 0x8084);
753 if (ret_val)
754 goto out;
755
756 ret_val = hw->phy.ops.commit(hw);
757
758 out:
759 return ret_val;
760 }
761
762 /**
763 * e1000_set_d0_lplu_state_82575 - Set Low Power Linkup D0 state
764 * @hw: pointer to the HW structure
765 * @active: true to enable LPLU, false to disable
766 *
767 * Sets the LPLU D0 state according to the active flag. When
768 * activating LPLU this function also disables smart speed
769 * and vice versa. LPLU will not be activated unless the
770 * device autonegotiation advertisement meets standards of
771 * either 10 or 10/100 or 10/100/1000 at all duplexes.
772 * This is a function pointer entry point only called by
773 * PHY setup routines.
774 **/
775 static s32 e1000_set_d0_lplu_state_82575(struct e1000_hw *hw, bool active)
776 {
777 struct e1000_phy_info *phy = &hw->phy;
778 s32 ret_val = E1000_SUCCESS;
779 u16 data;
780
781 DEBUGFUNC("e1000_set_d0_lplu_state_82575");
782
783 if (!(hw->phy.ops.read_reg))
784 goto out;
785
786 ret_val = phy->ops.read_reg(hw, IGP02E1000_PHY_POWER_MGMT, &data);
787 if (ret_val)
788 goto out;
789
790 if (active) {
791 data |= IGP02E1000_PM_D0_LPLU;
792 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
793 data);
794 if (ret_val)
795 goto out;
796
797 /* When LPLU is enabled, we should disable SmartSpeed */
798 ret_val = phy->ops.read_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
799 &data);
800 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
801 ret_val = phy->ops.write_reg(hw, IGP01E1000_PHY_PORT_CONFIG,
802 data);
803 if (ret_val)
804 goto out;
805 } else {
806 data &= ~IGP02E1000_PM_D0_LPLU;
807 ret_val = phy->ops.write_reg(hw, IGP02E1000_PHY_POWER_MGMT,
808 data);
809 /*
810 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
811 * during Dx states where the power conservation is most
812 * important. During driver activity we should enable
813 * SmartSpeed, so performance is maintained.
814 */
815 if (phy->smart_speed == e1000_smart_speed_on) {
816 ret_val = phy->ops.read_reg(hw,
817 IGP01E1000_PHY_PORT_CONFIG,
818 &data);
819 if (ret_val)
820 goto out;
821
822 data |= IGP01E1000_PSCFR_SMART_SPEED;
823 ret_val = phy->ops.write_reg(hw,
824 IGP01E1000_PHY_PORT_CONFIG,
825 data);
826 if (ret_val)
827 goto out;
828 } else if (phy->smart_speed == e1000_smart_speed_off) {
829 ret_val = phy->ops.read_reg(hw,
830 IGP01E1000_PHY_PORT_CONFIG,
831 &data);
832 if (ret_val)
833 goto out;
834
835 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
836 ret_val = phy->ops.write_reg(hw,
837 IGP01E1000_PHY_PORT_CONFIG,
838 data);
839 if (ret_val)
840 goto out;
841 }
842 }
843
844 out:
845 return ret_val;
846 }
847
848 /**
849 * e1000_set_d0_lplu_state_82580 - Set Low Power Linkup D0 state
850 * @hw: pointer to the HW structure
851 * @active: true to enable LPLU, false to disable
852 *
853 * Sets the LPLU D0 state according to the active flag. When
854 * activating LPLU this function also disables smart speed
855 * and vice versa. LPLU will not be activated unless the
856 * device autonegotiation advertisement meets standards of
857 * either 10 or 10/100 or 10/100/1000 at all duplexes.
858 * This is a function pointer entry point only called by
859 * PHY setup routines.
860 **/
861 static s32 e1000_set_d0_lplu_state_82580(struct e1000_hw *hw, bool active)
862 {
863 struct e1000_phy_info *phy = &hw->phy;
864 s32 ret_val = E1000_SUCCESS;
865 u32 data;
866
867 DEBUGFUNC("e1000_set_d0_lplu_state_82580");
868
869 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
870
871 if (active) {
872 data |= E1000_82580_PM_D0_LPLU;
873
874 /* When LPLU is enabled, we should disable SmartSpeed */
875 data &= ~E1000_82580_PM_SPD;
876 } else {
877 data &= ~E1000_82580_PM_D0_LPLU;
878
879 /*
880 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
881 * during Dx states where the power conservation is most
882 * important. During driver activity we should enable
883 * SmartSpeed, so performance is maintained.
884 */
885 if (phy->smart_speed == e1000_smart_speed_on)
886 data |= E1000_82580_PM_SPD;
887 else if (phy->smart_speed == e1000_smart_speed_off)
888 data &= ~E1000_82580_PM_SPD;
889 }
890
891 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
892 return ret_val;
893 }
894
895 /**
896 * e1000_set_d3_lplu_state_82580 - Sets low power link up state for D3
897 * @hw: pointer to the HW structure
898 * @active: boolean used to enable/disable lplu
899 *
900 * Success returns 0, Failure returns 1
901 *
902 * The low power link up (lplu) state is set to the power management level D3
903 * and SmartSpeed is disabled when active is true, else clear lplu for D3
904 * and enable Smartspeed. LPLU and Smartspeed are mutually exclusive. LPLU
905 * is used during Dx states where the power conservation is most important.
906 * During driver activity, SmartSpeed should be enabled so performance is
907 * maintained.
908 **/
909 s32 e1000_set_d3_lplu_state_82580(struct e1000_hw *hw, bool active)
910 {
911 struct e1000_phy_info *phy = &hw->phy;
912 s32 ret_val = E1000_SUCCESS;
913 u32 data;
914
915 DEBUGFUNC("e1000_set_d3_lplu_state_82580");
916
917 data = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
918
919 if (!active) {
920 data &= ~E1000_82580_PM_D3_LPLU;
921 /*
922 * LPLU and SmartSpeed are mutually exclusive. LPLU is used
923 * during Dx states where the power conservation is most
924 * important. During driver activity we should enable
925 * SmartSpeed, so performance is maintained.
926 */
927 if (phy->smart_speed == e1000_smart_speed_on)
928 data |= E1000_82580_PM_SPD;
929 else if (phy->smart_speed == e1000_smart_speed_off)
930 data &= ~E1000_82580_PM_SPD;
931 } else if ((phy->autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
932 (phy->autoneg_advertised == E1000_ALL_NOT_GIG) ||
933 (phy->autoneg_advertised == E1000_ALL_10_SPEED)) {
934 data |= E1000_82580_PM_D3_LPLU;
935 /* When LPLU is enabled, we should disable SmartSpeed */
936 data &= ~E1000_82580_PM_SPD;
937 }
938
939 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, data);
940 return ret_val;
941 }
942
943 /**
944 * e1000_acquire_nvm_82575 - Request for access to EEPROM
945 * @hw: pointer to the HW structure
946 *
947 * Acquire the necessary semaphores for exclusive access to the EEPROM.
948 * Set the EEPROM access request bit and wait for EEPROM access grant bit.
949 * Return successful if access grant bit set, else clear the request for
950 * EEPROM access and return -E1000_ERR_NVM (-1).
951 **/
952 static s32 e1000_acquire_nvm_82575(struct e1000_hw *hw)
953 {
954 s32 ret_val;
955
956 DEBUGFUNC("e1000_acquire_nvm_82575");
957
958 ret_val = e1000_acquire_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
959 if (ret_val)
960 goto out;
961
962 /*
963 * Check if there is some access
964 * error this access may hook on
965 */
966 if (hw->mac.type == e1000_i350) {
967 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
968 if (eecd & (E1000_EECD_BLOCKED | E1000_EECD_ABORT |
969 E1000_EECD_TIMEOUT)) {
970 /* Clear all access error flags */
971 E1000_WRITE_REG(hw, E1000_EECD, eecd |
972 E1000_EECD_ERROR_CLR);
973 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
974 }
975 }
976 if (hw->mac.type == e1000_82580) {
977 u32 eecd = E1000_READ_REG(hw, E1000_EECD);
978 if (eecd & E1000_EECD_BLOCKED) {
979 /* Clear access error flag */
980 E1000_WRITE_REG(hw, E1000_EECD, eecd |
981 E1000_EECD_BLOCKED);
982 DEBUGOUT("Nvm bit banging access error detected and cleared.\n");
983 }
984 }
985
986
987 ret_val = e1000_acquire_nvm_generic(hw);
988 if (ret_val)
989 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
990
991 out:
992 return ret_val;
993 }
994
995 /**
996 * e1000_release_nvm_82575 - Release exclusive access to EEPROM
997 * @hw: pointer to the HW structure
998 *
999 * Stop any current commands to the EEPROM and clear the EEPROM request bit,
1000 * then release the semaphores acquired.
1001 **/
1002 static void e1000_release_nvm_82575(struct e1000_hw *hw)
1003 {
1004 DEBUGFUNC("e1000_release_nvm_82575");
1005
1006 e1000_release_nvm_generic(hw);
1007
1008 e1000_release_swfw_sync_82575(hw, E1000_SWFW_EEP_SM);
1009 }
1010
1011 /**
1012 * e1000_acquire_swfw_sync_82575 - Acquire SW/FW semaphore
1013 * @hw: pointer to the HW structure
1014 * @mask: specifies which semaphore to acquire
1015 *
1016 * Acquire the SW/FW semaphore to access the PHY or NVM. The mask
1017 * will also specify which port we're acquiring the lock for.
1018 **/
1019 static s32 e1000_acquire_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1020 {
1021 u32 swfw_sync;
1022 u32 swmask = mask;
1023 u32 fwmask = mask << 16;
1024 s32 ret_val = E1000_SUCCESS;
1025 s32 i = 0, timeout = 200; /* FIXME: find real value to use here */
1026
1027 DEBUGFUNC("e1000_acquire_swfw_sync_82575");
1028
1029 while (i < timeout) {
1030 if (e1000_get_hw_semaphore_generic(hw)) {
1031 ret_val = -E1000_ERR_SWFW_SYNC;
1032 goto out;
1033 }
1034
1035 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1036 if (!(swfw_sync & (fwmask | swmask)))
1037 break;
1038
1039 /*
1040 * Firmware currently using resource (fwmask)
1041 * or other software thread using resource (swmask)
1042 */
1043 e1000_put_hw_semaphore_generic(hw);
1044 msec_delay_irq(5);
1045 i++;
1046 }
1047
1048 if (i == timeout) {
1049 DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
1050 ret_val = -E1000_ERR_SWFW_SYNC;
1051 goto out;
1052 }
1053
1054 swfw_sync |= swmask;
1055 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1056
1057 e1000_put_hw_semaphore_generic(hw);
1058
1059 out:
1060 return ret_val;
1061 }
1062
1063 /**
1064 * e1000_release_swfw_sync_82575 - Release SW/FW semaphore
1065 * @hw: pointer to the HW structure
1066 * @mask: specifies which semaphore to acquire
1067 *
1068 * Release the SW/FW semaphore used to access the PHY or NVM. The mask
1069 * will also specify which port we're releasing the lock for.
1070 **/
1071 static void e1000_release_swfw_sync_82575(struct e1000_hw *hw, u16 mask)
1072 {
1073 u32 swfw_sync;
1074
1075 DEBUGFUNC("e1000_release_swfw_sync_82575");
1076
1077 while (e1000_get_hw_semaphore_generic(hw) != E1000_SUCCESS)
1078 ; /* Empty */
1079
1080 swfw_sync = E1000_READ_REG(hw, E1000_SW_FW_SYNC);
1081 swfw_sync &= ~mask;
1082 E1000_WRITE_REG(hw, E1000_SW_FW_SYNC, swfw_sync);
1083
1084 e1000_put_hw_semaphore_generic(hw);
1085 }
1086
1087 /**
1088 * e1000_get_cfg_done_82575 - Read config done bit
1089 * @hw: pointer to the HW structure
1090 *
1091 * Read the management control register for the config done bit for
1092 * completion status. NOTE: silicon which is EEPROM-less will fail trying
1093 * to read the config done bit, so an error is *ONLY* logged and returns
1094 * E1000_SUCCESS. If we were to return with error, EEPROM-less silicon
1095 * would not be able to be reset or change link.
1096 **/
1097 static s32 e1000_get_cfg_done_82575(struct e1000_hw *hw)
1098 {
1099 s32 timeout = PHY_CFG_TIMEOUT;
1100 s32 ret_val = E1000_SUCCESS;
1101 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
1102
1103 DEBUGFUNC("e1000_get_cfg_done_82575");
1104
1105 if (hw->bus.func == E1000_FUNC_1)
1106 mask = E1000_NVM_CFG_DONE_PORT_1;
1107 else if (hw->bus.func == E1000_FUNC_2)
1108 mask = E1000_NVM_CFG_DONE_PORT_2;
1109 else if (hw->bus.func == E1000_FUNC_3)
1110 mask = E1000_NVM_CFG_DONE_PORT_3;
1111 while (timeout) {
1112 if (E1000_READ_REG(hw, E1000_EEMNGCTL) & mask)
1113 break;
1114 msec_delay(1);
1115 timeout--;
1116 }
1117 if (!timeout)
1118 DEBUGOUT("MNG configuration cycle has not completed.\n");
1119
1120 /* If EEPROM is not marked present, init the PHY manually */
1121 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES) &&
1122 (hw->phy.type == e1000_phy_igp_3))
1123 e1000_phy_init_script_igp3(hw);
1124
1125 return ret_val;
1126 }
1127
1128 /**
1129 * e1000_get_link_up_info_82575 - Get link speed/duplex info
1130 * @hw: pointer to the HW structure
1131 * @speed: stores the current speed
1132 * @duplex: stores the current duplex
1133 *
1134 * This is a wrapper function, if using the serial gigabit media independent
1135 * interface, use PCS to retrieve the link speed and duplex information.
1136 * Otherwise, use the generic function to get the link speed and duplex info.
1137 **/
1138 static s32 e1000_get_link_up_info_82575(struct e1000_hw *hw, u16 *speed,
1139 u16 *duplex)
1140 {
1141 s32 ret_val;
1142
1143 DEBUGFUNC("e1000_get_link_up_info_82575");
1144
1145 if (hw->phy.media_type != e1000_media_type_copper)
1146 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, speed,
1147 duplex);
1148 else
1149 ret_val = e1000_get_speed_and_duplex_copper_generic(hw, speed,
1150 duplex);
1151
1152 return ret_val;
1153 }
1154
1155 /**
1156 * e1000_check_for_link_82575 - Check for link
1157 * @hw: pointer to the HW structure
1158 *
1159 * If sgmii is enabled, then use the pcs register to determine link, otherwise
1160 * use the generic interface for determining link.
1161 **/
1162 static s32 e1000_check_for_link_82575(struct e1000_hw *hw)
1163 {
1164 s32 ret_val;
1165 u16 speed, duplex;
1166
1167 DEBUGFUNC("e1000_check_for_link_82575");
1168
1169 if (hw->phy.media_type != e1000_media_type_copper) {
1170 ret_val = e1000_get_pcs_speed_and_duplex_82575(hw, &speed,
1171 &duplex);
1172 /*
1173 * Use this flag to determine if link needs to be checked or
1174 * not. If we have link clear the flag so that we do not
1175 * continue to check for link.
1176 */
1177 hw->mac.get_link_status = !hw->mac.serdes_has_link;
1178
1179 /*
1180 * Configure Flow Control now that Auto-Neg has completed.
1181 * First, we need to restore the desired flow control
1182 * settings because we may have had to re-autoneg with a
1183 * different link partner.
1184 */
1185 ret_val = e1000_config_fc_after_link_up_generic(hw);
1186 if (ret_val)
1187 DEBUGOUT("Error configuring flow control\n");
1188 } else {
1189 ret_val = e1000_check_for_copper_link_generic(hw);
1190 }
1191
1192 return ret_val;
1193 }
1194
1195 /**
1196 * e1000_check_for_link_media_swap - Check which M88E1112 interface linked
1197 * @hw: pointer to the HW structure
1198 *
1199 * Poll the M88E1112 interfaces to see which interface achieved link.
1200 */
1201 static s32 e1000_check_for_link_media_swap(struct e1000_hw *hw)
1202 {
1203 struct e1000_phy_info *phy = &hw->phy;
1204 s32 ret_val;
1205 u16 data;
1206 u8 port = 0;
1207
1208 DEBUGFUNC("e1000_check_for_link_media_swap");
1209
1210 /* Check the copper medium. */
1211 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 0);
1212 if (ret_val)
1213 return ret_val;
1214
1215 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1216 if (ret_val)
1217 return ret_val;
1218
1219 if (data & E1000_M88E1112_STATUS_LINK)
1220 port = E1000_MEDIA_PORT_COPPER;
1221
1222 /* Check the other medium. */
1223 ret_val = phy->ops.write_reg(hw, E1000_M88E1112_PAGE_ADDR, 1);
1224 if (ret_val)
1225 return ret_val;
1226
1227 ret_val = phy->ops.read_reg(hw, E1000_M88E1112_STATUS, &data);
1228 if (ret_val)
1229 return ret_val;
1230
1231 if (data & E1000_M88E1112_STATUS_LINK)
1232 port = E1000_MEDIA_PORT_OTHER;
1233
1234 /* Determine if a swap needs to happen. */
1235 if (port && (hw->dev_spec._82575.media_port != port)) {
1236 hw->dev_spec._82575.media_port = port;
1237 hw->dev_spec._82575.media_changed = true;
1238 } else {
1239 ret_val = e1000_check_for_link_82575(hw);
1240 }
1241
1242 return E1000_SUCCESS;
1243 }
1244
1245 /**
1246 * e1000_power_up_serdes_link_82575 - Power up the serdes link after shutdown
1247 * @hw: pointer to the HW structure
1248 **/
1249 static void e1000_power_up_serdes_link_82575(struct e1000_hw *hw)
1250 {
1251 u32 reg;
1252
1253 DEBUGFUNC("e1000_power_up_serdes_link_82575");
1254
1255 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1256 !e1000_sgmii_active_82575(hw))
1257 return;
1258
1259 /* Enable PCS to turn on link */
1260 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1261 reg |= E1000_PCS_CFG_PCS_EN;
1262 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1263
1264 /* Power up the laser */
1265 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1266 reg &= ~E1000_CTRL_EXT_SDP3_DATA;
1267 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1268
1269 /* flush the write to verify completion */
1270 E1000_WRITE_FLUSH(hw);
1271 msec_delay(1);
1272 }
1273
1274 /**
1275 * e1000_get_pcs_speed_and_duplex_82575 - Retrieve current speed/duplex
1276 * @hw: pointer to the HW structure
1277 * @speed: stores the current speed
1278 * @duplex: stores the current duplex
1279 *
1280 * Using the physical coding sub-layer (PCS), retrieve the current speed and
1281 * duplex, then store the values in the pointers provided.
1282 **/
1283 static s32 e1000_get_pcs_speed_and_duplex_82575(struct e1000_hw *hw,
1284 u16 *speed, u16 *duplex)
1285 {
1286 struct e1000_mac_info *mac = &hw->mac;
1287 u32 pcs;
1288 u32 status;
1289
1290 DEBUGFUNC("e1000_get_pcs_speed_and_duplex_82575");
1291
1292 /*
1293 * Read the PCS Status register for link state. For non-copper mode,
1294 * the status register is not accurate. The PCS status register is
1295 * used instead.
1296 */
1297 pcs = E1000_READ_REG(hw, E1000_PCS_LSTAT);
1298
1299 /*
1300 * The link up bit determines when link is up on autoneg.
1301 */
1302 if (pcs & E1000_PCS_LSTS_LINK_OK) {
1303 mac->serdes_has_link = true;
1304
1305 /* Detect and store PCS speed */
1306 if (pcs & E1000_PCS_LSTS_SPEED_1000)
1307 *speed = SPEED_1000;
1308 else if (pcs & E1000_PCS_LSTS_SPEED_100)
1309 *speed = SPEED_100;
1310 else
1311 *speed = SPEED_10;
1312
1313 /* Detect and store PCS duplex */
1314 if (pcs & E1000_PCS_LSTS_DUPLEX_FULL)
1315 *duplex = FULL_DUPLEX;
1316 else
1317 *duplex = HALF_DUPLEX;
1318
1319 /* Check if it is an I354 2.5Gb backplane connection. */
1320 if (mac->type == e1000_i354) {
1321 status = E1000_READ_REG(hw, E1000_STATUS);
1322 if ((status & E1000_STATUS_2P5_SKU) &&
1323 !(status & E1000_STATUS_2P5_SKU_OVER)) {
1324 *speed = SPEED_2500;
1325 *duplex = FULL_DUPLEX;
1326 DEBUGOUT("2500 Mbs, ");
1327 DEBUGOUT("Full Duplex\n");
1328 }
1329 }
1330
1331 } else {
1332 mac->serdes_has_link = false;
1333 *speed = 0;
1334 *duplex = 0;
1335 }
1336
1337 return E1000_SUCCESS;
1338 }
1339
1340 /**
1341 * e1000_shutdown_serdes_link_82575 - Remove link during power down
1342 * @hw: pointer to the HW structure
1343 *
1344 * In the case of serdes shut down sfp and PCS on driver unload
1345 * when management pass through is not enabled.
1346 **/
1347 void e1000_shutdown_serdes_link_82575(struct e1000_hw *hw)
1348 {
1349 u32 reg;
1350
1351 DEBUGFUNC("e1000_shutdown_serdes_link_82575");
1352
1353 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1354 !e1000_sgmii_active_82575(hw))
1355 return;
1356
1357 if (!e1000_enable_mng_pass_thru(hw)) {
1358 /* Disable PCS to turn off link */
1359 reg = E1000_READ_REG(hw, E1000_PCS_CFG0);
1360 reg &= ~E1000_PCS_CFG_PCS_EN;
1361 E1000_WRITE_REG(hw, E1000_PCS_CFG0, reg);
1362
1363 /* shutdown the laser */
1364 reg = E1000_READ_REG(hw, E1000_CTRL_EXT);
1365 reg |= E1000_CTRL_EXT_SDP3_DATA;
1366 E1000_WRITE_REG(hw, E1000_CTRL_EXT, reg);
1367
1368 /* flush the write to verify completion */
1369 E1000_WRITE_FLUSH(hw);
1370 msec_delay(1);
1371 }
1372
1373 return;
1374 }
1375
1376 /**
1377 * e1000_reset_hw_82575 - Reset hardware
1378 * @hw: pointer to the HW structure
1379 *
1380 * This resets the hardware into a known state.
1381 **/
1382 static s32 e1000_reset_hw_82575(struct e1000_hw *hw)
1383 {
1384 u32 ctrl;
1385 s32 ret_val;
1386
1387 DEBUGFUNC("e1000_reset_hw_82575");
1388
1389 /*
1390 * Prevent the PCI-E bus from sticking if there is no TLP connection
1391 * on the last TLP read/write transaction when MAC is reset.
1392 */
1393 ret_val = e1000_disable_pcie_master_generic(hw);
1394 if (ret_val)
1395 DEBUGOUT("PCI-E Master disable polling has failed.\n");
1396
1397 /* set the completion timeout for interface */
1398 ret_val = e1000_set_pcie_completion_timeout(hw);
1399 if (ret_val)
1400 DEBUGOUT("PCI-E Set completion timeout has failed.\n");
1401
1402 DEBUGOUT("Masking off all interrupts\n");
1403 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1404
1405 E1000_WRITE_REG(hw, E1000_RCTL, 0);
1406 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
1407 E1000_WRITE_FLUSH(hw);
1408
1409 msec_delay(10);
1410
1411 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1412
1413 DEBUGOUT("Issuing a global reset to MAC\n");
1414 E1000_WRITE_REG(hw, E1000_CTRL, ctrl | E1000_CTRL_RST);
1415
1416 ret_val = e1000_get_auto_rd_done_generic(hw);
1417 if (ret_val) {
1418 /*
1419 * When auto config read does not complete, do not
1420 * return with an error. This can happen in situations
1421 * where there is no eeprom and prevents getting link.
1422 */
1423 DEBUGOUT("Auto Read Done did not complete\n");
1424 }
1425
1426 /* If EEPROM is not present, run manual init scripts */
1427 if (!(E1000_READ_REG(hw, E1000_EECD) & E1000_EECD_PRES))
1428 e1000_reset_init_script_82575(hw);
1429
1430 /* Clear any pending interrupt events. */
1431 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
1432 E1000_READ_REG(hw, E1000_ICR);
1433
1434 /* Install any alternate MAC address into RAR0 */
1435 ret_val = e1000_check_alt_mac_addr_generic(hw);
1436
1437 return ret_val;
1438 }
1439
1440 /**
1441 * e1000_init_hw_82575 - Initialize hardware
1442 * @hw: pointer to the HW structure
1443 *
1444 * This inits the hardware readying it for operation.
1445 **/
1446 static s32 e1000_init_hw_82575(struct e1000_hw *hw)
1447 {
1448 struct e1000_mac_info *mac = &hw->mac;
1449 s32 ret_val;
1450 u16 i, rar_count = mac->rar_entry_count;
1451
1452 DEBUGFUNC("e1000_init_hw_82575");
1453
1454 /* Initialize identification LED */
1455 ret_val = mac->ops.id_led_init(hw);
1456 if (ret_val) {
1457 DEBUGOUT("Error initializing identification LED\n");
1458 /* This is not fatal and we should not stop init due to this */
1459 }
1460
1461 /* Disabling VLAN filtering */
1462 DEBUGOUT("Initializing the IEEE VLAN\n");
1463 mac->ops.clear_vfta(hw);
1464
1465 /* Setup the receive address */
1466 e1000_init_rx_addrs_generic(hw, rar_count);
1467
1468 /* Zero out the Multicast HASH table */
1469 DEBUGOUT("Zeroing the MTA\n");
1470 for (i = 0; i < mac->mta_reg_count; i++)
1471 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1472
1473 /* Zero out the Unicast HASH table */
1474 DEBUGOUT("Zeroing the UTA\n");
1475 for (i = 0; i < mac->uta_reg_count; i++)
1476 E1000_WRITE_REG_ARRAY(hw, E1000_UTA, i, 0);
1477
1478 /* Setup link and flow control */
1479 ret_val = mac->ops.setup_link(hw);
1480
1481 /* Set the default MTU size */
1482 hw->dev_spec._82575.mtu = 1500;
1483
1484 /*
1485 * Clear all of the statistics registers (clear on read). It is
1486 * important that we do this after we have tried to establish link
1487 * because the symbol error count will increment wildly if there
1488 * is no link.
1489 */
1490 e1000_clear_hw_cntrs_82575(hw);
1491
1492 return ret_val;
1493 }
1494
1495 /**
1496 * e1000_setup_copper_link_82575 - Configure copper link settings
1497 * @hw: pointer to the HW structure
1498 *
1499 * Configures the link for auto-neg or forced speed and duplex. Then we check
1500 * for link, once link is established calls to configure collision distance
1501 * and flow control are called.
1502 **/
1503 static s32 e1000_setup_copper_link_82575(struct e1000_hw *hw)
1504 {
1505 u32 ctrl;
1506 s32 ret_val;
1507 u32 phpm_reg;
1508
1509 DEBUGFUNC("e1000_setup_copper_link_82575");
1510
1511 ctrl = E1000_READ_REG(hw, E1000_CTRL);
1512 ctrl |= E1000_CTRL_SLU;
1513 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1514 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
1515
1516 /* Clear Go Link Disconnect bit on supported devices */
1517 switch (hw->mac.type) {
1518 case e1000_82580:
1519 case e1000_i350:
1520 case e1000_i210:
1521 case e1000_i211:
1522 phpm_reg = E1000_READ_REG(hw, E1000_82580_PHY_POWER_MGMT);
1523 phpm_reg &= ~E1000_82580_PM_GO_LINKD;
1524 E1000_WRITE_REG(hw, E1000_82580_PHY_POWER_MGMT, phpm_reg);
1525 break;
1526 default:
1527 break;
1528 }
1529
1530 ret_val = e1000_setup_serdes_link_82575(hw);
1531 if (ret_val)
1532 goto out;
1533
1534 if (e1000_sgmii_active_82575(hw) && !hw->phy.reset_disable) {
1535 /* allow time for SFP cage time to power up phy */
1536 msec_delay(300);
1537
1538 ret_val = hw->phy.ops.reset(hw);
1539 if (ret_val) {
1540 DEBUGOUT("Error resetting the PHY.\n");
1541 goto out;
1542 }
1543 }
1544 switch (hw->phy.type) {
1545 case e1000_phy_i210:
1546 case e1000_phy_m88:
1547 switch (hw->phy.id) {
1548 case I347AT4_E_PHY_ID:
1549 case M88E1112_E_PHY_ID:
1550 case M88E1340M_E_PHY_ID:
1551 case M88E1543_E_PHY_ID:
1552 case I210_I_PHY_ID:
1553 ret_val = e1000_copper_link_setup_m88_gen2(hw);
1554 break;
1555 default:
1556 ret_val = e1000_copper_link_setup_m88(hw);
1557 break;
1558 }
1559 break;
1560 case e1000_phy_igp_3:
1561 ret_val = e1000_copper_link_setup_igp(hw);
1562 break;
1563 case e1000_phy_82580:
1564 ret_val = e1000_copper_link_setup_82577(hw);
1565 break;
1566 default:
1567 ret_val = -E1000_ERR_PHY;
1568 break;
1569 }
1570
1571 if (ret_val)
1572 goto out;
1573
1574 ret_val = e1000_setup_copper_link_generic(hw);
1575 out:
1576 return ret_val;
1577 }
1578
1579 /**
1580 * e1000_setup_serdes_link_82575 - Setup link for serdes
1581 * @hw: pointer to the HW structure
1582 *
1583 * Configure the physical coding sub-layer (PCS) link. The PCS link is
1584 * used on copper connections where the serialized gigabit media independent
1585 * interface (sgmii), or serdes fiber is being used. Configures the link
1586 * for auto-negotiation or forces speed/duplex.
1587 **/
1588 static s32 e1000_setup_serdes_link_82575(struct e1000_hw *hw)
1589 {
1590 u32 ctrl_ext, ctrl_reg, reg, anadv_reg;
1591 bool pcs_autoneg;
1592 s32 ret_val = E1000_SUCCESS;
1593 u16 data;
1594
1595 DEBUGFUNC("e1000_setup_serdes_link_82575");
1596
1597 if ((hw->phy.media_type != e1000_media_type_internal_serdes) &&
1598 !e1000_sgmii_active_82575(hw))
1599 return ret_val;
1600
1601 /*
1602 * On the 82575, SerDes loopback mode persists until it is
1603 * explicitly turned off or a power cycle is performed. A read to
1604 * the register does not indicate its status. Therefore, we ensure
1605 * loopback mode is disabled during initialization.
1606 */
1607 E1000_WRITE_REG(hw, E1000_SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1608
1609 /* power on the sfp cage if present */
1610 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1611 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1612 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1613
1614 ctrl_reg = E1000_READ_REG(hw, E1000_CTRL);
1615 ctrl_reg |= E1000_CTRL_SLU;
1616
1617 /* set both sw defined pins on 82575/82576*/
1618 if (hw->mac.type == e1000_82575 || hw->mac.type == e1000_82576)
1619 ctrl_reg |= E1000_CTRL_SWDPIN0 | E1000_CTRL_SWDPIN1;
1620
1621 reg = E1000_READ_REG(hw, E1000_PCS_LCTL);
1622
1623 /* default pcs_autoneg to the same setting as mac autoneg */
1624 pcs_autoneg = hw->mac.autoneg;
1625
1626 switch (ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK) {
1627 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1628 /* sgmii mode lets the phy handle forcing speed/duplex */
1629 pcs_autoneg = true;
1630 /* autoneg time out should be disabled for SGMII mode */
1631 reg &= ~(E1000_PCS_LCTL_AN_TIMEOUT);
1632 break;
1633 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1634 /* disable PCS autoneg and support parallel detect only */
1635 pcs_autoneg = false;
1636 /* fall through to default case */
1637 default:
1638 if (hw->mac.type == e1000_82575 ||
1639 hw->mac.type == e1000_82576) {
1640 ret_val = hw->nvm.ops.read(hw, NVM_COMPAT, 1, &data);
1641 if (ret_val) {
1642 DEBUGOUT("NVM Read Error\n");
1643 return ret_val;
1644 }
1645
1646 if (data & E1000_EEPROM_PCS_AUTONEG_DISABLE_BIT)
1647 pcs_autoneg = false;
1648 }
1649
1650 /*
1651 * non-SGMII modes only supports a speed of 1000/Full for the
1652 * link so it is best to just force the MAC and let the pcs
1653 * link either autoneg or be forced to 1000/Full
1654 */
1655 ctrl_reg |= E1000_CTRL_SPD_1000 | E1000_CTRL_FRCSPD |
1656 E1000_CTRL_FD | E1000_CTRL_FRCDPX;
1657
1658 /* set speed of 1000/Full if speed/duplex is forced */
1659 reg |= E1000_PCS_LCTL_FSV_1000 | E1000_PCS_LCTL_FDV_FULL;
1660 break;
1661 }
1662
1663 E1000_WRITE_REG(hw, E1000_CTRL, ctrl_reg);
1664
1665 /*
1666 * New SerDes mode allows for forcing speed or autonegotiating speed
1667 * at 1gb. Autoneg should be default set by most drivers. This is the
1668 * mode that will be compatible with older link partners and switches.
1669 * However, both are supported by the hardware and some drivers/tools.
1670 */
1671 reg &= ~(E1000_PCS_LCTL_AN_ENABLE | E1000_PCS_LCTL_FLV_LINK_UP |
1672 E1000_PCS_LCTL_FSD | E1000_PCS_LCTL_FORCE_LINK);
1673
1674 if (pcs_autoneg) {
1675 /* Set PCS register for autoneg */
1676 reg |= E1000_PCS_LCTL_AN_ENABLE | /* Enable Autoneg */
1677 E1000_PCS_LCTL_AN_RESTART; /* Restart autoneg */
1678
1679 /* Disable force flow control for autoneg */
1680 reg &= ~E1000_PCS_LCTL_FORCE_FCTRL;
1681
1682 /* Configure flow control advertisement for autoneg */
1683 anadv_reg = E1000_READ_REG(hw, E1000_PCS_ANADV);
1684 anadv_reg &= ~(E1000_TXCW_ASM_DIR | E1000_TXCW_PAUSE);
1685
1686 switch (hw->fc.requested_mode) {
1687 case e1000_fc_full:
1688 case e1000_fc_rx_pause:
1689 anadv_reg |= E1000_TXCW_ASM_DIR;
1690 anadv_reg |= E1000_TXCW_PAUSE;
1691 break;
1692 case e1000_fc_tx_pause:
1693 anadv_reg |= E1000_TXCW_ASM_DIR;
1694 break;
1695 default:
1696 break;
1697 }
1698
1699 E1000_WRITE_REG(hw, E1000_PCS_ANADV, anadv_reg);
1700
1701 DEBUGOUT1("Configuring Autoneg:PCS_LCTL=0x%08X\n", reg);
1702 } else {
1703 /* Set PCS register for forced link */
1704 reg |= E1000_PCS_LCTL_FSD; /* Force Speed */
1705
1706 /* Force flow control for forced link */
1707 reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1708
1709 DEBUGOUT1("Configuring Forced Link:PCS_LCTL=0x%08X\n", reg);
1710 }
1711
1712 E1000_WRITE_REG(hw, E1000_PCS_LCTL, reg);
1713
1714 if (!pcs_autoneg && !e1000_sgmii_active_82575(hw))
1715 e1000_force_mac_fc_generic(hw);
1716
1717 return ret_val;
1718 }
1719
1720 /**
1721 * e1000_get_media_type_82575 - derives current media type.
1722 * @hw: pointer to the HW structure
1723 *
1724 * The media type is chosen reflecting few settings.
1725 * The following are taken into account:
1726 * - link mode set in the current port Init Control Word #3
1727 * - current link mode settings in CSR register
1728 * - MDIO vs. I2C PHY control interface chosen
1729 * - SFP module media type
1730 **/
1731 static s32 e1000_get_media_type_82575(struct e1000_hw *hw)
1732 {
1733 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1734 s32 ret_val = E1000_SUCCESS;
1735 u32 ctrl_ext = 0;
1736 u32 link_mode = 0;
1737
1738 /* Set internal phy as default */
1739 dev_spec->sgmii_active = false;
1740 dev_spec->module_plugged = false;
1741
1742 /* Get CSR setting */
1743 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1744
1745 /* extract link mode setting */
1746 link_mode = ctrl_ext & E1000_CTRL_EXT_LINK_MODE_MASK;
1747
1748 switch (link_mode) {
1749 case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX:
1750 hw->phy.media_type = e1000_media_type_internal_serdes;
1751 break;
1752 case E1000_CTRL_EXT_LINK_MODE_GMII:
1753 hw->phy.media_type = e1000_media_type_copper;
1754 break;
1755 case E1000_CTRL_EXT_LINK_MODE_SGMII:
1756 /* Get phy control interface type set (MDIO vs. I2C)*/
1757 if (e1000_sgmii_uses_mdio_82575(hw)) {
1758 hw->phy.media_type = e1000_media_type_copper;
1759 dev_spec->sgmii_active = true;
1760 break;
1761 }
1762 /* fall through for I2C based SGMII */
1763 case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES:
1764 /* read media type from SFP EEPROM */
1765 ret_val = e1000_set_sfp_media_type_82575(hw);
1766 if ((ret_val != E1000_SUCCESS) ||
1767 (hw->phy.media_type == e1000_media_type_unknown)) {
1768 /*
1769 * If media type was not identified then return media
1770 * type defined by the CTRL_EXT settings.
1771 */
1772 hw->phy.media_type = e1000_media_type_internal_serdes;
1773
1774 if (link_mode == E1000_CTRL_EXT_LINK_MODE_SGMII) {
1775 hw->phy.media_type = e1000_media_type_copper;
1776 dev_spec->sgmii_active = true;
1777 }
1778
1779 break;
1780 }
1781
1782 /* do not change link mode for 100BaseFX */
1783 if (dev_spec->eth_flags.e100_base_fx)
1784 break;
1785
1786 /* change current link mode setting */
1787 ctrl_ext &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
1788
1789 if (hw->phy.media_type == e1000_media_type_copper)
1790 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_SGMII;
1791 else
1792 ctrl_ext |= E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES;
1793
1794 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1795
1796 break;
1797 }
1798
1799 return ret_val;
1800 }
1801
1802 /**
1803 * e1000_set_sfp_media_type_82575 - derives SFP module media type.
1804 * @hw: pointer to the HW structure
1805 *
1806 * The media type is chosen based on SFP module.
1807 * compatibility flags retrieved from SFP ID EEPROM.
1808 **/
1809 static s32 e1000_set_sfp_media_type_82575(struct e1000_hw *hw)
1810 {
1811 s32 ret_val = E1000_ERR_CONFIG;
1812 u32 ctrl_ext = 0;
1813 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1814 struct sfp_e1000_flags *eth_flags = &dev_spec->eth_flags;
1815 u8 tranceiver_type = 0;
1816 s32 timeout = 3;
1817
1818 /* Turn I2C interface ON and power on sfp cage */
1819 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
1820 ctrl_ext &= ~E1000_CTRL_EXT_SDP3_DATA;
1821 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext | E1000_CTRL_I2C_ENA);
1822
1823 E1000_WRITE_FLUSH(hw);
1824
1825 /* Read SFP module data */
1826 while (timeout) {
1827 ret_val = e1000_read_sfp_data_byte(hw,
1828 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_IDENTIFIER_OFFSET),
1829 &tranceiver_type);
1830 if (ret_val == E1000_SUCCESS)
1831 break;
1832 msec_delay(100);
1833 timeout--;
1834 }
1835 if (ret_val != E1000_SUCCESS)
1836 goto out;
1837
1838 ret_val = e1000_read_sfp_data_byte(hw,
1839 E1000_I2CCMD_SFP_DATA_ADDR(E1000_SFF_ETH_FLAGS_OFFSET),
1840 (u8 *)eth_flags);
1841 if (ret_val != E1000_SUCCESS)
1842 goto out;
1843
1844 /* Check if there is some SFP module plugged and powered */
1845 if ((tranceiver_type == E1000_SFF_IDENTIFIER_SFP) ||
1846 (tranceiver_type == E1000_SFF_IDENTIFIER_SFF)) {
1847 dev_spec->module_plugged = true;
1848 if (eth_flags->e1000_base_lx || eth_flags->e1000_base_sx) {
1849 hw->phy.media_type = e1000_media_type_internal_serdes;
1850 } else if (eth_flags->e100_base_fx) {
1851 dev_spec->sgmii_active = true;
1852 hw->phy.media_type = e1000_media_type_internal_serdes;
1853 } else if (eth_flags->e1000_base_t) {
1854 dev_spec->sgmii_active = true;
1855 hw->phy.media_type = e1000_media_type_copper;
1856 } else {
1857 hw->phy.media_type = e1000_media_type_unknown;
1858 DEBUGOUT("PHY module has not been recognized\n");
1859 goto out;
1860 }
1861 } else {
1862 hw->phy.media_type = e1000_media_type_unknown;
1863 }
1864 ret_val = E1000_SUCCESS;
1865 out:
1866 /* Restore I2C interface setting */
1867 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
1868 return ret_val;
1869 }
1870
1871 /**
1872 * e1000_valid_led_default_82575 - Verify a valid default LED config
1873 * @hw: pointer to the HW structure
1874 * @data: pointer to the NVM (EEPROM)
1875 *
1876 * Read the EEPROM for the current default LED configuration. If the
1877 * LED configuration is not valid, set to a valid LED configuration.
1878 **/
1879 static s32 e1000_valid_led_default_82575(struct e1000_hw *hw, u16 *data)
1880 {
1881 s32 ret_val;
1882
1883 DEBUGFUNC("e1000_valid_led_default_82575");
1884
1885 ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1886 if (ret_val) {
1887 DEBUGOUT("NVM Read Error\n");
1888 goto out;
1889 }
1890
1891 if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1892 switch (hw->phy.media_type) {
1893 case e1000_media_type_internal_serdes:
1894 *data = ID_LED_DEFAULT_82575_SERDES;
1895 break;
1896 case e1000_media_type_copper:
1897 default:
1898 *data = ID_LED_DEFAULT;
1899 break;
1900 }
1901 }
1902 out:
1903 return ret_val;
1904 }
1905
1906 /**
1907 * e1000_sgmii_active_82575 - Return sgmii state
1908 * @hw: pointer to the HW structure
1909 *
1910 * 82575 silicon has a serialized gigabit media independent interface (sgmii)
1911 * which can be enabled for use in the embedded applications. Simply
1912 * return the current state of the sgmii interface.
1913 **/
1914 static bool e1000_sgmii_active_82575(struct e1000_hw *hw)
1915 {
1916 struct e1000_dev_spec_82575 *dev_spec = &hw->dev_spec._82575;
1917 return dev_spec->sgmii_active;
1918 }
1919
1920 /**
1921 * e1000_reset_init_script_82575 - Inits HW defaults after reset
1922 * @hw: pointer to the HW structure
1923 *
1924 * Inits recommended HW defaults after a reset when there is no EEPROM
1925 * detected. This is only for the 82575.
1926 **/
1927 static s32 e1000_reset_init_script_82575(struct e1000_hw *hw)
1928 {
1929 DEBUGFUNC("e1000_reset_init_script_82575");
1930
1931 if (hw->mac.type == e1000_82575) {
1932 DEBUGOUT("Running reset init script for 82575\n");
1933 /* SerDes configuration via SERDESCTRL */
1934 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x00, 0x0C);
1935 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x01, 0x78);
1936 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x1B, 0x23);
1937 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCTL, 0x23, 0x15);
1938
1939 /* CCM configuration via CCMCTL register */
1940 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x14, 0x00);
1941 e1000_write_8bit_ctrl_reg_generic(hw, E1000_CCMCTL, 0x10, 0x00);
1942
1943 /* PCIe lanes configuration */
1944 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x00, 0xEC);
1945 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x61, 0xDF);
1946 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x34, 0x05);
1947 e1000_write_8bit_ctrl_reg_generic(hw, E1000_GIOCTL, 0x2F, 0x81);
1948
1949 /* PCIe PLL Configuration */
1950 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x02, 0x47);
1951 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x14, 0x00);
1952 e1000_write_8bit_ctrl_reg_generic(hw, E1000_SCCTL, 0x10, 0x00);
1953 }
1954
1955 return E1000_SUCCESS;
1956 }
1957
1958 /**
1959 * e1000_read_mac_addr_82575 - Read device MAC address
1960 * @hw: pointer to the HW structure
1961 **/
1962 static s32 e1000_read_mac_addr_82575(struct e1000_hw *hw)
1963 {
1964 s32 ret_val = E1000_SUCCESS;
1965
1966 DEBUGFUNC("e1000_read_mac_addr_82575");
1967
1968 /*
1969 * If there's an alternate MAC address place it in RAR0
1970 * so that it will override the Si installed default perm
1971 * address.
1972 */
1973 ret_val = e1000_check_alt_mac_addr_generic(hw);
1974 if (ret_val)
1975 goto out;
1976
1977 ret_val = e1000_read_mac_addr_generic(hw);
1978
1979 out:
1980 return ret_val;
1981 }
1982
1983 /**
1984 * e1000_config_collision_dist_82575 - Configure collision distance
1985 * @hw: pointer to the HW structure
1986 *
1987 * Configures the collision distance to the default value and is used
1988 * during link setup.
1989 **/
1990 static void e1000_config_collision_dist_82575(struct e1000_hw *hw)
1991 {
1992 u32 tctl_ext;
1993
1994 DEBUGFUNC("e1000_config_collision_dist_82575");
1995
1996 tctl_ext = E1000_READ_REG(hw, E1000_TCTL_EXT);
1997
1998 tctl_ext &= ~E1000_TCTL_EXT_COLD;
1999 tctl_ext |= E1000_COLLISION_DISTANCE << E1000_TCTL_EXT_COLD_SHIFT;
2000
2001 E1000_WRITE_REG(hw, E1000_TCTL_EXT, tctl_ext);
2002 E1000_WRITE_FLUSH(hw);
2003 }
2004
2005 /**
2006 * e1000_power_down_phy_copper_82575 - Remove link during PHY power down
2007 * @hw: pointer to the HW structure
2008 *
2009 * In the case of a PHY power down to save power, or to turn off link during a
2010 * driver unload, or wake on lan is not enabled, remove the link.
2011 **/
2012 static void e1000_power_down_phy_copper_82575(struct e1000_hw *hw)
2013 {
2014 struct e1000_phy_info *phy = &hw->phy;
2015
2016 if (!(phy->ops.check_reset_block))
2017 return;
2018
2019 /* If the management interface is not enabled, then power down */
2020 if (!(e1000_enable_mng_pass_thru(hw) || phy->ops.check_reset_block(hw)))
2021 e1000_power_down_phy_copper(hw);
2022
2023 return;
2024 }
2025
2026 /**
2027 * e1000_clear_hw_cntrs_82575 - Clear device specific hardware counters
2028 * @hw: pointer to the HW structure
2029 *
2030 * Clears the hardware counters by reading the counter registers.
2031 **/
2032 static void e1000_clear_hw_cntrs_82575(struct e1000_hw *hw)
2033 {
2034 DEBUGFUNC("e1000_clear_hw_cntrs_82575");
2035
2036 e1000_clear_hw_cntrs_base_generic(hw);
2037
2038 E1000_READ_REG(hw, E1000_PRC64);
2039 E1000_READ_REG(hw, E1000_PRC127);
2040 E1000_READ_REG(hw, E1000_PRC255);
2041 E1000_READ_REG(hw, E1000_PRC511);
2042 E1000_READ_REG(hw, E1000_PRC1023);
2043 E1000_READ_REG(hw, E1000_PRC1522);
2044 E1000_READ_REG(hw, E1000_PTC64);
2045 E1000_READ_REG(hw, E1000_PTC127);
2046 E1000_READ_REG(hw, E1000_PTC255);
2047 E1000_READ_REG(hw, E1000_PTC511);
2048 E1000_READ_REG(hw, E1000_PTC1023);
2049 E1000_READ_REG(hw, E1000_PTC1522);
2050
2051 E1000_READ_REG(hw, E1000_ALGNERRC);
2052 E1000_READ_REG(hw, E1000_RXERRC);
2053 E1000_READ_REG(hw, E1000_TNCRS);
2054 E1000_READ_REG(hw, E1000_CEXTERR);
2055 E1000_READ_REG(hw, E1000_TSCTC);
2056 E1000_READ_REG(hw, E1000_TSCTFC);
2057
2058 E1000_READ_REG(hw, E1000_MGTPRC);
2059 E1000_READ_REG(hw, E1000_MGTPDC);
2060 E1000_READ_REG(hw, E1000_MGTPTC);
2061
2062 E1000_READ_REG(hw, E1000_IAC);
2063 E1000_READ_REG(hw, E1000_ICRXOC);
2064
2065 E1000_READ_REG(hw, E1000_ICRXPTC);
2066 E1000_READ_REG(hw, E1000_ICRXATC);
2067 E1000_READ_REG(hw, E1000_ICTXPTC);
2068 E1000_READ_REG(hw, E1000_ICTXATC);
2069 E1000_READ_REG(hw, E1000_ICTXQEC);
2070 E1000_READ_REG(hw, E1000_ICTXQMTC);
2071 E1000_READ_REG(hw, E1000_ICRXDMTC);
2072
2073 E1000_READ_REG(hw, E1000_CBTMPC);
2074 E1000_READ_REG(hw, E1000_HTDPMC);
2075 E1000_READ_REG(hw, E1000_CBRMPC);
2076 E1000_READ_REG(hw, E1000_RPTHC);
2077 E1000_READ_REG(hw, E1000_HGPTC);
2078 E1000_READ_REG(hw, E1000_HTCBDPC);
2079 E1000_READ_REG(hw, E1000_HGORCL);
2080 E1000_READ_REG(hw, E1000_HGORCH);
2081 E1000_READ_REG(hw, E1000_HGOTCL);
2082 E1000_READ_REG(hw, E1000_HGOTCH);
2083 E1000_READ_REG(hw, E1000_LENERRS);
2084
2085 /* This register should not be read in copper configurations */
2086 if ((hw->phy.media_type == e1000_media_type_internal_serdes) ||
2087 e1000_sgmii_active_82575(hw))
2088 E1000_READ_REG(hw, E1000_SCVPC);
2089 }
2090
2091 /**
2092 * e1000_rx_fifo_flush_82575 - Clean rx fifo after Rx enable
2093 * @hw: pointer to the HW structure
2094 *
2095 * After rx enable if managability is enabled then there is likely some
2096 * bad data at the start of the fifo and possibly in the DMA fifo. This
2097 * function clears the fifos and flushes any packets that came in as rx was
2098 * being enabled.
2099 **/
2100 void e1000_rx_fifo_flush_82575(struct e1000_hw *hw)
2101 {
2102 u32 rctl, rlpml, rxdctl[4], rfctl, temp_rctl, rx_enabled;
2103 int i, ms_wait;
2104
2105 DEBUGFUNC("e1000_rx_fifo_workaround_82575");
2106 if (hw->mac.type != e1000_82575 ||
2107 !(E1000_READ_REG(hw, E1000_MANC) & E1000_MANC_RCV_TCO_EN))
2108 return;
2109
2110 /* Disable all Rx queues */
2111 for (i = 0; i < 4; i++) {
2112 rxdctl[i] = E1000_READ_REG(hw, E1000_RXDCTL(i));
2113 E1000_WRITE_REG(hw, E1000_RXDCTL(i),
2114 rxdctl[i] & ~E1000_RXDCTL_QUEUE_ENABLE);
2115 }
2116 /* Poll all queues to verify they have shut down */
2117 for (ms_wait = 0; ms_wait < 10; ms_wait++) {
2118 msec_delay(1);
2119 rx_enabled = 0;
2120 for (i = 0; i < 4; i++)
2121 rx_enabled |= E1000_READ_REG(hw, E1000_RXDCTL(i));
2122 if (!(rx_enabled & E1000_RXDCTL_QUEUE_ENABLE))
2123 break;
2124 }
2125
2126 if (ms_wait == 10)
2127 DEBUGOUT("Queue disable timed out after 10ms\n");
2128
2129 /* Clear RLPML, RCTL.SBP, RFCTL.LEF, and set RCTL.LPE so that all
2130 * incoming packets are rejected. Set enable and wait 2ms so that
2131 * any packet that was coming in as RCTL.EN was set is flushed
2132 */
2133 rfctl = E1000_READ_REG(hw, E1000_RFCTL);
2134 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl & ~E1000_RFCTL_LEF);
2135
2136 rlpml = E1000_READ_REG(hw, E1000_RLPML);
2137 E1000_WRITE_REG(hw, E1000_RLPML, 0);
2138
2139 rctl = E1000_READ_REG(hw, E1000_RCTL);
2140 temp_rctl = rctl & ~(E1000_RCTL_EN | E1000_RCTL_SBP);
2141 temp_rctl |= E1000_RCTL_LPE;
2142
2143 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl);
2144 E1000_WRITE_REG(hw, E1000_RCTL, temp_rctl | E1000_RCTL_EN);
2145 E1000_WRITE_FLUSH(hw);
2146 msec_delay(2);
2147
2148 /* Enable Rx queues that were previously enabled and restore our
2149 * previous state
2150 */
2151 for (i = 0; i < 4; i++)
2152 E1000_WRITE_REG(hw, E1000_RXDCTL(i), rxdctl[i]);
2153 E1000_WRITE_REG(hw, E1000_RCTL, rctl);
2154 E1000_WRITE_FLUSH(hw);
2155
2156 E1000_WRITE_REG(hw, E1000_RLPML, rlpml);
2157 E1000_WRITE_REG(hw, E1000_RFCTL, rfctl);
2158
2159 /* Flush receive errors generated by workaround */
2160 E1000_READ_REG(hw, E1000_ROC);
2161 E1000_READ_REG(hw, E1000_RNBC);
2162 E1000_READ_REG(hw, E1000_MPC);
2163 }
2164
2165 /**
2166 * e1000_set_pcie_completion_timeout - set pci-e completion timeout
2167 * @hw: pointer to the HW structure
2168 *
2169 * The defaults for 82575 and 82576 should be in the range of 50us to 50ms,
2170 * however the hardware default for these parts is 500us to 1ms which is less
2171 * than the 10ms recommended by the pci-e spec. To address this we need to
2172 * increase the value to either 10ms to 200ms for capability version 1 config,
2173 * or 16ms to 55ms for version 2.
2174 **/
2175 static s32 e1000_set_pcie_completion_timeout(struct e1000_hw *hw)
2176 {
2177 u32 gcr = E1000_READ_REG(hw, E1000_GCR);
2178 s32 ret_val = E1000_SUCCESS;
2179 u16 pcie_devctl2;
2180
2181 /* only take action if timeout value is defaulted to 0 */
2182 if (gcr & E1000_GCR_CMPL_TMOUT_MASK)
2183 goto out;
2184
2185 /*
2186 * if capababilities version is type 1 we can write the
2187 * timeout of 10ms to 200ms through the GCR register
2188 */
2189 if (!(gcr & E1000_GCR_CAP_VER2)) {
2190 gcr |= E1000_GCR_CMPL_TMOUT_10ms;
2191 goto out;
2192 }
2193
2194 /*
2195 * for version 2 capabilities we need to write the config space
2196 * directly in order to set the completion timeout value for
2197 * 16ms to 55ms
2198 */
2199 ret_val = e1000_read_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2200 &pcie_devctl2);
2201 if (ret_val)
2202 goto out;
2203
2204 pcie_devctl2 |= PCIE_DEVICE_CONTROL2_16ms;
2205
2206 ret_val = e1000_write_pcie_cap_reg(hw, PCIE_DEVICE_CONTROL2,
2207 &pcie_devctl2);
2208 out:
2209 /* disable completion timeout resend */
2210 gcr &= ~E1000_GCR_CMPL_TMOUT_RESEND;
2211
2212 E1000_WRITE_REG(hw, E1000_GCR, gcr);
2213 return ret_val;
2214 }
2215
2216 /**
2217 * e1000_vmdq_set_anti_spoofing_pf - enable or disable anti-spoofing
2218 * @hw: pointer to the hardware struct
2219 * @enable: state to enter, either enabled or disabled
2220 * @pf: Physical Function pool - do not set anti-spoofing for the PF
2221 *
2222 * enables/disables L2 switch anti-spoofing functionality.
2223 **/
2224 void e1000_vmdq_set_anti_spoofing_pf(struct e1000_hw *hw, bool enable, int pf)
2225 {
2226 u32 reg_val, reg_offset;
2227
2228 switch (hw->mac.type) {
2229 case e1000_82576:
2230 reg_offset = E1000_DTXSWC;
2231 break;
2232 case e1000_i350:
2233 case e1000_i354:
2234 reg_offset = E1000_TXSWC;
2235 break;
2236 default:
2237 return;
2238 }
2239
2240 reg_val = E1000_READ_REG(hw, reg_offset);
2241 if (enable) {
2242 reg_val |= (E1000_DTXSWC_MAC_SPOOF_MASK |
2243 E1000_DTXSWC_VLAN_SPOOF_MASK);
2244 /* The PF can spoof - it has to in order to
2245 * support emulation mode NICs
2246 */
2247 reg_val ^= (1 << pf | 1 << (pf + MAX_NUM_VFS));
2248 } else {
2249 reg_val &= ~(E1000_DTXSWC_MAC_SPOOF_MASK |
2250 E1000_DTXSWC_VLAN_SPOOF_MASK);
2251 }
2252 E1000_WRITE_REG(hw, reg_offset, reg_val);
2253 }
2254
2255 /**
2256 * e1000_vmdq_set_loopback_pf - enable or disable vmdq loopback
2257 * @hw: pointer to the hardware struct
2258 * @enable: state to enter, either enabled or disabled
2259 *
2260 * enables/disables L2 switch loopback functionality.
2261 **/
2262 void e1000_vmdq_set_loopback_pf(struct e1000_hw *hw, bool enable)
2263 {
2264 u32 dtxswc;
2265
2266 switch (hw->mac.type) {
2267 case e1000_82576:
2268 dtxswc = E1000_READ_REG(hw, E1000_DTXSWC);
2269 if (enable)
2270 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2271 else
2272 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2273 E1000_WRITE_REG(hw, E1000_DTXSWC, dtxswc);
2274 break;
2275 case e1000_i350:
2276 case e1000_i354:
2277 dtxswc = E1000_READ_REG(hw, E1000_TXSWC);
2278 if (enable)
2279 dtxswc |= E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2280 else
2281 dtxswc &= ~E1000_DTXSWC_VMDQ_LOOPBACK_EN;
2282 E1000_WRITE_REG(hw, E1000_TXSWC, dtxswc);
2283 break;
2284 default:
2285 /* Currently no other hardware supports loopback */
2286 break;
2287 }
2288
2289
2290 }
2291
2292 /**
2293 * e1000_vmdq_set_replication_pf - enable or disable vmdq replication
2294 * @hw: pointer to the hardware struct
2295 * @enable: state to enter, either enabled or disabled
2296 *
2297 * enables/disables replication of packets across multiple pools.
2298 **/
2299 void e1000_vmdq_set_replication_pf(struct e1000_hw *hw, bool enable)
2300 {
2301 u32 vt_ctl = E1000_READ_REG(hw, E1000_VT_CTL);
2302
2303 if (enable)
2304 vt_ctl |= E1000_VT_CTL_VM_REPL_EN;
2305 else
2306 vt_ctl &= ~E1000_VT_CTL_VM_REPL_EN;
2307
2308 E1000_WRITE_REG(hw, E1000_VT_CTL, vt_ctl);
2309 }
2310
2311 /**
2312 * e1000_read_phy_reg_82580 - Read 82580 MDI control register
2313 * @hw: pointer to the HW structure
2314 * @offset: register offset to be read
2315 * @data: pointer to the read data
2316 *
2317 * Reads the MDI control register in the PHY at offset and stores the
2318 * information read to data.
2319 **/
2320 static s32 e1000_read_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 *data)
2321 {
2322 s32 ret_val;
2323
2324 DEBUGFUNC("e1000_read_phy_reg_82580");
2325
2326 ret_val = hw->phy.ops.acquire(hw);
2327 if (ret_val)
2328 goto out;
2329
2330 ret_val = e1000_read_phy_reg_mdic(hw, offset, data);
2331
2332 hw->phy.ops.release(hw);
2333
2334 out:
2335 return ret_val;
2336 }
2337
2338 /**
2339 * e1000_write_phy_reg_82580 - Write 82580 MDI control register
2340 * @hw: pointer to the HW structure
2341 * @offset: register offset to write to
2342 * @data: data to write to register at offset
2343 *
2344 * Writes data to MDI control register in the PHY at offset.
2345 **/
2346 static s32 e1000_write_phy_reg_82580(struct e1000_hw *hw, u32 offset, u16 data)
2347 {
2348 s32 ret_val;
2349
2350 DEBUGFUNC("e1000_write_phy_reg_82580");
2351
2352 ret_val = hw->phy.ops.acquire(hw);
2353 if (ret_val)
2354 goto out;
2355
2356 ret_val = e1000_write_phy_reg_mdic(hw, offset, data);
2357
2358 hw->phy.ops.release(hw);
2359
2360 out:
2361 return ret_val;
2362 }
2363
2364 /**
2365 * e1000_reset_mdicnfg_82580 - Reset MDICNFG destination and com_mdio bits
2366 * @hw: pointer to the HW structure
2367 *
2368 * This resets the MDICNFG.Destination and MDICNFG.Com_MDIO bits based on
2369 * the values found in the EEPROM. This addresses an issue in which these
2370 * bits are not restored from EEPROM after reset.
2371 **/
2372 static s32 e1000_reset_mdicnfg_82580(struct e1000_hw *hw)
2373 {
2374 s32 ret_val = E1000_SUCCESS;
2375 u32 mdicnfg;
2376 u16 nvm_data = 0;
2377
2378 DEBUGFUNC("e1000_reset_mdicnfg_82580");
2379
2380 if (hw->mac.type != e1000_82580)
2381 goto out;
2382 if (!e1000_sgmii_active_82575(hw))
2383 goto out;
2384
2385 ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL3_PORT_A +
2386 NVM_82580_LAN_FUNC_OFFSET(hw->bus.func), 1,
2387 &nvm_data);
2388 if (ret_val) {
2389 DEBUGOUT("NVM Read Error\n");
2390 goto out;
2391 }
2392
2393 mdicnfg = E1000_READ_REG(hw, E1000_MDICNFG);
2394 if (nvm_data & NVM_WORD24_EXT_MDIO)
2395 mdicnfg |= E1000_MDICNFG_EXT_MDIO;
2396 if (nvm_data & NVM_WORD24_COM_MDIO)
2397 mdicnfg |= E1000_MDICNFG_COM_MDIO;
2398 E1000_WRITE_REG(hw, E1000_MDICNFG, mdicnfg);
2399 out:
2400 return ret_val;
2401 }
2402
2403 /**
2404 * e1000_reset_hw_82580 - Reset hardware
2405 * @hw: pointer to the HW structure
2406 *
2407 * This resets function or entire device (all ports, etc.)
2408 * to a known state.
2409 **/
2410 static s32 e1000_reset_hw_82580(struct e1000_hw *hw)
2411 {
2412 s32 ret_val = E1000_SUCCESS;
2413 /* BH SW mailbox bit in SW_FW_SYNC */
2414 u16 swmbsw_mask = E1000_SW_SYNCH_MB;
2415 u32 ctrl;
2416 bool global_device_reset = hw->dev_spec._82575.global_device_reset;
2417
2418 DEBUGFUNC("e1000_reset_hw_82580");
2419
2420 hw->dev_spec._82575.global_device_reset = false;
2421
2422 /* 82580 does not reliably do global_device_reset due to hw errata */
2423 if (hw->mac.type == e1000_82580)
2424 global_device_reset = false;
2425
2426 /* Get current control state. */
2427 ctrl = E1000_READ_REG(hw, E1000_CTRL);
2428
2429 /*
2430 * Prevent the PCI-E bus from sticking if there is no TLP connection
2431 * on the last TLP read/write transaction when MAC is reset.
2432 */
2433 ret_val = e1000_disable_pcie_master_generic(hw);
2434 if (ret_val)
2435 DEBUGOUT("PCI-E Master disable polling has failed.\n");
2436
2437 DEBUGOUT("Masking off all interrupts\n");
2438 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2439 E1000_WRITE_REG(hw, E1000_RCTL, 0);
2440 E1000_WRITE_REG(hw, E1000_TCTL, E1000_TCTL_PSP);
2441 E1000_WRITE_FLUSH(hw);
2442
2443 msec_delay(10);
2444
2445 /* Determine whether or not a global dev reset is requested */
2446 if (global_device_reset && hw->mac.ops.acquire_swfw_sync(hw,
2447 swmbsw_mask))
2448 global_device_reset = false;
2449
2450 if (global_device_reset && !(E1000_READ_REG(hw, E1000_STATUS) &
2451 E1000_STAT_DEV_RST_SET))
2452 ctrl |= E1000_CTRL_DEV_RST;
2453 else
2454 ctrl |= E1000_CTRL_RST;
2455
2456 E1000_WRITE_REG(hw, E1000_CTRL, ctrl);
2457 E1000_WRITE_FLUSH(hw);
2458
2459 /* Add delay to insure DEV_RST has time to complete */
2460 if (global_device_reset)
2461 msec_delay(5);
2462
2463 ret_val = e1000_get_auto_rd_done_generic(hw);
2464 if (ret_val) {
2465 /*
2466 * When auto config read does not complete, do not
2467 * return with an error. This can happen in situations
2468 * where there is no eeprom and prevents getting link.
2469 */
2470 DEBUGOUT("Auto Read Done did not complete\n");
2471 }
2472
2473 /* clear global device reset status bit */
2474 E1000_WRITE_REG(hw, E1000_STATUS, E1000_STAT_DEV_RST_SET);
2475
2476 /* Clear any pending interrupt events. */
2477 E1000_WRITE_REG(hw, E1000_IMC, 0xffffffff);
2478 E1000_READ_REG(hw, E1000_ICR);
2479
2480 ret_val = e1000_reset_mdicnfg_82580(hw);
2481 if (ret_val)
2482 DEBUGOUT("Could not reset MDICNFG based on EEPROM\n");
2483
2484 /* Install any alternate MAC address into RAR0 */
2485 ret_val = e1000_check_alt_mac_addr_generic(hw);
2486
2487 /* Release semaphore */
2488 if (global_device_reset)
2489 hw->mac.ops.release_swfw_sync(hw, swmbsw_mask);
2490
2491 return ret_val;
2492 }
2493
2494 /**
2495 * e1000_rxpbs_adjust_82580 - adjust RXPBS value to reflect actual Rx PBA size
2496 * @data: data received by reading RXPBS register
2497 *
2498 * The 82580 uses a table based approach for packet buffer allocation sizes.
2499 * This function converts the retrieved value into the correct table value
2500 * 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7
2501 * 0x0 36 72 144 1 2 4 8 16
2502 * 0x8 35 70 140 rsv rsv rsv rsv rsv
2503 */
2504 u16 e1000_rxpbs_adjust_82580(u32 data)
2505 {
2506 u16 ret_val = 0;
2507
2508 if (data < E1000_82580_RXPBS_TABLE_SIZE)
2509 ret_val = e1000_82580_rxpbs_table[data];
2510
2511 return ret_val;
2512 }
2513
2514 /**
2515 * e1000_validate_nvm_checksum_with_offset - Validate EEPROM
2516 * checksum
2517 * @hw: pointer to the HW structure
2518 * @offset: offset in words of the checksum protected region
2519 *
2520 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM
2521 * and then verifies that the sum of the EEPROM is equal to 0xBABA.
2522 **/
2523 s32 e1000_validate_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2524 {
2525 s32 ret_val = E1000_SUCCESS;
2526 u16 checksum = 0;
2527 u16 i, nvm_data;
2528
2529 DEBUGFUNC("e1000_validate_nvm_checksum_with_offset");
2530
2531 for (i = offset; i < ((NVM_CHECKSUM_REG + offset) + 1); i++) {
2532 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2533 if (ret_val) {
2534 DEBUGOUT("NVM Read Error\n");
2535 goto out;
2536 }
2537 checksum += nvm_data;
2538 }
2539
2540 if (checksum != (u16) NVM_SUM) {
2541 DEBUGOUT("NVM Checksum Invalid\n");
2542 ret_val = -E1000_ERR_NVM;
2543 goto out;
2544 }
2545
2546 out:
2547 return ret_val;
2548 }
2549
2550 /**
2551 * e1000_update_nvm_checksum_with_offset - Update EEPROM
2552 * checksum
2553 * @hw: pointer to the HW structure
2554 * @offset: offset in words of the checksum protected region
2555 *
2556 * Updates the EEPROM checksum by reading/adding each word of the EEPROM
2557 * up to the checksum. Then calculates the EEPROM checksum and writes the
2558 * value to the EEPROM.
2559 **/
2560 s32 e1000_update_nvm_checksum_with_offset(struct e1000_hw *hw, u16 offset)
2561 {
2562 s32 ret_val;
2563 u16 checksum = 0;
2564 u16 i, nvm_data;
2565
2566 DEBUGFUNC("e1000_update_nvm_checksum_with_offset");
2567
2568 for (i = offset; i < (NVM_CHECKSUM_REG + offset); i++) {
2569 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data);
2570 if (ret_val) {
2571 DEBUGOUT("NVM Read Error while updating checksum.\n");
2572 goto out;
2573 }
2574 checksum += nvm_data;
2575 }
2576 checksum = (u16) NVM_SUM - checksum;
2577 ret_val = hw->nvm.ops.write(hw, (NVM_CHECKSUM_REG + offset), 1,
2578 &checksum);
2579 if (ret_val)
2580 DEBUGOUT("NVM Write Error while updating checksum.\n");
2581
2582 out:
2583 return ret_val;
2584 }
2585
2586 /**
2587 * e1000_validate_nvm_checksum_82580 - Validate EEPROM checksum
2588 * @hw: pointer to the HW structure
2589 *
2590 * Calculates the EEPROM section checksum by reading/adding each word of
2591 * the EEPROM and then verifies that the sum of the EEPROM is
2592 * equal to 0xBABA.
2593 **/
2594 static s32 e1000_validate_nvm_checksum_82580(struct e1000_hw *hw)
2595 {
2596 s32 ret_val = E1000_SUCCESS;
2597 u16 eeprom_regions_count = 1;
2598 u16 j, nvm_data;
2599 u16 nvm_offset;
2600
2601 DEBUGFUNC("e1000_validate_nvm_checksum_82580");
2602
2603 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2604 if (ret_val) {
2605 DEBUGOUT("NVM Read Error\n");
2606 goto out;
2607 }
2608
2609 if (nvm_data & NVM_COMPATIBILITY_BIT_MASK) {
2610 /* if chekcsums compatibility bit is set validate checksums
2611 * for all 4 ports. */
2612 eeprom_regions_count = 4;
2613 }
2614
2615 for (j = 0; j < eeprom_regions_count; j++) {
2616 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2617 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2618 nvm_offset);
2619 if (ret_val != E1000_SUCCESS)
2620 goto out;
2621 }
2622
2623 out:
2624 return ret_val;
2625 }
2626
2627 /**
2628 * e1000_update_nvm_checksum_82580 - Update EEPROM checksum
2629 * @hw: pointer to the HW structure
2630 *
2631 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2632 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2633 * checksum and writes the value to the EEPROM.
2634 **/
2635 static s32 e1000_update_nvm_checksum_82580(struct e1000_hw *hw)
2636 {
2637 s32 ret_val;
2638 u16 j, nvm_data;
2639 u16 nvm_offset;
2640
2641 DEBUGFUNC("e1000_update_nvm_checksum_82580");
2642
2643 ret_val = hw->nvm.ops.read(hw, NVM_COMPATIBILITY_REG_3, 1, &nvm_data);
2644 if (ret_val) {
2645 DEBUGOUT("NVM Read Error while updating checksum compatibility bit.\n");
2646 goto out;
2647 }
2648
2649 if (!(nvm_data & NVM_COMPATIBILITY_BIT_MASK)) {
2650 /* set compatibility bit to validate checksums appropriately */
2651 nvm_data = nvm_data | NVM_COMPATIBILITY_BIT_MASK;
2652 ret_val = hw->nvm.ops.write(hw, NVM_COMPATIBILITY_REG_3, 1,
2653 &nvm_data);
2654 if (ret_val) {
2655 DEBUGOUT("NVM Write Error while updating checksum compatibility bit.\n");
2656 goto out;
2657 }
2658 }
2659
2660 for (j = 0; j < 4; j++) {
2661 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2662 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2663 if (ret_val)
2664 goto out;
2665 }
2666
2667 out:
2668 return ret_val;
2669 }
2670
2671 /**
2672 * e1000_validate_nvm_checksum_i350 - Validate EEPROM checksum
2673 * @hw: pointer to the HW structure
2674 *
2675 * Calculates the EEPROM section checksum by reading/adding each word of
2676 * the EEPROM and then verifies that the sum of the EEPROM is
2677 * equal to 0xBABA.
2678 **/
2679 static s32 e1000_validate_nvm_checksum_i350(struct e1000_hw *hw)
2680 {
2681 s32 ret_val = E1000_SUCCESS;
2682 u16 j;
2683 u16 nvm_offset;
2684
2685 DEBUGFUNC("e1000_validate_nvm_checksum_i350");
2686
2687 for (j = 0; j < 4; j++) {
2688 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2689 ret_val = e1000_validate_nvm_checksum_with_offset(hw,
2690 nvm_offset);
2691 if (ret_val != E1000_SUCCESS)
2692 goto out;
2693 }
2694
2695 out:
2696 return ret_val;
2697 }
2698
2699 /**
2700 * e1000_update_nvm_checksum_i350 - Update EEPROM checksum
2701 * @hw: pointer to the HW structure
2702 *
2703 * Updates the EEPROM section checksums for all 4 ports by reading/adding
2704 * each word of the EEPROM up to the checksum. Then calculates the EEPROM
2705 * checksum and writes the value to the EEPROM.
2706 **/
2707 static s32 e1000_update_nvm_checksum_i350(struct e1000_hw *hw)
2708 {
2709 s32 ret_val = E1000_SUCCESS;
2710 u16 j;
2711 u16 nvm_offset;
2712
2713 DEBUGFUNC("e1000_update_nvm_checksum_i350");
2714
2715 for (j = 0; j < 4; j++) {
2716 nvm_offset = NVM_82580_LAN_FUNC_OFFSET(j);
2717 ret_val = e1000_update_nvm_checksum_with_offset(hw, nvm_offset);
2718 if (ret_val != E1000_SUCCESS)
2719 goto out;
2720 }
2721
2722 out:
2723 return ret_val;
2724 }
2725
2726 /**
2727 * __e1000_access_emi_reg - Read/write EMI register
2728 * @hw: pointer to the HW structure
2729 * @addr: EMI address to program
2730 * @data: pointer to value to read/write from/to the EMI address
2731 * @read: boolean flag to indicate read or write
2732 **/
2733 static s32 __e1000_access_emi_reg(struct e1000_hw *hw, u16 address,
2734 u16 *data, bool read)
2735 {
2736 s32 ret_val = E1000_SUCCESS;
2737
2738 DEBUGFUNC("__e1000_access_emi_reg");
2739
2740 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIADD, address);
2741 if (ret_val)
2742 return ret_val;
2743
2744 if (read)
2745 ret_val = hw->phy.ops.read_reg(hw, E1000_EMIDATA, data);
2746 else
2747 ret_val = hw->phy.ops.write_reg(hw, E1000_EMIDATA, *data);
2748
2749 return ret_val;
2750 }
2751
2752 /**
2753 * e1000_read_emi_reg - Read Extended Management Interface register
2754 * @hw: pointer to the HW structure
2755 * @addr: EMI address to program
2756 * @data: value to be read from the EMI address
2757 **/
2758 s32 e1000_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
2759 {
2760 DEBUGFUNC("e1000_read_emi_reg");
2761
2762 return __e1000_access_emi_reg(hw, addr, data, true);
2763 }
2764
2765 /**
2766 * e1000_set_eee_i350 - Enable/disable EEE support
2767 * @hw: pointer to the HW structure
2768 *
2769 * Enable/disable EEE based on setting in dev_spec structure.
2770 *
2771 **/
2772 s32 e1000_set_eee_i350(struct e1000_hw *hw)
2773 {
2774 s32 ret_val = E1000_SUCCESS;
2775 u32 ipcnfg, eeer;
2776
2777 DEBUGFUNC("e1000_set_eee_i350");
2778
2779 if ((hw->mac.type < e1000_i350) ||
2780 (hw->phy.media_type != e1000_media_type_copper))
2781 goto out;
2782 ipcnfg = E1000_READ_REG(hw, E1000_IPCNFG);
2783 eeer = E1000_READ_REG(hw, E1000_EEER);
2784
2785 /* enable or disable per user setting */
2786 if (!(hw->dev_spec._82575.eee_disable)) {
2787 u32 eee_su = E1000_READ_REG(hw, E1000_EEE_SU);
2788
2789 ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2790 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2791 E1000_EEER_LPI_FC);
2792
2793 /* This bit should not be set in normal operation. */
2794 if (eee_su & E1000_EEE_SU_LPI_CLK_STP)
2795 DEBUGOUT("LPI Clock Stop Bit should not be set!\n");
2796 } else {
2797 ipcnfg &= ~(E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
2798 eeer &= ~(E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
2799 E1000_EEER_LPI_FC);
2800 }
2801 E1000_WRITE_REG(hw, E1000_IPCNFG, ipcnfg);
2802 E1000_WRITE_REG(hw, E1000_EEER, eeer);
2803 E1000_READ_REG(hw, E1000_IPCNFG);
2804 E1000_READ_REG(hw, E1000_EEER);
2805 out:
2806
2807 return ret_val;
2808 }
2809
2810 /**
2811 * e1000_set_eee_i354 - Enable/disable EEE support
2812 * @hw: pointer to the HW structure
2813 *
2814 * Enable/disable EEE legacy mode based on setting in dev_spec structure.
2815 *
2816 **/
2817 s32 e1000_set_eee_i354(struct e1000_hw *hw)
2818 {
2819 struct e1000_phy_info *phy = &hw->phy;
2820 s32 ret_val = E1000_SUCCESS;
2821 u16 phy_data;
2822
2823 DEBUGFUNC("e1000_set_eee_i354");
2824
2825 if ((hw->phy.media_type != e1000_media_type_copper) ||
2826 ((phy->id != M88E1543_E_PHY_ID)))
2827 goto out;
2828
2829 if (!hw->dev_spec._82575.eee_disable) {
2830 /* Switch to PHY page 18. */
2831 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 18);
2832 if (ret_val)
2833 goto out;
2834
2835 ret_val = phy->ops.read_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2836 &phy_data);
2837 if (ret_val)
2838 goto out;
2839
2840 phy_data |= E1000_M88E1543_EEE_CTRL_1_MS;
2841 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_EEE_CTRL_1,
2842 phy_data);
2843 if (ret_val)
2844 goto out;
2845
2846 /* Return the PHY to page 0. */
2847 ret_val = phy->ops.write_reg(hw, E1000_M88E1543_PAGE_ADDR, 0);
2848 if (ret_val)
2849 goto out;
2850
2851 /* Turn on EEE advertisement. */
2852 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2853 E1000_EEE_ADV_DEV_I354,
2854 &phy_data);
2855 if (ret_val)
2856 goto out;
2857
2858 phy_data |= E1000_EEE_ADV_100_SUPPORTED |
2859 E1000_EEE_ADV_1000_SUPPORTED;
2860 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2861 E1000_EEE_ADV_DEV_I354,
2862 phy_data);
2863 } else {
2864 /* Turn off EEE advertisement. */
2865 ret_val = e1000_read_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2866 E1000_EEE_ADV_DEV_I354,
2867 &phy_data);
2868 if (ret_val)
2869 goto out;
2870
2871 phy_data &= ~(E1000_EEE_ADV_100_SUPPORTED |
2872 E1000_EEE_ADV_1000_SUPPORTED);
2873 ret_val = e1000_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
2874 E1000_EEE_ADV_DEV_I354,
2875 phy_data);
2876 }
2877
2878 out:
2879 return ret_val;
2880 }
2881
2882 /**
2883 * e1000_get_eee_status_i354 - Get EEE status
2884 * @hw: pointer to the HW structure
2885 * @status: EEE status
2886 *
2887 * Get EEE status by guessing based on whether Tx or Rx LPI indications have
2888 * been received.
2889 **/
2890 s32 e1000_get_eee_status_i354(struct e1000_hw *hw, bool *status)
2891 {
2892 struct e1000_phy_info *phy = &hw->phy;
2893 s32 ret_val = E1000_SUCCESS;
2894 u16 phy_data;
2895
2896 DEBUGFUNC("e1000_get_eee_status_i354");
2897
2898 /* Check if EEE is supported on this device. */
2899 if ((hw->phy.media_type != e1000_media_type_copper) ||
2900 ((phy->id != M88E1543_E_PHY_ID)))
2901 goto out;
2902
2903 ret_val = e1000_read_xmdio_reg(hw, E1000_PCS_STATUS_ADDR_I354,
2904 E1000_PCS_STATUS_DEV_I354,
2905 &phy_data);
2906 if (ret_val)
2907 goto out;
2908
2909 *status = phy_data & (E1000_PCS_STATUS_TX_LPI_RCVD |
2910 E1000_PCS_STATUS_RX_LPI_RCVD) ? true : false;
2911
2912 out:
2913 return ret_val;
2914 }
2915
2916 /* Due to a hw errata, if the host tries to configure the VFTA register
2917 * while performing queries from the BMC or DMA, then the VFTA in some
2918 * cases won't be written.
2919 */
2920
2921 /**
2922 * e1000_clear_vfta_i350 - Clear VLAN filter table
2923 * @hw: pointer to the HW structure
2924 *
2925 * Clears the register array which contains the VLAN filter table by
2926 * setting all the values to 0.
2927 **/
2928 void e1000_clear_vfta_i350(struct e1000_hw *hw)
2929 {
2930 u32 offset;
2931 int i;
2932
2933 DEBUGFUNC("e1000_clear_vfta_350");
2934
2935 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
2936 for (i = 0; i < 10; i++)
2937 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, 0);
2938
2939 E1000_WRITE_FLUSH(hw);
2940 }
2941 }
2942
2943 /**
2944 * e1000_write_vfta_i350 - Write value to VLAN filter table
2945 * @hw: pointer to the HW structure
2946 * @offset: register offset in VLAN filter table
2947 * @value: register value written to VLAN filter table
2948 *
2949 * Writes value at the given offset in the register array which stores
2950 * the VLAN filter table.
2951 **/
2952 void e1000_write_vfta_i350(struct e1000_hw *hw, u32 offset, u32 value)
2953 {
2954 int i;
2955
2956 DEBUGFUNC("e1000_write_vfta_350");
2957
2958 for (i = 0; i < 10; i++)
2959 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, value);
2960
2961 E1000_WRITE_FLUSH(hw);
2962 }
2963
2964
2965 /**
2966 * e1000_set_i2c_bb - Enable I2C bit-bang
2967 * @hw: pointer to the HW structure
2968 *
2969 * Enable I2C bit-bang interface
2970 *
2971 **/
2972 s32 e1000_set_i2c_bb(struct e1000_hw *hw)
2973 {
2974 s32 ret_val = E1000_SUCCESS;
2975 u32 ctrl_ext, i2cparams;
2976
2977 DEBUGFUNC("e1000_set_i2c_bb");
2978
2979 ctrl_ext = E1000_READ_REG(hw, E1000_CTRL_EXT);
2980 ctrl_ext |= E1000_CTRL_I2C_ENA;
2981 E1000_WRITE_REG(hw, E1000_CTRL_EXT, ctrl_ext);
2982 E1000_WRITE_FLUSH(hw);
2983
2984 i2cparams = E1000_READ_REG(hw, E1000_I2CPARAMS);
2985 i2cparams |= E1000_I2CBB_EN;
2986 i2cparams |= E1000_I2C_DATA_OE_N;
2987 i2cparams |= E1000_I2C_CLK_OE_N;
2988 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cparams);
2989 E1000_WRITE_FLUSH(hw);
2990
2991 return ret_val;
2992 }
2993
2994 /**
2995 * e1000_read_i2c_byte_generic - Reads 8 bit word over I2C
2996 * @hw: pointer to hardware structure
2997 * @byte_offset: byte offset to read
2998 * @dev_addr: device address
2999 * @data: value read
3000 *
3001 * Performs byte read operation over I2C interface at
3002 * a specified device address.
3003 **/
3004 s32 e1000_read_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3005 u8 dev_addr, u8 *data)
3006 {
3007 s32 status = E1000_SUCCESS;
3008 u32 max_retry = 10;
3009 u32 retry = 1;
3010 u16 swfw_mask = 0;
3011
3012 bool nack = true;
3013
3014 DEBUGFUNC("e1000_read_i2c_byte_generic");
3015
3016 swfw_mask = E1000_SWFW_PHY0_SM;
3017
3018 do {
3019 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)
3020 != E1000_SUCCESS) {
3021 status = E1000_ERR_SWFW_SYNC;
3022 goto read_byte_out;
3023 }
3024
3025 e1000_i2c_start(hw);
3026
3027 /* Device Address and write indication */
3028 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3029 if (status != E1000_SUCCESS)
3030 goto fail;
3031
3032 status = e1000_get_i2c_ack(hw);
3033 if (status != E1000_SUCCESS)
3034 goto fail;
3035
3036 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3037 if (status != E1000_SUCCESS)
3038 goto fail;
3039
3040 status = e1000_get_i2c_ack(hw);
3041 if (status != E1000_SUCCESS)
3042 goto fail;
3043
3044 e1000_i2c_start(hw);
3045
3046 /* Device Address and read indication */
3047 status = e1000_clock_out_i2c_byte(hw, (dev_addr | 0x1));
3048 if (status != E1000_SUCCESS)
3049 goto fail;
3050
3051 status = e1000_get_i2c_ack(hw);
3052 if (status != E1000_SUCCESS)
3053 goto fail;
3054
3055 status = e1000_clock_in_i2c_byte(hw, data);
3056 if (status != E1000_SUCCESS)
3057 goto fail;
3058
3059 status = e1000_clock_out_i2c_bit(hw, nack);
3060 if (status != E1000_SUCCESS)
3061 goto fail;
3062
3063 e1000_i2c_stop(hw);
3064 break;
3065
3066 fail:
3067 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3068 msec_delay(100);
3069 e1000_i2c_bus_clear(hw);
3070 retry++;
3071 if (retry < max_retry)
3072 DEBUGOUT("I2C byte read error - Retrying.\n");
3073 else
3074 DEBUGOUT("I2C byte read error.\n");
3075
3076 } while (retry < max_retry);
3077
3078 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3079
3080 read_byte_out:
3081
3082 return status;
3083 }
3084
3085 /**
3086 * e1000_write_i2c_byte_generic - Writes 8 bit word over I2C
3087 * @hw: pointer to hardware structure
3088 * @byte_offset: byte offset to write
3089 * @dev_addr: device address
3090 * @data: value to write
3091 *
3092 * Performs byte write operation over I2C interface at
3093 * a specified device address.
3094 **/
3095 s32 e1000_write_i2c_byte_generic(struct e1000_hw *hw, u8 byte_offset,
3096 u8 dev_addr, u8 data)
3097 {
3098 s32 status = E1000_SUCCESS;
3099 u32 max_retry = 1;
3100 u32 retry = 0;
3101 u16 swfw_mask = 0;
3102
3103 DEBUGFUNC("e1000_write_i2c_byte_generic");
3104
3105 swfw_mask = E1000_SWFW_PHY0_SM;
3106
3107 if (hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != E1000_SUCCESS) {
3108 status = E1000_ERR_SWFW_SYNC;
3109 goto write_byte_out;
3110 }
3111
3112 do {
3113 e1000_i2c_start(hw);
3114
3115 status = e1000_clock_out_i2c_byte(hw, dev_addr);
3116 if (status != E1000_SUCCESS)
3117 goto fail;
3118
3119 status = e1000_get_i2c_ack(hw);
3120 if (status != E1000_SUCCESS)
3121 goto fail;
3122
3123 status = e1000_clock_out_i2c_byte(hw, byte_offset);
3124 if (status != E1000_SUCCESS)
3125 goto fail;
3126
3127 status = e1000_get_i2c_ack(hw);
3128 if (status != E1000_SUCCESS)
3129 goto fail;
3130
3131 status = e1000_clock_out_i2c_byte(hw, data);
3132 if (status != E1000_SUCCESS)
3133 goto fail;
3134
3135 status = e1000_get_i2c_ack(hw);
3136 if (status != E1000_SUCCESS)
3137 goto fail;
3138
3139 e1000_i2c_stop(hw);
3140 break;
3141
3142 fail:
3143 e1000_i2c_bus_clear(hw);
3144 retry++;
3145 if (retry < max_retry)
3146 DEBUGOUT("I2C byte write error - Retrying.\n");
3147 else
3148 DEBUGOUT("I2C byte write error.\n");
3149 } while (retry < max_retry);
3150
3151 hw->mac.ops.release_swfw_sync(hw, swfw_mask);
3152
3153 write_byte_out:
3154
3155 return status;
3156 }
3157
3158 /**
3159 * e1000_i2c_start - Sets I2C start condition
3160 * @hw: pointer to hardware structure
3161 *
3162 * Sets I2C start condition (High -> Low on SDA while SCL is High)
3163 **/
3164 static void e1000_i2c_start(struct e1000_hw *hw)
3165 {
3166 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3167
3168 DEBUGFUNC("e1000_i2c_start");
3169
3170 /* Start condition must begin with data and clock high */
3171 e1000_set_i2c_data(hw, &i2cctl, 1);
3172 e1000_raise_i2c_clk(hw, &i2cctl);
3173
3174 /* Setup time for start condition (4.7us) */
3175 usec_delay(E1000_I2C_T_SU_STA);
3176
3177 e1000_set_i2c_data(hw, &i2cctl, 0);
3178
3179 /* Hold time for start condition (4us) */
3180 usec_delay(E1000_I2C_T_HD_STA);
3181
3182 e1000_lower_i2c_clk(hw, &i2cctl);
3183
3184 /* Minimum low period of clock is 4.7 us */
3185 usec_delay(E1000_I2C_T_LOW);
3186
3187 }
3188
3189 /**
3190 * e1000_i2c_stop - Sets I2C stop condition
3191 * @hw: pointer to hardware structure
3192 *
3193 * Sets I2C stop condition (Low -> High on SDA while SCL is High)
3194 **/
3195 static void e1000_i2c_stop(struct e1000_hw *hw)
3196 {
3197 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3198
3199 DEBUGFUNC("e1000_i2c_stop");
3200
3201 /* Stop condition must begin with data low and clock high */
3202 e1000_set_i2c_data(hw, &i2cctl, 0);
3203 e1000_raise_i2c_clk(hw, &i2cctl);
3204
3205 /* Setup time for stop condition (4us) */
3206 usec_delay(E1000_I2C_T_SU_STO);
3207
3208 e1000_set_i2c_data(hw, &i2cctl, 1);
3209
3210 /* bus free time between stop and start (4.7us)*/
3211 usec_delay(E1000_I2C_T_BUF);
3212 }
3213
3214 /**
3215 * e1000_clock_in_i2c_byte - Clocks in one byte via I2C
3216 * @hw: pointer to hardware structure
3217 * @data: data byte to clock in
3218 *
3219 * Clocks in one byte data via I2C data/clock
3220 **/
3221 static s32 e1000_clock_in_i2c_byte(struct e1000_hw *hw, u8 *data)
3222 {
3223 s32 i;
3224 bool bit = 0;
3225
3226 DEBUGFUNC("e1000_clock_in_i2c_byte");
3227
3228 *data = 0;
3229 for (i = 7; i >= 0; i--) {
3230 e1000_clock_in_i2c_bit(hw, &bit);
3231 *data |= bit << i;
3232 }
3233
3234 return E1000_SUCCESS;
3235 }
3236
3237 /**
3238 * e1000_clock_out_i2c_byte - Clocks out one byte via I2C
3239 * @hw: pointer to hardware structure
3240 * @data: data byte clocked out
3241 *
3242 * Clocks out one byte data via I2C data/clock
3243 **/
3244 static s32 e1000_clock_out_i2c_byte(struct e1000_hw *hw, u8 data)
3245 {
3246 s32 status = E1000_SUCCESS;
3247 s32 i;
3248 u32 i2cctl;
3249 bool bit = 0;
3250
3251 DEBUGFUNC("e1000_clock_out_i2c_byte");
3252
3253 for (i = 7; i >= 0; i--) {
3254 bit = (data >> i) & 0x1;
3255 status = e1000_clock_out_i2c_bit(hw, bit);
3256
3257 if (status != E1000_SUCCESS)
3258 break;
3259 }
3260
3261 /* Release SDA line (set high) */
3262 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3263
3264 i2cctl |= E1000_I2C_DATA_OE_N;
3265 E1000_WRITE_REG(hw, E1000_I2CPARAMS, i2cctl);
3266 E1000_WRITE_FLUSH(hw);
3267
3268 return status;
3269 }
3270
3271 /**
3272 * e1000_get_i2c_ack - Polls for I2C ACK
3273 * @hw: pointer to hardware structure
3274 *
3275 * Clocks in/out one bit via I2C data/clock
3276 **/
3277 static s32 e1000_get_i2c_ack(struct e1000_hw *hw)
3278 {
3279 s32 status = E1000_SUCCESS;
3280 u32 i = 0;
3281 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3282 u32 timeout = 10;
3283 bool ack = true;
3284
3285 DEBUGFUNC("e1000_get_i2c_ack");
3286
3287 e1000_raise_i2c_clk(hw, &i2cctl);
3288
3289 /* Minimum high period of clock is 4us */
3290 usec_delay(E1000_I2C_T_HIGH);
3291
3292 /* Wait until SCL returns high */
3293 for (i = 0; i < timeout; i++) {
3294 usec_delay(1);
3295 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3296 if (i2cctl & E1000_I2C_CLK_IN)
3297 break;
3298 }
3299 if (!(i2cctl & E1000_I2C_CLK_IN))
3300 return E1000_ERR_I2C;
3301
3302 ack = e1000_get_i2c_data(&i2cctl);
3303 if (ack) {
3304 DEBUGOUT("I2C ack was not received.\n");
3305 status = E1000_ERR_I2C;
3306 }
3307
3308 e1000_lower_i2c_clk(hw, &i2cctl);
3309
3310 /* Minimum low period of clock is 4.7 us */
3311 usec_delay(E1000_I2C_T_LOW);
3312
3313 return status;
3314 }
3315
3316 /**
3317 * e1000_clock_in_i2c_bit - Clocks in one bit via I2C data/clock
3318 * @hw: pointer to hardware structure
3319 * @data: read data value
3320 *
3321 * Clocks in one bit via I2C data/clock
3322 **/
3323 static s32 e1000_clock_in_i2c_bit(struct e1000_hw *hw, bool *data)
3324 {
3325 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3326
3327 DEBUGFUNC("e1000_clock_in_i2c_bit");
3328
3329 e1000_raise_i2c_clk(hw, &i2cctl);
3330
3331 /* Minimum high period of clock is 4us */
3332 usec_delay(E1000_I2C_T_HIGH);
3333
3334 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3335 *data = e1000_get_i2c_data(&i2cctl);
3336
3337 e1000_lower_i2c_clk(hw, &i2cctl);
3338
3339 /* Minimum low period of clock is 4.7 us */
3340 usec_delay(E1000_I2C_T_LOW);
3341
3342 return E1000_SUCCESS;
3343 }
3344
3345 /**
3346 * e1000_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock
3347 * @hw: pointer to hardware structure
3348 * @data: data value to write
3349 *
3350 * Clocks out one bit via I2C data/clock
3351 **/
3352 static s32 e1000_clock_out_i2c_bit(struct e1000_hw *hw, bool data)
3353 {
3354 s32 status;
3355 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3356
3357 DEBUGFUNC("e1000_clock_out_i2c_bit");
3358
3359 status = e1000_set_i2c_data(hw, &i2cctl, data);
3360 if (status == E1000_SUCCESS) {
3361 e1000_raise_i2c_clk(hw, &i2cctl);
3362
3363 /* Minimum high period of clock is 4us */
3364 usec_delay(E1000_I2C_T_HIGH);
3365
3366 e1000_lower_i2c_clk(hw, &i2cctl);
3367
3368 /* Minimum low period of clock is 4.7 us.
3369 * This also takes care of the data hold time.
3370 */
3371 usec_delay(E1000_I2C_T_LOW);
3372 } else {
3373 status = E1000_ERR_I2C;
3374 DEBUGOUT1("I2C data was not set to %X\n", data);
3375 }
3376
3377 return status;
3378 }
3379 /**
3380 * e1000_raise_i2c_clk - Raises the I2C SCL clock
3381 * @hw: pointer to hardware structure
3382 * @i2cctl: Current value of I2CCTL register
3383 *
3384 * Raises the I2C clock line '0'->'1'
3385 **/
3386 static void e1000_raise_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3387 {
3388 DEBUGFUNC("e1000_raise_i2c_clk");
3389
3390 *i2cctl |= E1000_I2C_CLK_OUT;
3391 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3392 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3393 E1000_WRITE_FLUSH(hw);
3394
3395 /* SCL rise time (1000ns) */
3396 usec_delay(E1000_I2C_T_RISE);
3397 }
3398
3399 /**
3400 * e1000_lower_i2c_clk - Lowers the I2C SCL clock
3401 * @hw: pointer to hardware structure
3402 * @i2cctl: Current value of I2CCTL register
3403 *
3404 * Lowers the I2C clock line '1'->'0'
3405 **/
3406 static void e1000_lower_i2c_clk(struct e1000_hw *hw, u32 *i2cctl)
3407 {
3408
3409 DEBUGFUNC("e1000_lower_i2c_clk");
3410
3411 *i2cctl &= ~E1000_I2C_CLK_OUT;
3412 *i2cctl &= ~E1000_I2C_CLK_OE_N;
3413 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3414 E1000_WRITE_FLUSH(hw);
3415
3416 /* SCL fall time (300ns) */
3417 usec_delay(E1000_I2C_T_FALL);
3418 }
3419
3420 /**
3421 * e1000_set_i2c_data - Sets the I2C data bit
3422 * @hw: pointer to hardware structure
3423 * @i2cctl: Current value of I2CCTL register
3424 * @data: I2C data value (0 or 1) to set
3425 *
3426 * Sets the I2C data bit
3427 **/
3428 static s32 e1000_set_i2c_data(struct e1000_hw *hw, u32 *i2cctl, bool data)
3429 {
3430 s32 status = E1000_SUCCESS;
3431
3432 DEBUGFUNC("e1000_set_i2c_data");
3433
3434 if (data)
3435 *i2cctl |= E1000_I2C_DATA_OUT;
3436 else
3437 *i2cctl &= ~E1000_I2C_DATA_OUT;
3438
3439 *i2cctl &= ~E1000_I2C_DATA_OE_N;
3440 *i2cctl |= E1000_I2C_CLK_OE_N;
3441 E1000_WRITE_REG(hw, E1000_I2CPARAMS, *i2cctl);
3442 E1000_WRITE_FLUSH(hw);
3443
3444 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */
3445 usec_delay(E1000_I2C_T_RISE + E1000_I2C_T_FALL + E1000_I2C_T_SU_DATA);
3446
3447 *i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3448 if (data != e1000_get_i2c_data(i2cctl)) {
3449 status = E1000_ERR_I2C;
3450 DEBUGOUT1("Error - I2C data was not set to %X.\n", data);
3451 }
3452
3453 return status;
3454 }
3455
3456 /**
3457 * e1000_get_i2c_data - Reads the I2C SDA data bit
3458 * @hw: pointer to hardware structure
3459 * @i2cctl: Current value of I2CCTL register
3460 *
3461 * Returns the I2C data bit value
3462 **/
3463 static bool e1000_get_i2c_data(u32 *i2cctl)
3464 {
3465 bool data;
3466
3467 DEBUGFUNC("e1000_get_i2c_data");
3468
3469 if (*i2cctl & E1000_I2C_DATA_IN)
3470 data = 1;
3471 else
3472 data = 0;
3473
3474 return data;
3475 }
3476
3477 /**
3478 * e1000_i2c_bus_clear - Clears the I2C bus
3479 * @hw: pointer to hardware structure
3480 *
3481 * Clears the I2C bus by sending nine clock pulses.
3482 * Used when data line is stuck low.
3483 **/
3484 void e1000_i2c_bus_clear(struct e1000_hw *hw)
3485 {
3486 u32 i2cctl = E1000_READ_REG(hw, E1000_I2CPARAMS);
3487 u32 i;
3488
3489 DEBUGFUNC("e1000_i2c_bus_clear");
3490
3491 e1000_i2c_start(hw);
3492
3493 e1000_set_i2c_data(hw, &i2cctl, 1);
3494
3495 for (i = 0; i < 9; i++) {
3496 e1000_raise_i2c_clk(hw, &i2cctl);
3497
3498 /* Min high period of clock is 4us */
3499 usec_delay(E1000_I2C_T_HIGH);
3500
3501 e1000_lower_i2c_clk(hw, &i2cctl);
3502
3503 /* Min low period of clock is 4.7us*/
3504 usec_delay(E1000_I2C_T_LOW);
3505 }
3506
3507 e1000_i2c_start(hw);
3508
3509 /* Put the i2c bus back to default state */
3510 e1000_i2c_stop(hw);
3511 }
3512
3513 static const u8 e1000_emc_temp_data[4] = {
3514 E1000_EMC_INTERNAL_DATA,
3515 E1000_EMC_DIODE1_DATA,
3516 E1000_EMC_DIODE2_DATA,
3517 E1000_EMC_DIODE3_DATA
3518 };
3519 static const u8 e1000_emc_therm_limit[4] = {
3520 E1000_EMC_INTERNAL_THERM_LIMIT,
3521 E1000_EMC_DIODE1_THERM_LIMIT,
3522 E1000_EMC_DIODE2_THERM_LIMIT,
3523 E1000_EMC_DIODE3_THERM_LIMIT
3524 };
3525
3526 /**
3527 * e1000_get_thermal_sensor_data_generic - Gathers thermal sensor data
3528 * @hw: pointer to hardware structure
3529 *
3530 * Updates the temperatures in mac.thermal_sensor_data
3531 **/
3532 s32 e1000_get_thermal_sensor_data_generic(struct e1000_hw *hw)
3533 {
3534 s32 status = E1000_SUCCESS;
3535 u16 ets_offset;
3536 u16 ets_cfg;
3537 u16 ets_sensor;
3538 u8 num_sensors;
3539 u8 sensor_index;
3540 u8 sensor_location;
3541 u8 i;
3542 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3543
3544 DEBUGFUNC("e1000_get_thermal_sensor_data_generic");
3545
3546 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
3547 return E1000_NOT_IMPLEMENTED;
3548
3549 data->sensor[0].temp = (E1000_READ_REG(hw, E1000_THMJT) & 0xFF);
3550
3551 /* Return the internal sensor only if ETS is unsupported */
3552 e1000_read_nvm(hw, NVM_ETS_CFG, 1, &ets_offset);
3553 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
3554 return status;
3555
3556 e1000_read_nvm(hw, ets_offset, 1, &ets_cfg);
3557 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
3558 != NVM_ETS_TYPE_EMC)
3559 return E1000_NOT_IMPLEMENTED;
3560
3561 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
3562 if (num_sensors > E1000_MAX_SENSORS)
3563 num_sensors = E1000_MAX_SENSORS;
3564
3565 for (i = 1; i < num_sensors; i++) {
3566 e1000_read_nvm(hw, (ets_offset + i), 1, &ets_sensor);
3567 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
3568 NVM_ETS_DATA_INDEX_SHIFT);
3569 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
3570 NVM_ETS_DATA_LOC_SHIFT);
3571
3572 if (sensor_location != 0)
3573 hw->phy.ops.read_i2c_byte(hw,
3574 e1000_emc_temp_data[sensor_index],
3575 E1000_I2C_THERMAL_SENSOR_ADDR,
3576 &data->sensor[i].temp);
3577 }
3578 return status;
3579 }
3580
3581 /**
3582 * e1000_init_thermal_sensor_thresh_generic - Sets thermal sensor thresholds
3583 * @hw: pointer to hardware structure
3584 *
3585 * Sets the thermal sensor thresholds according to the NVM map
3586 * and save off the threshold and location values into mac.thermal_sensor_data
3587 **/
3588 s32 e1000_init_thermal_sensor_thresh_generic(struct e1000_hw *hw)
3589 {
3590 s32 status = E1000_SUCCESS;
3591 u16 ets_offset;
3592 u16 ets_cfg;
3593 u16 ets_sensor;
3594 u8 low_thresh_delta;
3595 u8 num_sensors;
3596 u8 sensor_index;
3597 u8 sensor_location;
3598 u8 therm_limit;
3599 u8 i;
3600 struct e1000_thermal_sensor_data *data = &hw->mac.thermal_sensor_data;
3601
3602 DEBUGFUNC("e1000_init_thermal_sensor_thresh_generic");
3603
3604 if ((hw->mac.type != e1000_i350) || (hw->bus.func != 0))
3605 return E1000_NOT_IMPLEMENTED;
3606
3607 memset(data, 0, sizeof(struct e1000_thermal_sensor_data));
3608
3609 data->sensor[0].location = 0x1;
3610 data->sensor[0].caution_thresh =
3611 (E1000_READ_REG(hw, E1000_THHIGHTC) & 0xFF);
3612 data->sensor[0].max_op_thresh =
3613 (E1000_READ_REG(hw, E1000_THLOWTC) & 0xFF);
3614
3615 /* Return the internal sensor only if ETS is unsupported */
3616 e1000_read_nvm(hw, NVM_ETS_CFG, 1, &ets_offset);
3617 if ((ets_offset == 0x0000) || (ets_offset == 0xFFFF))
3618 return status;
3619
3620 e1000_read_nvm(hw, ets_offset, 1, &ets_cfg);
3621 if (((ets_cfg & NVM_ETS_TYPE_MASK) >> NVM_ETS_TYPE_SHIFT)
3622 != NVM_ETS_TYPE_EMC)
3623 return E1000_NOT_IMPLEMENTED;
3624
3625 low_thresh_delta = ((ets_cfg & NVM_ETS_LTHRES_DELTA_MASK) >>
3626 NVM_ETS_LTHRES_DELTA_SHIFT);
3627 num_sensors = (ets_cfg & NVM_ETS_NUM_SENSORS_MASK);
3628
3629 for (i = 1; i <= num_sensors; i++) {
3630 e1000_read_nvm(hw, (ets_offset + i), 1, &ets_sensor);
3631 sensor_index = ((ets_sensor & NVM_ETS_DATA_INDEX_MASK) >>
3632 NVM_ETS_DATA_INDEX_SHIFT);
3633 sensor_location = ((ets_sensor & NVM_ETS_DATA_LOC_MASK) >>
3634 NVM_ETS_DATA_LOC_SHIFT);
3635 therm_limit = ets_sensor & NVM_ETS_DATA_HTHRESH_MASK;
3636
3637 hw->phy.ops.write_i2c_byte(hw,
3638 e1000_emc_therm_limit[sensor_index],
3639 E1000_I2C_THERMAL_SENSOR_ADDR,
3640 therm_limit);
3641
3642 if ((i < E1000_MAX_SENSORS) && (sensor_location != 0)) {
3643 data->sensor[i].location = sensor_location;
3644 data->sensor[i].caution_thresh = therm_limit;
3645 data->sensor[i].max_op_thresh = therm_limit -
3646 low_thresh_delta;
3647 }
3648 }
3649 return status;
3650 }
Ceph