ceph/src/spdk/dpdk/kernel/linux/kni/ethtool/igb/e1000_hw.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*******************************************************************************
   3
   4   Intel(R) Gigabit Ethernet Linux driver
   5   Copyright(c) 2007-2013 Intel Corporation.
   6
   7   Contact Information:
   8   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   9   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  10
  11 *******************************************************************************/
  12
  13 #ifndef _E1000_HW_H_
  14 #define _E1000_HW_H_
  15
  16 #include "e1000_osdep.h"
  17 #include "e1000_regs.h"
  18 #include "e1000_defines.h"
  19
  20 struct e1000_hw;
  21
  22 #define E1000_DEV_ID_82576                      0x10C9
  23 #define E1000_DEV_ID_82576_FIBER                0x10E6
  24 #define E1000_DEV_ID_82576_SERDES               0x10E7
  25 #define E1000_DEV_ID_82576_QUAD_COPPER          0x10E8
  26 #define E1000_DEV_ID_82576_QUAD_COPPER_ET2      0x1526
  27 #define E1000_DEV_ID_82576_NS                   0x150A
  28 #define E1000_DEV_ID_82576_NS_SERDES            0x1518
  29 #define E1000_DEV_ID_82576_SERDES_QUAD          0x150D
  30 #define E1000_DEV_ID_82575EB_COPPER             0x10A7
  31 #define E1000_DEV_ID_82575EB_FIBER_SERDES       0x10A9
  32 #define E1000_DEV_ID_82575GB_QUAD_COPPER        0x10D6
  33 #define E1000_DEV_ID_82580_COPPER               0x150E
  34 #define E1000_DEV_ID_82580_FIBER                0x150F
  35 #define E1000_DEV_ID_82580_SERDES               0x1510
  36 #define E1000_DEV_ID_82580_SGMII                0x1511
  37 #define E1000_DEV_ID_82580_COPPER_DUAL          0x1516
  38 #define E1000_DEV_ID_82580_QUAD_FIBER           0x1527
  39 #define E1000_DEV_ID_I350_COPPER                0x1521
  40 #define E1000_DEV_ID_I350_FIBER                 0x1522
  41 #define E1000_DEV_ID_I350_SERDES                0x1523
  42 #define E1000_DEV_ID_I350_SGMII                 0x1524
  43 #define E1000_DEV_ID_I350_DA4                   0x1546
  44 #define E1000_DEV_ID_I210_COPPER                0x1533
  45 #define E1000_DEV_ID_I210_COPPER_OEM1           0x1534
  46 #define E1000_DEV_ID_I210_COPPER_IT             0x1535
  47 #define E1000_DEV_ID_I210_FIBER                 0x1536
  48 #define E1000_DEV_ID_I210_SERDES                0x1537
  49 #define E1000_DEV_ID_I210_SGMII                 0x1538
  50 #define E1000_DEV_ID_I210_COPPER_FLASHLESS      0x157B
  51 #define E1000_DEV_ID_I210_SERDES_FLASHLESS      0x157C
  52 #define E1000_DEV_ID_I211_COPPER                0x1539
  53 #define E1000_DEV_ID_I354_BACKPLANE_1GBPS       0x1F40
  54 #define E1000_DEV_ID_I354_SGMII                 0x1F41
  55 #define E1000_DEV_ID_I354_BACKPLANE_2_5GBPS     0x1F45
  56 #define E1000_DEV_ID_DH89XXCC_SGMII             0x0438
  57 #define E1000_DEV_ID_DH89XXCC_SERDES            0x043A
  58 #define E1000_DEV_ID_DH89XXCC_BACKPLANE         0x043C
  59 #define E1000_DEV_ID_DH89XXCC_SFP               0x0440
  60
  61 #define E1000_REVISION_0        0
  62 #define E1000_REVISION_1        1
  63 #define E1000_REVISION_2        2
  64 #define E1000_REVISION_3        3
  65 #define E1000_REVISION_4        4
  66
  67 #define E1000_FUNC_0            0
  68 #define E1000_FUNC_1            1
  69 #define E1000_FUNC_2            2
  70 #define E1000_FUNC_3            3
  71
  72 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN0       0
  73 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN1       3
  74 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN2       6
  75 #define E1000_ALT_MAC_ADDRESS_OFFSET_LAN3       9
  76
  77 enum e1000_mac_type {
  78         e1000_undefined = 0,
  79         e1000_82575,
  80         e1000_82576,
  81         e1000_82580,
  82         e1000_i350,
  83         e1000_i354,
  84         e1000_i210,
  85         e1000_i211,
  86         e1000_num_macs  /* List is 1-based, so subtract 1 for true count. */
  87 };
  88
  89 enum e1000_media_type {
  90         e1000_media_type_unknown = 0,
  91         e1000_media_type_copper = 1,
  92         e1000_media_type_fiber = 2,
  93         e1000_media_type_internal_serdes = 3,
  94         e1000_num_media_types
  95 };
  96
  97 enum e1000_nvm_type {
  98         e1000_nvm_unknown = 0,
  99         e1000_nvm_none,
 100         e1000_nvm_eeprom_spi,
 101         e1000_nvm_flash_hw,
 102         e1000_nvm_invm,
 103         e1000_nvm_flash_sw
 104 };
 105
 106 enum e1000_nvm_override {
 107         e1000_nvm_override_none = 0,
 108         e1000_nvm_override_spi_small,
 109         e1000_nvm_override_spi_large,
 110 };
 111
 112 enum e1000_phy_type {
 113         e1000_phy_unknown = 0,
 114         e1000_phy_none,
 115         e1000_phy_m88,
 116         e1000_phy_igp,
 117         e1000_phy_igp_2,
 118         e1000_phy_gg82563,
 119         e1000_phy_igp_3,
 120         e1000_phy_ife,
 121         e1000_phy_82580,
 122         e1000_phy_vf,
 123         e1000_phy_i210,
 124 };
 125
 126 enum e1000_bus_type {
 127         e1000_bus_type_unknown = 0,
 128         e1000_bus_type_pci,
 129         e1000_bus_type_pcix,
 130         e1000_bus_type_pci_express,
 131         e1000_bus_type_reserved
 132 };
 133
 134 enum e1000_bus_speed {
 135         e1000_bus_speed_unknown = 0,
 136         e1000_bus_speed_33,
 137         e1000_bus_speed_66,
 138         e1000_bus_speed_100,
 139         e1000_bus_speed_120,
 140         e1000_bus_speed_133,
 141         e1000_bus_speed_2500,
 142         e1000_bus_speed_5000,
 143         e1000_bus_speed_reserved
 144 };
 145
 146 enum e1000_bus_width {
 147         e1000_bus_width_unknown = 0,
 148         e1000_bus_width_pcie_x1,
 149         e1000_bus_width_pcie_x2,
 150         e1000_bus_width_pcie_x4 = 4,
 151         e1000_bus_width_pcie_x8 = 8,
 152         e1000_bus_width_32,
 153         e1000_bus_width_64,
 154         e1000_bus_width_reserved
 155 };
 156
 157 enum e1000_1000t_rx_status {
 158         e1000_1000t_rx_status_not_ok = 0,
 159         e1000_1000t_rx_status_ok,
 160         e1000_1000t_rx_status_undefined = 0xFF
 161 };
 162
 163 enum e1000_rev_polarity {
 164         e1000_rev_polarity_normal = 0,
 165         e1000_rev_polarity_reversed,
 166         e1000_rev_polarity_undefined = 0xFF
 167 };
 168
 169 enum e1000_fc_mode {
 170         e1000_fc_none = 0,
 171         e1000_fc_rx_pause,
 172         e1000_fc_tx_pause,
 173         e1000_fc_full,
 174         e1000_fc_default = 0xFF
 175 };
 176
 177 enum e1000_ms_type {
 178         e1000_ms_hw_default = 0,
 179         e1000_ms_force_master,
 180         e1000_ms_force_slave,
 181         e1000_ms_auto
 182 };
 183
 184 enum e1000_smart_speed {
 185         e1000_smart_speed_default = 0,
 186         e1000_smart_speed_on,
 187         e1000_smart_speed_off
 188 };
 189
 190 enum e1000_serdes_link_state {
 191         e1000_serdes_link_down = 0,
 192         e1000_serdes_link_autoneg_progress,
 193         e1000_serdes_link_autoneg_complete,
 194         e1000_serdes_link_forced_up
 195 };
 196
 197 #ifndef __le16
 198 #define __le16 u16
 199 #endif
 200 #ifndef __le32
 201 #define __le32 u32
 202 #endif
 203 #ifndef __le64
 204 #define __le64 u64
 205 #endif
 206 /* Receive Descriptor */
 207 struct e1000_rx_desc {
 208         __le64 buffer_addr; /* Address of the descriptor's data buffer */
 209         __le16 length;      /* Length of data DMAed into data buffer */
 210         __le16 csum; /* Packet checksum */
 211         u8  status;  /* Descriptor status */
 212         u8  errors;  /* Descriptor Errors */
 213         __le16 special;
 214 };
 215
 216 /* Receive Descriptor - Extended */
 217 union e1000_rx_desc_extended {
 218         struct {
 219                 __le64 buffer_addr;
 220                 __le64 reserved;
 221         } read;
 222         struct {
 223                 struct {
 224                         __le32 mrq; /* Multiple Rx Queues */
 225                         union {
 226                                 __le32 rss; /* RSS Hash */
 227                                 struct {
 228                                         __le16 ip_id;  /* IP id */
 229                                         __le16 csum;   /* Packet Checksum */
 230                                 } csum_ip;
 231                         } hi_dword;
 232                 } lower;
 233                 struct {
 234                         __le32 status_error;  /* ext status/error */
 235                         __le16 length;
 236                         __le16 vlan; /* VLAN tag */
 237                 } upper;
 238         } wb;  /* writeback */
 239 };
 240
 241 #define MAX_PS_BUFFERS 4
 242
 243 /* Number of packet split data buffers (not including the header buffer) */
 244 #define PS_PAGE_BUFFERS (MAX_PS_BUFFERS - 1)
 245
 246 /* Receive Descriptor - Packet Split */
 247 union e1000_rx_desc_packet_split {
 248         struct {
 249                 /* one buffer for protocol header(s), three data buffers */
 250                 __le64 buffer_addr[MAX_PS_BUFFERS];
 251         } read;
 252         struct {
 253                 struct {
 254                         __le32 mrq;  /* Multiple Rx Queues */
 255                         union {
 256                                 __le32 rss; /* RSS Hash */
 257                                 struct {
 258                                         __le16 ip_id;    /* IP id */
 259                                         __le16 csum;     /* Packet Checksum */
 260                                 } csum_ip;
 261                         } hi_dword;
 262                 } lower;
 263                 struct {
 264                         __le32 status_error;  /* ext status/error */
 265                         __le16 length0;  /* length of buffer 0 */
 266                         __le16 vlan;  /* VLAN tag */
 267                 } middle;
 268                 struct {
 269                         __le16 header_status;
 270                         /* length of buffers 1-3 */
 271                         __le16 length[PS_PAGE_BUFFERS];
 272                 } upper;
 273                 __le64 reserved;
 274         } wb; /* writeback */
 275 };
 276
 277 /* Transmit Descriptor */
 278 struct e1000_tx_desc {
 279         __le64 buffer_addr;   /* Address of the descriptor's data buffer */
 280         union {
 281                 __le32 data;
 282                 struct {
 283                         __le16 length;  /* Data buffer length */
 284                         u8 cso;  /* Checksum offset */
 285                         u8 cmd;  /* Descriptor control */
 286                 } flags;
 287         } lower;
 288         union {
 289                 __le32 data;
 290                 struct {
 291                         u8 status; /* Descriptor status */
 292                         u8 css;  /* Checksum start */
 293                         __le16 special;
 294                 } fields;
 295         } upper;
 296 };
 297
 298 /* Offload Context Descriptor */
 299 struct e1000_context_desc {
 300         union {
 301                 __le32 ip_config;
 302                 struct {
 303                         u8 ipcss;  /* IP checksum start */
 304                         u8 ipcso;  /* IP checksum offset */
 305                         __le16 ipcse;  /* IP checksum end */
 306                 } ip_fields;
 307         } lower_setup;
 308         union {
 309                 __le32 tcp_config;
 310                 struct {
 311                         u8 tucss;  /* TCP checksum start */
 312                         u8 tucso;  /* TCP checksum offset */
 313                         __le16 tucse;  /* TCP checksum end */
 314                 } tcp_fields;
 315         } upper_setup;
 316         __le32 cmd_and_length;
 317         union {
 318                 __le32 data;
 319                 struct {
 320                         u8 status;  /* Descriptor status */
 321                         u8 hdr_len;  /* Header length */
 322                         __le16 mss;  /* Maximum segment size */
 323                 } fields;
 324         } tcp_seg_setup;
 325 };
 326
 327 /* Offload data descriptor */
 328 struct e1000_data_desc {
 329         __le64 buffer_addr;  /* Address of the descriptor's buffer address */
 330         union {
 331                 __le32 data;
 332                 struct {
 333                         __le16 length;  /* Data buffer length */
 334                         u8 typ_len_ext;
 335                         u8 cmd;
 336                 } flags;
 337         } lower;
 338         union {
 339                 __le32 data;
 340                 struct {
 341                         u8 status;  /* Descriptor status */
 342                         u8 popts;  /* Packet Options */
 343                         __le16 special;
 344                 } fields;
 345         } upper;
 346 };
 347
 348 /* Statistics counters collected by the MAC */
 349 struct e1000_hw_stats {
 350         u64 crcerrs;
 351         u64 algnerrc;
 352         u64 symerrs;
 353         u64 rxerrc;
 354         u64 mpc;
 355         u64 scc;
 356         u64 ecol;
 357         u64 mcc;
 358         u64 latecol;
 359         u64 colc;
 360         u64 dc;
 361         u64 tncrs;
 362         u64 sec;
 363         u64 cexterr;
 364         u64 rlec;
 365         u64 xonrxc;
 366         u64 xontxc;
 367         u64 xoffrxc;
 368         u64 xofftxc;
 369         u64 fcruc;
 370         u64 prc64;
 371         u64 prc127;
 372         u64 prc255;
 373         u64 prc511;
 374         u64 prc1023;
 375         u64 prc1522;
 376         u64 gprc;
 377         u64 bprc;
 378         u64 mprc;
 379         u64 gptc;
 380         u64 gorc;
 381         u64 gotc;
 382         u64 rnbc;
 383         u64 ruc;
 384         u64 rfc;
 385         u64 roc;
 386         u64 rjc;
 387         u64 mgprc;
 388         u64 mgpdc;
 389         u64 mgptc;
 390         u64 tor;
 391         u64 tot;
 392         u64 tpr;
 393         u64 tpt;
 394         u64 ptc64;
 395         u64 ptc127;
 396         u64 ptc255;
 397         u64 ptc511;
 398         u64 ptc1023;
 399         u64 ptc1522;
 400         u64 mptc;
 401         u64 bptc;
 402         u64 tsctc;
 403         u64 tsctfc;
 404         u64 iac;
 405         u64 icrxptc;
 406         u64 icrxatc;
 407         u64 ictxptc;
 408         u64 ictxatc;
 409         u64 ictxqec;
 410         u64 ictxqmtc;
 411         u64 icrxdmtc;
 412         u64 icrxoc;
 413         u64 cbtmpc;
 414         u64 htdpmc;
 415         u64 cbrdpc;
 416         u64 cbrmpc;
 417         u64 rpthc;
 418         u64 hgptc;
 419         u64 htcbdpc;
 420         u64 hgorc;
 421         u64 hgotc;
 422         u64 lenerrs;
 423         u64 scvpc;
 424         u64 hrmpc;
 425         u64 doosync;
 426         u64 o2bgptc;
 427         u64 o2bspc;
 428         u64 b2ospc;
 429         u64 b2ogprc;
 430 };
 431
 432
 433 struct e1000_phy_stats {
 434         u32 idle_errors;
 435         u32 receive_errors;
 436 };
 437
 438 struct e1000_host_mng_dhcp_cookie {
 439         u32 signature;
 440         u8  status;
 441         u8  reserved0;
 442         u16 vlan_id;
 443         u32 reserved1;
 444         u16 reserved2;
 445         u8  reserved3;
 446         u8  checksum;
 447 };
 448
 449 /* Host Interface "Rev 1" */
 450 struct e1000_host_command_header {
 451         u8 command_id;
 452         u8 command_length;
 453         u8 command_options;
 454         u8 checksum;
 455 };
 456
 457 #define E1000_HI_MAX_DATA_LENGTH        252
 458 struct e1000_host_command_info {
 459         struct e1000_host_command_header command_header;
 460         u8 command_data[E1000_HI_MAX_DATA_LENGTH];
 461 };
 462
 463 /* Host Interface "Rev 2" */
 464 struct e1000_host_mng_command_header {
 465         u8  command_id;
 466         u8  checksum;
 467         u16 reserved1;
 468         u16 reserved2;
 469         u16 command_length;
 470 };
 471
 472 #define E1000_HI_MAX_MNG_DATA_LENGTH    0x6F8
 473 struct e1000_host_mng_command_info {
 474         struct e1000_host_mng_command_header command_header;
 475         u8 command_data[E1000_HI_MAX_MNG_DATA_LENGTH];
 476 };
 477
 478 #include "e1000_mac.h"
 479 #include "e1000_phy.h"
 480 #include "e1000_nvm.h"
 481 #include "e1000_manage.h"
 482 #include "e1000_mbx.h"
 483
 484 /* Function pointers for the MAC. */
 485 struct e1000_mac_operations {
 486         s32  (*init_params)(struct e1000_hw *);
 487         s32  (*id_led_init)(struct e1000_hw *);
 488         s32  (*blink_led)(struct e1000_hw *);
 489         bool (*check_mng_mode)(struct e1000_hw *);
 490         s32  (*check_for_link)(struct e1000_hw *);
 491         s32  (*cleanup_led)(struct e1000_hw *);
 492         void (*clear_hw_cntrs)(struct e1000_hw *);
 493         void (*clear_vfta)(struct e1000_hw *);
 494         s32  (*get_bus_info)(struct e1000_hw *);
 495         void (*set_lan_id)(struct e1000_hw *);
 496         s32  (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
 497         s32  (*led_on)(struct e1000_hw *);
 498         s32  (*led_off)(struct e1000_hw *);
 499         void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
 500         s32  (*reset_hw)(struct e1000_hw *);
 501         s32  (*init_hw)(struct e1000_hw *);
 502         void (*shutdown_serdes)(struct e1000_hw *);
 503         void (*power_up_serdes)(struct e1000_hw *);
 504         s32  (*setup_link)(struct e1000_hw *);
 505         s32  (*setup_physical_interface)(struct e1000_hw *);
 506         s32  (*setup_led)(struct e1000_hw *);
 507         void (*write_vfta)(struct e1000_hw *, u32, u32);
 508         void (*config_collision_dist)(struct e1000_hw *);
 509         void (*rar_set)(struct e1000_hw *, u8*, u32);
 510         s32  (*read_mac_addr)(struct e1000_hw *);
 511         s32  (*validate_mdi_setting)(struct e1000_hw *);
 512         s32 (*get_thermal_sensor_data)(struct e1000_hw *);
 513         s32 (*init_thermal_sensor_thresh)(struct e1000_hw *);
 514         s32  (*acquire_swfw_sync)(struct e1000_hw *, u16);
 515         void (*release_swfw_sync)(struct e1000_hw *, u16);
 516 };
 517
 518 /* When to use various PHY register access functions:
 519  *
 520  *                 Func   Caller
 521  *   Function      Does   Does    When to use
 522  *   ~~~~~~~~~~~~  ~~~~~  ~~~~~~  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
 523  *   X_reg         L,P,A  n/a     for simple PHY reg accesses
 524  *   X_reg_locked  P,A    L       for multiple accesses of different regs
 525  *                                on different pages
 526  *   X_reg_page    A      L,P     for multiple accesses of different regs
 527  *                                on the same page
 528  *
 529  * Where X=[read|write], L=locking, P=sets page, A=register access
 530  *
 531  */
 532 struct e1000_phy_operations {
 533         s32  (*init_params)(struct e1000_hw *);
 534         s32  (*acquire)(struct e1000_hw *);
 535         s32  (*check_polarity)(struct e1000_hw *);
 536         s32  (*check_reset_block)(struct e1000_hw *);
 537         s32  (*commit)(struct e1000_hw *);
 538         s32  (*force_speed_duplex)(struct e1000_hw *);
 539         s32  (*get_cfg_done)(struct e1000_hw *hw);
 540         s32  (*get_cable_length)(struct e1000_hw *);
 541         s32  (*get_info)(struct e1000_hw *);
 542         s32  (*set_page)(struct e1000_hw *, u16);
 543         s32  (*read_reg)(struct e1000_hw *, u32, u16 *);
 544         s32  (*read_reg_locked)(struct e1000_hw *, u32, u16 *);
 545         s32  (*read_reg_page)(struct e1000_hw *, u32, u16 *);
 546         void (*release)(struct e1000_hw *);
 547         s32  (*reset)(struct e1000_hw *);
 548         s32  (*set_d0_lplu_state)(struct e1000_hw *, bool);
 549         s32  (*set_d3_lplu_state)(struct e1000_hw *, bool);
 550         s32  (*write_reg)(struct e1000_hw *, u32, u16);
 551         s32  (*write_reg_locked)(struct e1000_hw *, u32, u16);
 552         s32  (*write_reg_page)(struct e1000_hw *, u32, u16);
 553         void (*power_up)(struct e1000_hw *);
 554         void (*power_down)(struct e1000_hw *);
 555         s32 (*read_i2c_byte)(struct e1000_hw *, u8, u8, u8 *);
 556         s32 (*write_i2c_byte)(struct e1000_hw *, u8, u8, u8);
 557 };
 558
 559 /* Function pointers for the NVM. */
 560 struct e1000_nvm_operations {
 561         s32  (*init_params)(struct e1000_hw *);
 562         s32  (*acquire)(struct e1000_hw *);
 563         s32  (*read)(struct e1000_hw *, u16, u16, u16 *);
 564         void (*release)(struct e1000_hw *);
 565         void (*reload)(struct e1000_hw *);
 566         s32  (*update)(struct e1000_hw *);
 567         s32  (*valid_led_default)(struct e1000_hw *, u16 *);
 568         s32  (*validate)(struct e1000_hw *);
 569         s32  (*write)(struct e1000_hw *, u16, u16, u16 *);
 570 };
 571
 572 #define E1000_MAX_SENSORS               3
 573
 574 struct e1000_thermal_diode_data {
 575         u8 location;
 576         u8 temp;
 577         u8 caution_thresh;
 578         u8 max_op_thresh;
 579 };
 580
 581 struct e1000_thermal_sensor_data {
 582         struct e1000_thermal_diode_data sensor[E1000_MAX_SENSORS];
 583 };
 584
 585 struct e1000_mac_info {
 586         struct e1000_mac_operations ops;
 587         u8 addr[ETH_ADDR_LEN];
 588         u8 perm_addr[ETH_ADDR_LEN];
 589
 590         enum e1000_mac_type type;
 591
 592         u32 collision_delta;
 593         u32 ledctl_default;
 594         u32 ledctl_mode1;
 595         u32 ledctl_mode2;
 596         u32 mc_filter_type;
 597         u32 tx_packet_delta;
 598         u32 txcw;
 599
 600         u16 current_ifs_val;
 601         u16 ifs_max_val;
 602         u16 ifs_min_val;
 603         u16 ifs_ratio;
 604         u16 ifs_step_size;
 605         u16 mta_reg_count;
 606         u16 uta_reg_count;
 607
 608         /* Maximum size of the MTA register table in all supported adapters */
 609         #define MAX_MTA_REG 128
 610         u32 mta_shadow[MAX_MTA_REG];
 611         u16 rar_entry_count;
 612
 613         u8  forced_speed_duplex;
 614
 615         bool adaptive_ifs;
 616         bool has_fwsm;
 617         bool arc_subsystem_valid;
 618         bool asf_firmware_present;
 619         bool autoneg;
 620         bool autoneg_failed;
 621         bool get_link_status;
 622         bool in_ifs_mode;
 623         enum e1000_serdes_link_state serdes_link_state;
 624         bool serdes_has_link;
 625         bool tx_pkt_filtering;
 626         struct e1000_thermal_sensor_data thermal_sensor_data;
 627 };
 628
 629 struct e1000_phy_info {
 630         struct e1000_phy_operations ops;
 631         enum e1000_phy_type type;
 632
 633         enum e1000_1000t_rx_status local_rx;
 634         enum e1000_1000t_rx_status remote_rx;
 635         enum e1000_ms_type ms_type;
 636         enum e1000_ms_type original_ms_type;
 637         enum e1000_rev_polarity cable_polarity;
 638         enum e1000_smart_speed smart_speed;
 639
 640         u32 addr;
 641         u32 id;
 642         u32 reset_delay_us; /* in usec */
 643         u32 revision;
 644
 645         enum e1000_media_type media_type;
 646
 647         u16 autoneg_advertised;
 648         u16 autoneg_mask;
 649         u16 cable_length;
 650         u16 max_cable_length;
 651         u16 min_cable_length;
 652
 653         u8 mdix;
 654
 655         bool disable_polarity_correction;
 656         bool is_mdix;
 657         bool polarity_correction;
 658         bool reset_disable;
 659         bool speed_downgraded;
 660         bool autoneg_wait_to_complete;
 661 };
 662
 663 struct e1000_nvm_info {
 664         struct e1000_nvm_operations ops;
 665         enum e1000_nvm_type type;
 666         enum e1000_nvm_override override;
 667
 668         u32 flash_bank_size;
 669         u32 flash_base_addr;
 670
 671         u16 word_size;
 672         u16 delay_usec;
 673         u16 address_bits;
 674         u16 opcode_bits;
 675         u16 page_size;
 676 };
 677
 678 struct e1000_bus_info {
 679         enum e1000_bus_type type;
 680         enum e1000_bus_speed speed;
 681         enum e1000_bus_width width;
 682
 683         u16 func;
 684         u16 pci_cmd_word;
 685 };
 686
 687 struct e1000_fc_info {
 688         u32 high_water;  /* Flow control high-water mark */
 689         u32 low_water;  /* Flow control low-water mark */
 690         u16 pause_time;  /* Flow control pause timer */
 691         u16 refresh_time;  /* Flow control refresh timer */
 692         bool send_xon;  /* Flow control send XON */
 693         bool strict_ieee;  /* Strict IEEE mode */
 694         enum e1000_fc_mode current_mode;  /* FC mode in effect */
 695         enum e1000_fc_mode requested_mode;  /* FC mode requested by caller */
 696 };
 697
 698 struct e1000_mbx_operations {
 699         s32 (*init_params)(struct e1000_hw *hw);
 700         s32 (*read)(struct e1000_hw *, u32 *, u16,  u16);
 701         s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
 702         s32 (*read_posted)(struct e1000_hw *, u32 *, u16,  u16);
 703         s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
 704         s32 (*check_for_msg)(struct e1000_hw *, u16);
 705         s32 (*check_for_ack)(struct e1000_hw *, u16);
 706         s32 (*check_for_rst)(struct e1000_hw *, u16);
 707 };
 708
 709 struct e1000_mbx_stats {
 710         u32 msgs_tx;
 711         u32 msgs_rx;
 712
 713         u32 acks;
 714         u32 reqs;
 715         u32 rsts;
 716 };
 717
 718 struct e1000_mbx_info {
 719         struct e1000_mbx_operations ops;
 720         struct e1000_mbx_stats stats;
 721         u32 timeout;
 722         u32 usec_delay;
 723         u16 size;
 724 };
 725
 726 struct e1000_dev_spec_82575 {
 727         bool sgmii_active;
 728         bool global_device_reset;
 729         bool eee_disable;
 730         bool module_plugged;
 731         bool clear_semaphore_once;
 732         u32 mtu;
 733         struct sfp_e1000_flags eth_flags;
 734         u8 media_port;
 735         bool media_changed;
 736 };
 737
 738 struct e1000_dev_spec_vf {
 739         u32 vf_number;
 740         u32 v2p_mailbox;
 741 };
 742
 743 struct e1000_hw {
 744         void *back;
 745
 746         u8 __iomem *hw_addr;
 747         u8 __iomem *flash_address;
 748         unsigned long io_base;
 749
 750         struct e1000_mac_info  mac;
 751         struct e1000_fc_info   fc;
 752         struct e1000_phy_info  phy;
 753         struct e1000_nvm_info  nvm;
 754         struct e1000_bus_info  bus;
 755         struct e1000_mbx_info mbx;
 756         struct e1000_host_mng_dhcp_cookie mng_cookie;
 757
 758         union {
 759                 struct e1000_dev_spec_82575 _82575;
 760                 struct e1000_dev_spec_vf vf;
 761         } dev_spec;
 762
 763         u16 device_id;
 764         u16 subsystem_vendor_id;
 765         u16 subsystem_device_id;
 766         u16 vendor_id;
 767
 768         u8  revision_id;
 769 };
 770
 771 #include "e1000_82575.h"
 772 #include "e1000_i210.h"
 773
 774 /* These functions must be implemented by drivers */
 775 s32  e1000_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 776 s32  e1000_write_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
 777
 778 #endif