ceph/src/spdk/dpdk/kernel/linux/kni/ethtool/igb/e1000_phy.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*******************************************************************************
   3
   4   Intel(R) Gigabit Ethernet Linux driver
   5   Copyright(c) 2007-2013 Intel Corporation.
   6
   7   Contact Information:
   8   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   9   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  10
  11 *******************************************************************************/
  12
  13 #ifndef _E1000_PHY_H_
  14 #define _E1000_PHY_H_
  15
  16 void e1000_init_phy_ops_generic(struct e1000_hw *hw);
  17 s32  e1000_null_read_reg(struct e1000_hw *hw, u32 offset, u16 *data);
  18 void e1000_null_phy_generic(struct e1000_hw *hw);
  19 s32  e1000_null_lplu_state(struct e1000_hw *hw, bool active);
  20 s32  e1000_null_write_reg(struct e1000_hw *hw, u32 offset, u16 data);
  21 s32  e1000_null_set_page(struct e1000_hw *hw, u16 data);
  22 s32 e1000_read_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
  23                              u8 dev_addr, u8 *data);
  24 s32 e1000_write_i2c_byte_null(struct e1000_hw *hw, u8 byte_offset,
  25                               u8 dev_addr, u8 data);
  26 s32  e1000_check_downshift_generic(struct e1000_hw *hw);
  27 s32  e1000_check_polarity_m88(struct e1000_hw *hw);
  28 s32  e1000_check_polarity_igp(struct e1000_hw *hw);
  29 s32  e1000_check_polarity_ife(struct e1000_hw *hw);
  30 s32  e1000_check_reset_block_generic(struct e1000_hw *hw);
  31 s32  e1000_copper_link_setup_igp(struct e1000_hw *hw);
  32 s32  e1000_copper_link_setup_m88(struct e1000_hw *hw);
  33 s32  e1000_copper_link_setup_m88_gen2(struct e1000_hw *hw);
  34 s32  e1000_phy_force_speed_duplex_igp(struct e1000_hw *hw);
  35 s32  e1000_phy_force_speed_duplex_m88(struct e1000_hw *hw);
  36 s32  e1000_phy_force_speed_duplex_ife(struct e1000_hw *hw);
  37 s32  e1000_get_cable_length_m88(struct e1000_hw *hw);
  38 s32  e1000_get_cable_length_m88_gen2(struct e1000_hw *hw);
  39 s32  e1000_get_cable_length_igp_2(struct e1000_hw *hw);
  40 s32  e1000_get_cfg_done_generic(struct e1000_hw *hw);
  41 s32  e1000_get_phy_id(struct e1000_hw *hw);
  42 s32  e1000_get_phy_info_igp(struct e1000_hw *hw);
  43 s32  e1000_get_phy_info_m88(struct e1000_hw *hw);
  44 s32  e1000_get_phy_info_ife(struct e1000_hw *hw);
  45 s32  e1000_phy_sw_reset_generic(struct e1000_hw *hw);
  46 void e1000_phy_force_speed_duplex_setup(struct e1000_hw *hw, u16 *phy_ctrl);
  47 s32  e1000_phy_hw_reset_generic(struct e1000_hw *hw);
  48 s32  e1000_phy_reset_dsp_generic(struct e1000_hw *hw);
  49 s32  e1000_read_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 *data);
  50 s32  e1000_read_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  51 s32  e1000_set_page_igp(struct e1000_hw *hw, u16 page);
  52 s32  e1000_read_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 *data);
  53 s32  e1000_read_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 *data);
  54 s32  e1000_read_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 *data);
  55 s32  e1000_set_d3_lplu_state_generic(struct e1000_hw *hw, bool active);
  56 s32  e1000_setup_copper_link_generic(struct e1000_hw *hw);
  57 s32  e1000_write_kmrn_reg_generic(struct e1000_hw *hw, u32 offset, u16 data);
  58 s32  e1000_write_kmrn_reg_locked(struct e1000_hw *hw, u32 offset, u16 data);
  59 s32  e1000_write_phy_reg_igp(struct e1000_hw *hw, u32 offset, u16 data);
  60 s32  e1000_write_phy_reg_igp_locked(struct e1000_hw *hw, u32 offset, u16 data);
  61 s32  e1000_write_phy_reg_m88(struct e1000_hw *hw, u32 offset, u16 data);
  62 s32  e1000_phy_has_link_generic(struct e1000_hw *hw, u32 iterations,
  63                                 u32 usec_interval, bool *success);
  64 s32  e1000_phy_init_script_igp3(struct e1000_hw *hw);
  65 enum e1000_phy_type e1000_get_phy_type_from_id(u32 phy_id);
  66 s32  e1000_determine_phy_address(struct e1000_hw *hw);
  67 s32  e1000_enable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
  68 s32  e1000_disable_phy_wakeup_reg_access_bm(struct e1000_hw *hw, u16 *phy_reg);
  69 void e1000_power_up_phy_copper(struct e1000_hw *hw);
  70 void e1000_power_down_phy_copper(struct e1000_hw *hw);
  71 s32  e1000_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data);
  72 s32  e1000_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data);
  73 s32  e1000_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data);
  74 s32  e1000_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data);
  75 s32  e1000_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data);
  76 s32  e1000_write_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 data);
  77 s32  e1000_copper_link_setup_82577(struct e1000_hw *hw);
  78 s32  e1000_check_polarity_82577(struct e1000_hw *hw);
  79 s32  e1000_get_phy_info_82577(struct e1000_hw *hw);
  80 s32  e1000_phy_force_speed_duplex_82577(struct e1000_hw *hw);
  81 s32  e1000_get_cable_length_82577(struct e1000_hw *hw);
  82 s32  e1000_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data);
  83 s32  e1000_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data);
  84 s32 e1000_read_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 *data);
  85 s32 e1000_write_phy_reg_mphy(struct e1000_hw *hw, u32 address, u32 data,
  86                              bool line_override);
  87 bool e1000_is_mphy_ready(struct e1000_hw *hw);
  88
  89 #define E1000_MAX_PHY_ADDR              8
  90
  91 /* IGP01E1000 Specific Registers */
  92 #define IGP01E1000_PHY_PORT_CONFIG      0x10 /* Port Config */
  93 #define IGP01E1000_PHY_PORT_STATUS      0x11 /* Status */
  94 #define IGP01E1000_PHY_PORT_CTRL        0x12 /* Control */
  95 #define IGP01E1000_PHY_LINK_HEALTH      0x13 /* PHY Link Health */
  96 #define IGP02E1000_PHY_POWER_MGMT       0x19 /* Power Management */
  97 #define IGP01E1000_PHY_PAGE_SELECT      0x1F /* Page Select */
  98 #define BM_PHY_PAGE_SELECT              22   /* Page Select for BM */
  99 #define IGP_PAGE_SHIFT                  5
 100 #define PHY_REG_MASK                    0x1F
 101
 102 /* GS40G - I210 PHY defines */
 103 #define GS40G_PAGE_SELECT               0x16
 104 #define GS40G_PAGE_SHIFT                16
 105 #define GS40G_OFFSET_MASK               0xFFFF
 106 #define GS40G_PAGE_2                    0x20000
 107 #define GS40G_MAC_REG2                  0x15
 108 #define GS40G_MAC_LB                    0x4140
 109 #define GS40G_MAC_SPEED_1G              0X0006
 110 #define GS40G_COPPER_SPEC               0x0010
 111 #define GS40G_CS_POWER_DOWN             0x0002
 112
 113 #define HV_INTC_FC_PAGE_START           768
 114 #define I82578_ADDR_REG                 29
 115 #define I82577_ADDR_REG                 16
 116 #define I82577_CFG_REG                  22
 117 #define I82577_CFG_ASSERT_CRS_ON_TX     (1 << 15)
 118 #define I82577_CFG_ENABLE_DOWNSHIFT     (3 << 10) /* auto downshift */
 119 #define I82577_CTRL_REG                 23
 120
 121 /* 82577 specific PHY registers */
 122 #define I82577_PHY_CTRL_2               18
 123 #define I82577_PHY_LBK_CTRL             19
 124 #define I82577_PHY_STATUS_2             26
 125 #define I82577_PHY_DIAG_STATUS          31
 126
 127 /* I82577 PHY Status 2 */
 128 #define I82577_PHY_STATUS2_REV_POLARITY         0x0400
 129 #define I82577_PHY_STATUS2_MDIX                 0x0800
 130 #define I82577_PHY_STATUS2_SPEED_MASK           0x0300
 131 #define I82577_PHY_STATUS2_SPEED_1000MBPS       0x0200
 132
 133 /* I82577 PHY Control 2 */
 134 #define I82577_PHY_CTRL2_MANUAL_MDIX            0x0200
 135 #define I82577_PHY_CTRL2_AUTO_MDI_MDIX          0x0400
 136 #define I82577_PHY_CTRL2_MDIX_CFG_MASK          0x0600
 137
 138 /* I82577 PHY Diagnostics Status */
 139 #define I82577_DSTATUS_CABLE_LENGTH             0x03FC
 140 #define I82577_DSTATUS_CABLE_LENGTH_SHIFT       2
 141
 142 /* 82580 PHY Power Management */
 143 #define E1000_82580_PHY_POWER_MGMT      0xE14
 144 #define E1000_82580_PM_SPD              0x0001 /* Smart Power Down */
 145 #define E1000_82580_PM_D0_LPLU          0x0002 /* For D0a states */
 146 #define E1000_82580_PM_D3_LPLU          0x0004 /* For all other states */
 147 #define E1000_82580_PM_GO_LINKD         0x0020 /* Go Link Disconnect */
 148
 149 #define E1000_MPHY_DIS_ACCESS           0x80000000 /* disable_access bit */
 150 #define E1000_MPHY_ENA_ACCESS           0x40000000 /* enable_access bit */
 151 #define E1000_MPHY_BUSY                 0x00010000 /* busy bit */
 152 #define E1000_MPHY_ADDRESS_FNC_OVERRIDE 0x20000000 /* fnc_override bit */
 153 #define E1000_MPHY_ADDRESS_MASK         0x0000FFFF /* address mask */
 154
 155 #define IGP01E1000_PHY_PCS_INIT_REG     0x00B4
 156 #define IGP01E1000_PHY_POLARITY_MASK    0x0078
 157
 158 #define IGP01E1000_PSCR_AUTO_MDIX       0x1000
 159 #define IGP01E1000_PSCR_FORCE_MDI_MDIX  0x2000 /* 0=MDI, 1=MDIX */
 160
 161 #define IGP01E1000_PSCFR_SMART_SPEED    0x0080
 162
 163 #define IGP02E1000_PM_SPD               0x0001 /* Smart Power Down */
 164 #define IGP02E1000_PM_D0_LPLU           0x0002 /* For D0a states */
 165 #define IGP02E1000_PM_D3_LPLU           0x0004 /* For all other states */
 166
 167 #define IGP01E1000_PLHR_SS_DOWNGRADE    0x8000
 168
 169 #define IGP01E1000_PSSR_POLARITY_REVERSED       0x0002
 170 #define IGP01E1000_PSSR_MDIX            0x0800
 171 #define IGP01E1000_PSSR_SPEED_MASK      0xC000
 172 #define IGP01E1000_PSSR_SPEED_1000MBPS  0xC000
 173
 174 #define IGP02E1000_PHY_CHANNEL_NUM      4
 175 #define IGP02E1000_PHY_AGC_A            0x11B1
 176 #define IGP02E1000_PHY_AGC_B            0x12B1
 177 #define IGP02E1000_PHY_AGC_C            0x14B1
 178 #define IGP02E1000_PHY_AGC_D            0x18B1
 179
 180 #define IGP02E1000_AGC_LENGTH_SHIFT     9   /* Course=15:13, Fine=12:9 */
 181 #define IGP02E1000_AGC_LENGTH_MASK      0x7F
 182 #define IGP02E1000_AGC_RANGE            15
 183
 184 #define E1000_CABLE_LENGTH_UNDEFINED    0xFF
 185
 186 #define E1000_KMRNCTRLSTA_OFFSET        0x001F0000
 187 #define E1000_KMRNCTRLSTA_OFFSET_SHIFT  16
 188 #define E1000_KMRNCTRLSTA_REN           0x00200000
 189 #define E1000_KMRNCTRLSTA_DIAG_OFFSET   0x3    /* Kumeran Diagnostic */
 190 #define E1000_KMRNCTRLSTA_TIMEOUTS      0x4    /* Kumeran Timeouts */
 191 #define E1000_KMRNCTRLSTA_INBAND_PARAM  0x9    /* Kumeran InBand Parameters */
 192 #define E1000_KMRNCTRLSTA_IBIST_DISABLE 0x0200 /* Kumeran IBIST Disable */
 193 #define E1000_KMRNCTRLSTA_DIAG_NELPBK   0x1000 /* Nearend Loopback mode */
 194
 195 #define IFE_PHY_EXTENDED_STATUS_CONTROL 0x10
 196 #define IFE_PHY_SPECIAL_CONTROL         0x11 /* 100BaseTx PHY Special Ctrl */
 197 #define IFE_PHY_SPECIAL_CONTROL_LED     0x1B /* PHY Special and LED Ctrl */
 198 #define IFE_PHY_MDIX_CONTROL            0x1C /* MDI/MDI-X Control */
 199
 200 /* IFE PHY Extended Status Control */
 201 #define IFE_PESC_POLARITY_REVERSED      0x0100
 202
 203 /* IFE PHY Special Control */
 204 #define IFE_PSC_AUTO_POLARITY_DISABLE   0x0010
 205 #define IFE_PSC_FORCE_POLARITY          0x0020
 206
 207 /* IFE PHY Special Control and LED Control */
 208 #define IFE_PSCL_PROBE_MODE             0x0020
 209 #define IFE_PSCL_PROBE_LEDS_OFF         0x0006 /* Force LEDs 0 and 2 off */
 210 #define IFE_PSCL_PROBE_LEDS_ON          0x0007 /* Force LEDs 0 and 2 on */
 211
 212 /* IFE PHY MDIX Control */
 213 #define IFE_PMC_MDIX_STATUS             0x0020 /* 1=MDI-X, 0=MDI */
 214 #define IFE_PMC_FORCE_MDIX              0x0040 /* 1=force MDI-X, 0=force MDI */
 215 #define IFE_PMC_AUTO_MDIX               0x0080 /* 1=enable auto, 0=disable */
 216
 217 /* SFP modules ID memory locations */
 218 #define E1000_SFF_IDENTIFIER_OFFSET     0x00
 219 #define E1000_SFF_IDENTIFIER_SFF        0x02
 220 #define E1000_SFF_IDENTIFIER_SFP        0x03
 221
 222 #define E1000_SFF_ETH_FLAGS_OFFSET      0x06
 223 /* Flags for SFP modules compatible with ETH up to 1Gb */
 224 struct sfp_e1000_flags {
 225         u8 e1000_base_sx:1;
 226         u8 e1000_base_lx:1;
 227         u8 e1000_base_cx:1;
 228         u8 e1000_base_t:1;
 229         u8 e100_base_lx:1;
 230         u8 e100_base_fx:1;
 231         u8 e10_base_bx10:1;
 232         u8 e10_base_px:1;
 233 };
 234
 235 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
 236 #define E1000_SFF_VENDOR_OUI_TYCO       0x00407600
 237 #define E1000_SFF_VENDOR_OUI_FTL        0x00906500
 238 #define E1000_SFF_VENDOR_OUI_AVAGO      0x00176A00
 239 #define E1000_SFF_VENDOR_OUI_INTEL      0x001B2100
 240
 241 #endif