ceph/src/spdk/dpdk/kernel/linux/kni/ethtool/ixgbe/ixgbe_phy.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 /*******************************************************************************
   3
   4   Intel 10 Gigabit PCI Express Linux driver
   5   Copyright(c) 1999 - 2012 Intel Corporation.
   6
   7   Contact Information:
   8   e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
   9   Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  10
  11 *******************************************************************************/
  12
  13 #ifndef _IXGBE_PHY_H_
  14 #define _IXGBE_PHY_H_
  15
  16 #include "ixgbe_type.h"
  17 #define IXGBE_I2C_EEPROM_DEV_ADDR    0xA0
  18
  19 /* EEPROM byte offsets */
  20 #define IXGBE_SFF_IDENTIFIER            0x0
  21 #define IXGBE_SFF_IDENTIFIER_SFP        0x3
  22 #define IXGBE_SFF_VENDOR_OUI_BYTE0      0x25
  23 #define IXGBE_SFF_VENDOR_OUI_BYTE1      0x26
  24 #define IXGBE_SFF_VENDOR_OUI_BYTE2      0x27
  25 #define IXGBE_SFF_1GBE_COMP_CODES       0x6
  26 #define IXGBE_SFF_10GBE_COMP_CODES      0x3
  27 #define IXGBE_SFF_CABLE_TECHNOLOGY      0x8
  28 #define IXGBE_SFF_CABLE_SPEC_COMP       0x3C
  29
  30 /* Bitmasks */
  31 #define IXGBE_SFF_DA_PASSIVE_CABLE      0x4
  32 #define IXGBE_SFF_DA_ACTIVE_CABLE       0x8
  33 #define IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING       0x4
  34 #define IXGBE_SFF_1GBASESX_CAPABLE      0x1
  35 #define IXGBE_SFF_1GBASELX_CAPABLE      0x2
  36 #define IXGBE_SFF_1GBASET_CAPABLE       0x8
  37 #define IXGBE_SFF_10GBASESR_CAPABLE     0x10
  38 #define IXGBE_SFF_10GBASELR_CAPABLE     0x20
  39 #define IXGBE_I2C_EEPROM_READ_MASK      0x100
  40 #define IXGBE_I2C_EEPROM_STATUS_MASK    0x3
  41 #define IXGBE_I2C_EEPROM_STATUS_NO_OPERATION    0x0
  42 #define IXGBE_I2C_EEPROM_STATUS_PASS    0x1
  43 #define IXGBE_I2C_EEPROM_STATUS_FAIL    0x2
  44 #define IXGBE_I2C_EEPROM_STATUS_IN_PROGRESS     0x3
  45
  46 /* Flow control defines */
  47 #define IXGBE_TAF_SYM_PAUSE             0x400
  48 #define IXGBE_TAF_ASM_PAUSE             0x800
  49
  50 /* Bit-shift macros */
  51 #define IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT        24
  52 #define IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT        16
  53 #define IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT        8
  54
  55 /* Vendor OUIs: format of OUI is 0x[byte0][byte1][byte2][00] */
  56 #define IXGBE_SFF_VENDOR_OUI_TYCO       0x00407600
  57 #define IXGBE_SFF_VENDOR_OUI_FTL        0x00906500
  58 #define IXGBE_SFF_VENDOR_OUI_AVAGO      0x00176A00
  59 #define IXGBE_SFF_VENDOR_OUI_INTEL      0x001B2100
  60
  61 /* I2C SDA and SCL timing parameters for standard mode */
  62 #define IXGBE_I2C_T_HD_STA      4
  63 #define IXGBE_I2C_T_LOW         5
  64 #define IXGBE_I2C_T_HIGH        4
  65 #define IXGBE_I2C_T_SU_STA      5
  66 #define IXGBE_I2C_T_HD_DATA     5
  67 #define IXGBE_I2C_T_SU_DATA     1
  68 #define IXGBE_I2C_T_RISE        1
  69 #define IXGBE_I2C_T_FALL        1
  70 #define IXGBE_I2C_T_SU_STO      4
  71 #define IXGBE_I2C_T_BUF         5
  72
  73 #define IXGBE_TN_LASI_STATUS_REG        0x9005
  74 #define IXGBE_TN_LASI_STATUS_TEMP_ALARM 0x0008
  75
  76 s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw);
  77 bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr);
  78 enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id);
  79 s32 ixgbe_get_phy_id(struct ixgbe_hw *hw);
  80 s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw);
  81 s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw);
  82 s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
  83                                u32 device_type, u16 *phy_data);
  84 s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr,
  85                                 u32 device_type, u16 phy_data);
  86 s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw);
  87 s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw,
  88                                        ixgbe_link_speed speed,
  89                                        bool autoneg,
  90                                        bool autoneg_wait_to_complete);
  91 s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw,
  92                                                ixgbe_link_speed *speed,
  93                                                bool *autoneg);
  94
  95 /* PHY specific */
  96 s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw,
  97                              ixgbe_link_speed *speed,
  98                              bool *link_up);
  99 s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw);
 100 s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw,
 101                                        u16 *firmware_version);
 102 s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw,
 103                                            u16 *firmware_version);
 104
 105 s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw);
 106 s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw);
 107 s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw);
 108 s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw);
 109 s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw,
 110                                         u16 *list_offset,
 111                                         u16 *data_offset);
 112 s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw);
 113 s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 114                                 u8 dev_addr, u8 *data);
 115 s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset,
 116                                  u8 dev_addr, u8 data);
 117 s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 118                                   u8 *eeprom_data);
 119 s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset,
 120                                    u8 eeprom_data);
 121 void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw);
 122 #endif /* _IXGBE_PHY_H_ */