ceph/src/spdk/dpdk/lib/librte_eal/common/include/arch/arm/rte_atomic_32.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2015 RehiveTech. All rights reserved.
   3  */
   4
   5 #ifndef _RTE_ATOMIC_ARM32_H_
   6 #define _RTE_ATOMIC_ARM32_H_
   7
   8 #ifndef RTE_FORCE_INTRINSICS
   9 #  error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
  10 #endif
  11
  12 #ifdef __cplusplus
  13 extern "C" {
  14 #endif
  15
  16 #include "generic/rte_atomic.h"
  17
  18 /**
  19  * General memory barrier.
  20  *
  21  * Guarantees that the LOAD and STORE operations generated before the
  22  * barrier occur before the LOAD and STORE operations generated after.
  23  */
  24 #define rte_mb()  __sync_synchronize()
  25
  26 /**
  27  * Write memory barrier.
  28  *
  29  * Guarantees that the STORE operations generated before the barrier
  30  * occur before the STORE operations generated after.
  31  */
  32 #define rte_wmb() do { asm volatile ("dmb st" : : : "memory"); } while (0)
  33
  34 /**
  35  * Read memory barrier.
  36  *
  37  * Guarantees that the LOAD operations generated before the barrier
  38  * occur before the LOAD operations generated after.
  39  */
  40 #define rte_rmb() __sync_synchronize()
  41
  42 #define rte_smp_mb() rte_mb()
  43
  44 #define rte_smp_wmb() rte_wmb()
  45
  46 #define rte_smp_rmb() rte_rmb()
  47
  48 #define rte_io_mb() rte_mb()
  49
  50 #define rte_io_wmb() rte_wmb()
  51
  52 #define rte_io_rmb() rte_rmb()
  53
  54 #define rte_cio_wmb() rte_wmb()
  55
  56 #define rte_cio_rmb() rte_rmb()
  57
  58 #ifdef __cplusplus
  59 }
  60 #endif
  61
  62 #endif /* _RTE_ATOMIC_ARM32_H_ */