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20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 * Inspired from FreeBSD src/sys/powerpc/include/atomic.h
35 * Copyright (c) 2008 Marcel Moolenaar
36 * Copyright (c) 2001 Benno Rice
37 * Copyright (c) 2001 David E. O'Brien
38 * Copyright (c) 1998 Doug Rabson
39 * All rights reserved.
42 #ifndef _RTE_ATOMIC_PPC_64_H_
43 #define _RTE_ATOMIC_PPC_64_H_
50 #include "generic/rte_atomic.h"
53 * General memory barrier.
55 * Guarantees that the LOAD and STORE operations generated before the
56 * barrier occur before the LOAD and STORE operations generated after.
58 #define rte_mb() asm volatile("sync" : : : "memory")
61 * Write memory barrier.
63 * Guarantees that the STORE operations generated before the barrier
64 * occur before the STORE operations generated after.
67 #define rte_wmb() asm volatile("lwsync" : : : "memory")
69 #define rte_wmb() asm volatile("sync" : : : "memory")
73 * Read memory barrier.
75 * Guarantees that the LOAD operations generated before the barrier
76 * occur before the LOAD operations generated after.
79 #define rte_rmb() asm volatile("lwsync" : : : "memory")
81 #define rte_rmb() asm volatile("sync" : : : "memory")
84 #define rte_smp_mb() rte_mb()
86 #define rte_smp_wmb() rte_wmb()
88 #define rte_smp_rmb() rte_rmb()
90 #define rte_io_mb() rte_mb()
92 #define rte_io_wmb() rte_wmb()
94 #define rte_io_rmb() rte_rmb()
96 #define rte_cio_wmb() rte_wmb()
98 #define rte_cio_rmb() rte_rmb()
100 /*------------------------- 16 bit atomic operations -------------------------*/
101 /* To be compatible with Power7, use GCC built-in functions for 16 bit
104 #ifndef RTE_FORCE_INTRINSICS
106 rte_atomic16_cmpset(volatile uint16_t *dst
, uint16_t exp
, uint16_t src
)
108 return __atomic_compare_exchange(dst
, &exp
, &src
, 0, __ATOMIC_ACQUIRE
,
109 __ATOMIC_ACQUIRE
) ? 1 : 0;
112 static inline int rte_atomic16_test_and_set(rte_atomic16_t
*v
)
114 return rte_atomic16_cmpset((volatile uint16_t *)&v
->cnt
, 0, 1);
118 rte_atomic16_inc(rte_atomic16_t
*v
)
120 __atomic_add_fetch(&v
->cnt
, 1, __ATOMIC_ACQUIRE
);
124 rte_atomic16_dec(rte_atomic16_t
*v
)
126 __atomic_sub_fetch(&v
->cnt
, 1, __ATOMIC_ACQUIRE
);
129 static inline int rte_atomic16_inc_and_test(rte_atomic16_t
*v
)
131 return __atomic_add_fetch(&v
->cnt
, 1, __ATOMIC_ACQUIRE
) == 0;
134 static inline int rte_atomic16_dec_and_test(rte_atomic16_t
*v
)
136 return __atomic_sub_fetch(&v
->cnt
, 1, __ATOMIC_ACQUIRE
) == 0;
139 static inline uint16_t
140 rte_atomic16_exchange(volatile uint16_t *dst
, uint16_t val
)
142 return __atomic_exchange_2(dst
, val
, __ATOMIC_SEQ_CST
);
145 /*------------------------- 32 bit atomic operations -------------------------*/
148 rte_atomic32_cmpset(volatile uint32_t *dst
, uint32_t exp
, uint32_t src
)
150 unsigned int ret
= 0;
154 "1:\tlwarx %[ret], 0, %[dst]\n"
155 "cmplw %[exp], %[ret]\n"
157 "stwcx. %[src], 0, %[dst]\n"
162 "stwcx. %[ret], 0, %[dst]\n"
166 : [ret
] "=&r" (ret
), "=m" (*dst
)
176 static inline int rte_atomic32_test_and_set(rte_atomic32_t
*v
)
178 return rte_atomic32_cmpset((volatile uint32_t *)&v
->cnt
, 0, 1);
182 rte_atomic32_inc(rte_atomic32_t
*v
)
187 "1: lwarx %[t],0,%[cnt]\n"
188 "addic %[t],%[t],1\n"
189 "stwcx. %[t],0,%[cnt]\n"
191 : [t
] "=&r" (t
), "=m" (v
->cnt
)
192 : [cnt
] "r" (&v
->cnt
), "m" (v
->cnt
)
193 : "cc", "xer", "memory");
197 rte_atomic32_dec(rte_atomic32_t
*v
)
202 "1: lwarx %[t],0,%[cnt]\n"
203 "addic %[t],%[t],-1\n"
204 "stwcx. %[t],0,%[cnt]\n"
206 : [t
] "=&r" (t
), "=m" (v
->cnt
)
207 : [cnt
] "r" (&v
->cnt
), "m" (v
->cnt
)
208 : "cc", "xer", "memory");
211 static inline int rte_atomic32_inc_and_test(rte_atomic32_t
*v
)
217 "1: lwarx %[ret],0,%[cnt]\n"
218 "addic %[ret],%[ret],1\n"
219 "stwcx. %[ret],0,%[cnt]\n"
223 : [cnt
] "r" (&v
->cnt
)
224 : "cc", "xer", "memory");
229 static inline int rte_atomic32_dec_and_test(rte_atomic32_t
*v
)
235 "1: lwarx %[ret],0,%[cnt]\n"
236 "addic %[ret],%[ret],-1\n"
237 "stwcx. %[ret],0,%[cnt]\n"
241 : [cnt
] "r" (&v
->cnt
)
242 : "cc", "xer", "memory");
247 static inline uint32_t
248 rte_atomic32_exchange(volatile uint32_t *dst
, uint32_t val
)
250 return __atomic_exchange_4(dst
, val
, __ATOMIC_SEQ_CST
);
253 /*------------------------- 64 bit atomic operations -------------------------*/
256 rte_atomic64_cmpset(volatile uint64_t *dst
, uint64_t exp
, uint64_t src
)
258 unsigned int ret
= 0;
262 "1: ldarx %[ret], 0, %[dst]\n"
263 "cmpld %[exp], %[ret]\n"
265 "stdcx. %[src], 0, %[dst]\n"
270 "stdcx. %[ret], 0, %[dst]\n"
274 : [ret
] "=&r" (ret
), "=m" (*dst
)
284 rte_atomic64_init(rte_atomic64_t
*v
)
289 static inline int64_t
290 rte_atomic64_read(rte_atomic64_t
*v
)
294 asm volatile("ld%U1%X1 %[ret],%[cnt]"
296 : [cnt
] "m"(v
->cnt
));
302 rte_atomic64_set(rte_atomic64_t
*v
, int64_t new_value
)
304 asm volatile("std%U0%X0 %[new_value],%[cnt]"
306 : [new_value
] "r"(new_value
));
310 rte_atomic64_add(rte_atomic64_t
*v
, int64_t inc
)
315 "1: ldarx %[t],0,%[cnt]\n"
316 "add %[t],%[inc],%[t]\n"
317 "stdcx. %[t],0,%[cnt]\n"
319 : [t
] "=&r" (t
), "=m" (v
->cnt
)
320 : [cnt
] "r" (&v
->cnt
), [inc
] "r" (inc
), "m" (v
->cnt
)
325 rte_atomic64_sub(rte_atomic64_t
*v
, int64_t dec
)
330 "1: ldarx %[t],0,%[cnt]\n"
331 "subf %[t],%[dec],%[t]\n"
332 "stdcx. %[t],0,%[cnt]\n"
334 : [t
] "=&r" (t
), "+m" (v
->cnt
)
335 : [cnt
] "r" (&v
->cnt
), [dec
] "r" (dec
), "m" (v
->cnt
)
340 rte_atomic64_inc(rte_atomic64_t
*v
)
345 "1: ldarx %[t],0,%[cnt]\n"
346 "addic %[t],%[t],1\n"
347 "stdcx. %[t],0,%[cnt]\n"
349 : [t
] "=&r" (t
), "+m" (v
->cnt
)
350 : [cnt
] "r" (&v
->cnt
), "m" (v
->cnt
)
351 : "cc", "xer", "memory");
355 rte_atomic64_dec(rte_atomic64_t
*v
)
360 "1: ldarx %[t],0,%[cnt]\n"
361 "addic %[t],%[t],-1\n"
362 "stdcx. %[t],0,%[cnt]\n"
364 : [t
] "=&r" (t
), "+m" (v
->cnt
)
365 : [cnt
] "r" (&v
->cnt
), "m" (v
->cnt
)
366 : "cc", "xer", "memory");
369 static inline int64_t
370 rte_atomic64_add_return(rte_atomic64_t
*v
, int64_t inc
)
376 "1: ldarx %[ret],0,%[cnt]\n"
377 "add %[ret],%[inc],%[ret]\n"
378 "stdcx. %[ret],0,%[cnt]\n"
382 : [inc
] "r" (inc
), [cnt
] "r" (&v
->cnt
)
388 static inline int64_t
389 rte_atomic64_sub_return(rte_atomic64_t
*v
, int64_t dec
)
395 "1: ldarx %[ret],0,%[cnt]\n"
396 "subf %[ret],%[dec],%[ret]\n"
397 "stdcx. %[ret],0,%[cnt]\n"
401 : [dec
] "r" (dec
), [cnt
] "r" (&v
->cnt
)
407 static inline int rte_atomic64_inc_and_test(rte_atomic64_t
*v
)
413 "1: ldarx %[ret],0,%[cnt]\n"
414 "addic %[ret],%[ret],1\n"
415 "stdcx. %[ret],0,%[cnt]\n"
419 : [cnt
] "r" (&v
->cnt
)
420 : "cc", "xer", "memory");
425 static inline int rte_atomic64_dec_and_test(rte_atomic64_t
*v
)
431 "1: ldarx %[ret],0,%[cnt]\n"
432 "addic %[ret],%[ret],-1\n"
433 "stdcx. %[ret],0,%[cnt]\n"
437 : [cnt
] "r" (&v
->cnt
)
438 : "cc", "xer", "memory");
443 static inline int rte_atomic64_test_and_set(rte_atomic64_t
*v
)
445 return rte_atomic64_cmpset((volatile uint64_t *)&v
->cnt
, 0, 1);
448 * Atomically set a 64-bit counter to 0.
451 * A pointer to the atomic counter.
453 static inline void rte_atomic64_clear(rte_atomic64_t
*v
)
458 static inline uint64_t
459 rte_atomic64_exchange(volatile uint64_t *dst
, uint64_t val
)
461 return __atomic_exchange_4(dst
, val
, __ATOMIC_SEQ_CST
);
470 #endif /* _RTE_ATOMIC_PPC_64_H_ */