ceph/src/spdk/intel-ipsec-mb/avx512/sha256_x16_avx512.asm

   1 ;;
   2 ;; Copyright (c) 2017-2018, Intel Corporation
   3 ;;
   4 ;; Redistribution and use in source and binary forms, with or without
   5 ;; modification, are permitted provided that the following conditions are met:
   6 ;;
   7 ;;     * Redistributions of source code must retain the above copyright notice,
   8 ;;       this list of conditions and the following disclaimer.
   9 ;;     * Redistributions in binary form must reproduce the above copyright
  10 ;;       notice, this list of conditions and the following disclaimer in the
  11 ;;       documentation and/or other materials provided with the distribution.
  12 ;;     * Neither the name of Intel Corporation nor the names of its contributors
  13 ;;       may be used to endorse or promote products derived from this software
  14 ;;       without specific prior written permission.
  15 ;;
  16 ;; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17 ;; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18 ;; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  19 ;; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
  20 ;; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21 ;; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  22 ;; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  23 ;; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  24 ;; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 ;; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 ;;
  27
  28 ;; Stack must be aligned to 32 bytes before call
  29 ;;
  30 ;; Registers:           RAX RBX RCX RDX RBP RSI RDI R8  R9  R10 R11 R12 R13 R14 R15
  31 ;;                      -----------------------------------------------------------
  32 ;; Windows clobbers:    RAX         RDX     RSI RDI     R9  R10 R11 R12 R13 R14 R15
  33 ;; Windows preserves:           RCX
  34 ;;                      -----------------------------------------------------------
  35 ;; Linux clobbers:      RAX     RCX RDX     RSI         R9  R10 R11 R12 R13 R14 R15
  36 ;; Linux preserves:                             RDI
  37 ;;                      -----------------------------------------------------------
  38 ;; Clobbers ZMM0-31
  39
  40 %include "os.asm"
  41 ;%define DO_DBGPRINT
  42 %include "dbgprint.asm"
  43 %include "mb_mgr_datastruct.asm"
  44
  45 ; re-use K256 from sha256_oct_avx2.asm
  46 extern K256
  47
  48 ;; code to compute x16 SHA256 using AVX512
  49
  50 %macro TRANSPOSE16 18
  51 %define %%r0 %1
  52 %define %%r1 %2
  53 %define %%r2 %3
  54 %define %%r3 %4
  55 %define %%r4 %5
  56 %define %%r5 %6
  57 %define %%r6 %7
  58 %define %%r7 %8
  59 %define %%r8 %9
  60 %define %%r9 %10
  61 %define %%r10 %11
  62 %define %%r11 %12
  63 %define %%r12 %13
  64 %define %%r13 %14
  65 %define %%r14 %15
  66 %define %%r15 %16
  67 %define %%t0 %17
  68 %define %%t1 %18
  69
  70 ; r0  = {a15 a14 a13 a12   a11 a10 a9 a8   a7 a6 a5 a4   a3 a2 a1 a0}
  71 ; r1  = {b15 b14 b13 b12   b11 b10 b9 b8   b7 b6 b5 b4   b3 b2 b1 b0}
  72 ; r2  = {c15 c14 c13 c12   c11 c10 c9 c8   c7 c6 c5 c4   c3 c2 c1 c0}
  73 ; r3  = {d15 d14 d13 d12   d11 d10 d9 d8   d7 d6 d5 d4   d3 d2 d1 d0}
  74 ; r4  = {e15 e14 e13 e12   e11 e10 e9 e8   e7 e6 e5 e4   e3 e2 e1 e0}
  75 ; r5  = {f15 f14 f13 f12   f11 f10 f9 f8   f7 f6 f5 f4   f3 f2 f1 f0}
  76 ; r6  = {g15 g14 g13 g12   g11 g10 g9 g8   g7 g6 g5 g4   g3 g2 g1 g0}
  77 ; r7  = {h15 h14 h13 h12   h11 h10 h9 h8   h7 h6 h5 h4   h3 h2 h1 h0}
  78 ; r8  = {i15 i14 i13 i12   i11 i10 i9 i8   i7 i6 i5 i4   i3 i2 i1 i0}
  79 ; r9  = {j15 j14 j13 j12   j11 j10 j9 j8   j7 j6 j5 j4   j3 j2 j1 j0}
  80 ; r10 = {k15 k14 k13 k12   k11 k10 k9 k8   k7 k6 k5 k4   k3 k2 k1 k0}
  81 ; r11 = {l15 l14 l13 l12   l11 l10 l9 l8   l7 l6 l5 l4   l3 l2 l1 l0}
  82 ; r12 = {m15 m14 m13 m12   m11 m10 m9 m8   m7 m6 m5 m4   m3 m2 m1 m0}
  83 ; r13 = {n15 n14 n13 n12   n11 n10 n9 n8   n7 n6 n5 n4   n3 n2 n1 n0}
  84 ; r14 = {o15 o14 o13 o12   o11 o10 o9 o8   o7 o6 o5 o4   o3 o2 o1 o0}
  85 ; r15 = {p15 p14 p13 p12   p11 p10 p9 p8   p7 p6 p5 p4   p3 p2 p1 p0}
  86
  87 ; r0   = {p0  o0  n0  m0    l0  k0  j0  i0    h0  g0  f0  e0    d0  c0  b0  a0}
  88 ; r1   = {p1  o1  n1  m1    l1  k1  j1  i1    h1  g1  f1  e1    d1  c1  b1  a1}
  89 ; r2   = {p2  o2  n2  m2    l2  k2  j2  i2    h2  g2  f2  e2    d2  c2  b2  a2}
  90 ; r3   = {p3  o3  n3  m3    l3  k3  j3  i3    h3  g3  f3  e3    d3  c3  b3  a3}
  91 ; r4   = {p4  o4  n4  m4    l4  k4  j4  i4    h4  g4  f4  e4    d4  c4  b4  a4}
  92 ; r5   = {p5  o5  n5  m5    l5  k5  j5  i5    h5  g5  f5  e5    d5  c5  b5  a5}
  93 ; r6   = {p6  o6  n6  m6    l6  k6  j6  i6    h6  g6  f6  e6    d6  c6  b6  a6}
  94 ; r7   = {p7  o7  n7  m7    l7  k7  j7  i7    h7  g7  f7  e7    d7  c7  b7  a7}
  95 ; r8   = {p8  o8  n8  m8    l8  k8  j8  i8    h8  g8  f8  e8    d8  c8  b8  a8}
  96 ; r9   = {p9  o9  n9  m9    l9  k9  j9  i9    h9  g9  f9  e9    d9  c9  b9  a9}
  97 ; r10  = {p10 o10 n10 m10   l10 k10 j10 i10   h10 g10 f10 e10   d10 c10 b10 a10}
  98 ; r11  = {p11 o11 n11 m11   l11 k11 j11 i11   h11 g11 f11 e11   d11 c11 b11 a11}
  99 ; r12  = {p12 o12 n12 m12   l12 k12 j12 i12   h12 g12 f12 e12   d12 c12 b12 a12}
 100 ; r13  = {p13 o13 n13 m13   l13 k13 j13 i13   h13 g13 f13 e13   d13 c13 b13 a13}
 101 ; r14  = {p14 o14 n14 m14   l14 k14 j14 i14   h14 g14 f14 e14   d14 c14 b14 a14}
 102 ; r15  = {p15 o15 n15 m15   l15 k15 j15 i15   h15 g15 f15 e15   d15 c15 b15 a15}
 103
 104
 105         ; process top half (r0..r3) {a...d}
 106         vshufps %%t0, %%r0, %%r1, 0x44  ; t0 = {b13 b12 a13 a12   b9  b8  a9  a8   b5 b4 a5 a4   b1 b0 a1 a0}
 107         vshufps %%r0, %%r0, %%r1, 0xEE  ; r0 = {b15 b14 a15 a14   b11 b10 a11 a10  b7 b6 a7 a6   b3 b2 a3 a2}
 108         vshufps %%t1, %%r2, %%r3, 0x44  ; t1 = {d13 d12 c13 c12   d9  d8  c9  c8   d5 d4 c5 c4   d1 d0 c1 c0}
 109         vshufps %%r2, %%r2, %%r3, 0xEE  ; r2 = {d15 d14 c15 c14   d11 d10 c11 c10  d7 d6 c7 c6   d3 d2 c3 c2}
 110
 111         vshufps %%r3, %%t0, %%t1, 0xDD  ; r3 = {d13 c13 b13 a13   d9  c9  b9  a9   d5 c5 b5 a5   d1 c1 b1 a1}
 112         vshufps %%r1, %%r0, %%r2, 0x88  ; r1 = {d14 c14 b14 a14   d10 c10 b10 a10  d6 c6 b6 a6   d2 c2 b2 a2}
 113         vshufps %%r0, %%r0, %%r2, 0xDD  ; r0 = {d15 c15 b15 a15   d11 c11 b11 a11  d7 c7 b7 a7   d3 c3 b3 a3}
 114         vshufps %%t0, %%t0, %%t1, 0x88  ; t0 = {d12 c12 b12 a12   d8  c8  b8  a8   d4 c4 b4 a4   d0 c0 b0 a0}
 115
 116         ; use r2 in place of t0
 117         vshufps %%r2, %%r4, %%r5, 0x44  ; r2 = {f13 f12 e13 e12   f9  f8  e9  e8   f5 f4 e5 e4   f1 f0 e1 e0}
 118         vshufps %%r4, %%r4, %%r5, 0xEE  ; r4 = {f15 f14 e15 e14   f11 f10 e11 e10  f7 f6 e7 e6   f3 f2 e3 e2}
 119         vshufps %%t1, %%r6, %%r7, 0x44  ; t1 = {h13 h12 g13 g12   h9  h8  g9  g8   h5 h4 g5 g4   h1 h0 g1 g0}
 120         vshufps %%r6, %%r6, %%r7, 0xEE  ; r6 = {h15 h14 g15 g14   h11 h10 g11 g10  h7 h6 g7 g6   h3 h2 g3 g2}
 121
 122         vshufps %%r7, %%r2, %%t1, 0xDD  ; r7 = {h13 g13 f13 e13   h9  g9  f9  e9   h5 g5 f5 e5   h1 g1 f1 e1}
 123         vshufps %%r5, %%r4, %%r6, 0x88  ; r5 = {h14 g14 f14 e14   h10 g10 f10 e10  h6 g6 f6 e6   h2 g2 f2 e2}
 124         vshufps %%r4, %%r4, %%r6, 0xDD  ; r4 = {h15 g15 f15 e15   h11 g11 f11 e11  h7 g7 f7 e7   h3 g3 f3 e3}
 125         vshufps %%r2, %%r2, %%t1, 0x88  ; r2 = {h12 g12 f12 e12   h8  g8  f8  e8   h4 g4 f4 e4   h0 g0 f0 e0}
 126
 127         ; use r6 in place of t0
 128         vshufps %%r6, %%r8, %%r9,    0x44       ; r6  = {j13 j12 i13 i12   j9  j8  i9  i8   j5 j4 i5 i4   j1 j0 i1 i0}
 129         vshufps %%r8, %%r8, %%r9,    0xEE       ; r8  = {j15 j14 i15 i14   j11 j10 i11 i10  j7 j6 i7 i6   j3 j2 i3 i2}
 130         vshufps %%t1, %%r10, %%r11,  0x44       ; t1  = {l13 l12 k13 k12   l9  l8  k9  k8   l5 l4 k5 k4   l1 l0 k1 k0}
 131         vshufps %%r10, %%r10, %%r11, 0xEE       ; r10 = {l15 l14 k15 k14   l11 l10 k11 k10  l7 l6 k7 k6   l3 l2 k3 k2}
 132
 133         vshufps %%r11, %%r6, %%t1, 0xDD         ; r11 = {l13 k13 j13 113   l9  k9  j9  i9   l5 k5 j5 i5   l1 k1 j1 i1}
 134         vshufps %%r9, %%r8, %%r10, 0x88         ; r9  = {l14 k14 j14 114   l10 k10 j10 i10  l6 k6 j6 i6   l2 k2 j2 i2}
 135         vshufps %%r8, %%r8, %%r10, 0xDD         ; r8  = {l15 k15 j15 115   l11 k11 j11 i11  l7 k7 j7 i7   l3 k3 j3 i3}
 136         vshufps %%r6, %%r6, %%t1,  0x88         ; r6  = {l12 k12 j12 112   l8  k8  j8  i8   l4 k4 j4 i4   l0 k0 j0 i0}
 137
 138         ; use r10 in place of t0
 139         vshufps %%r10, %%r12, %%r13, 0x44       ; r10 = {n13 n12 m13 m12   n9  n8  m9  m8   n5 n4 m5 m4   n1 n0 a1 m0}
 140         vshufps %%r12, %%r12, %%r13, 0xEE       ; r12 = {n15 n14 m15 m14   n11 n10 m11 m10  n7 n6 m7 m6   n3 n2 a3 m2}
 141         vshufps %%t1, %%r14, %%r15,  0x44       ; t1  = {p13 p12 013 012   p9  p8  09  08   p5 p4 05 04   p1 p0 01 00}
 142         vshufps %%r14, %%r14, %%r15, 0xEE       ; r14 = {p15 p14 015 014   p11 p10 011 010  p7 p6 07 06   p3 p2 03 02}
 143
 144         vshufps %%r15, %%r10, %%t1,  0xDD       ; r15 = {p13 013 n13 m13   p9  09  n9  m9   p5 05 n5 m5   p1 01 n1 m1}
 145         vshufps %%r13, %%r12, %%r14, 0x88       ; r13 = {p14 014 n14 m14   p10 010 n10 m10  p6 06 n6 m6   p2 02 n2 m2}
 146         vshufps %%r12, %%r12, %%r14, 0xDD       ; r12 = {p15 015 n15 m15   p11 011 n11 m11  p7 07 n7 m7   p3 03 n3 m3}
 147         vshufps %%r10, %%r10, %%t1,  0x88       ; r10 = {p12 012 n12 m12   p8  08  n8  m8   p4 04 n4 m4   p0 00 n0 m0}
 148
 149 ;; At this point, the registers that contain interesting data are:
 150 ;; t0, r3, r1, r0, r2, r7, r5, r4, r6, r11, r9, r8, r10, r15, r13, r12
 151 ;; Can use t1 and r14 as scratch registers
 152
 153         vmovdqa32 %%r14, [PSHUFFLE_TRANSPOSE16_MASK1]
 154         vpermi2q  %%r14, %%t0, %%r2             ; r14 = {h8  g8  f8  e8   d8  c8  b8  a8   h0 g0 f0 e0   d0 c0 b0 a0}
 155         vmovdqa32 %%t1,  [PSHUFFLE_TRANSPOSE16_MASK2]
 156         vpermi2q  %%t1,  %%t0, %%r2             ; t1  = {h12 g12 f12 e12  d12 c12 b12 a12  h4 g4 f4 e4   d4 c4 b4 a4}
 157
 158         vmovdqa32 %%r2, [PSHUFFLE_TRANSPOSE16_MASK1]
 159         vpermi2q  %%r2, %%r3, %%r7              ; r2  = {h9  g9  f9  e9   d9  c9  b9  a9   h1 g1 f1 e1   d1 c1 b1 a1}
 160         vmovdqa32 %%t0, [PSHUFFLE_TRANSPOSE16_MASK2]
 161         vpermi2q  %%t0, %%r3, %%r7              ; t0  = {h13 g13 f13 e13  d13 c13 b13 a13  h5 g5 f5 e5   d5 c5 b5 a5}
 162
 163         vmovdqa32 %%r3, [PSHUFFLE_TRANSPOSE16_MASK1]
 164         vpermi2q  %%r3, %%r1, %%r5              ; r3  = {h10 g10 f10 e10  d10 c10 b10 a10  h2 g2 f2 e2   d2 c2 b2 a2}
 165         vmovdqa32 %%r7, [PSHUFFLE_TRANSPOSE16_MASK2]
 166         vpermi2q  %%r7, %%r1, %%r5              ; r7  = {h14 g14 f14 e14  d14 c14 b14 a14  h6 g6 f6 e6   d6 c6 b6 a6}
 167
 168         vmovdqa32 %%r1, [PSHUFFLE_TRANSPOSE16_MASK1]
 169         vpermi2q  %%r1, %%r0, %%r4              ; r1  = {h11 g11 f11 e11  d11 c11 b11 a11  h3 g3 f3 e3   d3 c3 b3 a3}
 170         vmovdqa32 %%r5, [PSHUFFLE_TRANSPOSE16_MASK2]
 171         vpermi2q  %%r5, %%r0, %%r4              ; r5  = {h15 g15 f15 e15  d15 c15 b15 a15  h7 g7 f7 e7   d7 c7 b7 a7}
 172
 173         vmovdqa32 %%r0, [PSHUFFLE_TRANSPOSE16_MASK1]
 174         vpermi2q  %%r0, %%r6, %%r10             ; r0 = {p8  o8  n8  m8   l8  k8  j8  i8   p0 o0 n0 m0    l0 k0 j0 i0}
 175         vmovdqa32 %%r4,  [PSHUFFLE_TRANSPOSE16_MASK2]
 176         vpermi2q  %%r4, %%r6, %%r10             ; r4  = {p12 o12 n12 m12  l12 k12 j12 i12  p4 o4 n4 m4   l4 k4 j4 i4}
 177
 178         vmovdqa32 %%r6, [PSHUFFLE_TRANSPOSE16_MASK1]
 179         vpermi2q  %%r6, %%r11, %%r15            ; r6  = {p9  o9  n9  m9   l9  k9  j9  i9   p1 o1 n1 m1   l1 k1 j1 i1}
 180         vmovdqa32 %%r10, [PSHUFFLE_TRANSPOSE16_MASK2]
 181         vpermi2q  %%r10, %%r11, %%r15           ; r10 = {p13 o13 n13 m13  l13 k13 j13 i13  p5 o5 n5 m5   l5 k5 j5 i5}
 182
 183         vmovdqa32 %%r11, [PSHUFFLE_TRANSPOSE16_MASK1]
 184         vpermi2q  %%r11, %%r9, %%r13            ; r11 = {p10 o10 n10 m10  l10 k10 j10 i10  p2 o2 n2 m2   l2 k2 j2 i2}
 185         vmovdqa32 %%r15, [PSHUFFLE_TRANSPOSE16_MASK2]
 186         vpermi2q  %%r15, %%r9, %%r13            ; r15 = {p14 o14 n14 m14  l14 k14 j14 i14  p6 o6 n6 m6   l6 k6 j6 i6}
 187
 188         vmovdqa32 %%r9, [PSHUFFLE_TRANSPOSE16_MASK1]
 189         vpermi2q  %%r9, %%r8, %%r12             ; r9  = {p11 o11 n11 m11  l11 k11 j11 i11  p3 o3 n3 m3   l3 k3 j3 i3}
 190         vmovdqa32 %%r13, [PSHUFFLE_TRANSPOSE16_MASK2]
 191         vpermi2q  %%r13, %%r8, %%r12            ; r13 = {p15 o15 n15 m15  l15 k15 j15 i15  p7 o7 n7 m7   l7 k7 j7 i7}
 192
 193 ;; At this point r8 and r12 can be used as scratch registers
 194
 195         vshuff64x2 %%r8, %%r14, %%r0, 0xEE      ; r8  = {p8  o8  n8  m8   l8  k8  j8  i8   h8 g8 f8 e8   d8 c8 b8 a8}
 196         vshuff64x2 %%r0, %%r14, %%r0, 0x44      ; r0  = {p0  o0  n0  m0   l0  k0  j0  i0   h0 g0 f0 e0   d0 c0 b0 a0}
 197
 198         vshuff64x2 %%r12, %%t1, %%r4, 0xEE      ; r12 = {p12 o12 n12 m12  l12 k12 j12 i12  h12 g12 f12 e12  d12 c12 b12 a12}
 199         vshuff64x2 %%r4, %%t1, %%r4, 0x44       ; r4  = {p4  o4  n4  m4   l4  k4  j4  i4   h4 g4 f4 e4   d4 c4 b4 a4}
 200
 201         vshuff64x2 %%r14, %%r7, %%r15, 0xEE     ; r14 = {p14 o14 n14 m14  l14 k14 j14 i14  h14 g14 f14 e14  d14 c14 b14 a14}
 202         vshuff64x2 %%t1, %%r7, %%r15, 0x44      ; t1  = {p6  o6  n6  m6   l6  k6  j6  i6   h6 g6 f6 e6   d6 c6 b6 a6}
 203
 204         vshuff64x2 %%r15, %%r5, %%r13, 0xEE     ; r15 = {p15 o15 n15 m15  l15 k15 j15 i15  h15 g15 f15 e15  d15 c15 b15 a15}
 205         vshuff64x2 %%r7, %%r5, %%r13, 0x44      ; r7  = {p7  o7  n7  m7   l7  k7  j7  i7   h7 g7 f7 e7   d7 c7 b7 a7}
 206
 207         vshuff64x2 %%r13, %%t0, %%r10, 0xEE     ; r13 = {p13 o13 n13 m13  l13 k13 j13 i13  h13 g13 f13 e13  d13 c13 b13 a13}
 208         vshuff64x2 %%r5, %%t0, %%r10, 0x44      ; r5  = {p5  o5  n5  m5   l5  k5  j5  i5   h5 g5 f5 e5   d5 c5 b5 a5}
 209
 210         vshuff64x2 %%r10, %%r3, %%r11, 0xEE     ; r10 = {p10 o10 n10 m10  l10 k10 j10 i10  h10 g10 f10 e10  d10 c10 b10 a10}
 211         vshuff64x2 %%t0, %%r3, %%r11, 0x44      ; t0  = {p2  o2  n2  m2   l2  k2  j2  i2   h2 g2 f2 e2   d2 c2 b2 a2}
 212
 213         vshuff64x2 %%r11, %%r1, %%r9, 0xEE      ; r11 = {p11 o11 n11 m11  l11 k11 j11 i11  h11 g11 f11 e11  d11 c11 b11 a11}
 214         vshuff64x2 %%r3, %%r1, %%r9, 0x44       ; r3  = {p3  o3  n3  m3   l3  k3  j3  i3   h3 g3 f3 e3   d3 c3 b3 a3}
 215
 216         vshuff64x2 %%r9, %%r2, %%r6, 0xEE       ; r9  = {p9  o9  n9  m9   l9  k9  j9  i9   h9 g9 f9 e9   d9 c9 b9 a9}
 217         vshuff64x2 %%r1, %%r2, %%r6, 0x44       ; r1  = {p1  o1  n1  m1   l1  k1  j1  i1   h1 g1 f1 e1   d1 c1 b1 a1}
 218
 219         vmovdqa32 %%r2, %%t0                    ; r2  = {p2  o2  n2  m2   l2  k2  j2  i2   h2 g2 f2 e2   d2 c2 b2 a2}
 220         vmovdqa32 %%r6, %%t1                    ; r6  = {p6  o6  n6  m6   l6  k6  j6  i6   h6 g6 f6 e6   d6 c6 b6 a6}
 221 %endmacro
 222
 223 %define APPEND(a,b) a %+ b
 224
 225 ; Define Stack Layout
 226 START_FIELDS
 227 ;;;     name            size    align
 228 FIELD   _DIGEST_SAVE,   8*64,   64
 229 FIELD   _rsp,           8,      8
 230 %assign STACK_SPACE     _FIELD_OFFSET
 231
 232 %ifdef LINUX
 233 ; Linux register definitions
 234      %define arg1       rdi
 235      %define arg2       rsi
 236      %define arg3       rcx
 237      %define arg4       rdx
 238 %else
 239 ; Windows definitions
 240      %define arg1       rcx
 241      %define arg2       rdx
 242      %define arg3       rsi
 243      %define arg4       rdi
 244 %endif
 245
 246 %define STATE           arg1
 247 %define INP_SIZE        arg2
 248 %define IDX             arg3
 249 %define TBL             arg4
 250
 251 %define A       zmm0
 252 %define B       zmm1
 253 %define C       zmm2
 254 %define D       zmm3
 255 %define E       zmm4
 256 %define F       zmm5
 257 %define G       zmm6
 258 %define H       zmm7
 259 %define T1      zmm8
 260 %define TMP0    zmm9
 261 %define TMP1    zmm10
 262 %define TMP2    zmm11
 263 %define TMP3    zmm12
 264 %define TMP4    zmm13
 265 %define TMP5    zmm14
 266 %define TMP6    zmm15
 267
 268 %define W0      zmm16
 269 %define W1      zmm17
 270 %define W2      zmm18
 271 %define W3      zmm19
 272 %define W4      zmm20
 273 %define W5      zmm21
 274 %define W6      zmm22
 275 %define W7      zmm23
 276 %define W8      zmm24
 277 %define W9      zmm25
 278 %define W10     zmm26
 279 %define W11     zmm27
 280 %define W12     zmm28
 281 %define W13     zmm29
 282 %define W14     zmm30
 283 %define W15     zmm31
 284
 285 %define inp0    r9
 286 %define inp1    r10
 287 %define inp2    r11
 288 %define inp3    r12
 289 %define inp4    r13
 290 %define inp5    r14
 291 %define inp6    r15
 292 %define inp7    rax
 293
 294 %macro ROTATE_ARGS 0
 295 %xdefine TMP_ H
 296 %xdefine H G
 297 %xdefine G F
 298 %xdefine F E
 299 %xdefine E D
 300 %xdefine D C
 301 %xdefine C B
 302 %xdefine B A
 303 %xdefine A TMP_
 304 %endm
 305
 306 ;;  CH(A, B, C) = (A&B) ^ (~A&C)
 307 ;; MAJ(E, F, G) = (E&F) ^ (E&G) ^ (F&G)
 308 ;; SIGMA0 = ROR_2  ^ ROR_13 ^ ROR_22
 309 ;; SIGMA1 = ROR_6  ^ ROR_11 ^ ROR_25
 310 ;; sigma0 = ROR_7  ^ ROR_18 ^ SHR_3
 311 ;; sigma1 = ROR_17 ^ ROR_19 ^ SHR_10
 312
 313 ; Main processing loop per round
 314 %macro PROCESS_LOOP 2
 315 %define %%WT    %1
 316 %define %%ROUND %2
 317         ;; T1 = H + SIGMA1(E) + CH(E, F, G) + Kt + Wt
 318         ;; T2 = SIGMA0(A) + MAJ(A, B, C)
 319         ;; H=G, G=F, F=E, E=D+T1, D=C, C=B, B=A, A=T1+T2
 320
 321         ;; H becomes T2, then add T1 for A
 322         ;; D becomes D + T1 for E
 323
 324         vpaddd          T1, H, TMP3             ; T1 = H + Kt
 325         vmovdqa32       TMP0, E
 326         vprord          TMP1, E, 6              ; ROR_6(E)
 327         vprord          TMP2, E, 11             ; ROR_11(E)
 328         vprord          TMP3, E, 25             ; ROR_25(E)
 329         vpternlogd      TMP0, F, G, 0xCA        ; TMP0 = CH(E,F,G)
 330         vpaddd          T1, T1, %%WT            ; T1 = T1 + Wt
 331         vpternlogd      TMP1, TMP2, TMP3, 0x96  ; TMP1 = SIGMA1(E)
 332         vpaddd          T1, T1, TMP0            ; T1 = T1 + CH(E,F,G)
 333         vpaddd          T1, T1, TMP1            ; T1 = T1 + SIGMA1(E)
 334         vpaddd          D, D, T1                ; D = D + T1
 335
 336         vprord          H, A, 2                 ; ROR_2(A)
 337         vprord          TMP2, A, 13             ; ROR_13(A)
 338         vprord          TMP3, A, 22             ; ROR_22(A)
 339         vmovdqa32       TMP0, A
 340         vpternlogd      TMP0, B, C, 0xE8        ; TMP0 = MAJ(A,B,C)
 341         vpternlogd      H, TMP2, TMP3, 0x96     ; H(T2) = SIGMA0(A)
 342         vpaddd          H, H, TMP0              ; H(T2) = SIGMA0(A) + MAJ(A,B,C)
 343         vpaddd          H, H, T1                ; H(A) = H(T2) + T1
 344
 345         vmovdqa32       TMP3, [TBL + ((%%ROUND+1)*64)]  ; Next Kt
 346
 347         ;; Rotate the args A-H (rotation of names associated with regs)
 348         ROTATE_ARGS
 349 %endmacro
 350
 351 ; This is supposed to be SKL optimized assuming:
 352 ; vpternlog, vpaddd ports 5,8
 353 ; vprord ports 1,8
 354 ; However, vprord is only working on port 8
 355 ;
 356 ; Main processing loop per round
 357 ; Get the msg schedule word 16 from the current, now unneccessary word
 358 %macro PROCESS_LOOP_00_47 5
 359 %define %%WT    %1
 360 %define %%ROUND %2
 361 %define %%WTp1  %3
 362 %define %%WTp9  %4
 363 %define %%WTp14 %5
 364         ;; T1 = H + SIGMA1(E) + CH(E, F, G) + Kt + Wt
 365         ;; T2 = SIGMA0(A) + MAJ(A, B, C)
 366         ;; H=G, G=F, F=E, E=D+T1, D=C, C=B, B=A, A=T1+T2
 367
 368         ;; H becomes T2, then add T1 for A
 369         ;; D becomes D + T1 for E
 370
 371         ;; For next value in msg schedule
 372         ;; Wt+16 = sigma1(Wt+14) + Wt+9 + sigma0(Wt+1) + Wt
 373
 374         vmovdqa32       TMP0, E
 375         vprord          TMP1, E, 6              ; ROR_6(E)
 376         vprord          TMP2, E, 11             ; ROR_11(E)
 377         vprord          TMP3, E, 25             ; ROR_25(E)
 378         vpternlogd      TMP0, F, G, 0xCA        ; TMP0 = CH(E,F,G)
 379         vpaddd          T1, H, %%WT             ; T1 = H + Wt
 380         vpternlogd      TMP1, TMP2, TMP3, 0x96  ; TMP1 = SIGMA1(E)
 381         vpaddd          T1, T1, TMP6            ; T1 = T1 + Kt
 382         vprord          H, A, 2                 ; ROR_2(A)
 383         vpaddd          T1, T1, TMP0            ; T1 = T1 + CH(E,F,G)
 384         vprord          TMP2, A, 13             ; ROR_13(A)
 385         vmovdqa32       TMP0, A
 386         vprord          TMP3, A, 22             ; ROR_22(A)
 387         vpaddd          T1, T1, TMP1            ; T1 = T1 + SIGMA1(E)
 388         vpternlogd      TMP0, B, C, 0xE8        ; TMP0 = MAJ(A,B,C)
 389         vpaddd          D, D, T1                ; D = D + T1
 390         vpternlogd      H, TMP2, TMP3, 0x96     ; H(T2) = SIGMA0(A)
 391         vprord          TMP4, %%WTp14, 17       ; ROR_17(Wt-2)
 392         vpaddd          H, H, TMP0              ; H(T2) = SIGMA0(A) + MAJ(A,B,C)
 393         vprord          TMP5, %%WTp14, 19       ; ROR_19(Wt-2)
 394         vpsrld          TMP6, %%WTp14, 10       ; SHR_10(Wt-2)
 395         vpaddd          H, H, T1                ; H(A) = H(T2) + T1
 396         vpternlogd      TMP4, TMP5, TMP6, 0x96  ; TMP4 = sigma1(Wt-2)
 397         vpaddd          %%WT, %%WT, TMP4        ; Wt = Wt-16 + sigma1(Wt-2)
 398         vprord          TMP4, %%WTp1, 7         ; ROR_7(Wt-15)
 399         vprord          TMP5, %%WTp1, 18        ; ROR_18(Wt-15)
 400         vpaddd          %%WT, %%WT, %%WTp9      ; Wt = Wt-16 + sigma1(Wt-2) + Wt-7
 401         vpsrld          TMP6, %%WTp1, 3         ; SHR_3(Wt-15)
 402         vpternlogd      TMP4, TMP5, TMP6, 0x96  ; TMP4 = sigma0(Wt-15)
 403         vpaddd          %%WT, %%WT, TMP4        ; Wt = Wt-16 + sigma1(Wt-2) +
 404                                                 ;      Wt-7 + sigma0(Wt-15) +
 405
 406         vmovdqa32       TMP6, [TBL + ((%%ROUND+1)*64)]  ; Next Kt
 407
 408         ;; Rotate the args A-H (rotation of names associated with regs)
 409         ROTATE_ARGS
 410 %endmacro
 411
 412 %macro MSG_SCHED_ROUND_16_63 4
 413 %define %%WT    %1
 414 %define %%WTp1  %2
 415 %define %%WTp9  %3
 416 %define %%WTp14 %4
 417         vprord          TMP4, %%WTp14, 17       ; ROR_17(Wt-2)
 418         vprord          TMP5, %%WTp14, 19       ; ROR_19(Wt-2)
 419         vpsrld          TMP6, %%WTp14, 10       ; SHR_10(Wt-2)
 420         vpternlogd      TMP4, TMP5, TMP6, 0x96  ; TMP4 = sigma1(Wt-2)
 421
 422         vpaddd          %%WT, %%WT, TMP4        ; Wt = Wt-16 + sigma1(Wt-2)
 423         vpaddd          %%WT, %%WT, %%WTp9      ; Wt = Wt-16 + sigma1(Wt-2) + Wt-7
 424
 425         vprord          TMP4, %%WTp1, 7         ; ROR_7(Wt-15)
 426         vprord          TMP5, %%WTp1, 18        ; ROR_18(Wt-15)
 427         vpsrld          TMP6, %%WTp1, 3         ; SHR_3(Wt-15)
 428         vpternlogd      TMP4, TMP5, TMP6, 0x96  ; TMP4 = sigma0(Wt-15)
 429
 430         vpaddd          %%WT, %%WT, TMP4        ; Wt = Wt-16 + sigma1(Wt-2) +
 431                                                 ;      Wt-7 + sigma0(Wt-15) +
 432 %endmacro
 433
 434 ; Note this is reading in a block of data for one lane
 435 ; When all 16 are read, the data must be transposed to build msg schedule
 436 %macro MSG_SCHED_ROUND_00_15 2
 437 %define %%WT     %1
 438 %define %%OFFSET %2
 439         mov             inp0, [STATE + _data_ptr_sha256 + (%%OFFSET*PTR_SZ)]
 440         vmovups         %%WT, [inp0+IDX]
 441 %endmacro
 442
 443         section .data
 444 default rel
 445 align 64
 446 TABLE:
 447         dq      0x428a2f98428a2f98, 0x428a2f98428a2f98
 448         dq      0x428a2f98428a2f98, 0x428a2f98428a2f98
 449         dq      0x428a2f98428a2f98, 0x428a2f98428a2f98
 450         dq      0x428a2f98428a2f98, 0x428a2f98428a2f98
 451         dq      0x7137449171374491, 0x7137449171374491
 452         dq      0x7137449171374491, 0x7137449171374491
 453         dq      0x7137449171374491, 0x7137449171374491
 454         dq      0x7137449171374491, 0x7137449171374491
 455         dq      0xb5c0fbcfb5c0fbcf, 0xb5c0fbcfb5c0fbcf
 456         dq      0xb5c0fbcfb5c0fbcf, 0xb5c0fbcfb5c0fbcf
 457         dq      0xb5c0fbcfb5c0fbcf, 0xb5c0fbcfb5c0fbcf
 458         dq      0xb5c0fbcfb5c0fbcf, 0xb5c0fbcfb5c0fbcf
 459         dq      0xe9b5dba5e9b5dba5, 0xe9b5dba5e9b5dba5
 460         dq      0xe9b5dba5e9b5dba5, 0xe9b5dba5e9b5dba5
 461         dq      0xe9b5dba5e9b5dba5, 0xe9b5dba5e9b5dba5
 462         dq      0xe9b5dba5e9b5dba5, 0xe9b5dba5e9b5dba5
 463         dq      0x3956c25b3956c25b, 0x3956c25b3956c25b
 464         dq      0x3956c25b3956c25b, 0x3956c25b3956c25b
 465         dq      0x3956c25b3956c25b, 0x3956c25b3956c25b
 466         dq      0x3956c25b3956c25b, 0x3956c25b3956c25b
 467         dq      0x59f111f159f111f1, 0x59f111f159f111f1
 468         dq      0x59f111f159f111f1, 0x59f111f159f111f1
 469         dq      0x59f111f159f111f1, 0x59f111f159f111f1
 470         dq      0x59f111f159f111f1, 0x59f111f159f111f1
 471         dq      0x923f82a4923f82a4, 0x923f82a4923f82a4
 472         dq      0x923f82a4923f82a4, 0x923f82a4923f82a4
 473         dq      0x923f82a4923f82a4, 0x923f82a4923f82a4
 474         dq      0x923f82a4923f82a4, 0x923f82a4923f82a4
 475         dq      0xab1c5ed5ab1c5ed5, 0xab1c5ed5ab1c5ed5
 476         dq      0xab1c5ed5ab1c5ed5, 0xab1c5ed5ab1c5ed5
 477         dq      0xab1c5ed5ab1c5ed5, 0xab1c5ed5ab1c5ed5
 478         dq      0xab1c5ed5ab1c5ed5, 0xab1c5ed5ab1c5ed5
 479         dq      0xd807aa98d807aa98, 0xd807aa98d807aa98
 480         dq      0xd807aa98d807aa98, 0xd807aa98d807aa98
 481         dq      0xd807aa98d807aa98, 0xd807aa98d807aa98
 482         dq      0xd807aa98d807aa98, 0xd807aa98d807aa98
 483         dq      0x12835b0112835b01, 0x12835b0112835b01
 484         dq      0x12835b0112835b01, 0x12835b0112835b01
 485         dq      0x12835b0112835b01, 0x12835b0112835b01
 486         dq      0x12835b0112835b01, 0x12835b0112835b01
 487         dq      0x243185be243185be, 0x243185be243185be
 488         dq      0x243185be243185be, 0x243185be243185be
 489         dq      0x243185be243185be, 0x243185be243185be
 490         dq      0x243185be243185be, 0x243185be243185be
 491         dq      0x550c7dc3550c7dc3, 0x550c7dc3550c7dc3
 492         dq      0x550c7dc3550c7dc3, 0x550c7dc3550c7dc3
 493         dq      0x550c7dc3550c7dc3, 0x550c7dc3550c7dc3
 494         dq      0x550c7dc3550c7dc3, 0x550c7dc3550c7dc3
 495         dq      0x72be5d7472be5d74, 0x72be5d7472be5d74
 496         dq      0x72be5d7472be5d74, 0x72be5d7472be5d74
 497         dq      0x72be5d7472be5d74, 0x72be5d7472be5d74
 498         dq      0x72be5d7472be5d74, 0x72be5d7472be5d74
 499         dq      0x80deb1fe80deb1fe, 0x80deb1fe80deb1fe
 500         dq      0x80deb1fe80deb1fe, 0x80deb1fe80deb1fe
 501         dq      0x80deb1fe80deb1fe, 0x80deb1fe80deb1fe
 502         dq      0x80deb1fe80deb1fe, 0x80deb1fe80deb1fe
 503         dq      0x9bdc06a79bdc06a7, 0x9bdc06a79bdc06a7
 504         dq      0x9bdc06a79bdc06a7, 0x9bdc06a79bdc06a7
 505         dq      0x9bdc06a79bdc06a7, 0x9bdc06a79bdc06a7
 506         dq      0x9bdc06a79bdc06a7, 0x9bdc06a79bdc06a7
 507         dq      0xc19bf174c19bf174, 0xc19bf174c19bf174
 508         dq      0xc19bf174c19bf174, 0xc19bf174c19bf174
 509         dq      0xc19bf174c19bf174, 0xc19bf174c19bf174
 510         dq      0xc19bf174c19bf174, 0xc19bf174c19bf174
 511         dq      0xe49b69c1e49b69c1, 0xe49b69c1e49b69c1
 512         dq      0xe49b69c1e49b69c1, 0xe49b69c1e49b69c1
 513         dq      0xe49b69c1e49b69c1, 0xe49b69c1e49b69c1
 514         dq      0xe49b69c1e49b69c1, 0xe49b69c1e49b69c1
 515         dq      0xefbe4786efbe4786, 0xefbe4786efbe4786
 516         dq      0xefbe4786efbe4786, 0xefbe4786efbe4786
 517         dq      0xefbe4786efbe4786, 0xefbe4786efbe4786
 518         dq      0xefbe4786efbe4786, 0xefbe4786efbe4786
 519         dq      0x0fc19dc60fc19dc6, 0x0fc19dc60fc19dc6
 520         dq      0x0fc19dc60fc19dc6, 0x0fc19dc60fc19dc6
 521         dq      0x0fc19dc60fc19dc6, 0x0fc19dc60fc19dc6
 522         dq      0x0fc19dc60fc19dc6, 0x0fc19dc60fc19dc6
 523         dq      0x240ca1cc240ca1cc, 0x240ca1cc240ca1cc
 524         dq      0x240ca1cc240ca1cc, 0x240ca1cc240ca1cc
 525         dq      0x240ca1cc240ca1cc, 0x240ca1cc240ca1cc
 526         dq      0x240ca1cc240ca1cc, 0x240ca1cc240ca1cc
 527         dq      0x2de92c6f2de92c6f, 0x2de92c6f2de92c6f
 528         dq      0x2de92c6f2de92c6f, 0x2de92c6f2de92c6f
 529         dq      0x2de92c6f2de92c6f, 0x2de92c6f2de92c6f
 530         dq      0x2de92c6f2de92c6f, 0x2de92c6f2de92c6f
 531         dq      0x4a7484aa4a7484aa, 0x4a7484aa4a7484aa
 532         dq      0x4a7484aa4a7484aa, 0x4a7484aa4a7484aa
 533         dq      0x4a7484aa4a7484aa, 0x4a7484aa4a7484aa
 534         dq      0x4a7484aa4a7484aa, 0x4a7484aa4a7484aa
 535         dq      0x5cb0a9dc5cb0a9dc, 0x5cb0a9dc5cb0a9dc
 536         dq      0x5cb0a9dc5cb0a9dc, 0x5cb0a9dc5cb0a9dc
 537         dq      0x5cb0a9dc5cb0a9dc, 0x5cb0a9dc5cb0a9dc
 538         dq      0x5cb0a9dc5cb0a9dc, 0x5cb0a9dc5cb0a9dc
 539         dq      0x76f988da76f988da, 0x76f988da76f988da
 540         dq      0x76f988da76f988da, 0x76f988da76f988da
 541         dq      0x76f988da76f988da, 0x76f988da76f988da
 542         dq      0x76f988da76f988da, 0x76f988da76f988da
 543         dq      0x983e5152983e5152, 0x983e5152983e5152
 544         dq      0x983e5152983e5152, 0x983e5152983e5152
 545         dq      0x983e5152983e5152, 0x983e5152983e5152
 546         dq      0x983e5152983e5152, 0x983e5152983e5152
 547         dq      0xa831c66da831c66d, 0xa831c66da831c66d
 548         dq      0xa831c66da831c66d, 0xa831c66da831c66d
 549         dq      0xa831c66da831c66d, 0xa831c66da831c66d
 550         dq      0xa831c66da831c66d, 0xa831c66da831c66d
 551         dq      0xb00327c8b00327c8, 0xb00327c8b00327c8
 552         dq      0xb00327c8b00327c8, 0xb00327c8b00327c8
 553         dq      0xb00327c8b00327c8, 0xb00327c8b00327c8
 554         dq      0xb00327c8b00327c8, 0xb00327c8b00327c8
 555         dq      0xbf597fc7bf597fc7, 0xbf597fc7bf597fc7
 556         dq      0xbf597fc7bf597fc7, 0xbf597fc7bf597fc7
 557         dq      0xbf597fc7bf597fc7, 0xbf597fc7bf597fc7
 558         dq      0xbf597fc7bf597fc7, 0xbf597fc7bf597fc7
 559         dq      0xc6e00bf3c6e00bf3, 0xc6e00bf3c6e00bf3
 560         dq      0xc6e00bf3c6e00bf3, 0xc6e00bf3c6e00bf3
 561         dq      0xc6e00bf3c6e00bf3, 0xc6e00bf3c6e00bf3
 562         dq      0xc6e00bf3c6e00bf3, 0xc6e00bf3c6e00bf3
 563         dq      0xd5a79147d5a79147, 0xd5a79147d5a79147
 564         dq      0xd5a79147d5a79147, 0xd5a79147d5a79147
 565         dq      0xd5a79147d5a79147, 0xd5a79147d5a79147
 566         dq      0xd5a79147d5a79147, 0xd5a79147d5a79147
 567         dq      0x06ca635106ca6351, 0x06ca635106ca6351
 568         dq      0x06ca635106ca6351, 0x06ca635106ca6351
 569         dq      0x06ca635106ca6351, 0x06ca635106ca6351
 570         dq      0x06ca635106ca6351, 0x06ca635106ca6351
 571         dq      0x1429296714292967, 0x1429296714292967
 572         dq      0x1429296714292967, 0x1429296714292967
 573         dq      0x1429296714292967, 0x1429296714292967
 574         dq      0x1429296714292967, 0x1429296714292967
 575         dq      0x27b70a8527b70a85, 0x27b70a8527b70a85
 576         dq      0x27b70a8527b70a85, 0x27b70a8527b70a85
 577         dq      0x27b70a8527b70a85, 0x27b70a8527b70a85
 578         dq      0x27b70a8527b70a85, 0x27b70a8527b70a85
 579         dq      0x2e1b21382e1b2138, 0x2e1b21382e1b2138
 580         dq      0x2e1b21382e1b2138, 0x2e1b21382e1b2138
 581         dq      0x2e1b21382e1b2138, 0x2e1b21382e1b2138
 582         dq      0x2e1b21382e1b2138, 0x2e1b21382e1b2138
 583         dq      0x4d2c6dfc4d2c6dfc, 0x4d2c6dfc4d2c6dfc
 584         dq      0x4d2c6dfc4d2c6dfc, 0x4d2c6dfc4d2c6dfc
 585         dq      0x4d2c6dfc4d2c6dfc, 0x4d2c6dfc4d2c6dfc
 586         dq      0x4d2c6dfc4d2c6dfc, 0x4d2c6dfc4d2c6dfc
 587         dq      0x53380d1353380d13, 0x53380d1353380d13
 588         dq      0x53380d1353380d13, 0x53380d1353380d13
 589         dq      0x53380d1353380d13, 0x53380d1353380d13
 590         dq      0x53380d1353380d13, 0x53380d1353380d13
 591         dq      0x650a7354650a7354, 0x650a7354650a7354
 592         dq      0x650a7354650a7354, 0x650a7354650a7354
 593         dq      0x650a7354650a7354, 0x650a7354650a7354
 594         dq      0x650a7354650a7354, 0x650a7354650a7354
 595         dq      0x766a0abb766a0abb, 0x766a0abb766a0abb
 596         dq      0x766a0abb766a0abb, 0x766a0abb766a0abb
 597         dq      0x766a0abb766a0abb, 0x766a0abb766a0abb
 598         dq      0x766a0abb766a0abb, 0x766a0abb766a0abb
 599         dq      0x81c2c92e81c2c92e, 0x81c2c92e81c2c92e
 600         dq      0x81c2c92e81c2c92e, 0x81c2c92e81c2c92e
 601         dq      0x81c2c92e81c2c92e, 0x81c2c92e81c2c92e
 602         dq      0x81c2c92e81c2c92e, 0x81c2c92e81c2c92e
 603         dq      0x92722c8592722c85, 0x92722c8592722c85
 604         dq      0x92722c8592722c85, 0x92722c8592722c85
 605         dq      0x92722c8592722c85, 0x92722c8592722c85
 606         dq      0x92722c8592722c85, 0x92722c8592722c85
 607         dq      0xa2bfe8a1a2bfe8a1, 0xa2bfe8a1a2bfe8a1
 608         dq      0xa2bfe8a1a2bfe8a1, 0xa2bfe8a1a2bfe8a1
 609         dq      0xa2bfe8a1a2bfe8a1, 0xa2bfe8a1a2bfe8a1
 610         dq      0xa2bfe8a1a2bfe8a1, 0xa2bfe8a1a2bfe8a1
 611         dq      0xa81a664ba81a664b, 0xa81a664ba81a664b
 612         dq      0xa81a664ba81a664b, 0xa81a664ba81a664b
 613         dq      0xa81a664ba81a664b, 0xa81a664ba81a664b
 614         dq      0xa81a664ba81a664b, 0xa81a664ba81a664b
 615         dq      0xc24b8b70c24b8b70, 0xc24b8b70c24b8b70
 616         dq      0xc24b8b70c24b8b70, 0xc24b8b70c24b8b70
 617         dq      0xc24b8b70c24b8b70, 0xc24b8b70c24b8b70
 618         dq      0xc24b8b70c24b8b70, 0xc24b8b70c24b8b70
 619         dq      0xc76c51a3c76c51a3, 0xc76c51a3c76c51a3
 620         dq      0xc76c51a3c76c51a3, 0xc76c51a3c76c51a3
 621         dq      0xc76c51a3c76c51a3, 0xc76c51a3c76c51a3
 622         dq      0xc76c51a3c76c51a3, 0xc76c51a3c76c51a3
 623         dq      0xd192e819d192e819, 0xd192e819d192e819
 624         dq      0xd192e819d192e819, 0xd192e819d192e819
 625         dq      0xd192e819d192e819, 0xd192e819d192e819
 626         dq      0xd192e819d192e819, 0xd192e819d192e819
 627         dq      0xd6990624d6990624, 0xd6990624d6990624
 628         dq      0xd6990624d6990624, 0xd6990624d6990624
 629         dq      0xd6990624d6990624, 0xd6990624d6990624
 630         dq      0xd6990624d6990624, 0xd6990624d6990624
 631         dq      0xf40e3585f40e3585, 0xf40e3585f40e3585
 632         dq      0xf40e3585f40e3585, 0xf40e3585f40e3585
 633         dq      0xf40e3585f40e3585, 0xf40e3585f40e3585
 634         dq      0xf40e3585f40e3585, 0xf40e3585f40e3585
 635         dq      0x106aa070106aa070, 0x106aa070106aa070
 636         dq      0x106aa070106aa070, 0x106aa070106aa070
 637         dq      0x106aa070106aa070, 0x106aa070106aa070
 638         dq      0x106aa070106aa070, 0x106aa070106aa070
 639         dq      0x19a4c11619a4c116, 0x19a4c11619a4c116
 640         dq      0x19a4c11619a4c116, 0x19a4c11619a4c116
 641         dq      0x19a4c11619a4c116, 0x19a4c11619a4c116
 642         dq      0x19a4c11619a4c116, 0x19a4c11619a4c116
 643         dq      0x1e376c081e376c08, 0x1e376c081e376c08
 644         dq      0x1e376c081e376c08, 0x1e376c081e376c08
 645         dq      0x1e376c081e376c08, 0x1e376c081e376c08
 646         dq      0x1e376c081e376c08, 0x1e376c081e376c08
 647         dq      0x2748774c2748774c, 0x2748774c2748774c
 648         dq      0x2748774c2748774c, 0x2748774c2748774c
 649         dq      0x2748774c2748774c, 0x2748774c2748774c
 650         dq      0x2748774c2748774c, 0x2748774c2748774c
 651         dq      0x34b0bcb534b0bcb5, 0x34b0bcb534b0bcb5
 652         dq      0x34b0bcb534b0bcb5, 0x34b0bcb534b0bcb5
 653         dq      0x34b0bcb534b0bcb5, 0x34b0bcb534b0bcb5
 654         dq      0x34b0bcb534b0bcb5, 0x34b0bcb534b0bcb5
 655         dq      0x391c0cb3391c0cb3, 0x391c0cb3391c0cb3
 656         dq      0x391c0cb3391c0cb3, 0x391c0cb3391c0cb3
 657         dq      0x391c0cb3391c0cb3, 0x391c0cb3391c0cb3
 658         dq      0x391c0cb3391c0cb3, 0x391c0cb3391c0cb3
 659         dq      0x4ed8aa4a4ed8aa4a, 0x4ed8aa4a4ed8aa4a
 660         dq      0x4ed8aa4a4ed8aa4a, 0x4ed8aa4a4ed8aa4a
 661         dq      0x4ed8aa4a4ed8aa4a, 0x4ed8aa4a4ed8aa4a
 662         dq      0x4ed8aa4a4ed8aa4a, 0x4ed8aa4a4ed8aa4a
 663         dq      0x5b9cca4f5b9cca4f, 0x5b9cca4f5b9cca4f
 664         dq      0x5b9cca4f5b9cca4f, 0x5b9cca4f5b9cca4f
 665         dq      0x5b9cca4f5b9cca4f, 0x5b9cca4f5b9cca4f
 666         dq      0x5b9cca4f5b9cca4f, 0x5b9cca4f5b9cca4f
 667         dq      0x682e6ff3682e6ff3, 0x682e6ff3682e6ff3
 668         dq      0x682e6ff3682e6ff3, 0x682e6ff3682e6ff3
 669         dq      0x682e6ff3682e6ff3, 0x682e6ff3682e6ff3
 670         dq      0x682e6ff3682e6ff3, 0x682e6ff3682e6ff3
 671         dq      0x748f82ee748f82ee, 0x748f82ee748f82ee
 672         dq      0x748f82ee748f82ee, 0x748f82ee748f82ee
 673         dq      0x748f82ee748f82ee, 0x748f82ee748f82ee
 674         dq      0x748f82ee748f82ee, 0x748f82ee748f82ee
 675         dq      0x78a5636f78a5636f, 0x78a5636f78a5636f
 676         dq      0x78a5636f78a5636f, 0x78a5636f78a5636f
 677         dq      0x78a5636f78a5636f, 0x78a5636f78a5636f
 678         dq      0x78a5636f78a5636f, 0x78a5636f78a5636f
 679         dq      0x84c8781484c87814, 0x84c8781484c87814
 680         dq      0x84c8781484c87814, 0x84c8781484c87814
 681         dq      0x84c8781484c87814, 0x84c8781484c87814
 682         dq      0x84c8781484c87814, 0x84c8781484c87814
 683         dq      0x8cc702088cc70208, 0x8cc702088cc70208
 684         dq      0x8cc702088cc70208, 0x8cc702088cc70208
 685         dq      0x8cc702088cc70208, 0x8cc702088cc70208
 686         dq      0x8cc702088cc70208, 0x8cc702088cc70208
 687         dq      0x90befffa90befffa, 0x90befffa90befffa
 688         dq      0x90befffa90befffa, 0x90befffa90befffa
 689         dq      0x90befffa90befffa, 0x90befffa90befffa
 690         dq      0x90befffa90befffa, 0x90befffa90befffa
 691         dq      0xa4506ceba4506ceb, 0xa4506ceba4506ceb
 692         dq      0xa4506ceba4506ceb, 0xa4506ceba4506ceb
 693         dq      0xa4506ceba4506ceb, 0xa4506ceba4506ceb
 694         dq      0xa4506ceba4506ceb, 0xa4506ceba4506ceb
 695         dq      0xbef9a3f7bef9a3f7, 0xbef9a3f7bef9a3f7
 696         dq      0xbef9a3f7bef9a3f7, 0xbef9a3f7bef9a3f7
 697         dq      0xbef9a3f7bef9a3f7, 0xbef9a3f7bef9a3f7
 698         dq      0xbef9a3f7bef9a3f7, 0xbef9a3f7bef9a3f7
 699         dq      0xc67178f2c67178f2, 0xc67178f2c67178f2
 700         dq      0xc67178f2c67178f2, 0xc67178f2c67178f2
 701         dq      0xc67178f2c67178f2, 0xc67178f2c67178f2
 702         dq      0xc67178f2c67178f2, 0xc67178f2c67178f2
 703
 704 PSHUFFLE_BYTE_FLIP_MASK:
 705         ;ddq 0x0c0d0e0f08090a0b0405060700010203
 706          dq 0x0405060700010203, 0x0c0d0e0f08090a0b
 707         ;ddq 0x0c0d0e0f08090a0b0405060700010203
 708          dq 0x0405060700010203, 0x0c0d0e0f08090a0b
 709         ;ddq 0x0c0d0e0f08090a0b0405060700010203
 710          dq 0x0405060700010203, 0x0c0d0e0f08090a0b
 711         ;ddq 0x0c0d0e0f08090a0b0405060700010203
 712          dq 0x0405060700010203, 0x0c0d0e0f08090a0b
 713
 714 PSHUFFLE_TRANSPOSE16_MASK1:     dq 0x0000000000000000
 715                                 dq 0x0000000000000001
 716                                 dq 0x0000000000000008
 717                                 dq 0x0000000000000009
 718                                 dq 0x0000000000000004
 719                                 dq 0x0000000000000005
 720                                 dq 0x000000000000000C
 721                                 dq 0x000000000000000D
 722
 723
 724 PSHUFFLE_TRANSPOSE16_MASK2:     dq 0x0000000000000002
 725                                 dq 0x0000000000000003
 726                                 dq 0x000000000000000A
 727                                 dq 0x000000000000000B
 728                                 dq 0x0000000000000006
 729                                 dq 0x0000000000000007
 730                                 dq 0x000000000000000E
 731                                 dq 0x000000000000000F
 732
 733 section .text
 734
 735 ;; void sha256_x16_avx512(void **input_data, UINT128 *digest[16], UINT64 size)
 736 ;; arg 1 : pointer to SHA256 args structure
 737 ;; arg 2 : size (in blocks) ;; assumed to be >= 1
 738 ;; arg 1 : rcx : pointer to array of pointers to input data
 739 ;; arg 2 : rdx : pointer to array of pointers to digest
 740 ;; arg 3 : r8  : size of input in bytes
 741 MKGLOBAL(sha256_x16_avx512,function,internal)
 742 align 64
 743 sha256_x16_avx512:
 744         mov     rax, rsp
 745         sub     rsp, STACK_SPACE
 746         and     rsp, ~63        ; align stack to multiple of 64
 747         mov     [rsp + _rsp], rax
 748
 749         ;; Initialize digests
 750         vmovdqu32       A, [STATE + 0*SHA256_DIGEST_ROW_SIZE]
 751         vmovdqu32       B, [STATE + 1*SHA256_DIGEST_ROW_SIZE]
 752         vmovdqu32       C, [STATE + 2*SHA256_DIGEST_ROW_SIZE]
 753         vmovdqu32       D, [STATE + 3*SHA256_DIGEST_ROW_SIZE]
 754         vmovdqu32       E, [STATE + 4*SHA256_DIGEST_ROW_SIZE]
 755         vmovdqu32       F, [STATE + 5*SHA256_DIGEST_ROW_SIZE]
 756         vmovdqu32       G, [STATE + 6*SHA256_DIGEST_ROW_SIZE]
 757         vmovdqu32       H, [STATE + 7*SHA256_DIGEST_ROW_SIZE]
 758
 759         lea             TBL, [rel TABLE]
 760
 761         ; Do we need to transpose digests???
 762         ; SHA1 does not, but SHA256 has been
 763
 764         xor IDX, IDX
 765
 766         ;; Read in first block of input data
 767         ;; Transpose input data
 768         mov     inp0, [STATE + _data_ptr_sha256 + 0*PTR_SZ]
 769         mov     inp1, [STATE + _data_ptr_sha256 + 1*PTR_SZ]
 770         mov     inp2, [STATE + _data_ptr_sha256 + 2*PTR_SZ]
 771         mov     inp3, [STATE + _data_ptr_sha256 + 3*PTR_SZ]
 772         mov     inp4, [STATE + _data_ptr_sha256 + 4*PTR_SZ]
 773         mov     inp5, [STATE + _data_ptr_sha256 + 5*PTR_SZ]
 774         mov     inp6, [STATE + _data_ptr_sha256 + 6*PTR_SZ]
 775         mov     inp7, [STATE + _data_ptr_sha256 + 7*PTR_SZ]
 776
 777         vmovups W0,[inp0+IDX]
 778         vmovups W1,[inp1+IDX]
 779         vmovups W2,[inp2+IDX]
 780         vmovups W3,[inp3+IDX]
 781         vmovups W4,[inp4+IDX]
 782         vmovups W5,[inp5+IDX]
 783         vmovups W6,[inp6+IDX]
 784         vmovups W7,[inp7+IDX]
 785
 786         mov     inp0, [STATE + _data_ptr_sha256 + 8*PTR_SZ]
 787         mov     inp1, [STATE + _data_ptr_sha256 + 9*PTR_SZ]
 788         mov     inp2, [STATE + _data_ptr_sha256 +10*PTR_SZ]
 789         mov     inp3, [STATE + _data_ptr_sha256 +11*PTR_SZ]
 790         mov     inp4, [STATE + _data_ptr_sha256 +12*PTR_SZ]
 791         mov     inp5, [STATE + _data_ptr_sha256 +13*PTR_SZ]
 792         mov     inp6, [STATE + _data_ptr_sha256 +14*PTR_SZ]
 793         mov     inp7, [STATE + _data_ptr_sha256 +15*PTR_SZ]
 794
 795         vmovups W8, [inp0+IDX]
 796         vmovups W9, [inp1+IDX]
 797         vmovups W10,[inp2+IDX]
 798         vmovups W11,[inp3+IDX]
 799         vmovups W12,[inp4+IDX]
 800         vmovups W13,[inp5+IDX]
 801         vmovups W14,[inp6+IDX]
 802         vmovups W15,[inp7+IDX]
 803         jmp     lloop
 804
 805         align 32
 806 lloop:
 807         vmovdqa32       TMP2, [rel PSHUFFLE_BYTE_FLIP_MASK]
 808
 809         vmovdqa32       TMP3, [TBL]     ; First K
 810
 811         ; Save digests for later addition
 812         vmovdqa32       [rsp + _DIGEST_SAVE + 64*0], A
 813         vmovdqa32       [rsp + _DIGEST_SAVE + 64*1], B
 814         vmovdqa32       [rsp + _DIGEST_SAVE + 64*2], C
 815         vmovdqa32       [rsp + _DIGEST_SAVE + 64*3], D
 816         vmovdqa32       [rsp + _DIGEST_SAVE + 64*4], E
 817         vmovdqa32       [rsp + _DIGEST_SAVE + 64*5], F
 818         vmovdqa32       [rsp + _DIGEST_SAVE + 64*6], G
 819         vmovdqa32       [rsp + _DIGEST_SAVE + 64*7], H
 820
 821         add     IDX, 64
 822
 823         TRANSPOSE16 W0, W1, W2, W3, W4, W5, W6, W7, W8, W9, W10, W11, W12, W13, W14, W15, TMP0, TMP1
 824
 825 %assign I 0
 826 %rep 16
 827         vpshufb APPEND(W,I), APPEND(W,I), TMP2
 828 %assign I (I+1)
 829 %endrep
 830
 831         ; MSG Schedule for W0-W15 is now complete in registers
 832         ; Process first 48 rounds
 833         ; Calculate next Wt+16 after processing is complete and Wt is unneeded
 834
 835         ; PROCESS_LOOP_00_47 APPEND(W,J), I, APPEND(W,K), APPEND(W,L), APPEND(W,M)
 836 %assign I 0
 837 %assign J 0
 838 %assign K 1
 839 %assign L 9
 840 %assign M 14
 841 %rep 48
 842         PROCESS_LOOP  APPEND(W,J),  I
 843         MSG_SCHED_ROUND_16_63  APPEND(W,J), APPEND(W,K), APPEND(W,L), APPEND(W,M)
 844 %assign I (I+1)
 845 %assign J ((J+1)% 16)
 846 %assign K ((K+1)% 16)
 847 %assign L ((L+1)% 16)
 848 %assign M ((M+1)% 16)
 849 %endrep
 850
 851         ; Check is this is the last block
 852         sub     INP_SIZE, 1
 853         je      lastLoop
 854
 855         ; Process last 16 rounds
 856         ; Read in next block msg data for use in first 16 words of msg sched
 857 %assign I 48
 858 %assign J 0
 859 %rep 16
 860         PROCESS_LOOP  APPEND(W,J), I
 861         MSG_SCHED_ROUND_00_15  APPEND(W,J), J
 862 %assign I (I+1)
 863 %assign J (J+1)
 864 %endrep
 865
 866         ; Add old digest
 867         vpaddd          A, A, [rsp + _DIGEST_SAVE + 64*0]
 868         vpaddd          B, B, [rsp + _DIGEST_SAVE + 64*1]
 869         vpaddd          C, C, [rsp + _DIGEST_SAVE + 64*2]
 870         vpaddd          D, D, [rsp + _DIGEST_SAVE + 64*3]
 871         vpaddd          E, E, [rsp + _DIGEST_SAVE + 64*4]
 872         vpaddd          F, F, [rsp + _DIGEST_SAVE + 64*5]
 873         vpaddd          G, G, [rsp + _DIGEST_SAVE + 64*6]
 874         vpaddd          H, H, [rsp + _DIGEST_SAVE + 64*7]
 875
 876         jmp     lloop
 877
 878 lastLoop:
 879         ; Process last 16 rounds
 880 %assign I 48
 881 %assign J 0
 882 %rep 16
 883         PROCESS_LOOP  APPEND(W,J), I
 884 %assign I (I+1)
 885 %assign J (J+1)
 886 %endrep
 887
 888         ; Add old digest
 889         vpaddd          A, A, [rsp + _DIGEST_SAVE + 64*0]
 890         vpaddd          B, B, [rsp + _DIGEST_SAVE + 64*1]
 891         vpaddd          C, C, [rsp + _DIGEST_SAVE + 64*2]
 892         vpaddd          D, D, [rsp + _DIGEST_SAVE + 64*3]
 893         vpaddd          E, E, [rsp + _DIGEST_SAVE + 64*4]
 894         vpaddd          F, F, [rsp + _DIGEST_SAVE + 64*5]
 895         vpaddd          G, G, [rsp + _DIGEST_SAVE + 64*6]
 896         vpaddd          H, H, [rsp + _DIGEST_SAVE + 64*7]
 897
 898         ; Write out digest
 899         ; Do we need to untranspose digests???
 900         vmovdqu32       [STATE + 0*SHA256_DIGEST_ROW_SIZE], A
 901         vmovdqu32       [STATE + 1*SHA256_DIGEST_ROW_SIZE], B
 902         vmovdqu32       [STATE + 2*SHA256_DIGEST_ROW_SIZE], C
 903         vmovdqu32       [STATE + 3*SHA256_DIGEST_ROW_SIZE], D
 904         vmovdqu32       [STATE + 4*SHA256_DIGEST_ROW_SIZE], E
 905         vmovdqu32       [STATE + 5*SHA256_DIGEST_ROW_SIZE], F
 906         vmovdqu32       [STATE + 6*SHA256_DIGEST_ROW_SIZE], G
 907         vmovdqu32       [STATE + 7*SHA256_DIGEST_ROW_SIZE], H
 908
 909         ; update input pointers
 910 %assign I 0
 911 %rep 16
 912         add     [STATE + _data_ptr_sha256 + I*PTR_SZ], IDX
 913 %assign I (I+1)
 914 %endrep
 915
 916         mov     rsp, [rsp + _rsp]
 917         ret
 918
 919 %ifdef LINUX
 920 section .note.GNU-stack noalloc noexec nowrite progbits
 921 %endif