]>
git.proxmox.com Git - ceph.git/blob - ceph/src/spdk/intel-ipsec-mb/md5_one_block.c
1 /*******************************************************************************
2 Copyright (c) 2012-2018, Intel Corporation
4 Redistribution and use in source and binary forms, with or without
5 modification, are permitted provided that the following conditions are met:
7 * Redistributions of source code must retain the above copyright notice,
8 this list of conditions and the following disclaimer.
9 * Redistributions in binary form must reproduce the above copyright
10 notice, this list of conditions and the following disclaimer in the
11 documentation and/or other materials provided with the distribution.
12 * Neither the name of Intel Corporation nor the names of its contributors
13 may be used to endorse or promote products derived from this software
14 without specific prior written permission.
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
19 DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
20 FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
22 SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
23 CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
24 OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *******************************************************************************/
31 void md5_one_block_sse(const uint8_t *data
, uint32_t digest
[4]);
34 #define ROTATE(a, n) (((a) << (n)) ^ ((a) >> (32 - (n))))
37 #define ROTATE(a, n) _rotl(a, n)
45 #define F1(b, c, d) ((((c) ^ (d)) & (b)) ^ (d))
46 #define F2(b, c, d) ((((b) ^ (c)) & (d)) ^ (c))
47 #define F3(b, c, d) ((b) ^ (c) ^ (d))
48 #define F4(b, c, d) (((~(d)) | (b)) ^ (c))
50 #define STEP1(a, b, c, d, k, w, r) { \
51 a += w + k + F1(b, c, d); \
55 #define STEP2(a, b, c, d, k, w, r) { \
56 a += w + k + F2(b, c, d); \
60 #define STEP3(a, b, c, d, k, w, r) { \
61 a += w + k + F3(b, c, d); \
65 #define STEP4(a, b, c, d, k, w, r) { \
66 a += w + k + F4(b, c, d); \
71 md5_one_block_sse(const uint8_t *data
, uint32_t digest
[4])
74 uint32_t w00
, w01
, w02
, w03
, w04
, w05
, w06
, w07
,
75 w08
, w09
, w10
, w11
, w12
, w13
, w14
, w15
;
76 const uint32_t *data32
= (const uint32_t *)data
;
86 STEP1(a
, b
, c
, d
, 0xd76aa478, w00
, 7);
88 STEP1(d
, a
, b
, c
, 0xe8c7b756, w01
, 12);
90 STEP1(c
, d
, a
, b
, 0x242070db, w02
, 17);
92 STEP1(b
, c
, d
, a
, 0xc1bdceee, w03
, 22);
94 STEP1(a
, b
, c
, d
, 0xf57c0faf, w04
, 7);
96 STEP1(d
, a
, b
, c
, 0x4787c62a, w05
, 12);
98 STEP1(c
, d
, a
, b
, 0xa8304613, w06
, 17);
100 STEP1(b
, c
, d
, a
, 0xfd469501, w07
, 22);
102 STEP1(a
, b
, c
, d
, 0x698098d8, w08
, 7);
104 STEP1(d
, a
, b
, c
, 0x8b44f7af, w09
, 12);
106 STEP1(c
, d
, a
, b
, 0xffff5bb1, w10
, 17);
108 STEP1(b
, c
, d
, a
, 0x895cd7be, w11
, 22);
110 STEP1(a
, b
, c
, d
, 0x6b901122, w12
, 7);
112 STEP1(d
, a
, b
, c
, 0xfd987193, w13
, 12);
114 STEP1(c
, d
, a
, b
, 0xa679438e, w14
, 17);
115 STEP1(b
, c
, d
, a
, 0x49b40821, w15
, 22);
116 STEP2(a
, b
, c
, d
, 0xf61e2562, w01
, 5);
117 STEP2(d
, a
, b
, c
, 0xc040b340, w06
, 9);
118 STEP2(c
, d
, a
, b
, 0x265e5a51, w11
, 14);
119 STEP2(b
, c
, d
, a
, 0xe9b6c7aa, w00
, 20);
120 STEP2(a
, b
, c
, d
, 0xd62f105d, w05
, 5);
121 STEP2(d
, a
, b
, c
, 0x02441453, w10
, 9);
122 STEP2(c
, d
, a
, b
, 0xd8a1e681, w15
, 14);
123 STEP2(b
, c
, d
, a
, 0xe7d3fbc8, w04
, 20);
124 STEP2(a
, b
, c
, d
, 0x21e1cde6, w09
, 5);
125 STEP2(d
, a
, b
, c
, 0xc33707d6, w14
, 9);
126 STEP2(c
, d
, a
, b
, 0xf4d50d87, w03
, 14);
127 STEP2(b
, c
, d
, a
, 0x455a14ed, w08
, 20);
128 STEP2(a
, b
, c
, d
, 0xa9e3e905, w13
, 5);
129 STEP2(d
, a
, b
, c
, 0xfcefa3f8, w02
, 9);
130 STEP2(c
, d
, a
, b
, 0x676f02d9, w07
, 14);
131 STEP2(b
, c
, d
, a
, 0x8d2a4c8a, w12
, 20);
132 STEP3(a
, b
, c
, d
, 0xfffa3942, w05
, 4);
133 STEP3(d
, a
, b
, c
, 0x8771f681, w08
, 11);
134 STEP3(c
, d
, a
, b
, 0x6d9d6122, w11
, 16);
135 STEP3(b
, c
, d
, a
, 0xfde5380c, w14
, 23);
136 STEP3(a
, b
, c
, d
, 0xa4beea44, w01
, 4);
137 STEP3(d
, a
, b
, c
, 0x4bdecfa9, w04
, 11);
138 STEP3(c
, d
, a
, b
, 0xf6bb4b60, w07
, 16);
139 STEP3(b
, c
, d
, a
, 0xbebfbc70, w10
, 23);
140 STEP3(a
, b
, c
, d
, 0x289b7ec6, w13
, 4);
141 STEP3(d
, a
, b
, c
, 0xeaa127fa, w00
, 11);
142 STEP3(c
, d
, a
, b
, 0xd4ef3085, w03
, 16);
143 STEP3(b
, c
, d
, a
, 0x04881d05, w06
, 23);
144 STEP3(a
, b
, c
, d
, 0xd9d4d039, w09
, 4);
145 STEP3(d
, a
, b
, c
, 0xe6db99e5, w12
, 11);
146 STEP3(c
, d
, a
, b
, 0x1fa27cf8, w15
, 16);
147 STEP3(b
, c
, d
, a
, 0xc4ac5665, w02
, 23);
148 STEP4(a
, b
, c
, d
, 0xf4292244, w00
, 6);
149 STEP4(d
, a
, b
, c
, 0x432aff97, w07
, 10);
150 STEP4(c
, d
, a
, b
, 0xab9423a7, w14
, 15);
151 STEP4(b
, c
, d
, a
, 0xfc93a039, w05
, 21);
152 STEP4(a
, b
, c
, d
, 0x655b59c3, w12
, 6);
153 STEP4(d
, a
, b
, c
, 0x8f0ccc92, w03
, 10);
154 STEP4(c
, d
, a
, b
, 0xffeff47d, w10
, 15);
155 STEP4(b
, c
, d
, a
, 0x85845dd1, w01
, 21);
156 STEP4(a
, b
, c
, d
, 0x6fa87e4f, w08
, 6);
157 STEP4(d
, a
, b
, c
, 0xfe2ce6e0, w15
, 10);
158 STEP4(c
, d
, a
, b
, 0xa3014314, w06
, 15);
159 STEP4(b
, c
, d
, a
, 0x4e0811a1, w13
, 21);
160 STEP4(a
, b
, c
, d
, 0xf7537e82, w04
, 6);
161 STEP4(d
, a
, b
, c
, 0xbd3af235, w11
, 10);
162 STEP4(c
, d
, a
, b
, 0x2ad7d2bb, w02
, 15);
163 STEP4(b
, c
, d
, a
, 0xeb86d391, w09
, 21);