ceph/src/spdk/isa-l/raid/raid_multibinary.asm

   1 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
   2 ;  Copyright(c) 2011-2015 Intel Corporation All rights reserved.
   3 ;
   4 ;  Redistribution and use in source and binary forms, with or without
   5 ;  modification, are permitted provided that the following conditions
   6 ;  are met:
   7 ;    * Redistributions of source code must retain the above copyright
   8 ;      notice, this list of conditions and the following disclaimer.
   9 ;    * Redistributions in binary form must reproduce the above copyright
  10 ;      notice, this list of conditions and the following disclaimer in
  11 ;      the documentation and/or other materials provided with the
  12 ;      distribution.
  13 ;    * Neither the name of Intel Corporation nor the names of its
  14 ;      contributors may be used to endorse or promote products derived
  15 ;      from this software without specific prior written permission.
  16 ;
  17 ;  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  18 ;  "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  19 ;  LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  20 ;  A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  21 ;  OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  22 ;  SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  23 ;  LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  24 ;  DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  25 ;  THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  26 ;  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  27 ;  OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  28 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
  29
  30 %include "reg_sizes.asm"
  31 %include "multibinary.asm"
  32
  33 default rel
  34 [bits 64]
  35
  36 extern pq_gen_base
  37 extern pq_gen_sse
  38 extern pq_gen_avx
  39 extern pq_gen_avx2
  40
  41 extern xor_gen_base
  42 extern xor_gen_sse
  43 extern xor_gen_avx
  44
  45 extern pq_check_base
  46 extern pq_check_sse
  47
  48 extern xor_check_base
  49 extern xor_check_sse
  50
  51 %ifdef HAVE_AS_KNOWS_AVX512
  52  extern xor_gen_avx512
  53  extern pq_gen_avx512
  54 %endif
  55
  56 mbin_interface xor_gen
  57 mbin_interface pq_gen
  58
  59 %ifdef HAVE_AS_KNOWS_AVX512
  60  mbin_dispatch_init6 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx, xor_gen_avx512
  61  mbin_dispatch_init6 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2, pq_gen_avx512
  62 %else
  63  mbin_dispatch_init5 xor_gen, xor_gen_base, xor_gen_sse, xor_gen_avx, xor_gen_avx
  64  mbin_dispatch_init5 pq_gen, pq_gen_base, pq_gen_sse, pq_gen_avx, pq_gen_avx2
  65 %endif
  66
  67 section .data
  68
  69 xor_check_dispatched:
  70         dq      xor_check_mbinit
  71 pq_check_dispatched:
  72         dq      pq_check_mbinit
  73
  74 section .text
  75
  76 ;;;;
  77 ; pq_check multibinary function
  78 ;;;;
  79 global pq_check:function
  80 pq_check_mbinit:
  81         call    pq_check_dispatch_init
  82 pq_check:
  83         jmp     qword [pq_check_dispatched]
  84
  85 pq_check_dispatch_init:
  86         push    rax
  87         push    rbx
  88         push    rcx
  89         push    rdx
  90         push    rsi
  91         lea     rsi, [pq_check_base WRT_OPT] ; Default
  92
  93         mov     eax, 1
  94         cpuid
  95         test    ecx, FLAG_CPUID1_ECX_SSE4_1
  96         lea     rbx, [pq_check_sse WRT_OPT]
  97         cmovne  rsi, rbx
  98
  99         mov     [pq_check_dispatched], rsi
 100         pop     rsi
 101         pop     rdx
 102         pop     rcx
 103         pop     rbx
 104         pop     rax
 105         ret
 106
 107
 108 ;;;;
 109 ; xor_check multibinary function
 110 ;;;;
 111 global xor_check:function
 112 xor_check_mbinit:
 113         call    xor_check_dispatch_init
 114 xor_check:
 115         jmp     qword [xor_check_dispatched]
 116
 117 xor_check_dispatch_init:
 118         push    rax
 119         push    rbx
 120         push    rcx
 121         push    rdx
 122         push    rsi
 123         lea     rsi, [xor_check_base WRT_OPT] ; Default
 124
 125         mov     eax, 1
 126         cpuid
 127         test    ecx, FLAG_CPUID1_ECX_SSE4_1
 128         lea     rbx, [xor_check_sse WRT_OPT]
 129         cmovne  rsi, rbx
 130
 131         mov     [xor_check_dispatched], rsi
 132         pop     rsi
 133         pop     rdx
 134         pop     rcx
 135         pop     rbx
 136         pop     rax
 137         ret
 138
 139 ;;;       func                  core, ver, snum
 140 slversion xor_gen,              00,   03,  0126
 141 slversion xor_check,            00,   03,  0127
 142 slversion pq_gen,               00,   03,  0128
 143 slversion pq_check,             00,   03,  0129