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2 * defines common to all virtual CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 #if defined(__arm__) || defined(__sparc__)
27 /* some important defines:
29 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
32 * WORDS_BIGENDIAN : if defined, the host cpu is big endian and
33 * otherwise little endian.
35 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
37 * TARGET_WORDS_BIGENDIAN : same for target cpu
40 /* NOTE: arm is horrible as double 32 bit words are stored in big endian ! */
43 #if !defined(WORDS_BIGENDIAN) && !defined(__arm__)
57 /* CPU memory access without any memory or io remapping */
60 * the generic syntax for the memory accesses is:
62 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
64 * store: st{type}{size}{endian}_{access_type}(ptr, val)
67 * (empty): integer access
71 * (empty): for floats or 32 bit size
82 * (empty): target cpu endianness or 8 bit access
83 * r : reversed target cpu endianness (not implemented yet)
84 * be : big endian (not implemented yet)
85 * le : little endian (not implemented yet)
88 * raw : host memory access
89 * user : user mode access using soft MMU
90 * kernel : kernel mode access using soft MMU
92 static inline int ldub_raw(void *ptr
)
94 return *(uint8_t *)ptr
;
97 static inline int ldsb_raw(void *ptr
)
99 return *(int8_t *)ptr
;
102 static inline void stb_raw(void *ptr
, int v
)
107 /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
108 kernel handles unaligned load/stores may give better results, but
109 it is a system wide setting : bad */
110 #if !defined(TARGET_WORDS_BIGENDIAN) && (defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
112 /* conservative code for little endian unaligned accesses */
113 static inline int lduw_raw(void *ptr
)
117 __asm__
__volatile__ ("lhbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
121 return p
[0] | (p
[1] << 8);
125 static inline int ldsw_raw(void *ptr
)
129 __asm__
__volatile__ ("lhbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
133 return (int16_t)(p
[0] | (p
[1] << 8));
137 static inline int ldl_raw(void *ptr
)
141 __asm__
__volatile__ ("lwbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
145 return p
[0] | (p
[1] << 8) | (p
[2] << 16) | (p
[3] << 24);
149 static inline uint64_t ldq_raw(void *ptr
)
155 return v1
| ((uint64_t)v2
<< 32);
158 static inline void stw_raw(void *ptr
, int v
)
161 __asm__
__volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr
) : "r" (v
), "r" (ptr
));
169 static inline void stl_raw(void *ptr
, int v
)
172 __asm__
__volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr
) : "r" (v
), "r" (ptr
));
182 static inline void stq_raw(void *ptr
, uint64_t v
)
185 stl_raw(p
, (uint32_t)v
);
186 stl_raw(p
+ 4, v
>> 32);
191 static inline float ldfl_raw(void *ptr
)
201 static inline void stfl_raw(void *ptr
, float v
)
211 static inline double ldfq_raw(void *ptr
)
214 u
.l
.lower
= ldl_raw(ptr
);
215 u
.l
.upper
= ldl_raw(ptr
+ 4);
219 static inline void stfq_raw(void *ptr
, double v
)
223 stl_raw(ptr
, u
.l
.lower
);
224 stl_raw(ptr
+ 4, u
.l
.upper
);
227 #elif defined(TARGET_WORDS_BIGENDIAN) && (!defined(WORDS_BIGENDIAN) || defined(WORDS_ALIGNED))
229 static inline int lduw_raw(void *ptr
)
231 #if defined(__i386__)
233 asm volatile ("movzwl %1, %0\n"
236 : "m" (*(uint16_t *)ptr
));
239 uint8_t *b
= (uint8_t *) ptr
;
240 return ((b
[0] << 8) | b
[1]);
244 static inline int ldsw_raw(void *ptr
)
246 #if defined(__i386__)
248 asm volatile ("movzwl %1, %0\n"
251 : "m" (*(uint16_t *)ptr
));
254 uint8_t *b
= (uint8_t *) ptr
;
255 return (int16_t)((b
[0] << 8) | b
[1]);
259 static inline int ldl_raw(void *ptr
)
261 #if defined(__i386__)
263 asm volatile ("movl %1, %0\n"
266 : "m" (*(uint32_t *)ptr
));
269 uint8_t *b
= (uint8_t *) ptr
;
270 return (b
[0] << 24) | (b
[1] << 16) | (b
[2] << 8) | b
[3];
274 static inline uint64_t ldq_raw(void *ptr
)
279 return (((uint64_t)a
<<32)|b
);
282 static inline void stw_raw(void *ptr
, int v
)
284 #if defined(__i386__)
285 asm volatile ("xchgb %b0, %h0\n"
288 : "m" (*(uint16_t *)ptr
), "0" (v
));
290 uint8_t *d
= (uint8_t *) ptr
;
296 static inline void stl_raw(void *ptr
, int v
)
298 #if defined(__i386__)
299 asm volatile ("bswap %0\n"
302 : "m" (*(uint32_t *)ptr
), "0" (v
));
304 uint8_t *d
= (uint8_t *) ptr
;
312 static inline void stq_raw(void *ptr
, uint64_t v
)
314 stl_raw(ptr
, v
>> 32);
320 static inline float ldfl_raw(void *ptr
)
330 static inline void stfl_raw(void *ptr
, float v
)
340 static inline double ldfq_raw(void *ptr
)
343 u
.l
.upper
= ldl_raw(ptr
);
344 u
.l
.lower
= ldl_raw(ptr
+ 4);
348 static inline void stfq_raw(void *ptr
, double v
)
352 stl_raw(ptr
, u
.l
.upper
);
353 stl_raw(ptr
+ 4, u
.l
.lower
);
358 static inline int lduw_raw(void *ptr
)
360 return *(uint16_t *)ptr
;
363 static inline int ldsw_raw(void *ptr
)
365 return *(int16_t *)ptr
;
368 static inline int ldl_raw(void *ptr
)
370 return *(uint32_t *)ptr
;
373 static inline uint64_t ldq_raw(void *ptr
)
375 return *(uint64_t *)ptr
;
378 static inline void stw_raw(void *ptr
, int v
)
380 *(uint16_t *)ptr
= v
;
383 static inline void stl_raw(void *ptr
, int v
)
385 *(uint32_t *)ptr
= v
;
388 static inline void stq_raw(void *ptr
, uint64_t v
)
390 *(uint64_t *)ptr
= v
;
395 static inline float ldfl_raw(void *ptr
)
397 return *(float *)ptr
;
400 static inline double ldfq_raw(void *ptr
)
402 return *(double *)ptr
;
405 static inline void stfl_raw(void *ptr
, float v
)
410 static inline void stfq_raw(void *ptr
, double v
)
416 /* MMU memory access macros */
418 #if defined(CONFIG_USER_ONLY)
420 /* if user mode, no other memory access functions */
421 #define ldub(p) ldub_raw(p)
422 #define ldsb(p) ldsb_raw(p)
423 #define lduw(p) lduw_raw(p)
424 #define ldsw(p) ldsw_raw(p)
425 #define ldl(p) ldl_raw(p)
426 #define ldq(p) ldq_raw(p)
427 #define ldfl(p) ldfl_raw(p)
428 #define ldfq(p) ldfq_raw(p)
429 #define stb(p, v) stb_raw(p, v)
430 #define stw(p, v) stw_raw(p, v)
431 #define stl(p, v) stl_raw(p, v)
432 #define stq(p, v) stq_raw(p, v)
433 #define stfl(p, v) stfl_raw(p, v)
434 #define stfq(p, v) stfq_raw(p, v)
436 #define ldub_code(p) ldub_raw(p)
437 #define ldsb_code(p) ldsb_raw(p)
438 #define lduw_code(p) lduw_raw(p)
439 #define ldsw_code(p) ldsw_raw(p)
440 #define ldl_code(p) ldl_raw(p)
442 #define ldub_kernel(p) ldub_raw(p)
443 #define ldsb_kernel(p) ldsb_raw(p)
444 #define lduw_kernel(p) lduw_raw(p)
445 #define ldsw_kernel(p) ldsw_raw(p)
446 #define ldl_kernel(p) ldl_raw(p)
447 #define ldfl_kernel(p) ldfl_raw(p)
448 #define ldfq_kernel(p) ldfq_raw(p)
449 #define stb_kernel(p, v) stb_raw(p, v)
450 #define stw_kernel(p, v) stw_raw(p, v)
451 #define stl_kernel(p, v) stl_raw(p, v)
452 #define stq_kernel(p, v) stq_raw(p, v)
453 #define stfl_kernel(p, v) stfl_raw(p, v)
454 #define stfq_kernel(p, vt) stfq_raw(p, v)
456 #endif /* defined(CONFIG_USER_ONLY) */
458 /* page related stuff */
460 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
461 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
462 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
464 extern unsigned long real_host_page_size
;
465 extern unsigned long host_page_bits
;
466 extern unsigned long host_page_size
;
467 extern unsigned long host_page_mask
;
469 #define HOST_PAGE_ALIGN(addr) (((addr) + host_page_size - 1) & host_page_mask)
471 /* same as PROT_xxx */
472 #define PAGE_READ 0x0001
473 #define PAGE_WRITE 0x0002
474 #define PAGE_EXEC 0x0004
475 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
476 #define PAGE_VALID 0x0008
477 /* original state of the write flag (used when tracking self-modifying
479 #define PAGE_WRITE_ORG 0x0010
481 void page_dump(FILE *f
);
482 int page_get_flags(unsigned long address
);
483 void page_set_flags(unsigned long start
, unsigned long end
, int flags
);
484 void page_unprotect_range(uint8_t *data
, unsigned long data_size
);
486 #define SINGLE_CPU_DEFINES
487 #ifdef SINGLE_CPU_DEFINES
489 #if defined(TARGET_I386)
491 #define CPUState CPUX86State
492 #define cpu_init cpu_x86_init
493 #define cpu_exec cpu_x86_exec
494 #define cpu_gen_code cpu_x86_gen_code
495 #define cpu_interrupt cpu_x86_interrupt
496 #define cpu_signal_handler cpu_x86_signal_handler
497 #define cpu_dump_state cpu_x86_dump_state
499 #elif defined(TARGET_ARM)
501 #define CPUState CPUARMState
502 #define cpu_init cpu_arm_init
503 #define cpu_exec cpu_arm_exec
504 #define cpu_gen_code cpu_arm_gen_code
505 #define cpu_interrupt cpu_arm_interrupt
506 #define cpu_signal_handler cpu_arm_signal_handler
507 #define cpu_dump_state cpu_arm_dump_state
509 #elif defined(TARGET_SPARC)
511 #define CPUState CPUSPARCState
512 #define cpu_init cpu_sparc_init
513 #define cpu_exec cpu_sparc_exec
514 #define cpu_gen_code cpu_sparc_gen_code
515 #define cpu_interrupt cpu_sparc_interrupt
516 #define cpu_signal_handler cpu_sparc_signal_handler
517 #define cpu_dump_state cpu_sparc_dump_state
519 #elif defined(TARGET_PPC)
521 #define CPUState CPUPPCState
522 #define cpu_init cpu_ppc_init
523 #define cpu_exec cpu_ppc_exec
524 #define cpu_gen_code cpu_ppc_gen_code
525 #define cpu_interrupt cpu_ppc_interrupt
526 #define cpu_signal_handler cpu_ppc_signal_handler
527 #define cpu_dump_state cpu_ppc_dump_state
531 #error unsupported target CPU
535 #endif /* SINGLE_CPU_DEFINES */
537 #define DEFAULT_GDBSTUB_PORT 1234
539 void cpu_abort(CPUState
*env
, const char *fmt
, ...);
540 extern CPUState
*cpu_single_env
;
541 extern int code_copy_enabled
;
543 #define CPU_INTERRUPT_EXIT 0x01 /* wants exit from main loop */
544 #define CPU_INTERRUPT_HARD 0x02 /* hardware interrupt pending */
545 #define CPU_INTERRUPT_EXITTB 0x04 /* exit the current TB (use for x86 a20 case) */
546 void cpu_interrupt(CPUState
*s
, int mask
);
548 int cpu_breakpoint_insert(CPUState
*env
, uint32_t pc
);
549 int cpu_breakpoint_remove(CPUState
*env
, uint32_t pc
);
550 void cpu_single_step(CPUState
*env
, int enabled
);
552 /* Return the physical page corresponding to a virtual one. Use it
553 only for debugging because no protection checks are done. Return -1
555 target_ulong
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
);
557 #define CPU_LOG_ALL 1
558 void cpu_set_log(int log_flags
);
559 void cpu_set_log_filename(const char *filename
);
563 /* NOTE: as these functions may be even used when there is an isa
564 brige on non x86 targets, we always defined them */
565 #ifndef NO_CPU_IO_DEFS
566 void cpu_outb(CPUState
*env
, int addr
, int val
);
567 void cpu_outw(CPUState
*env
, int addr
, int val
);
568 void cpu_outl(CPUState
*env
, int addr
, int val
);
569 int cpu_inb(CPUState
*env
, int addr
);
570 int cpu_inw(CPUState
*env
, int addr
);
571 int cpu_inl(CPUState
*env
, int addr
);
576 extern int phys_ram_size
;
577 extern int phys_ram_fd
;
578 extern uint8_t *phys_ram_base
;
579 extern uint8_t *phys_ram_dirty
;
581 /* physical memory access */
582 #define IO_MEM_NB_ENTRIES 256
583 #define TLB_INVALID_MASK (1 << 3)
584 #define IO_MEM_SHIFT 4
586 #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
587 #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
588 #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
589 #define IO_MEM_CODE (3 << IO_MEM_SHIFT) /* used internally, never use directly */
590 #define IO_MEM_NOTDIRTY (4 << IO_MEM_SHIFT) /* used internally, never use directly */
592 /* NOTE: vaddr is only used internally. Never use it except if you know what you do */
593 typedef void CPUWriteMemoryFunc(uint32_t addr
, uint32_t value
, uint32_t vaddr
);
594 typedef uint32_t CPUReadMemoryFunc(uint32_t addr
);
596 void cpu_register_physical_memory(unsigned long start_addr
, unsigned long size
,
598 int cpu_register_io_memory(int io_index
,
599 CPUReadMemoryFunc
**mem_read
,
600 CPUWriteMemoryFunc
**mem_write
);
602 void cpu_physical_memory_rw(target_ulong addr
, uint8_t *buf
,
603 int len
, int is_write
);
604 static inline void cpu_physical_memory_read(target_ulong addr
, uint8_t *buf
,
607 cpu_physical_memory_rw(addr
, buf
, len
, 0);
609 static inline void cpu_physical_memory_write(target_ulong addr
, const uint8_t *buf
,
612 cpu_physical_memory_rw(addr
, (uint8_t *)buf
, len
, 1);
615 int cpu_memory_rw_debug(CPUState
*env
, target_ulong addr
,
616 uint8_t *buf
, int len
, int is_write
);
618 /* read dirty bit (return 0 or 1) */
619 static inline int cpu_physical_memory_is_dirty(target_ulong addr
)
621 return phys_ram_dirty
[addr
>> TARGET_PAGE_BITS
];
624 static inline void cpu_physical_memory_set_dirty(target_ulong addr
)
626 phys_ram_dirty
[addr
>> TARGET_PAGE_BITS
] = 1;
629 void cpu_physical_memory_reset_dirty(target_ulong start
, target_ulong end
);
632 extern int gdbstub_fd
;
633 CPUState
*cpu_gdbstub_get_env(void *opaque
);
634 int cpu_gdbstub(void *opaque
, int (*main_loop
)(void *opaque
), int port
);
636 #endif /* CPU_ALL_H */