2 * defines common to all virtual CPUs
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "qemu-common.h"
23 #include "cpu-common.h"
25 /* some important defines:
27 * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
30 * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
31 * otherwise little endian.
33 * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
35 * TARGET_WORDS_BIGENDIAN : same for target cpu
38 #include "softfloat.h"
40 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
46 static inline uint16_t tswap16(uint16_t s
)
51 static inline uint32_t tswap32(uint32_t s
)
56 static inline uint64_t tswap64(uint64_t s
)
61 static inline void tswap16s(uint16_t *s
)
66 static inline void tswap32s(uint32_t *s
)
71 static inline void tswap64s(uint64_t *s
)
78 static inline uint16_t tswap16(uint16_t s
)
83 static inline uint32_t tswap32(uint32_t s
)
88 static inline uint64_t tswap64(uint64_t s
)
93 static inline void tswap16s(uint16_t *s
)
97 static inline void tswap32s(uint32_t *s
)
101 static inline void tswap64s(uint64_t *s
)
107 #if TARGET_LONG_SIZE == 4
108 #define tswapl(s) tswap32(s)
109 #define tswapls(s) tswap32s((uint32_t *)(s))
110 #define bswaptls(s) bswap32s(s)
112 #define tswapl(s) tswap64(s)
113 #define tswapls(s) tswap64s((uint64_t *)(s))
114 #define bswaptls(s) bswap64s(s)
122 /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
126 #if defined(HOST_WORDS_BIGENDIAN) \
127 || (defined(__arm__) && !defined(__VFP_FP__) && !defined(CONFIG_SOFTFLOAT))
141 #if defined(FLOATX80)
151 #if defined(CONFIG_SOFTFLOAT)
154 #if defined(HOST_WORDS_BIGENDIAN)
180 /* CPU memory access without any memory or io remapping */
183 * the generic syntax for the memory accesses is:
185 * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
187 * store: st{type}{size}{endian}_{access_type}(ptr, val)
190 * (empty): integer access
194 * (empty): for floats or 32 bit size
205 * (empty): target cpu endianness or 8 bit access
206 * r : reversed target cpu endianness (not implemented yet)
207 * be : big endian (not implemented yet)
208 * le : little endian (not implemented yet)
211 * raw : host memory access
212 * user : user mode access using soft MMU
213 * kernel : kernel mode access using soft MMU
215 static inline int ldub_p(const void *ptr
)
217 return *(uint8_t *)ptr
;
220 static inline int ldsb_p(const void *ptr
)
222 return *(int8_t *)ptr
;
225 static inline void stb_p(void *ptr
, int v
)
230 /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
231 kernel handles unaligned load/stores may give better results, but
232 it is a system wide setting : bad */
233 #if defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
235 /* conservative code for little endian unaligned accesses */
236 static inline int lduw_le_p(const void *ptr
)
240 __asm__
__volatile__ ("lhbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
243 const uint8_t *p
= ptr
;
244 return p
[0] | (p
[1] << 8);
248 static inline int ldsw_le_p(const void *ptr
)
252 __asm__
__volatile__ ("lhbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
255 const uint8_t *p
= ptr
;
256 return (int16_t)(p
[0] | (p
[1] << 8));
260 static inline int ldl_le_p(const void *ptr
)
264 __asm__
__volatile__ ("lwbrx %0,0,%1" : "=r" (val
) : "r" (ptr
));
267 const uint8_t *p
= ptr
;
268 return p
[0] | (p
[1] << 8) | (p
[2] << 16) | (p
[3] << 24);
272 static inline uint64_t ldq_le_p(const void *ptr
)
274 const uint8_t *p
= ptr
;
277 v2
= ldl_le_p(p
+ 4);
278 return v1
| ((uint64_t)v2
<< 32);
281 static inline void stw_le_p(void *ptr
, int v
)
284 __asm__
__volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr
) : "r" (v
), "r" (ptr
));
292 static inline void stl_le_p(void *ptr
, int v
)
295 __asm__
__volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr
) : "r" (v
), "r" (ptr
));
305 static inline void stq_le_p(void *ptr
, uint64_t v
)
308 stl_le_p(p
, (uint32_t)v
);
309 stl_le_p(p
+ 4, v
>> 32);
314 static inline float32
ldfl_le_p(const void *ptr
)
324 static inline void stfl_le_p(void *ptr
, float32 v
)
334 static inline float64
ldfq_le_p(const void *ptr
)
337 u
.l
.lower
= ldl_le_p(ptr
);
338 u
.l
.upper
= ldl_le_p(ptr
+ 4);
342 static inline void stfq_le_p(void *ptr
, float64 v
)
346 stl_le_p(ptr
, u
.l
.lower
);
347 stl_le_p(ptr
+ 4, u
.l
.upper
);
352 static inline int lduw_le_p(const void *ptr
)
354 return *(uint16_t *)ptr
;
357 static inline int ldsw_le_p(const void *ptr
)
359 return *(int16_t *)ptr
;
362 static inline int ldl_le_p(const void *ptr
)
364 return *(uint32_t *)ptr
;
367 static inline uint64_t ldq_le_p(const void *ptr
)
369 return *(uint64_t *)ptr
;
372 static inline void stw_le_p(void *ptr
, int v
)
374 *(uint16_t *)ptr
= v
;
377 static inline void stl_le_p(void *ptr
, int v
)
379 *(uint32_t *)ptr
= v
;
382 static inline void stq_le_p(void *ptr
, uint64_t v
)
384 *(uint64_t *)ptr
= v
;
389 static inline float32
ldfl_le_p(const void *ptr
)
391 return *(float32
*)ptr
;
394 static inline float64
ldfq_le_p(const void *ptr
)
396 return *(float64
*)ptr
;
399 static inline void stfl_le_p(void *ptr
, float32 v
)
404 static inline void stfq_le_p(void *ptr
, float64 v
)
410 #if !defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
412 static inline int lduw_be_p(const void *ptr
)
414 #if defined(__i386__)
416 asm volatile ("movzwl %1, %0\n"
419 : "m" (*(uint16_t *)ptr
));
422 const uint8_t *b
= ptr
;
423 return ((b
[0] << 8) | b
[1]);
427 static inline int ldsw_be_p(const void *ptr
)
429 #if defined(__i386__)
431 asm volatile ("movzwl %1, %0\n"
434 : "m" (*(uint16_t *)ptr
));
437 const uint8_t *b
= ptr
;
438 return (int16_t)((b
[0] << 8) | b
[1]);
442 static inline int ldl_be_p(const void *ptr
)
444 #if defined(__i386__) || defined(__x86_64__)
446 asm volatile ("movl %1, %0\n"
449 : "m" (*(uint32_t *)ptr
));
452 const uint8_t *b
= ptr
;
453 return (b
[0] << 24) | (b
[1] << 16) | (b
[2] << 8) | b
[3];
457 static inline uint64_t ldq_be_p(const void *ptr
)
461 b
= ldl_be_p((uint8_t *)ptr
+ 4);
462 return (((uint64_t)a
<<32)|b
);
465 static inline void stw_be_p(void *ptr
, int v
)
467 #if defined(__i386__)
468 asm volatile ("xchgb %b0, %h0\n"
471 : "m" (*(uint16_t *)ptr
), "0" (v
));
473 uint8_t *d
= (uint8_t *) ptr
;
479 static inline void stl_be_p(void *ptr
, int v
)
481 #if defined(__i386__) || defined(__x86_64__)
482 asm volatile ("bswap %0\n"
485 : "m" (*(uint32_t *)ptr
), "0" (v
));
487 uint8_t *d
= (uint8_t *) ptr
;
495 static inline void stq_be_p(void *ptr
, uint64_t v
)
497 stl_be_p(ptr
, v
>> 32);
498 stl_be_p((uint8_t *)ptr
+ 4, v
);
503 static inline float32
ldfl_be_p(const void *ptr
)
513 static inline void stfl_be_p(void *ptr
, float32 v
)
523 static inline float64
ldfq_be_p(const void *ptr
)
526 u
.l
.upper
= ldl_be_p(ptr
);
527 u
.l
.lower
= ldl_be_p((uint8_t *)ptr
+ 4);
531 static inline void stfq_be_p(void *ptr
, float64 v
)
535 stl_be_p(ptr
, u
.l
.upper
);
536 stl_be_p((uint8_t *)ptr
+ 4, u
.l
.lower
);
541 static inline int lduw_be_p(const void *ptr
)
543 return *(uint16_t *)ptr
;
546 static inline int ldsw_be_p(const void *ptr
)
548 return *(int16_t *)ptr
;
551 static inline int ldl_be_p(const void *ptr
)
553 return *(uint32_t *)ptr
;
556 static inline uint64_t ldq_be_p(const void *ptr
)
558 return *(uint64_t *)ptr
;
561 static inline void stw_be_p(void *ptr
, int v
)
563 *(uint16_t *)ptr
= v
;
566 static inline void stl_be_p(void *ptr
, int v
)
568 *(uint32_t *)ptr
= v
;
571 static inline void stq_be_p(void *ptr
, uint64_t v
)
573 *(uint64_t *)ptr
= v
;
578 static inline float32
ldfl_be_p(const void *ptr
)
580 return *(float32
*)ptr
;
583 static inline float64
ldfq_be_p(const void *ptr
)
585 return *(float64
*)ptr
;
588 static inline void stfl_be_p(void *ptr
, float32 v
)
593 static inline void stfq_be_p(void *ptr
, float64 v
)
600 /* target CPU memory access functions */
601 #if defined(TARGET_WORDS_BIGENDIAN)
602 #define lduw_p(p) lduw_be_p(p)
603 #define ldsw_p(p) ldsw_be_p(p)
604 #define ldl_p(p) ldl_be_p(p)
605 #define ldq_p(p) ldq_be_p(p)
606 #define ldfl_p(p) ldfl_be_p(p)
607 #define ldfq_p(p) ldfq_be_p(p)
608 #define stw_p(p, v) stw_be_p(p, v)
609 #define stl_p(p, v) stl_be_p(p, v)
610 #define stq_p(p, v) stq_be_p(p, v)
611 #define stfl_p(p, v) stfl_be_p(p, v)
612 #define stfq_p(p, v) stfq_be_p(p, v)
614 #define lduw_p(p) lduw_le_p(p)
615 #define ldsw_p(p) ldsw_le_p(p)
616 #define ldl_p(p) ldl_le_p(p)
617 #define ldq_p(p) ldq_le_p(p)
618 #define ldfl_p(p) ldfl_le_p(p)
619 #define ldfq_p(p) ldfq_le_p(p)
620 #define stw_p(p, v) stw_le_p(p, v)
621 #define stl_p(p, v) stl_le_p(p, v)
622 #define stq_p(p, v) stq_le_p(p, v)
623 #define stfl_p(p, v) stfl_le_p(p, v)
624 #define stfq_p(p, v) stfq_le_p(p, v)
627 /* MMU memory access macros */
629 #if defined(CONFIG_USER_ONLY)
631 #include "qemu-types.h"
633 /* On some host systems the guest address space is reserved on the host.
634 * This allows the guest address space to be offset to a convenient location.
636 #if defined(CONFIG_USE_GUEST_BASE)
637 extern unsigned long guest_base
;
638 extern int have_guest_base
;
639 extern unsigned long reserved_va
;
640 #define GUEST_BASE guest_base
641 #define RESERVED_VA reserved_va
643 #define GUEST_BASE 0ul
644 #define RESERVED_VA 0ul
647 /* All direct uses of g2h and h2g need to go away for usermode softmmu. */
648 #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
650 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
651 #define h2g_valid(x) 1
653 #define h2g_valid(x) ({ \
654 unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
655 __guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS); \
660 unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
661 /* Check if given address fits target address space */ \
662 assert(h2g_valid(x)); \
666 #define saddr(x) g2h(x)
667 #define laddr(x) g2h(x)
669 #else /* !CONFIG_USER_ONLY */
670 /* NOTE: we use double casts if pointers and target_ulong have
672 #define saddr(x) (uint8_t *)(long)(x)
673 #define laddr(x) (uint8_t *)(long)(x)
676 #define ldub_raw(p) ldub_p(laddr((p)))
677 #define ldsb_raw(p) ldsb_p(laddr((p)))
678 #define lduw_raw(p) lduw_p(laddr((p)))
679 #define ldsw_raw(p) ldsw_p(laddr((p)))
680 #define ldl_raw(p) ldl_p(laddr((p)))
681 #define ldq_raw(p) ldq_p(laddr((p)))
682 #define ldfl_raw(p) ldfl_p(laddr((p)))
683 #define ldfq_raw(p) ldfq_p(laddr((p)))
684 #define stb_raw(p, v) stb_p(saddr((p)), v)
685 #define stw_raw(p, v) stw_p(saddr((p)), v)
686 #define stl_raw(p, v) stl_p(saddr((p)), v)
687 #define stq_raw(p, v) stq_p(saddr((p)), v)
688 #define stfl_raw(p, v) stfl_p(saddr((p)), v)
689 #define stfq_raw(p, v) stfq_p(saddr((p)), v)
692 #if defined(CONFIG_USER_ONLY)
694 /* if user mode, no other memory access functions */
695 #define ldub(p) ldub_raw(p)
696 #define ldsb(p) ldsb_raw(p)
697 #define lduw(p) lduw_raw(p)
698 #define ldsw(p) ldsw_raw(p)
699 #define ldl(p) ldl_raw(p)
700 #define ldq(p) ldq_raw(p)
701 #define ldfl(p) ldfl_raw(p)
702 #define ldfq(p) ldfq_raw(p)
703 #define stb(p, v) stb_raw(p, v)
704 #define stw(p, v) stw_raw(p, v)
705 #define stl(p, v) stl_raw(p, v)
706 #define stq(p, v) stq_raw(p, v)
707 #define stfl(p, v) stfl_raw(p, v)
708 #define stfq(p, v) stfq_raw(p, v)
710 #define ldub_code(p) ldub_raw(p)
711 #define ldsb_code(p) ldsb_raw(p)
712 #define lduw_code(p) lduw_raw(p)
713 #define ldsw_code(p) ldsw_raw(p)
714 #define ldl_code(p) ldl_raw(p)
715 #define ldq_code(p) ldq_raw(p)
717 #define ldub_kernel(p) ldub_raw(p)
718 #define ldsb_kernel(p) ldsb_raw(p)
719 #define lduw_kernel(p) lduw_raw(p)
720 #define ldsw_kernel(p) ldsw_raw(p)
721 #define ldl_kernel(p) ldl_raw(p)
722 #define ldq_kernel(p) ldq_raw(p)
723 #define ldfl_kernel(p) ldfl_raw(p)
724 #define ldfq_kernel(p) ldfq_raw(p)
725 #define stb_kernel(p, v) stb_raw(p, v)
726 #define stw_kernel(p, v) stw_raw(p, v)
727 #define stl_kernel(p, v) stl_raw(p, v)
728 #define stq_kernel(p, v) stq_raw(p, v)
729 #define stfl_kernel(p, v) stfl_raw(p, v)
730 #define stfq_kernel(p, vt) stfq_raw(p, v)
732 #endif /* defined(CONFIG_USER_ONLY) */
734 /* page related stuff */
736 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
737 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
738 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
740 /* ??? These should be the larger of unsigned long and target_ulong. */
741 extern unsigned long qemu_real_host_page_size
;
742 extern unsigned long qemu_host_page_bits
;
743 extern unsigned long qemu_host_page_size
;
744 extern unsigned long qemu_host_page_mask
;
746 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
748 /* same as PROT_xxx */
749 #define PAGE_READ 0x0001
750 #define PAGE_WRITE 0x0002
751 #define PAGE_EXEC 0x0004
752 #define PAGE_BITS (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
753 #define PAGE_VALID 0x0008
754 /* original state of the write flag (used when tracking self-modifying
756 #define PAGE_WRITE_ORG 0x0010
757 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
758 /* FIXME: Code that sets/uses this is broken and needs to go away. */
759 #define PAGE_RESERVED 0x0020
762 #if defined(CONFIG_USER_ONLY)
763 void page_dump(FILE *f
);
765 typedef int (*walk_memory_regions_fn
)(void *, abi_ulong
,
766 abi_ulong
, unsigned long);
767 int walk_memory_regions(void *, walk_memory_regions_fn
);
769 int page_get_flags(target_ulong address
);
770 void page_set_flags(target_ulong start
, target_ulong end
, int flags
);
771 int page_check_range(target_ulong start
, target_ulong len
, int flags
);
774 CPUState
*cpu_copy(CPUState
*env
);
775 CPUState
*qemu_get_cpu(int cpu
);
777 #define CPU_DUMP_CODE 0x00010000
779 void cpu_dump_state(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
781 void cpu_dump_statistics(CPUState
*env
, FILE *f
, fprintf_function cpu_fprintf
,
784 void QEMU_NORETURN
cpu_abort(CPUState
*env
, const char *fmt
, ...)
786 extern CPUState
*first_cpu
;
787 extern CPUState
*cpu_single_env
;
789 /* Flags for use in ENV->INTERRUPT_PENDING.
791 The numbers assigned here are non-sequential in order to preserve
792 binary compatibility with the vmstate dump. Bit 0 (0x0001) was
793 previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
796 /* External hardware interrupt pending. This is typically used for
797 interrupts from devices. */
798 #define CPU_INTERRUPT_HARD 0x0002
800 /* Exit the current TB. This is typically used when some system-level device
801 makes some change to the memory mapping. E.g. the a20 line change. */
802 #define CPU_INTERRUPT_EXITTB 0x0004
805 #define CPU_INTERRUPT_HALT 0x0020
807 /* Debug event pending. */
808 #define CPU_INTERRUPT_DEBUG 0x0080
810 /* Several target-specific external hardware interrupts. Each target/cpu.h
811 should define proper names based on these defines. */
812 #define CPU_INTERRUPT_TGT_EXT_0 0x0008
813 #define CPU_INTERRUPT_TGT_EXT_1 0x0010
814 #define CPU_INTERRUPT_TGT_EXT_2 0x0040
815 #define CPU_INTERRUPT_TGT_EXT_3 0x0200
816 #define CPU_INTERRUPT_TGT_EXT_4 0x1000
818 /* Several target-specific internal interrupts. These differ from the
819 preceeding target-specific interrupts in that they are intended to
820 originate from within the cpu itself, typically in response to some
821 instruction being executed. These, therefore, are not masked while
822 single-stepping within the debugger. */
823 #define CPU_INTERRUPT_TGT_INT_0 0x0100
824 #define CPU_INTERRUPT_TGT_INT_1 0x0400
825 #define CPU_INTERRUPT_TGT_INT_2 0x0800
827 /* First unused bit: 0x2000. */
829 /* Temporary remapping from the generic names back to the previous
830 cpu-specific names. These will be moved to target-foo/cpu.h next. */
831 #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1
832 #define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
833 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
834 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
835 #define CPU_INTERRUPT_INIT CPU_INTERRUPT_TGT_INT_1
836 #define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_2
837 #define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
839 /* The set of all bits that should be masked when single-stepping. */
840 #define CPU_INTERRUPT_SSTEP_MASK \
841 (CPU_INTERRUPT_HARD \
842 | CPU_INTERRUPT_TGT_EXT_0 \
843 | CPU_INTERRUPT_TGT_EXT_1 \
844 | CPU_INTERRUPT_TGT_EXT_2 \
845 | CPU_INTERRUPT_TGT_EXT_3 \
846 | CPU_INTERRUPT_TGT_EXT_4)
848 #ifndef CONFIG_USER_ONLY
849 typedef void (*CPUInterruptHandler
)(CPUState
*, int);
851 extern CPUInterruptHandler cpu_interrupt_handler
;
853 static inline void cpu_interrupt(CPUState
*s
, int mask
)
855 cpu_interrupt_handler(s
, mask
);
857 #else /* USER_ONLY */
858 void cpu_interrupt(CPUState
*env
, int mask
);
859 #endif /* USER_ONLY */
861 void cpu_reset_interrupt(CPUState
*env
, int mask
);
863 void cpu_exit(CPUState
*s
);
865 int qemu_cpu_has_work(CPUState
*env
);
867 /* Breakpoint/watchpoint flags */
868 #define BP_MEM_READ 0x01
869 #define BP_MEM_WRITE 0x02
870 #define BP_MEM_ACCESS (BP_MEM_READ | BP_MEM_WRITE)
871 #define BP_STOP_BEFORE_ACCESS 0x04
872 #define BP_WATCHPOINT_HIT 0x08
876 int cpu_breakpoint_insert(CPUState
*env
, target_ulong pc
, int flags
,
877 CPUBreakpoint
**breakpoint
);
878 int cpu_breakpoint_remove(CPUState
*env
, target_ulong pc
, int flags
);
879 void cpu_breakpoint_remove_by_ref(CPUState
*env
, CPUBreakpoint
*breakpoint
);
880 void cpu_breakpoint_remove_all(CPUState
*env
, int mask
);
881 int cpu_watchpoint_insert(CPUState
*env
, target_ulong addr
, target_ulong len
,
882 int flags
, CPUWatchpoint
**watchpoint
);
883 int cpu_watchpoint_remove(CPUState
*env
, target_ulong addr
,
884 target_ulong len
, int flags
);
885 void cpu_watchpoint_remove_by_ref(CPUState
*env
, CPUWatchpoint
*watchpoint
);
886 void cpu_watchpoint_remove_all(CPUState
*env
, int mask
);
888 #define SSTEP_ENABLE 0x1 /* Enable simulated HW single stepping */
889 #define SSTEP_NOIRQ 0x2 /* Do not use IRQ while single stepping */
890 #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */
892 void cpu_single_step(CPUState
*env
, int enabled
);
893 void cpu_reset(CPUState
*s
);
894 int cpu_is_stopped(CPUState
*env
);
895 void run_on_cpu(CPUState
*env
, void (*func
)(void *data
), void *data
);
897 #define CPU_LOG_TB_OUT_ASM (1 << 0)
898 #define CPU_LOG_TB_IN_ASM (1 << 1)
899 #define CPU_LOG_TB_OP (1 << 2)
900 #define CPU_LOG_TB_OP_OPT (1 << 3)
901 #define CPU_LOG_INT (1 << 4)
902 #define CPU_LOG_EXEC (1 << 5)
903 #define CPU_LOG_PCALL (1 << 6)
904 #define CPU_LOG_IOPORT (1 << 7)
905 #define CPU_LOG_TB_CPU (1 << 8)
906 #define CPU_LOG_RESET (1 << 9)
908 /* define log items */
909 typedef struct CPULogItem
{
915 extern const CPULogItem cpu_log_items
[];
917 void cpu_set_log(int log_flags
);
918 void cpu_set_log_filename(const char *filename
);
919 int cpu_str_to_log_mask(const char *str
);
921 #if !defined(CONFIG_USER_ONLY)
923 /* Return the physical page corresponding to a virtual one. Use it
924 only for debugging because no protection checks are done. Return -1
926 target_phys_addr_t
cpu_get_phys_page_debug(CPUState
*env
, target_ulong addr
);
930 extern int phys_ram_fd
;
931 extern ram_addr_t ram_size
;
933 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
934 #define RAM_PREALLOC_MASK (1 << 0)
936 typedef struct RAMBlock
{
942 QLIST_ENTRY(RAMBlock
) next
;
943 #if defined(__linux__) && !defined(TARGET_S390X)
948 typedef struct RAMList
{
950 QLIST_HEAD(ram
, RAMBlock
) blocks
;
952 extern RAMList ram_list
;
954 extern const char *mem_path
;
955 extern int mem_prealloc
;
957 /* physical memory access */
959 /* MMIO pages are identified by a combination of an IO device index and
960 3 flags. The ROMD code stores the page ram offset in iotlb entry,
961 so only a limited number of ids are avaiable. */
963 #define IO_MEM_NB_ENTRIES (1 << (TARGET_PAGE_BITS - IO_MEM_SHIFT))
965 /* Flags stored in the low bits of the TLB virtual address. These are
966 defined so that fast path ram access is all zeros. */
967 /* Zero if TLB entry is valid. */
968 #define TLB_INVALID_MASK (1 << 3)
969 /* Set if TLB entry references a clean RAM page. The iotlb entry will
970 contain the page physical address. */
971 #define TLB_NOTDIRTY (1 << 4)
972 /* Set if TLB entry is an IO callback. */
973 #define TLB_MMIO (1 << 5)
975 #define VGA_DIRTY_FLAG 0x01
976 #define CODE_DIRTY_FLAG 0x02
977 #define MIGRATION_DIRTY_FLAG 0x08
979 /* read dirty bit (return 0 or 1) */
980 static inline int cpu_physical_memory_is_dirty(ram_addr_t addr
)
982 return ram_list
.phys_dirty
[addr
>> TARGET_PAGE_BITS
] == 0xff;
985 static inline int cpu_physical_memory_get_dirty_flags(ram_addr_t addr
)
987 return ram_list
.phys_dirty
[addr
>> TARGET_PAGE_BITS
];
990 static inline int cpu_physical_memory_get_dirty(ram_addr_t addr
,
993 return ram_list
.phys_dirty
[addr
>> TARGET_PAGE_BITS
] & dirty_flags
;
996 static inline void cpu_physical_memory_set_dirty(ram_addr_t addr
)
998 ram_list
.phys_dirty
[addr
>> TARGET_PAGE_BITS
] = 0xff;
1001 static inline int cpu_physical_memory_set_dirty_flags(ram_addr_t addr
,
1004 return ram_list
.phys_dirty
[addr
>> TARGET_PAGE_BITS
] |= dirty_flags
;
1007 static inline void cpu_physical_memory_mask_dirty_range(ram_addr_t start
,
1014 len
= length
>> TARGET_PAGE_BITS
;
1015 mask
= ~dirty_flags
;
1016 p
= ram_list
.phys_dirty
+ (start
>> TARGET_PAGE_BITS
);
1017 for (i
= 0; i
< len
; i
++) {
1022 void cpu_physical_memory_reset_dirty(ram_addr_t start
, ram_addr_t end
,
1024 void cpu_tlb_update_dirty(CPUState
*env
);
1026 int cpu_physical_memory_set_dirty_tracking(int enable
);
1028 int cpu_physical_memory_get_dirty_tracking(void);
1030 int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr
,
1031 target_phys_addr_t end_addr
);
1033 int cpu_physical_log_start(target_phys_addr_t start_addr
,
1036 int cpu_physical_log_stop(target_phys_addr_t start_addr
,
1039 void dump_exec_info(FILE *f
, fprintf_function cpu_fprintf
);
1040 #endif /* !CONFIG_USER_ONLY */
1042 int cpu_memory_rw_debug(CPUState
*env
, target_ulong addr
,
1043 uint8_t *buf
, int len
, int is_write
);
1045 #endif /* CPU_ALL_H */