4 /* CPU interfaces that are target independent. */
6 #ifdef TARGET_PHYS_ADDR_BITS
15 #include "qemu-queue.h"
17 #if !defined(CONFIG_USER_ONLY)
25 /* address in the RAM (different from a physical address) */
26 #if defined(CONFIG_XEN_BACKEND) && TARGET_PHYS_ADDR_BITS == 64
27 typedef uint64_t ram_addr_t
;
28 # define RAM_ADDR_MAX UINT64_MAX
29 # define RAM_ADDR_FMT "%" PRIx64
31 typedef unsigned long ram_addr_t
;
32 # define RAM_ADDR_MAX ULONG_MAX
33 # define RAM_ADDR_FMT "%lx"
38 typedef void CPUWriteMemoryFunc(void *opaque
, target_phys_addr_t addr
, uint32_t value
);
39 typedef uint32_t CPUReadMemoryFunc(void *opaque
, target_phys_addr_t addr
);
41 void cpu_register_physical_memory_log(target_phys_addr_t start_addr
,
43 ram_addr_t phys_offset
,
44 ram_addr_t region_offset
,
47 static inline void cpu_register_physical_memory_offset(target_phys_addr_t start_addr
,
49 ram_addr_t phys_offset
,
50 ram_addr_t region_offset
)
52 cpu_register_physical_memory_log(start_addr
, size
, phys_offset
,
53 region_offset
, false);
56 static inline void cpu_register_physical_memory(target_phys_addr_t start_addr
,
58 ram_addr_t phys_offset
)
60 cpu_register_physical_memory_offset(start_addr
, size
, phys_offset
, 0);
63 ram_addr_t
cpu_get_physical_page_desc(target_phys_addr_t addr
);
65 ram_addr_t
qemu_ram_alloc_from_ptr(DeviceState
*dev
, const char *name
,
66 ram_addr_t size
, void *host
,
67 struct MemoryRegion
*mr
);
68 ram_addr_t
qemu_ram_alloc(DeviceState
*dev
, const char *name
, ram_addr_t size
,
69 struct MemoryRegion
*mr
);
70 void qemu_ram_free(ram_addr_t addr
);
71 void qemu_ram_free_from_ptr(ram_addr_t addr
);
72 void qemu_ram_remap(ram_addr_t addr
, ram_addr_t length
);
73 /* This should only be used for ram local to a device. */
74 void *qemu_get_ram_ptr(ram_addr_t addr
);
75 void *qemu_ram_ptr_length(ram_addr_t addr
, ram_addr_t
*size
);
76 /* Same but slower, to use for migration, where the order of
77 * RAMBlocks must not change. */
78 void *qemu_safe_ram_ptr(ram_addr_t addr
);
79 void qemu_put_ram_ptr(void *addr
);
80 /* This should not be used by devices. */
81 int qemu_ram_addr_from_host(void *ptr
, ram_addr_t
*ram_addr
);
82 ram_addr_t
qemu_ram_addr_from_host_nofail(void *ptr
);
84 int cpu_register_io_memory(CPUReadMemoryFunc
* const *mem_read
,
85 CPUWriteMemoryFunc
* const *mem_write
,
86 void *opaque
, enum device_endian endian
);
87 void cpu_unregister_io_memory(int table_address
);
89 void cpu_physical_memory_rw(target_phys_addr_t addr
, uint8_t *buf
,
90 int len
, int is_write
);
91 static inline void cpu_physical_memory_read(target_phys_addr_t addr
,
94 cpu_physical_memory_rw(addr
, buf
, len
, 0);
96 static inline void cpu_physical_memory_write(target_phys_addr_t addr
,
97 const void *buf
, int len
)
99 cpu_physical_memory_rw(addr
, (void *)buf
, len
, 1);
101 void *cpu_physical_memory_map(target_phys_addr_t addr
,
102 target_phys_addr_t
*plen
,
104 void cpu_physical_memory_unmap(void *buffer
, target_phys_addr_t len
,
105 int is_write
, target_phys_addr_t access_len
);
106 void *cpu_register_map_client(void *opaque
, void (*callback
)(void *opaque
));
107 void cpu_unregister_map_client(void *cookie
);
109 struct CPUPhysMemoryClient
;
110 typedef struct CPUPhysMemoryClient CPUPhysMemoryClient
;
111 struct CPUPhysMemoryClient
{
112 void (*set_memory
)(struct CPUPhysMemoryClient
*client
,
113 target_phys_addr_t start_addr
,
115 ram_addr_t phys_offset
,
117 int (*sync_dirty_bitmap
)(struct CPUPhysMemoryClient
*client
,
118 target_phys_addr_t start_addr
,
119 target_phys_addr_t end_addr
);
120 int (*migration_log
)(struct CPUPhysMemoryClient
*client
,
122 int (*log_start
)(struct CPUPhysMemoryClient
*client
,
123 target_phys_addr_t phys_addr
, ram_addr_t size
);
124 int (*log_stop
)(struct CPUPhysMemoryClient
*client
,
125 target_phys_addr_t phys_addr
, ram_addr_t size
);
126 QLIST_ENTRY(CPUPhysMemoryClient
) list
;
129 void cpu_register_phys_memory_client(CPUPhysMemoryClient
*);
130 void cpu_unregister_phys_memory_client(CPUPhysMemoryClient
*);
132 /* Coalesced MMIO regions are areas where write operations can be reordered.
133 * This usually implies that write operations are side-effect free. This allows
134 * batching which can make a major impact on performance when using
137 void qemu_register_coalesced_mmio(target_phys_addr_t addr
, ram_addr_t size
);
139 void qemu_unregister_coalesced_mmio(target_phys_addr_t addr
, ram_addr_t size
);
141 void qemu_flush_coalesced_mmio_buffer(void);
143 uint32_t ldub_phys(target_phys_addr_t addr
);
144 uint32_t lduw_le_phys(target_phys_addr_t addr
);
145 uint32_t lduw_be_phys(target_phys_addr_t addr
);
146 uint32_t ldl_le_phys(target_phys_addr_t addr
);
147 uint32_t ldl_be_phys(target_phys_addr_t addr
);
148 uint64_t ldq_le_phys(target_phys_addr_t addr
);
149 uint64_t ldq_be_phys(target_phys_addr_t addr
);
150 void stb_phys(target_phys_addr_t addr
, uint32_t val
);
151 void stw_le_phys(target_phys_addr_t addr
, uint32_t val
);
152 void stw_be_phys(target_phys_addr_t addr
, uint32_t val
);
153 void stl_le_phys(target_phys_addr_t addr
, uint32_t val
);
154 void stl_be_phys(target_phys_addr_t addr
, uint32_t val
);
155 void stq_le_phys(target_phys_addr_t addr
, uint64_t val
);
156 void stq_be_phys(target_phys_addr_t addr
, uint64_t val
);
159 uint32_t lduw_phys(target_phys_addr_t addr
);
160 uint32_t ldl_phys(target_phys_addr_t addr
);
161 uint64_t ldq_phys(target_phys_addr_t addr
);
162 void stl_phys_notdirty(target_phys_addr_t addr
, uint32_t val
);
163 void stq_phys_notdirty(target_phys_addr_t addr
, uint64_t val
);
164 void stw_phys(target_phys_addr_t addr
, uint32_t val
);
165 void stl_phys(target_phys_addr_t addr
, uint32_t val
);
166 void stq_phys(target_phys_addr_t addr
, uint64_t val
);
169 void cpu_physical_memory_write_rom(target_phys_addr_t addr
,
170 const uint8_t *buf
, int len
);
172 #define IO_MEM_SHIFT 3
174 #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
175 #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
176 #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
177 #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
178 #define IO_MEM_SUBPAGE_RAM (4 << IO_MEM_SHIFT)
180 /* Acts like a ROM when read and like a device when written. */
181 #define IO_MEM_ROMD (1)
182 #define IO_MEM_SUBPAGE (2)
186 #endif /* !CPU_COMMON_H */