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cpu-common: Have a ram_addr_t of uint64 with Xen.
[qemu.git] / cpu-common.h
1 #ifndef CPU_COMMON_H
2 #define CPU_COMMON_H 1
3
4 /* CPU interfaces that are target indpendent. */
5
6 #if defined(__arm__) || defined(__sparc__) || defined(__mips__) || defined(__hppa__) || defined(__ia64__)
7 #define WORDS_ALIGNED
8 #endif
9
10 #ifdef TARGET_PHYS_ADDR_BITS
11 #include "targphys.h"
12 #endif
13
14 #ifndef NEED_CPU_H
15 #include "poison.h"
16 #endif
17
18 #include "bswap.h"
19 #include "qemu-queue.h"
20
21 #if !defined(CONFIG_USER_ONLY)
22
23 enum device_endian {
24 DEVICE_NATIVE_ENDIAN,
25 DEVICE_BIG_ENDIAN,
26 DEVICE_LITTLE_ENDIAN,
27 };
28
29 /* address in the RAM (different from a physical address) */
30 #if defined(CONFIG_XEN_BACKEND) && TARGET_PHYS_ADDR_BITS == 64
31 typedef uint64_t ram_addr_t;
32 # define RAM_ADDR_MAX UINT64_MAX
33 # define RAM_ADDR_FMT "%" PRIx64
34 #else
35 typedef unsigned long ram_addr_t;
36 # define RAM_ADDR_MAX ULONG_MAX
37 # define RAM_ADDR_FMT "%lx"
38 #endif
39
40 /* memory API */
41
42 typedef void CPUWriteMemoryFunc(void *opaque, target_phys_addr_t addr, uint32_t value);
43 typedef uint32_t CPUReadMemoryFunc(void *opaque, target_phys_addr_t addr);
44
45 void cpu_register_physical_memory_log(target_phys_addr_t start_addr,
46 ram_addr_t size,
47 ram_addr_t phys_offset,
48 ram_addr_t region_offset,
49 bool log_dirty);
50
51 static inline void cpu_register_physical_memory_offset(target_phys_addr_t start_addr,
52 ram_addr_t size,
53 ram_addr_t phys_offset,
54 ram_addr_t region_offset)
55 {
56 cpu_register_physical_memory_log(start_addr, size, phys_offset,
57 region_offset, false);
58 }
59
60 static inline void cpu_register_physical_memory(target_phys_addr_t start_addr,
61 ram_addr_t size,
62 ram_addr_t phys_offset)
63 {
64 cpu_register_physical_memory_offset(start_addr, size, phys_offset, 0);
65 }
66
67 ram_addr_t cpu_get_physical_page_desc(target_phys_addr_t addr);
68 ram_addr_t qemu_ram_alloc_from_ptr(DeviceState *dev, const char *name,
69 ram_addr_t size, void *host);
70 ram_addr_t qemu_ram_alloc(DeviceState *dev, const char *name, ram_addr_t size);
71 void qemu_ram_free(ram_addr_t addr);
72 void qemu_ram_free_from_ptr(ram_addr_t addr);
73 void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
74 /* This should only be used for ram local to a device. */
75 void *qemu_get_ram_ptr(ram_addr_t addr);
76 void *qemu_ram_ptr_length(ram_addr_t addr, ram_addr_t *size);
77 /* Same but slower, to use for migration, where the order of
78 * RAMBlocks must not change. */
79 void *qemu_safe_ram_ptr(ram_addr_t addr);
80 void qemu_put_ram_ptr(void *addr);
81 /* This should not be used by devices. */
82 int qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
83 ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr);
84
85 int cpu_register_io_memory(CPUReadMemoryFunc * const *mem_read,
86 CPUWriteMemoryFunc * const *mem_write,
87 void *opaque, enum device_endian endian);
88 void cpu_unregister_io_memory(int table_address);
89
90 void cpu_physical_memory_rw(target_phys_addr_t addr, uint8_t *buf,
91 int len, int is_write);
92 static inline void cpu_physical_memory_read(target_phys_addr_t addr,
93 void *buf, int len)
94 {
95 cpu_physical_memory_rw(addr, buf, len, 0);
96 }
97 static inline void cpu_physical_memory_write(target_phys_addr_t addr,
98 const void *buf, int len)
99 {
100 cpu_physical_memory_rw(addr, (void *)buf, len, 1);
101 }
102 void *cpu_physical_memory_map(target_phys_addr_t addr,
103 target_phys_addr_t *plen,
104 int is_write);
105 void cpu_physical_memory_unmap(void *buffer, target_phys_addr_t len,
106 int is_write, target_phys_addr_t access_len);
107 void *cpu_register_map_client(void *opaque, void (*callback)(void *opaque));
108 void cpu_unregister_map_client(void *cookie);
109
110 struct CPUPhysMemoryClient;
111 typedef struct CPUPhysMemoryClient CPUPhysMemoryClient;
112 struct CPUPhysMemoryClient {
113 void (*set_memory)(struct CPUPhysMemoryClient *client,
114 target_phys_addr_t start_addr,
115 ram_addr_t size,
116 ram_addr_t phys_offset,
117 bool log_dirty);
118 int (*sync_dirty_bitmap)(struct CPUPhysMemoryClient *client,
119 target_phys_addr_t start_addr,
120 target_phys_addr_t end_addr);
121 int (*migration_log)(struct CPUPhysMemoryClient *client,
122 int enable);
123 int (*log_start)(struct CPUPhysMemoryClient *client,
124 target_phys_addr_t phys_addr, ram_addr_t size);
125 int (*log_stop)(struct CPUPhysMemoryClient *client,
126 target_phys_addr_t phys_addr, ram_addr_t size);
127 QLIST_ENTRY(CPUPhysMemoryClient) list;
128 };
129
130 void cpu_register_phys_memory_client(CPUPhysMemoryClient *);
131 void cpu_unregister_phys_memory_client(CPUPhysMemoryClient *);
132
133 /* Coalesced MMIO regions are areas where write operations can be reordered.
134 * This usually implies that write operations are side-effect free. This allows
135 * batching which can make a major impact on performance when using
136 * virtualization.
137 */
138 void qemu_register_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
139
140 void qemu_unregister_coalesced_mmio(target_phys_addr_t addr, ram_addr_t size);
141
142 void qemu_flush_coalesced_mmio_buffer(void);
143
144 uint32_t ldub_phys(target_phys_addr_t addr);
145 uint32_t lduw_le_phys(target_phys_addr_t addr);
146 uint32_t lduw_be_phys(target_phys_addr_t addr);
147 uint32_t ldl_le_phys(target_phys_addr_t addr);
148 uint32_t ldl_be_phys(target_phys_addr_t addr);
149 uint64_t ldq_le_phys(target_phys_addr_t addr);
150 uint64_t ldq_be_phys(target_phys_addr_t addr);
151 void stb_phys(target_phys_addr_t addr, uint32_t val);
152 void stw_le_phys(target_phys_addr_t addr, uint32_t val);
153 void stw_be_phys(target_phys_addr_t addr, uint32_t val);
154 void stl_le_phys(target_phys_addr_t addr, uint32_t val);
155 void stl_be_phys(target_phys_addr_t addr, uint32_t val);
156 void stq_le_phys(target_phys_addr_t addr, uint64_t val);
157 void stq_be_phys(target_phys_addr_t addr, uint64_t val);
158
159 #ifdef NEED_CPU_H
160 uint32_t lduw_phys(target_phys_addr_t addr);
161 uint32_t ldl_phys(target_phys_addr_t addr);
162 uint64_t ldq_phys(target_phys_addr_t addr);
163 void stl_phys_notdirty(target_phys_addr_t addr, uint32_t val);
164 void stq_phys_notdirty(target_phys_addr_t addr, uint64_t val);
165 void stw_phys(target_phys_addr_t addr, uint32_t val);
166 void stl_phys(target_phys_addr_t addr, uint32_t val);
167 void stq_phys(target_phys_addr_t addr, uint64_t val);
168 #endif
169
170 void cpu_physical_memory_write_rom(target_phys_addr_t addr,
171 const uint8_t *buf, int len);
172
173 #define IO_MEM_SHIFT 3
174
175 #define IO_MEM_RAM (0 << IO_MEM_SHIFT) /* hardcoded offset */
176 #define IO_MEM_ROM (1 << IO_MEM_SHIFT) /* hardcoded offset */
177 #define IO_MEM_UNASSIGNED (2 << IO_MEM_SHIFT)
178 #define IO_MEM_NOTDIRTY (3 << IO_MEM_SHIFT)
179
180 /* Acts like a ROM when read and like a device when written. */
181 #define IO_MEM_ROMD (1)
182 #define IO_MEM_SUBPAGE (2)
183
184 #endif
185
186 #endif /* !CPU_COMMON_H */