cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #ifdef TARGET_I386
  22 #include "exec-i386.h"
  23 #endif
  24 #ifdef TARGET_ARM
  25 #include "exec-arm.h"
  26 #endif
  27
  28 #include "disas.h"
  29
  30 //#define DEBUG_EXEC
  31 //#define DEBUG_SIGNAL
  32
  33 #if defined(TARGET_ARM)
  34 /* XXX: unify with i386 target */
  35 void cpu_loop_exit(void)
  36 {
  37     longjmp(env->jmp_env, 1);
  38 }
  39 #endif
  40
  41 /* main execution loop */
  42
  43 int cpu_exec(CPUState *env1)
  44 {
  45     int saved_T0, saved_T1, saved_T2;
  46     CPUState *saved_env;
  47 #ifdef reg_EAX
  48     int saved_EAX;
  49 #endif
  50 #ifdef reg_ECX
  51     int saved_ECX;
  52 #endif
  53 #ifdef reg_EDX
  54     int saved_EDX;
  55 #endif
  56 #ifdef reg_EBX
  57     int saved_EBX;
  58 #endif
  59 #ifdef reg_ESP
  60     int saved_ESP;
  61 #endif
  62 #ifdef reg_EBP
  63     int saved_EBP;
  64 #endif
  65 #ifdef reg_ESI
  66     int saved_ESI;
  67 #endif
  68 #ifdef reg_EDI
  69     int saved_EDI;
  70 #endif
  71 #ifdef __sparc__
  72     int saved_i7, tmp_T0;
  73 #endif
  74     int code_gen_size, ret;
  75     void (*gen_func)(void);
  76     TranslationBlock *tb, **ptb;
  77     uint8_t *tc_ptr, *cs_base, *pc;
  78     unsigned int flags;
  79
  80     /* first we save global registers */
  81     saved_T0 = T0;
  82     saved_T1 = T1;
  83     saved_T2 = T2;
  84     saved_env = env;
  85     env = env1;
  86 #ifdef __sparc__
  87     /* we also save i7 because longjmp may not restore it */
  88     asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
  89 #endif
  90
  91 #if defined(TARGET_I386)
  92 #ifdef reg_EAX
  93     saved_EAX = EAX;
  94     EAX = env->regs[R_EAX];
  95 #endif
  96 #ifdef reg_ECX
  97     saved_ECX = ECX;
  98     ECX = env->regs[R_ECX];
  99 #endif
 100 #ifdef reg_EDX
 101     saved_EDX = EDX;
 102     EDX = env->regs[R_EDX];
 103 #endif
 104 #ifdef reg_EBX
 105     saved_EBX = EBX;
 106     EBX = env->regs[R_EBX];
 107 #endif
 108 #ifdef reg_ESP
 109     saved_ESP = ESP;
 110     ESP = env->regs[R_ESP];
 111 #endif
 112 #ifdef reg_EBP
 113     saved_EBP = EBP;
 114     EBP = env->regs[R_EBP];
 115 #endif
 116 #ifdef reg_ESI
 117     saved_ESI = ESI;
 118     ESI = env->regs[R_ESI];
 119 #endif
 120 #ifdef reg_EDI
 121     saved_EDI = EDI;
 122     EDI = env->regs[R_EDI];
 123 #endif
 124
 125     /* put eflags in CPU temporary format */
 126     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 127     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 128     CC_OP = CC_OP_EFLAGS;
 129     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 130 #elif defined(TARGET_ARM)
 131     {
 132         unsigned int psr;
 133         psr = env->cpsr;
 134         env->CF = (psr >> 29) & 1;
 135         env->NZF = (psr & 0xc0000000) ^ 0x40000000;
 136         env->VF = (psr << 3) & 0x80000000;
 137         env->cpsr = psr & ~0xf0000000;
 138     }
 139 #else
 140 #error unsupported target CPU
 141 #endif
 142     env->interrupt_request = 0;
 143     env->exception_index = -1;
 144
 145     /* prepare setjmp context for exception handling */
 146     for(;;) {
 147         if (setjmp(env->jmp_env) == 0) {
 148             /* if an exception is pending, we execute it here */
 149             if (env->exception_index >= 0) {
 150                 if (env->exception_index >= EXCP_INTERRUPT) {
 151                     /* exit request from the cpu execution loop */
 152                     ret = env->exception_index;
 153                     break;
 154                 } else if (env->user_mode_only) {
 155                     /* if user mode only, we simulate a fake exception
 156                        which will be hanlded outside the cpu execution
 157                        loop */
 158 #if defined(TARGET_I386)
 159                     do_interrupt_user(env->exception_index,
 160                                       env->exception_is_int,
 161                                       env->error_code,
 162                                       env->exception_next_eip);
 163 #endif
 164                     ret = env->exception_index;
 165                     break;
 166                 } else {
 167 #if defined(TARGET_I386)
 168                     /* simulate a real cpu exception. On i386, it can
 169                        trigger new exceptions, but we do not handle
 170                        double or triple faults yet. */
 171                     do_interrupt(env->exception_index,
 172                                  env->exception_is_int,
 173                                  env->error_code,
 174                                  env->exception_next_eip);
 175 #endif
 176                 }
 177                 env->exception_index = -1;
 178             }
 179 #if defined(TARGET_I386)
 180             /* if hardware interrupt pending, we execute it */
 181             if (env->hard_interrupt_request &&
 182                 (env->eflags & IF_MASK)) {
 183                 int intno;
 184                 intno = cpu_x86_get_pic_interrupt(env);
 185                 if (loglevel) {
 186                     fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
 187                 }
 188                 do_interrupt(intno, 0, 0, 0);
 189                 env->hard_interrupt_request = 0;
 190             }
 191 #endif
 192             T0 = 0; /* force lookup of first TB */
 193             for(;;) {
 194 #ifdef __sparc__
 195                 /* g1 can be modified by some libc? functions */
 196                 tmp_T0 = T0;
 197 #endif
 198                 if (env->interrupt_request) {
 199                     env->exception_index = EXCP_INTERRUPT;
 200                     cpu_loop_exit();
 201                 }
 202 #ifdef DEBUG_EXEC
 203                 if (loglevel) {
 204 #if defined(TARGET_I386)
 205                     /* restore flags in standard format */
 206                     env->regs[R_EAX] = EAX;
 207                     env->regs[R_EBX] = EBX;
 208                     env->regs[R_ECX] = ECX;
 209                     env->regs[R_EDX] = EDX;
 210                     env->regs[R_ESI] = ESI;
 211                     env->regs[R_EDI] = EDI;
 212                     env->regs[R_EBP] = EBP;
 213                     env->regs[R_ESP] = ESP;
 214                     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 215                     cpu_x86_dump_state(env, logfile, 0);
 216                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 217 #elif defined(TARGET_ARM)
 218                     cpu_arm_dump_state(env, logfile, 0);
 219 #else
 220 #error unsupported target CPU
 221 #endif
 222                 }
 223 #endif
 224                 /* we compute the CPU state. We assume it will not
 225                    change during the whole generated block. */
 226 #if defined(TARGET_I386)
 227                 flags = (env->segs[R_CS].flags & DESC_B_MASK)
 228                     >> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT);
 229                 flags |= (env->segs[R_SS].flags & DESC_B_MASK)
 230                     >> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT);
 231                 flags |= (((unsigned long)env->segs[R_DS].base |
 232                            (unsigned long)env->segs[R_ES].base |
 233                            (unsigned long)env->segs[R_SS].base) != 0) <<
 234                     GEN_FLAG_ADDSEG_SHIFT;
 235                 if (!(env->eflags & VM_MASK)) {
 236                     flags |= (env->segs[R_CS].selector & 3) << GEN_FLAG_CPL_SHIFT;
 237                 } else {
 238                     /* NOTE: a dummy CPL is kept */
 239                     flags |= (1 << GEN_FLAG_VM_SHIFT);
 240                     flags |= (3 << GEN_FLAG_CPL_SHIFT);
 241                 }
 242                 flags |= (env->eflags & (IOPL_MASK | TF_MASK));
 243                 cs_base = env->segs[R_CS].base;
 244                 pc = cs_base + env->eip;
 245 #elif defined(TARGET_ARM)
 246                 flags = 0;
 247                 cs_base = 0;
 248                 pc = (uint8_t *)env->regs[15];
 249 #else
 250 #error unsupported CPU
 251 #endif
 252                 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
 253                              flags);
 254                 if (!tb) {
 255                     spin_lock(&tb_lock);
 256                     /* if no translated code available, then translate it now */
 257                     tb = tb_alloc((unsigned long)pc);
 258                     if (!tb) {
 259                         /* flush must be done */
 260                         tb_flush();
 261                         /* cannot fail at this point */
 262                         tb = tb_alloc((unsigned long)pc);
 263                         /* don't forget to invalidate previous TB info */
 264                         ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 265                         T0 = 0;
 266                     }
 267                     tc_ptr = code_gen_ptr;
 268                     tb->tc_ptr = tc_ptr;
 269                     tb->cs_base = (unsigned long)cs_base;
 270                     tb->flags = flags;
 271                     ret = cpu_gen_code(tb, CODE_GEN_MAX_SIZE, &code_gen_size);
 272 #if defined(TARGET_I386)
 273                     /* XXX: suppress that, this is incorrect */
 274                     /* if invalid instruction, signal it */
 275                     if (ret != 0) {
 276                         /* NOTE: the tb is allocated but not linked, so we
 277                            can leave it */
 278                         spin_unlock(&tb_lock);
 279                         raise_exception(EXCP06_ILLOP);
 280                     }
 281 #endif
 282                     *ptb = tb;
 283                     tb->hash_next = NULL;
 284                     tb_link(tb);
 285                     code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
 286                     spin_unlock(&tb_lock);
 287                 }
 288 #ifdef DEBUG_EXEC
 289                 if (loglevel) {
 290                     fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
 291                             (long)tb->tc_ptr, (long)tb->pc,
 292                             lookup_symbol((void *)tb->pc));
 293                 }
 294 #endif
 295 #ifdef __sparc__
 296                 T0 = tmp_T0;
 297 #endif
 298                 /* see if we can patch the calling TB. XXX: remove TF test */
 299                 if (T0 != 0
 300 #if defined(TARGET_I386)
 301                     && !(env->eflags & TF_MASK)
 302 #endif
 303                     ) {
 304                     spin_lock(&tb_lock);
 305                     tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
 306                     spin_unlock(&tb_lock);
 307                 }
 308                 tc_ptr = tb->tc_ptr;
 309                 env->current_tb = tb;
 310                 /* execute the generated code */
 311                 gen_func = (void *)tc_ptr;
 312 #if defined(__sparc__)
 313                 __asm__ __volatile__("call      %0\n\t"
 314                                      "mov       %%o7,%%i0"
 315                                      : /* no outputs */
 316                                      : "r" (gen_func)
 317                                      : "i0", "i1", "i2", "i3", "i4", "i5");
 318 #elif defined(__arm__)
 319                 asm volatile ("mov pc, %0\n\t"
 320                               ".global exec_loop\n\t"
 321                               "exec_loop:\n\t"
 322                               : /* no outputs */
 323                               : "r" (gen_func)
 324                               : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
 325 #else
 326                 gen_func();
 327 #endif
 328                 env->current_tb = NULL;
 329             }
 330         } else {
 331         }
 332     } /* for(;;) */
 333
 334
 335 #if defined(TARGET_I386)
 336     /* restore flags in standard format */
 337     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 338
 339     /* restore global registers */
 340 #ifdef reg_EAX
 341     EAX = saved_EAX;
 342 #endif
 343 #ifdef reg_ECX
 344     ECX = saved_ECX;
 345 #endif
 346 #ifdef reg_EDX
 347     EDX = saved_EDX;
 348 #endif
 349 #ifdef reg_EBX
 350     EBX = saved_EBX;
 351 #endif
 352 #ifdef reg_ESP
 353     ESP = saved_ESP;
 354 #endif
 355 #ifdef reg_EBP
 356     EBP = saved_EBP;
 357 #endif
 358 #ifdef reg_ESI
 359     ESI = saved_ESI;
 360 #endif
 361 #ifdef reg_EDI
 362     EDI = saved_EDI;
 363 #endif
 364 #elif defined(TARGET_ARM)
 365     {
 366         int ZF;
 367         ZF = (env->NZF == 0);
 368         env->cpsr = env->cpsr | (env->NZF & 0x80000000) | (ZF << 30) |
 369             (env->CF << 29) | ((env->VF & 0x80000000) >> 3);
 370     }
 371 #else
 372 #error unsupported target CPU
 373 #endif
 374 #ifdef __sparc__
 375     asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
 376 #endif
 377     T0 = saved_T0;
 378     T1 = saved_T1;
 379     T2 = saved_T2;
 380     env = saved_env;
 381     return ret;
 382 }
 383
 384 #if defined(TARGET_I386)
 385
 386 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 387 {
 388     CPUX86State *saved_env;
 389
 390     saved_env = env;
 391     env = s;
 392     if (env->eflags & VM_MASK) {
 393         SegmentCache *sc;
 394         selector &= 0xffff;
 395         sc = &env->segs[seg_reg];
 396         /* NOTE: in VM86 mode, limit and flags are never reloaded,
 397            so we must load them here */
 398         sc->base = (void *)(selector << 4);
 399         sc->limit = 0xffff;
 400         sc->flags = 0;
 401         sc->selector = selector;
 402     } else {
 403         load_seg(seg_reg, selector, 0);
 404     }
 405     env = saved_env;
 406 }
 407
 408 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
 409 {
 410     CPUX86State *saved_env;
 411
 412     saved_env = env;
 413     env = s;
 414
 415     helper_fsave(ptr, data32);
 416
 417     env = saved_env;
 418 }
 419
 420 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
 421 {
 422     CPUX86State *saved_env;
 423
 424     saved_env = env;
 425     env = s;
 426
 427     helper_frstor(ptr, data32);
 428
 429     env = saved_env;
 430 }
 431
 432 #endif /* TARGET_I386 */
 433
 434 #undef EAX
 435 #undef ECX
 436 #undef EDX
 437 #undef EBX
 438 #undef ESP
 439 #undef EBP
 440 #undef ESI
 441 #undef EDI
 442 #undef EIP
 443 #include <signal.h>
 444 #include <sys/ucontext.h>
 445
 446 #if defined(TARGET_I386)
 447
 448 /* 'pc' is the host PC at which the exception was raised. 'address' is
 449    the effective address of the memory exception. 'is_write' is 1 if a
 450    write caused the exception and otherwise 0'. 'old_set' is the
 451    signal set which should be restored */
 452 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 453                                     int is_write, sigset_t *old_set)
 454 {
 455     TranslationBlock *tb;
 456     int ret;
 457
 458     if (cpu_single_env)
 459         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 460 #if defined(DEBUG_SIGNAL)
 461     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 462            pc, address, is_write, *(unsigned long *)old_set);
 463 #endif
 464     /* XXX: locking issue */
 465     if (is_write && page_unprotect(address)) {
 466         return 1;
 467     }
 468     /* see if it is an MMU fault */
 469     ret = cpu_x86_handle_mmu_fault(env, address, is_write);
 470     if (ret < 0)
 471         return 0; /* not an MMU fault */
 472     if (ret == 0)
 473         return 1; /* the MMU fault was handled without causing real CPU fault */
 474     /* now we have a real cpu fault */
 475     tb = tb_find_pc(pc);
 476     if (tb) {
 477         /* the PC is inside the translated code. It means that we have
 478            a virtual CPU fault */
 479         cpu_restore_state(tb, env, pc);
 480     }
 481 #if 0
 482     printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
 483            env->eip, env->cr[2], env->error_code);
 484 #endif
 485     /* we restore the process signal mask as the sigreturn should
 486        do it (XXX: use sigsetjmp) */
 487     sigprocmask(SIG_SETMASK, old_set, NULL);
 488     raise_exception_err(EXCP0E_PAGE, env->error_code);
 489     /* never comes here */
 490     return 1;
 491 }
 492
 493 #elif defined(TARGET_ARM)
 494 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 495                                     int is_write, sigset_t *old_set)
 496 {
 497     /* XXX: do more */
 498     return 0;
 499 }
 500 #else
 501 #error unsupported target CPU
 502 #endif
 503
 504 #if defined(__i386__)
 505
 506 int cpu_signal_handler(int host_signum, struct siginfo *info,
 507                        void *puc)
 508 {
 509     struct ucontext *uc = puc;
 510     unsigned long pc;
 511
 512 #ifndef REG_EIP
 513 /* for glibc 2.1 */
 514 #define REG_EIP    EIP
 515 #define REG_ERR    ERR
 516 #define REG_TRAPNO TRAPNO
 517 #endif
 518     pc = uc->uc_mcontext.gregs[REG_EIP];
 519     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 520                              uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
 521                              (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 522                              &uc->uc_sigmask);
 523 }
 524
 525 #elif defined(__powerpc)
 526
 527 int cpu_signal_handler(int host_signum, struct siginfo *info,
 528                        void *puc)
 529 {
 530     struct ucontext *uc = puc;
 531     struct pt_regs *regs = uc->uc_mcontext.regs;
 532     unsigned long pc;
 533     int is_write;
 534
 535     pc = regs->nip;
 536     is_write = 0;
 537 #if 0
 538     /* ppc 4xx case */
 539     if (regs->dsisr & 0x00800000)
 540         is_write = 1;
 541 #else
 542     if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
 543         is_write = 1;
 544 #endif
 545     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 546                              is_write, &uc->uc_sigmask);
 547 }
 548
 549 #elif defined(__alpha__)
 550
 551 int cpu_signal_handler(int host_signum, struct siginfo *info,
 552                            void *puc)
 553 {
 554     struct ucontext *uc = puc;
 555     uint32_t *pc = uc->uc_mcontext.sc_pc;
 556     uint32_t insn = *pc;
 557     int is_write = 0;
 558
 559     /* XXX: need kernel patch to get write flag faster */
 560     switch (insn >> 26) {
 561     case 0x0d: // stw
 562     case 0x0e: // stb
 563     case 0x0f: // stq_u
 564     case 0x24: // stf
 565     case 0x25: // stg
 566     case 0x26: // sts
 567     case 0x27: // stt
 568     case 0x2c: // stl
 569     case 0x2d: // stq
 570     case 0x2e: // stl_c
 571     case 0x2f: // stq_c
 572         is_write = 1;
 573     }
 574
 575     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 576                              is_write, &uc->uc_sigmask);
 577 }
 578 #elif defined(__sparc__)
 579
 580 int cpu_signal_handler(int host_signum, struct siginfo *info,
 581                        void *puc)
 582 {
 583     uint32_t *regs = (uint32_t *)(info + 1);
 584     void *sigmask = (regs + 20);
 585     unsigned long pc;
 586     int is_write;
 587     uint32_t insn;
 588
 589     /* XXX: is there a standard glibc define ? */
 590     pc = regs[1];
 591     /* XXX: need kernel patch to get write flag faster */
 592     is_write = 0;
 593     insn = *(uint32_t *)pc;
 594     if ((insn >> 30) == 3) {
 595       switch((insn >> 19) & 0x3f) {
 596       case 0x05: // stb
 597       case 0x06: // sth
 598       case 0x04: // st
 599       case 0x07: // std
 600       case 0x24: // stf
 601       case 0x27: // stdf
 602       case 0x25: // stfsr
 603         is_write = 1;
 604         break;
 605       }
 606     }
 607     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 608                              is_write, sigmask);
 609 }
 610
 611 #elif defined(__arm__)
 612
 613 int cpu_signal_handler(int host_signum, struct siginfo *info,
 614                        void *puc)
 615 {
 616     struct ucontext *uc = puc;
 617     unsigned long pc;
 618     int is_write;
 619
 620     pc = uc->uc_mcontext.gregs[R15];
 621     /* XXX: compute is_write */
 622     is_write = 0;
 623     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 624                              is_write,
 625                              &uc->uc_sigmask);
 626 }
 627
 628 #else
 629
 630 #error host CPU specific signal handler needed
 631
 632 #endif