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[qemu.git] / cpu-exec.c
1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
46 {
47 longjmp(env->jmp_env, 1);
48 }
49 #endif
50 #ifndef TARGET_SPARC
51 #define reg_T2
52 #endif
53
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
56 */
57 void cpu_resume_from_signal(CPUState *env1, void *puc)
58 {
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext *uc = puc;
61 #endif
62
63 env = env1;
64
65 /* XXX: restore cpu registers saved in host registers */
66
67 #if !defined(CONFIG_SOFTMMU)
68 if (puc) {
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
71 }
72 #endif
73 longjmp(env->jmp_env, 1);
74 }
75
76
77 static TranslationBlock *tb_find_slow(target_ulong pc,
78 target_ulong cs_base,
79 unsigned int flags)
80 {
81 TranslationBlock *tb, **ptb1;
82 int code_gen_size;
83 unsigned int h;
84 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
85 uint8_t *tc_ptr;
86
87 spin_lock(&tb_lock);
88
89 tb_invalidated_flag = 0;
90
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
92
93 /* find translated block using physical mappings */
94 phys_pc = get_phys_addr_code(env, pc);
95 phys_page1 = phys_pc & TARGET_PAGE_MASK;
96 phys_page2 = -1;
97 h = tb_phys_hash_func(phys_pc);
98 ptb1 = &tb_phys_hash[h];
99 for(;;) {
100 tb = *ptb1;
101 if (!tb)
102 goto not_found;
103 if (tb->pc == pc &&
104 tb->page_addr[0] == phys_page1 &&
105 tb->cs_base == cs_base &&
106 tb->flags == flags) {
107 /* check next page if needed */
108 if (tb->page_addr[1] != -1) {
109 virt_page2 = (pc & TARGET_PAGE_MASK) +
110 TARGET_PAGE_SIZE;
111 phys_page2 = get_phys_addr_code(env, virt_page2);
112 if (tb->page_addr[1] == phys_page2)
113 goto found;
114 } else {
115 goto found;
116 }
117 }
118 ptb1 = &tb->phys_hash_next;
119 }
120 not_found:
121 /* if no translated code available, then translate it now */
122 tb = tb_alloc(pc);
123 if (!tb) {
124 /* flush must be done */
125 tb_flush(env);
126 /* cannot fail at this point */
127 tb = tb_alloc(pc);
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag = 1;
130 }
131 tc_ptr = code_gen_ptr;
132 tb->tc_ptr = tc_ptr;
133 tb->cs_base = cs_base;
134 tb->flags = flags;
135 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
136 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
137
138 /* check next page if needed */
139 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
140 phys_page2 = -1;
141 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
142 phys_page2 = get_phys_addr_code(env, virt_page2);
143 }
144 tb_link_phys(tb, phys_pc, phys_page2);
145
146 found:
147 /* we add the TB in the virtual pc hash table */
148 env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
149 spin_unlock(&tb_lock);
150 return tb;
151 }
152
153 static inline TranslationBlock *tb_find_fast(void)
154 {
155 TranslationBlock *tb;
156 target_ulong cs_base, pc;
157 unsigned int flags;
158
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
161 is executed. */
162 #if defined(TARGET_I386)
163 flags = env->hflags;
164 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
165 cs_base = env->segs[R_CS].base;
166 pc = cs_base + env->eip;
167 #elif defined(TARGET_ARM)
168 flags = env->thumb | (env->vfp.vec_len << 1)
169 | (env->vfp.vec_stride << 4);
170 if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR)
171 flags |= (1 << 6);
172 if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30))
173 flags |= (1 << 7);
174 cs_base = 0;
175 pc = env->regs[15];
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);
179 #else
180 flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);
181 #endif
182 cs_base = env->npc;
183 pc = env->pc;
184 #elif defined(TARGET_PPC)
185 flags = (msr_pr << MSR_PR) | (msr_fp << MSR_FP) |
186 (msr_se << MSR_SE) | (msr_le << MSR_LE);
187 cs_base = 0;
188 pc = env->nip;
189 #elif defined(TARGET_MIPS)
190 flags = env->hflags & (MIPS_HFLAG_TMASK | MIPS_HFLAG_BMASK);
191 cs_base = 0;
192 pc = env->PC;
193 #elif defined(TARGET_SH4)
194 flags = env->sr & (SR_MD | SR_RB);
195 cs_base = 0; /* XXXXX */
196 pc = env->pc;
197 #else
198 #error unsupported CPU
199 #endif
200 tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
201 if (__builtin_expect(!tb || tb->pc != pc || tb->cs_base != cs_base ||
202 tb->flags != flags, 0)) {
203 tb = tb_find_slow(pc, cs_base, flags);
204 /* Note: we do it here to avoid a gcc bug on Mac OS X when
205 doing it in tb_find_slow */
206 if (tb_invalidated_flag) {
207 /* as some TB could have been invalidated because
208 of memory exceptions while generating the code, we
209 must recompute the hash index here */
210 T0 = 0;
211 }
212 }
213 return tb;
214 }
215
216
217 /* main execution loop */
218
219 int cpu_exec(CPUState *env1)
220 {
221 int saved_T0, saved_T1;
222 #if defined(reg_T2)
223 int saved_T2;
224 #endif
225 CPUState *saved_env;
226 #if defined(TARGET_I386)
227 #ifdef reg_EAX
228 int saved_EAX;
229 #endif
230 #ifdef reg_ECX
231 int saved_ECX;
232 #endif
233 #ifdef reg_EDX
234 int saved_EDX;
235 #endif
236 #ifdef reg_EBX
237 int saved_EBX;
238 #endif
239 #ifdef reg_ESP
240 int saved_ESP;
241 #endif
242 #ifdef reg_EBP
243 int saved_EBP;
244 #endif
245 #ifdef reg_ESI
246 int saved_ESI;
247 #endif
248 #ifdef reg_EDI
249 int saved_EDI;
250 #endif
251 #elif defined(TARGET_SPARC)
252 #if defined(reg_REGWPTR)
253 uint32_t *saved_regwptr;
254 #endif
255 #endif
256 #ifdef __sparc__
257 int saved_i7, tmp_T0;
258 #endif
259 int ret, interrupt_request;
260 void (*gen_func)(void);
261 TranslationBlock *tb;
262 uint8_t *tc_ptr;
263
264 #if defined(TARGET_I386)
265 /* handle exit of HALTED state */
266 if (env1->hflags & HF_HALTED_MASK) {
267 /* disable halt condition */
268 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
269 (env1->eflags & IF_MASK)) {
270 env1->hflags &= ~HF_HALTED_MASK;
271 } else {
272 return EXCP_HALTED;
273 }
274 }
275 #elif defined(TARGET_PPC)
276 if (env1->halted) {
277 if (env1->msr[MSR_EE] &&
278 (env1->interrupt_request &
279 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER))) {
280 env1->halted = 0;
281 } else {
282 return EXCP_HALTED;
283 }
284 }
285 #elif defined(TARGET_SPARC)
286 if (env1->halted) {
287 if ((env1->interrupt_request & CPU_INTERRUPT_HARD) &&
288 (env1->psret != 0)) {
289 env1->halted = 0;
290 } else {
291 return EXCP_HALTED;
292 }
293 }
294 #elif defined(TARGET_ARM)
295 if (env1->halted) {
296 /* An interrupt wakes the CPU even if the I and F CPSR bits are
297 set. */
298 if (env1->interrupt_request
299 & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD)) {
300 env1->halted = 0;
301 } else {
302 return EXCP_HALTED;
303 }
304 }
305 #elif defined(TARGET_MIPS)
306 if (env1->halted) {
307 if (env1->interrupt_request &
308 (CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER)) {
309 env1->halted = 0;
310 } else {
311 return EXCP_HALTED;
312 }
313 }
314 #endif
315
316 cpu_single_env = env1;
317
318 /* first we save global registers */
319 saved_env = env;
320 env = env1;
321 saved_T0 = T0;
322 saved_T1 = T1;
323 #if defined(reg_T2)
324 saved_T2 = T2;
325 #endif
326 #ifdef __sparc__
327 /* we also save i7 because longjmp may not restore it */
328 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
329 #endif
330
331 #if defined(TARGET_I386)
332 #ifdef reg_EAX
333 saved_EAX = EAX;
334 #endif
335 #ifdef reg_ECX
336 saved_ECX = ECX;
337 #endif
338 #ifdef reg_EDX
339 saved_EDX = EDX;
340 #endif
341 #ifdef reg_EBX
342 saved_EBX = EBX;
343 #endif
344 #ifdef reg_ESP
345 saved_ESP = ESP;
346 #endif
347 #ifdef reg_EBP
348 saved_EBP = EBP;
349 #endif
350 #ifdef reg_ESI
351 saved_ESI = ESI;
352 #endif
353 #ifdef reg_EDI
354 saved_EDI = EDI;
355 #endif
356
357 env_to_regs();
358 /* put eflags in CPU temporary format */
359 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
360 DF = 1 - (2 * ((env->eflags >> 10) & 1));
361 CC_OP = CC_OP_EFLAGS;
362 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
363 #elif defined(TARGET_ARM)
364 #elif defined(TARGET_SPARC)
365 #if defined(reg_REGWPTR)
366 saved_regwptr = REGWPTR;
367 #endif
368 #elif defined(TARGET_PPC)
369 #elif defined(TARGET_MIPS)
370 #elif defined(TARGET_SH4)
371 /* XXXXX */
372 #else
373 #error unsupported target CPU
374 #endif
375 env->exception_index = -1;
376
377 /* prepare setjmp context for exception handling */
378 for(;;) {
379 if (setjmp(env->jmp_env) == 0) {
380 env->current_tb = NULL;
381 /* if an exception is pending, we execute it here */
382 if (env->exception_index >= 0) {
383 if (env->exception_index >= EXCP_INTERRUPT) {
384 /* exit request from the cpu execution loop */
385 ret = env->exception_index;
386 break;
387 } else if (env->user_mode_only) {
388 /* if user mode only, we simulate a fake exception
389 which will be hanlded outside the cpu execution
390 loop */
391 #if defined(TARGET_I386)
392 do_interrupt_user(env->exception_index,
393 env->exception_is_int,
394 env->error_code,
395 env->exception_next_eip);
396 #endif
397 ret = env->exception_index;
398 break;
399 } else {
400 #if defined(TARGET_I386)
401 /* simulate a real cpu exception. On i386, it can
402 trigger new exceptions, but we do not handle
403 double or triple faults yet. */
404 do_interrupt(env->exception_index,
405 env->exception_is_int,
406 env->error_code,
407 env->exception_next_eip, 0);
408 #elif defined(TARGET_PPC)
409 do_interrupt(env);
410 #elif defined(TARGET_MIPS)
411 do_interrupt(env);
412 #elif defined(TARGET_SPARC)
413 do_interrupt(env->exception_index);
414 #elif defined(TARGET_ARM)
415 do_interrupt(env);
416 #elif defined(TARGET_SH4)
417 do_interrupt(env);
418 #endif
419 }
420 env->exception_index = -1;
421 }
422 #ifdef USE_KQEMU
423 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
424 int ret;
425 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
426 ret = kqemu_cpu_exec(env);
427 /* put eflags in CPU temporary format */
428 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
429 DF = 1 - (2 * ((env->eflags >> 10) & 1));
430 CC_OP = CC_OP_EFLAGS;
431 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
432 if (ret == 1) {
433 /* exception */
434 longjmp(env->jmp_env, 1);
435 } else if (ret == 2) {
436 /* softmmu execution needed */
437 } else {
438 if (env->interrupt_request != 0) {
439 /* hardware interrupt will be executed just after */
440 } else {
441 /* otherwise, we restart */
442 longjmp(env->jmp_env, 1);
443 }
444 }
445 }
446 #endif
447
448 T0 = 0; /* force lookup of first TB */
449 for(;;) {
450 #ifdef __sparc__
451 /* g1 can be modified by some libc? functions */
452 tmp_T0 = T0;
453 #endif
454 interrupt_request = env->interrupt_request;
455 if (__builtin_expect(interrupt_request, 0)) {
456 #if defined(TARGET_I386)
457 /* if hardware interrupt pending, we execute it */
458 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
459 (env->eflags & IF_MASK) &&
460 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
461 int intno;
462 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
463 intno = cpu_get_pic_interrupt(env);
464 if (loglevel & CPU_LOG_TB_IN_ASM) {
465 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
466 }
467 do_interrupt(intno, 0, 0, 0, 1);
468 /* ensure that no TB jump will be modified as
469 the program flow was changed */
470 #ifdef __sparc__
471 tmp_T0 = 0;
472 #else
473 T0 = 0;
474 #endif
475 }
476 #elif defined(TARGET_PPC)
477 #if 0
478 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
479 cpu_ppc_reset(env);
480 }
481 #endif
482 if (msr_ee != 0) {
483 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
484 /* Raise it */
485 env->exception_index = EXCP_EXTERNAL;
486 env->error_code = 0;
487 do_interrupt(env);
488 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
489 #ifdef __sparc__
490 tmp_T0 = 0;
491 #else
492 T0 = 0;
493 #endif
494 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
495 /* Raise it */
496 env->exception_index = EXCP_DECR;
497 env->error_code = 0;
498 do_interrupt(env);
499 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
500 #ifdef __sparc__
501 tmp_T0 = 0;
502 #else
503 T0 = 0;
504 #endif
505 }
506 }
507 #elif defined(TARGET_MIPS)
508 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
509 (env->CP0_Status & (1 << CP0St_IE)) &&
510 (env->CP0_Status & env->CP0_Cause & 0x0000FF00) &&
511 !(env->hflags & MIPS_HFLAG_EXL) &&
512 !(env->hflags & MIPS_HFLAG_ERL) &&
513 !(env->hflags & MIPS_HFLAG_DM)) {
514 /* Raise it */
515 env->exception_index = EXCP_EXT_INTERRUPT;
516 env->error_code = 0;
517 do_interrupt(env);
518 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
519 #ifdef __sparc__
520 tmp_T0 = 0;
521 #else
522 T0 = 0;
523 #endif
524 }
525 #elif defined(TARGET_SPARC)
526 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
527 (env->psret != 0)) {
528 int pil = env->interrupt_index & 15;
529 int type = env->interrupt_index & 0xf0;
530
531 if (((type == TT_EXTINT) &&
532 (pil == 15 || pil > env->psrpil)) ||
533 type != TT_EXTINT) {
534 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
535 do_interrupt(env->interrupt_index);
536 env->interrupt_index = 0;
537 #ifdef __sparc__
538 tmp_T0 = 0;
539 #else
540 T0 = 0;
541 #endif
542 }
543 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
544 //do_interrupt(0, 0, 0, 0, 0);
545 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
546 } else if (interrupt_request & CPU_INTERRUPT_HALT) {
547 env1->halted = 1;
548 return EXCP_HALTED;
549 }
550 #elif defined(TARGET_ARM)
551 if (interrupt_request & CPU_INTERRUPT_FIQ
552 && !(env->uncached_cpsr & CPSR_F)) {
553 env->exception_index = EXCP_FIQ;
554 do_interrupt(env);
555 }
556 if (interrupt_request & CPU_INTERRUPT_HARD
557 && !(env->uncached_cpsr & CPSR_I)) {
558 env->exception_index = EXCP_IRQ;
559 do_interrupt(env);
560 }
561 #elif defined(TARGET_SH4)
562 /* XXXXX */
563 #endif
564 /* Don't use the cached interupt_request value,
565 do_interrupt may have updated the EXITTB flag. */
566 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
567 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
568 /* ensure that no TB jump will be modified as
569 the program flow was changed */
570 #ifdef __sparc__
571 tmp_T0 = 0;
572 #else
573 T0 = 0;
574 #endif
575 }
576 if (interrupt_request & CPU_INTERRUPT_EXIT) {
577 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
578 env->exception_index = EXCP_INTERRUPT;
579 cpu_loop_exit();
580 }
581 }
582 #ifdef DEBUG_EXEC
583 if ((loglevel & CPU_LOG_TB_CPU)) {
584 #if defined(TARGET_I386)
585 /* restore flags in standard format */
586 #ifdef reg_EAX
587 env->regs[R_EAX] = EAX;
588 #endif
589 #ifdef reg_EBX
590 env->regs[R_EBX] = EBX;
591 #endif
592 #ifdef reg_ECX
593 env->regs[R_ECX] = ECX;
594 #endif
595 #ifdef reg_EDX
596 env->regs[R_EDX] = EDX;
597 #endif
598 #ifdef reg_ESI
599 env->regs[R_ESI] = ESI;
600 #endif
601 #ifdef reg_EDI
602 env->regs[R_EDI] = EDI;
603 #endif
604 #ifdef reg_EBP
605 env->regs[R_EBP] = EBP;
606 #endif
607 #ifdef reg_ESP
608 env->regs[R_ESP] = ESP;
609 #endif
610 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
611 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
612 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
613 #elif defined(TARGET_ARM)
614 cpu_dump_state(env, logfile, fprintf, 0);
615 #elif defined(TARGET_SPARC)
616 REGWPTR = env->regbase + (env->cwp * 16);
617 env->regwptr = REGWPTR;
618 cpu_dump_state(env, logfile, fprintf, 0);
619 #elif defined(TARGET_PPC)
620 cpu_dump_state(env, logfile, fprintf, 0);
621 #elif defined(TARGET_MIPS)
622 cpu_dump_state(env, logfile, fprintf, 0);
623 #elif defined(TARGET_SH4)
624 cpu_dump_state(env, logfile, fprintf, 0);
625 #else
626 #error unsupported target CPU
627 #endif
628 }
629 #endif
630 tb = tb_find_fast();
631 #ifdef DEBUG_EXEC
632 if ((loglevel & CPU_LOG_EXEC)) {
633 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
634 (long)tb->tc_ptr, tb->pc,
635 lookup_symbol(tb->pc));
636 }
637 #endif
638 #ifdef __sparc__
639 T0 = tmp_T0;
640 #endif
641 /* see if we can patch the calling TB. When the TB
642 spans two pages, we cannot safely do a direct
643 jump. */
644 {
645 if (T0 != 0 &&
646 #if USE_KQEMU
647 (env->kqemu_enabled != 2) &&
648 #endif
649 tb->page_addr[1] == -1
650 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
651 && (tb->cflags & CF_CODE_COPY) ==
652 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
653 #endif
654 ) {
655 spin_lock(&tb_lock);
656 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
657 #if defined(USE_CODE_COPY)
658 /* propagates the FP use info */
659 ((TranslationBlock *)(T0 & ~3))->cflags |=
660 (tb->cflags & CF_FP_USED);
661 #endif
662 spin_unlock(&tb_lock);
663 }
664 }
665 tc_ptr = tb->tc_ptr;
666 env->current_tb = tb;
667 /* execute the generated code */
668 gen_func = (void *)tc_ptr;
669 #if defined(__sparc__)
670 __asm__ __volatile__("call %0\n\t"
671 "mov %%o7,%%i0"
672 : /* no outputs */
673 : "r" (gen_func)
674 : "i0", "i1", "i2", "i3", "i4", "i5");
675 #elif defined(__arm__)
676 asm volatile ("mov pc, %0\n\t"
677 ".global exec_loop\n\t"
678 "exec_loop:\n\t"
679 : /* no outputs */
680 : "r" (gen_func)
681 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
682 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
683 {
684 if (!(tb->cflags & CF_CODE_COPY)) {
685 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
686 save_native_fp_state(env);
687 }
688 gen_func();
689 } else {
690 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
691 restore_native_fp_state(env);
692 }
693 /* we work with native eflags */
694 CC_SRC = cc_table[CC_OP].compute_all();
695 CC_OP = CC_OP_EFLAGS;
696 asm(".globl exec_loop\n"
697 "\n"
698 "debug1:\n"
699 " pushl %%ebp\n"
700 " fs movl %10, %9\n"
701 " fs movl %11, %%eax\n"
702 " andl $0x400, %%eax\n"
703 " fs orl %8, %%eax\n"
704 " pushl %%eax\n"
705 " popf\n"
706 " fs movl %%esp, %12\n"
707 " fs movl %0, %%eax\n"
708 " fs movl %1, %%ecx\n"
709 " fs movl %2, %%edx\n"
710 " fs movl %3, %%ebx\n"
711 " fs movl %4, %%esp\n"
712 " fs movl %5, %%ebp\n"
713 " fs movl %6, %%esi\n"
714 " fs movl %7, %%edi\n"
715 " fs jmp *%9\n"
716 "exec_loop:\n"
717 " fs movl %%esp, %4\n"
718 " fs movl %12, %%esp\n"
719 " fs movl %%eax, %0\n"
720 " fs movl %%ecx, %1\n"
721 " fs movl %%edx, %2\n"
722 " fs movl %%ebx, %3\n"
723 " fs movl %%ebp, %5\n"
724 " fs movl %%esi, %6\n"
725 " fs movl %%edi, %7\n"
726 " pushf\n"
727 " popl %%eax\n"
728 " movl %%eax, %%ecx\n"
729 " andl $0x400, %%ecx\n"
730 " shrl $9, %%ecx\n"
731 " andl $0x8d5, %%eax\n"
732 " fs movl %%eax, %8\n"
733 " movl $1, %%eax\n"
734 " subl %%ecx, %%eax\n"
735 " fs movl %%eax, %11\n"
736 " fs movl %9, %%ebx\n" /* get T0 value */
737 " popl %%ebp\n"
738 :
739 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
740 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
741 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
742 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
743 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
744 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
745 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
746 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
747 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
748 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
749 "a" (gen_func),
750 "m" (*(uint8_t *)offsetof(CPUState, df)),
751 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
752 : "%ecx", "%edx"
753 );
754 }
755 }
756 #elif defined(__ia64)
757 struct fptr {
758 void *ip;
759 void *gp;
760 } fp;
761
762 fp.ip = tc_ptr;
763 fp.gp = code_gen_buffer + 2 * (1 << 20);
764 (*(void (*)(void)) &fp)();
765 #else
766 gen_func();
767 #endif
768 env->current_tb = NULL;
769 /* reset soft MMU for next block (it can currently
770 only be set by a memory fault) */
771 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
772 if (env->hflags & HF_SOFTMMU_MASK) {
773 env->hflags &= ~HF_SOFTMMU_MASK;
774 /* do not allow linking to another block */
775 T0 = 0;
776 }
777 #endif
778 #if defined(USE_KQEMU)
779 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
780 if (kqemu_is_ok(env) &&
781 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) {
782 cpu_loop_exit();
783 }
784 #endif
785 }
786 } else {
787 env_to_regs();
788 }
789 } /* for(;;) */
790
791
792 #if defined(TARGET_I386)
793 #if defined(USE_CODE_COPY)
794 if (env->native_fp_regs) {
795 save_native_fp_state(env);
796 }
797 #endif
798 /* restore flags in standard format */
799 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
800
801 /* restore global registers */
802 #ifdef reg_EAX
803 EAX = saved_EAX;
804 #endif
805 #ifdef reg_ECX
806 ECX = saved_ECX;
807 #endif
808 #ifdef reg_EDX
809 EDX = saved_EDX;
810 #endif
811 #ifdef reg_EBX
812 EBX = saved_EBX;
813 #endif
814 #ifdef reg_ESP
815 ESP = saved_ESP;
816 #endif
817 #ifdef reg_EBP
818 EBP = saved_EBP;
819 #endif
820 #ifdef reg_ESI
821 ESI = saved_ESI;
822 #endif
823 #ifdef reg_EDI
824 EDI = saved_EDI;
825 #endif
826 #elif defined(TARGET_ARM)
827 /* XXX: Save/restore host fpu exception state?. */
828 #elif defined(TARGET_SPARC)
829 #if defined(reg_REGWPTR)
830 REGWPTR = saved_regwptr;
831 #endif
832 #elif defined(TARGET_PPC)
833 #elif defined(TARGET_MIPS)
834 #elif defined(TARGET_SH4)
835 /* XXXXX */
836 #else
837 #error unsupported target CPU
838 #endif
839 #ifdef __sparc__
840 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
841 #endif
842 T0 = saved_T0;
843 T1 = saved_T1;
844 #if defined(reg_T2)
845 T2 = saved_T2;
846 #endif
847 env = saved_env;
848 /* fail safe : never use cpu_single_env outside cpu_exec() */
849 cpu_single_env = NULL;
850 return ret;
851 }
852
853 /* must only be called from the generated code as an exception can be
854 generated */
855 void tb_invalidate_page_range(target_ulong start, target_ulong end)
856 {
857 /* XXX: cannot enable it yet because it yields to MMU exception
858 where NIP != read address on PowerPC */
859 #if 0
860 target_ulong phys_addr;
861 phys_addr = get_phys_addr_code(env, start);
862 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
863 #endif
864 }
865
866 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
867
868 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
869 {
870 CPUX86State *saved_env;
871
872 saved_env = env;
873 env = s;
874 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
875 selector &= 0xffff;
876 cpu_x86_load_seg_cache(env, seg_reg, selector,
877 (selector << 4), 0xffff, 0);
878 } else {
879 load_seg(seg_reg, selector);
880 }
881 env = saved_env;
882 }
883
884 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
885 {
886 CPUX86State *saved_env;
887
888 saved_env = env;
889 env = s;
890
891 helper_fsave((target_ulong)ptr, data32);
892
893 env = saved_env;
894 }
895
896 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
897 {
898 CPUX86State *saved_env;
899
900 saved_env = env;
901 env = s;
902
903 helper_frstor((target_ulong)ptr, data32);
904
905 env = saved_env;
906 }
907
908 #endif /* TARGET_I386 */
909
910 #if !defined(CONFIG_SOFTMMU)
911
912 #if defined(TARGET_I386)
913
914 /* 'pc' is the host PC at which the exception was raised. 'address' is
915 the effective address of the memory exception. 'is_write' is 1 if a
916 write caused the exception and otherwise 0'. 'old_set' is the
917 signal set which should be restored */
918 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
919 int is_write, sigset_t *old_set,
920 void *puc)
921 {
922 TranslationBlock *tb;
923 int ret;
924
925 if (cpu_single_env)
926 env = cpu_single_env; /* XXX: find a correct solution for multithread */
927 #if defined(DEBUG_SIGNAL)
928 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
929 pc, address, is_write, *(unsigned long *)old_set);
930 #endif
931 /* XXX: locking issue */
932 if (is_write && page_unprotect(h2g(address), pc, puc)) {
933 return 1;
934 }
935
936 /* see if it is an MMU fault */
937 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
938 ((env->hflags & HF_CPL_MASK) == 3), 0);
939 if (ret < 0)
940 return 0; /* not an MMU fault */
941 if (ret == 0)
942 return 1; /* the MMU fault was handled without causing real CPU fault */
943 /* now we have a real cpu fault */
944 tb = tb_find_pc(pc);
945 if (tb) {
946 /* the PC is inside the translated code. It means that we have
947 a virtual CPU fault */
948 cpu_restore_state(tb, env, pc, puc);
949 }
950 if (ret == 1) {
951 #if 0
952 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
953 env->eip, env->cr[2], env->error_code);
954 #endif
955 /* we restore the process signal mask as the sigreturn should
956 do it (XXX: use sigsetjmp) */
957 sigprocmask(SIG_SETMASK, old_set, NULL);
958 raise_exception_err(env->exception_index, env->error_code);
959 } else {
960 /* activate soft MMU for this block */
961 env->hflags |= HF_SOFTMMU_MASK;
962 cpu_resume_from_signal(env, puc);
963 }
964 /* never comes here */
965 return 1;
966 }
967
968 #elif defined(TARGET_ARM)
969 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
970 int is_write, sigset_t *old_set,
971 void *puc)
972 {
973 TranslationBlock *tb;
974 int ret;
975
976 if (cpu_single_env)
977 env = cpu_single_env; /* XXX: find a correct solution for multithread */
978 #if defined(DEBUG_SIGNAL)
979 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
980 pc, address, is_write, *(unsigned long *)old_set);
981 #endif
982 /* XXX: locking issue */
983 if (is_write && page_unprotect(h2g(address), pc, puc)) {
984 return 1;
985 }
986 /* see if it is an MMU fault */
987 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
988 if (ret < 0)
989 return 0; /* not an MMU fault */
990 if (ret == 0)
991 return 1; /* the MMU fault was handled without causing real CPU fault */
992 /* now we have a real cpu fault */
993 tb = tb_find_pc(pc);
994 if (tb) {
995 /* the PC is inside the translated code. It means that we have
996 a virtual CPU fault */
997 cpu_restore_state(tb, env, pc, puc);
998 }
999 /* we restore the process signal mask as the sigreturn should
1000 do it (XXX: use sigsetjmp) */
1001 sigprocmask(SIG_SETMASK, old_set, NULL);
1002 cpu_loop_exit();
1003 }
1004 #elif defined(TARGET_SPARC)
1005 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1006 int is_write, sigset_t *old_set,
1007 void *puc)
1008 {
1009 TranslationBlock *tb;
1010 int ret;
1011
1012 if (cpu_single_env)
1013 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1014 #if defined(DEBUG_SIGNAL)
1015 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1016 pc, address, is_write, *(unsigned long *)old_set);
1017 #endif
1018 /* XXX: locking issue */
1019 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1020 return 1;
1021 }
1022 /* see if it is an MMU fault */
1023 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
1024 if (ret < 0)
1025 return 0; /* not an MMU fault */
1026 if (ret == 0)
1027 return 1; /* the MMU fault was handled without causing real CPU fault */
1028 /* now we have a real cpu fault */
1029 tb = tb_find_pc(pc);
1030 if (tb) {
1031 /* the PC is inside the translated code. It means that we have
1032 a virtual CPU fault */
1033 cpu_restore_state(tb, env, pc, puc);
1034 }
1035 /* we restore the process signal mask as the sigreturn should
1036 do it (XXX: use sigsetjmp) */
1037 sigprocmask(SIG_SETMASK, old_set, NULL);
1038 cpu_loop_exit();
1039 }
1040 #elif defined (TARGET_PPC)
1041 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1042 int is_write, sigset_t *old_set,
1043 void *puc)
1044 {
1045 TranslationBlock *tb;
1046 int ret;
1047
1048 if (cpu_single_env)
1049 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1050 #if defined(DEBUG_SIGNAL)
1051 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1052 pc, address, is_write, *(unsigned long *)old_set);
1053 #endif
1054 /* XXX: locking issue */
1055 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1056 return 1;
1057 }
1058
1059 /* see if it is an MMU fault */
1060 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
1061 if (ret < 0)
1062 return 0; /* not an MMU fault */
1063 if (ret == 0)
1064 return 1; /* the MMU fault was handled without causing real CPU fault */
1065
1066 /* now we have a real cpu fault */
1067 tb = tb_find_pc(pc);
1068 if (tb) {
1069 /* the PC is inside the translated code. It means that we have
1070 a virtual CPU fault */
1071 cpu_restore_state(tb, env, pc, puc);
1072 }
1073 if (ret == 1) {
1074 #if 0
1075 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1076 env->nip, env->error_code, tb);
1077 #endif
1078 /* we restore the process signal mask as the sigreturn should
1079 do it (XXX: use sigsetjmp) */
1080 sigprocmask(SIG_SETMASK, old_set, NULL);
1081 do_raise_exception_err(env->exception_index, env->error_code);
1082 } else {
1083 /* activate soft MMU for this block */
1084 cpu_resume_from_signal(env, puc);
1085 }
1086 /* never comes here */
1087 return 1;
1088 }
1089
1090 #elif defined (TARGET_MIPS)
1091 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1092 int is_write, sigset_t *old_set,
1093 void *puc)
1094 {
1095 TranslationBlock *tb;
1096 int ret;
1097
1098 if (cpu_single_env)
1099 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1100 #if defined(DEBUG_SIGNAL)
1101 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1102 pc, address, is_write, *(unsigned long *)old_set);
1103 #endif
1104 /* XXX: locking issue */
1105 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1106 return 1;
1107 }
1108
1109 /* see if it is an MMU fault */
1110 ret = cpu_mips_handle_mmu_fault(env, address, is_write, 1, 0);
1111 if (ret < 0)
1112 return 0; /* not an MMU fault */
1113 if (ret == 0)
1114 return 1; /* the MMU fault was handled without causing real CPU fault */
1115
1116 /* now we have a real cpu fault */
1117 tb = tb_find_pc(pc);
1118 if (tb) {
1119 /* the PC is inside the translated code. It means that we have
1120 a virtual CPU fault */
1121 cpu_restore_state(tb, env, pc, puc);
1122 }
1123 if (ret == 1) {
1124 #if 0
1125 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1126 env->nip, env->error_code, tb);
1127 #endif
1128 /* we restore the process signal mask as the sigreturn should
1129 do it (XXX: use sigsetjmp) */
1130 sigprocmask(SIG_SETMASK, old_set, NULL);
1131 do_raise_exception_err(env->exception_index, env->error_code);
1132 } else {
1133 /* activate soft MMU for this block */
1134 cpu_resume_from_signal(env, puc);
1135 }
1136 /* never comes here */
1137 return 1;
1138 }
1139
1140 #elif defined (TARGET_SH4)
1141 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
1142 int is_write, sigset_t *old_set,
1143 void *puc)
1144 {
1145 TranslationBlock *tb;
1146 int ret;
1147
1148 if (cpu_single_env)
1149 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1150 #if defined(DEBUG_SIGNAL)
1151 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1152 pc, address, is_write, *(unsigned long *)old_set);
1153 #endif
1154 /* XXX: locking issue */
1155 if (is_write && page_unprotect(h2g(address), pc, puc)) {
1156 return 1;
1157 }
1158
1159 /* see if it is an MMU fault */
1160 ret = cpu_sh4_handle_mmu_fault(env, address, is_write, 1, 0);
1161 if (ret < 0)
1162 return 0; /* not an MMU fault */
1163 if (ret == 0)
1164 return 1; /* the MMU fault was handled without causing real CPU fault */
1165
1166 /* now we have a real cpu fault */
1167 tb = tb_find_pc(pc);
1168 if (tb) {
1169 /* the PC is inside the translated code. It means that we have
1170 a virtual CPU fault */
1171 cpu_restore_state(tb, env, pc, puc);
1172 }
1173 if (ret == 1) {
1174 #if 0
1175 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1176 env->nip, env->error_code, tb);
1177 #endif
1178 /* we restore the process signal mask as the sigreturn should
1179 do it (XXX: use sigsetjmp) */
1180 sigprocmask(SIG_SETMASK, old_set, NULL);
1181 // do_raise_exception_err(env->exception_index, env->error_code);
1182 } else {
1183 /* activate soft MMU for this block */
1184 cpu_resume_from_signal(env, puc);
1185 }
1186 /* never comes here */
1187 return 1;
1188 }
1189 #else
1190 #error unsupported target CPU
1191 #endif
1192
1193 #if defined(__i386__)
1194
1195 #if defined(USE_CODE_COPY)
1196 static void cpu_send_trap(unsigned long pc, int trap,
1197 struct ucontext *uc)
1198 {
1199 TranslationBlock *tb;
1200
1201 if (cpu_single_env)
1202 env = cpu_single_env; /* XXX: find a correct solution for multithread */
1203 /* now we have a real cpu fault */
1204 tb = tb_find_pc(pc);
1205 if (tb) {
1206 /* the PC is inside the translated code. It means that we have
1207 a virtual CPU fault */
1208 cpu_restore_state(tb, env, pc, uc);
1209 }
1210 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
1211 raise_exception_err(trap, env->error_code);
1212 }
1213 #endif
1214
1215 int cpu_signal_handler(int host_signum, struct siginfo *info,
1216 void *puc)
1217 {
1218 struct ucontext *uc = puc;
1219 unsigned long pc;
1220 int trapno;
1221
1222 #ifndef REG_EIP
1223 /* for glibc 2.1 */
1224 #define REG_EIP EIP
1225 #define REG_ERR ERR
1226 #define REG_TRAPNO TRAPNO
1227 #endif
1228 pc = uc->uc_mcontext.gregs[REG_EIP];
1229 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
1230 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1231 if (trapno == 0x00 || trapno == 0x05) {
1232 /* send division by zero or bound exception */
1233 cpu_send_trap(pc, trapno, uc);
1234 return 1;
1235 } else
1236 #endif
1237 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1238 trapno == 0xe ?
1239 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1240 &uc->uc_sigmask, puc);
1241 }
1242
1243 #elif defined(__x86_64__)
1244
1245 int cpu_signal_handler(int host_signum, struct siginfo *info,
1246 void *puc)
1247 {
1248 struct ucontext *uc = puc;
1249 unsigned long pc;
1250
1251 pc = uc->uc_mcontext.gregs[REG_RIP];
1252 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1253 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
1254 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
1255 &uc->uc_sigmask, puc);
1256 }
1257
1258 #elif defined(__powerpc__)
1259
1260 /***********************************************************************
1261 * signal context platform-specific definitions
1262 * From Wine
1263 */
1264 #ifdef linux
1265 /* All Registers access - only for local access */
1266 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1267 /* Gpr Registers access */
1268 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1269 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1270 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1271 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1272 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1273 # define LR_sig(context) REG_sig(link, context) /* Link register */
1274 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1275 /* Float Registers access */
1276 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1277 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1278 /* Exception Registers access */
1279 # define DAR_sig(context) REG_sig(dar, context)
1280 # define DSISR_sig(context) REG_sig(dsisr, context)
1281 # define TRAP_sig(context) REG_sig(trap, context)
1282 #endif /* linux */
1283
1284 #ifdef __APPLE__
1285 # include <sys/ucontext.h>
1286 typedef struct ucontext SIGCONTEXT;
1287 /* All Registers access - only for local access */
1288 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1289 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1290 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1291 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1292 /* Gpr Registers access */
1293 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1294 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1295 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1296 # define CTR_sig(context) REG_sig(ctr, context)
1297 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1298 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1299 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1300 /* Float Registers access */
1301 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1302 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1303 /* Exception Registers access */
1304 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1305 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1306 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1307 #endif /* __APPLE__ */
1308
1309 int cpu_signal_handler(int host_signum, struct siginfo *info,
1310 void *puc)
1311 {
1312 struct ucontext *uc = puc;
1313 unsigned long pc;
1314 int is_write;
1315
1316 pc = IAR_sig(uc);
1317 is_write = 0;
1318 #if 0
1319 /* ppc 4xx case */
1320 if (DSISR_sig(uc) & 0x00800000)
1321 is_write = 1;
1322 #else
1323 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1324 is_write = 1;
1325 #endif
1326 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1327 is_write, &uc->uc_sigmask, puc);
1328 }
1329
1330 #elif defined(__alpha__)
1331
1332 int cpu_signal_handler(int host_signum, struct siginfo *info,
1333 void *puc)
1334 {
1335 struct ucontext *uc = puc;
1336 uint32_t *pc = uc->uc_mcontext.sc_pc;
1337 uint32_t insn = *pc;
1338 int is_write = 0;
1339
1340 /* XXX: need kernel patch to get write flag faster */
1341 switch (insn >> 26) {
1342 case 0x0d: // stw
1343 case 0x0e: // stb
1344 case 0x0f: // stq_u
1345 case 0x24: // stf
1346 case 0x25: // stg
1347 case 0x26: // sts
1348 case 0x27: // stt
1349 case 0x2c: // stl
1350 case 0x2d: // stq
1351 case 0x2e: // stl_c
1352 case 0x2f: // stq_c
1353 is_write = 1;
1354 }
1355
1356 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1357 is_write, &uc->uc_sigmask, puc);
1358 }
1359 #elif defined(__sparc__)
1360
1361 int cpu_signal_handler(int host_signum, struct siginfo *info,
1362 void *puc)
1363 {
1364 uint32_t *regs = (uint32_t *)(info + 1);
1365 void *sigmask = (regs + 20);
1366 unsigned long pc;
1367 int is_write;
1368 uint32_t insn;
1369
1370 /* XXX: is there a standard glibc define ? */
1371 pc = regs[1];
1372 /* XXX: need kernel patch to get write flag faster */
1373 is_write = 0;
1374 insn = *(uint32_t *)pc;
1375 if ((insn >> 30) == 3) {
1376 switch((insn >> 19) & 0x3f) {
1377 case 0x05: // stb
1378 case 0x06: // sth
1379 case 0x04: // st
1380 case 0x07: // std
1381 case 0x24: // stf
1382 case 0x27: // stdf
1383 case 0x25: // stfsr
1384 is_write = 1;
1385 break;
1386 }
1387 }
1388 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1389 is_write, sigmask, NULL);
1390 }
1391
1392 #elif defined(__arm__)
1393
1394 int cpu_signal_handler(int host_signum, struct siginfo *info,
1395 void *puc)
1396 {
1397 struct ucontext *uc = puc;
1398 unsigned long pc;
1399 int is_write;
1400
1401 pc = uc->uc_mcontext.gregs[R15];
1402 /* XXX: compute is_write */
1403 is_write = 0;
1404 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1405 is_write,
1406 &uc->uc_sigmask);
1407 }
1408
1409 #elif defined(__mc68000)
1410
1411 int cpu_signal_handler(int host_signum, struct siginfo *info,
1412 void *puc)
1413 {
1414 struct ucontext *uc = puc;
1415 unsigned long pc;
1416 int is_write;
1417
1418 pc = uc->uc_mcontext.gregs[16];
1419 /* XXX: compute is_write */
1420 is_write = 0;
1421 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1422 is_write,
1423 &uc->uc_sigmask, puc);
1424 }
1425
1426 #elif defined(__ia64)
1427
1428 #ifndef __ISR_VALID
1429 /* This ought to be in <bits/siginfo.h>... */
1430 # define __ISR_VALID 1
1431 #endif
1432
1433 int cpu_signal_handler(int host_signum, struct siginfo *info, void *puc)
1434 {
1435 struct ucontext *uc = puc;
1436 unsigned long ip;
1437 int is_write = 0;
1438
1439 ip = uc->uc_mcontext.sc_ip;
1440 switch (host_signum) {
1441 case SIGILL:
1442 case SIGFPE:
1443 case SIGSEGV:
1444 case SIGBUS:
1445 case SIGTRAP:
1446 if (info->si_code && (info->si_segvflags & __ISR_VALID))
1447 /* ISR.W (write-access) is bit 33: */
1448 is_write = (info->si_isr >> 33) & 1;
1449 break;
1450
1451 default:
1452 break;
1453 }
1454 return handle_cpu_signal(ip, (unsigned long)info->si_addr,
1455 is_write,
1456 &uc->uc_sigmask, puc);
1457 }
1458
1459 #elif defined(__s390__)
1460
1461 int cpu_signal_handler(int host_signum, struct siginfo *info,
1462 void *puc)
1463 {
1464 struct ucontext *uc = puc;
1465 unsigned long pc;
1466 int is_write;
1467
1468 pc = uc->uc_mcontext.psw.addr;
1469 /* XXX: compute is_write */
1470 is_write = 0;
1471 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1472 is_write,
1473 &uc->uc_sigmask, puc);
1474 }
1475
1476 #else
1477
1478 #error host CPU specific signal handler needed
1479
1480 #endif
1481
1482 #endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing