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git.proxmox.com Git - qemu.git/blob - cpu-exec.c
2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag
;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_M68K)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env
->jmp_env
, 1);
50 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4) || defined(TARGET_M68K))
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
57 void cpu_resume_from_signal(CPUState
*env1
, void *puc
)
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext
*uc
= puc
;
65 /* XXX: restore cpu registers saved in host registers */
67 #if !defined(CONFIG_SOFTMMU)
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
73 longjmp(env
->jmp_env
, 1);
77 static TranslationBlock
*tb_find_slow(target_ulong pc
,
81 TranslationBlock
*tb
, **ptb1
;
84 target_ulong phys_pc
, phys_page1
, phys_page2
, virt_page2
;
89 tb_invalidated_flag
= 0;
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93 /* find translated block using physical mappings */
94 phys_pc
= get_phys_addr_code(env
, pc
);
95 phys_page1
= phys_pc
& TARGET_PAGE_MASK
;
97 h
= tb_phys_hash_func(phys_pc
);
98 ptb1
= &tb_phys_hash
[h
];
104 tb
->page_addr
[0] == phys_page1
&&
105 tb
->cs_base
== cs_base
&&
106 tb
->flags
== flags
) {
107 /* check next page if needed */
108 if (tb
->page_addr
[1] != -1) {
109 virt_page2
= (pc
& TARGET_PAGE_MASK
) +
111 phys_page2
= get_phys_addr_code(env
, virt_page2
);
112 if (tb
->page_addr
[1] == phys_page2
)
118 ptb1
= &tb
->phys_hash_next
;
121 /* if no translated code available, then translate it now */
124 /* flush must be done */
126 /* cannot fail at this point */
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag
= 1;
131 tc_ptr
= code_gen_ptr
;
133 tb
->cs_base
= cs_base
;
135 cpu_gen_code(env
, tb
, CODE_GEN_MAX_SIZE
, &code_gen_size
);
136 code_gen_ptr
= (void *)(((unsigned long)code_gen_ptr
+ code_gen_size
+ CODE_GEN_ALIGN
- 1) & ~(CODE_GEN_ALIGN
- 1));
138 /* check next page if needed */
139 virt_page2
= (pc
+ tb
->size
- 1) & TARGET_PAGE_MASK
;
141 if ((pc
& TARGET_PAGE_MASK
) != virt_page2
) {
142 phys_page2
= get_phys_addr_code(env
, virt_page2
);
144 tb_link_phys(tb
, phys_pc
, phys_page2
);
147 /* we add the TB in the virtual pc hash table */
148 env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)] = tb
;
149 spin_unlock(&tb_lock
);
153 static inline TranslationBlock
*tb_find_fast(void)
155 TranslationBlock
*tb
;
156 target_ulong cs_base
, pc
;
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
162 #if defined(TARGET_I386)
164 flags
|= (env
->eflags
& (IOPL_MASK
| TF_MASK
| VM_MASK
));
165 cs_base
= env
->segs
[R_CS
].base
;
166 pc
= cs_base
+ env
->eip
;
167 #elif defined(TARGET_ARM)
168 flags
= env
->thumb
| (env
->vfp
.vec_len
<< 1)
169 | (env
->vfp
.vec_stride
<< 4);
170 if ((env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
)
172 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30))
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags
= (((env
->pstate
& PS_PEF
) >> 1) | ((env
->fprs
& FPRS_FEF
) << 2))
180 | (env
->pstate
& PS_PRIV
) | ((env
->lsu
& (DMMU_E
| IMMU_E
)) >> 2);
182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags
= (env
->psref
<< 3) | ((env
->mmuregs
[0] & (MMU_E
| MMU_NF
)) << 1)
188 #elif defined(TARGET_PPC)
189 flags
= (msr_pr
<< MSR_PR
) | (msr_fp
<< MSR_FP
) |
190 (msr_se
<< MSR_SE
) | (msr_le
<< MSR_LE
);
193 #elif defined(TARGET_MIPS)
194 flags
= env
->hflags
& (MIPS_HFLAG_TMASK
| MIPS_HFLAG_BMASK
);
197 #elif defined(TARGET_M68K)
198 flags
= env
->fpcr
& M68K_FPCR_PREC
;
201 #elif defined(TARGET_SH4)
202 flags
= env
->sr
& (SR_MD
| SR_RB
);
203 cs_base
= 0; /* XXXXX */
206 #error unsupported CPU
208 tb
= env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)];
209 if (__builtin_expect(!tb
|| tb
->pc
!= pc
|| tb
->cs_base
!= cs_base
||
210 tb
->flags
!= flags
, 0)) {
211 tb
= tb_find_slow(pc
, cs_base
, flags
);
212 /* Note: we do it here to avoid a gcc bug on Mac OS X when
213 doing it in tb_find_slow */
214 if (tb_invalidated_flag
) {
215 /* as some TB could have been invalidated because
216 of memory exceptions while generating the code, we
217 must recompute the hash index here */
225 /* main execution loop */
227 int cpu_exec(CPUState
*env1
)
229 #define DECLARE_HOST_REGS 1
230 #include "hostregs_helper.h"
231 #if defined(TARGET_SPARC)
232 #if defined(reg_REGWPTR)
233 uint32_t *saved_regwptr
;
236 #if defined(__sparc__) && !defined(HOST_SOLARIS)
240 int ret
, interrupt_request
;
241 void (*gen_func
)(void);
242 TranslationBlock
*tb
;
245 #if defined(TARGET_I386)
246 /* handle exit of HALTED state */
247 if (env1
->hflags
& HF_HALTED_MASK
) {
248 /* disable halt condition */
249 if ((env1
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
250 (env1
->eflags
& IF_MASK
)) {
251 env1
->hflags
&= ~HF_HALTED_MASK
;
256 #elif defined(TARGET_PPC)
258 if (env1
->msr
[MSR_EE
] &&
259 (env1
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
265 #elif defined(TARGET_SPARC)
267 if ((env1
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
268 (env1
->psret
!= 0)) {
274 #elif defined(TARGET_ARM)
276 /* An interrupt wakes the CPU even if the I and F CPSR bits are
278 if (env1
->interrupt_request
279 & (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
)) {
285 #elif defined(TARGET_MIPS)
287 if (env1
->interrupt_request
&
288 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
)) {
296 cpu_single_env
= env1
;
298 /* first we save global registers */
299 #define SAVE_HOST_REGS 1
300 #include "hostregs_helper.h"
302 #if defined(__sparc__) && !defined(HOST_SOLARIS)
303 /* we also save i7 because longjmp may not restore it */
304 asm volatile ("mov %%i7, %0" : "=r" (saved_i7
));
307 #if defined(TARGET_I386)
309 /* put eflags in CPU temporary format */
310 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
311 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
312 CC_OP
= CC_OP_EFLAGS
;
313 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
314 #elif defined(TARGET_ARM)
315 #elif defined(TARGET_SPARC)
316 #if defined(reg_REGWPTR)
317 saved_regwptr
= REGWPTR
;
319 #elif defined(TARGET_PPC)
320 #elif defined(TARGET_M68K)
321 env
->cc_op
= CC_OP_FLAGS
;
322 env
->cc_dest
= env
->sr
& 0xf;
323 env
->cc_x
= (env
->sr
>> 4) & 1;
324 #elif defined(TARGET_MIPS)
325 #elif defined(TARGET_SH4)
328 #error unsupported target CPU
330 env
->exception_index
= -1;
332 /* prepare setjmp context for exception handling */
334 if (setjmp(env
->jmp_env
) == 0) {
335 env
->current_tb
= NULL
;
336 /* if an exception is pending, we execute it here */
337 if (env
->exception_index
>= 0) {
338 if (env
->exception_index
>= EXCP_INTERRUPT
) {
339 /* exit request from the cpu execution loop */
340 ret
= env
->exception_index
;
342 } else if (env
->user_mode_only
) {
343 /* if user mode only, we simulate a fake exception
344 which will be handled outside the cpu execution
346 #if defined(TARGET_I386)
347 do_interrupt_user(env
->exception_index
,
348 env
->exception_is_int
,
350 env
->exception_next_eip
);
352 ret
= env
->exception_index
;
355 #if defined(TARGET_I386)
356 /* simulate a real cpu exception. On i386, it can
357 trigger new exceptions, but we do not handle
358 double or triple faults yet. */
359 do_interrupt(env
->exception_index
,
360 env
->exception_is_int
,
362 env
->exception_next_eip
, 0);
363 #elif defined(TARGET_PPC)
365 #elif defined(TARGET_MIPS)
367 #elif defined(TARGET_SPARC)
368 do_interrupt(env
->exception_index
);
369 #elif defined(TARGET_ARM)
371 #elif defined(TARGET_SH4)
375 env
->exception_index
= -1;
378 if (kqemu_is_ok(env
) && env
->interrupt_request
== 0) {
380 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
381 ret
= kqemu_cpu_exec(env
);
382 /* put eflags in CPU temporary format */
383 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
384 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
385 CC_OP
= CC_OP_EFLAGS
;
386 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
389 longjmp(env
->jmp_env
, 1);
390 } else if (ret
== 2) {
391 /* softmmu execution needed */
393 if (env
->interrupt_request
!= 0) {
394 /* hardware interrupt will be executed just after */
396 /* otherwise, we restart */
397 longjmp(env
->jmp_env
, 1);
403 T0
= 0; /* force lookup of first TB */
405 #if defined(__sparc__) && !defined(HOST_SOLARIS)
406 /* g1 can be modified by some libc? functions */
409 interrupt_request
= env
->interrupt_request
;
410 if (__builtin_expect(interrupt_request
, 0)) {
411 if (interrupt_request
& CPU_INTERRUPT_DEBUG
) {
412 env
->interrupt_request
&= ~CPU_INTERRUPT_DEBUG
;
413 env
->exception_index
= EXCP_DEBUG
;
416 #if defined(TARGET_I386)
417 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
418 !(env
->hflags
& HF_SMM_MASK
)) {
419 env
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
421 #if defined(__sparc__) && !defined(HOST_SOLARIS)
426 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
427 (env
->eflags
& IF_MASK
) &&
428 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
430 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
431 intno
= cpu_get_pic_interrupt(env
);
432 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
433 fprintf(logfile
, "Servicing hardware INT=0x%02x\n", intno
);
435 do_interrupt(intno
, 0, 0, 0, 1);
436 /* ensure that no TB jump will be modified as
437 the program flow was changed */
438 #if defined(__sparc__) && !defined(HOST_SOLARIS)
444 #elif defined(TARGET_PPC)
446 if ((interrupt_request
& CPU_INTERRUPT_RESET
)) {
450 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
451 if (ppc_hw_interrupt(env
) == 1) {
452 /* Some exception was raised */
453 if (env
->pending_interrupts
== 0)
454 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
455 #if defined(__sparc__) && !defined(HOST_SOLARIS)
462 #elif defined(TARGET_MIPS)
463 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
464 (env
->CP0_Status
& env
->CP0_Cause
& CP0Ca_IP_mask
) &&
465 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
466 !(env
->CP0_Status
& (1 << CP0St_EXL
)) &&
467 !(env
->CP0_Status
& (1 << CP0St_ERL
)) &&
468 !(env
->hflags
& MIPS_HFLAG_DM
)) {
470 env
->exception_index
= EXCP_EXT_INTERRUPT
;
473 #if defined(__sparc__) && !defined(HOST_SOLARIS)
479 #elif defined(TARGET_SPARC)
480 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
482 int pil
= env
->interrupt_index
& 15;
483 int type
= env
->interrupt_index
& 0xf0;
485 if (((type
== TT_EXTINT
) &&
486 (pil
== 15 || pil
> env
->psrpil
)) ||
488 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
489 do_interrupt(env
->interrupt_index
);
490 env
->interrupt_index
= 0;
491 #if defined(__sparc__) && !defined(HOST_SOLARIS)
497 } else if (interrupt_request
& CPU_INTERRUPT_TIMER
) {
498 //do_interrupt(0, 0, 0, 0, 0);
499 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
500 } else if (interrupt_request
& CPU_INTERRUPT_HALT
) {
501 env
->interrupt_request
&= ~CPU_INTERRUPT_HALT
;
503 env
->exception_index
= EXCP_HLT
;
506 #elif defined(TARGET_ARM)
507 if (interrupt_request
& CPU_INTERRUPT_FIQ
508 && !(env
->uncached_cpsr
& CPSR_F
)) {
509 env
->exception_index
= EXCP_FIQ
;
512 if (interrupt_request
& CPU_INTERRUPT_HARD
513 && !(env
->uncached_cpsr
& CPSR_I
)) {
514 env
->exception_index
= EXCP_IRQ
;
517 #elif defined(TARGET_SH4)
520 /* Don't use the cached interupt_request value,
521 do_interrupt may have updated the EXITTB flag. */
522 if (env
->interrupt_request
& CPU_INTERRUPT_EXITTB
) {
523 env
->interrupt_request
&= ~CPU_INTERRUPT_EXITTB
;
524 /* ensure that no TB jump will be modified as
525 the program flow was changed */
526 #if defined(__sparc__) && !defined(HOST_SOLARIS)
532 if (interrupt_request
& CPU_INTERRUPT_EXIT
) {
533 env
->interrupt_request
&= ~CPU_INTERRUPT_EXIT
;
534 env
->exception_index
= EXCP_INTERRUPT
;
539 if ((loglevel
& CPU_LOG_TB_CPU
)) {
540 #if defined(TARGET_I386)
541 /* restore flags in standard format */
543 env
->regs
[R_EAX
] = EAX
;
546 env
->regs
[R_EBX
] = EBX
;
549 env
->regs
[R_ECX
] = ECX
;
552 env
->regs
[R_EDX
] = EDX
;
555 env
->regs
[R_ESI
] = ESI
;
558 env
->regs
[R_EDI
] = EDI
;
561 env
->regs
[R_EBP
] = EBP
;
564 env
->regs
[R_ESP
] = ESP
;
566 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
567 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
568 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
569 #elif defined(TARGET_ARM)
570 cpu_dump_state(env
, logfile
, fprintf
, 0);
571 #elif defined(TARGET_SPARC)
572 REGWPTR
= env
->regbase
+ (env
->cwp
* 16);
573 env
->regwptr
= REGWPTR
;
574 cpu_dump_state(env
, logfile
, fprintf
, 0);
575 #elif defined(TARGET_PPC)
576 cpu_dump_state(env
, logfile
, fprintf
, 0);
577 #elif defined(TARGET_M68K)
578 cpu_m68k_flush_flags(env
, env
->cc_op
);
579 env
->cc_op
= CC_OP_FLAGS
;
580 env
->sr
= (env
->sr
& 0xffe0)
581 | env
->cc_dest
| (env
->cc_x
<< 4);
582 cpu_dump_state(env
, logfile
, fprintf
, 0);
583 #elif defined(TARGET_MIPS)
584 cpu_dump_state(env
, logfile
, fprintf
, 0);
585 #elif defined(TARGET_SH4)
586 cpu_dump_state(env
, logfile
, fprintf
, 0);
588 #error unsupported target CPU
594 if ((loglevel
& CPU_LOG_EXEC
)) {
595 fprintf(logfile
, "Trace 0x%08lx [" TARGET_FMT_lx
"] %s\n",
596 (long)tb
->tc_ptr
, tb
->pc
,
597 lookup_symbol(tb
->pc
));
600 #if defined(__sparc__) && !defined(HOST_SOLARIS)
603 /* see if we can patch the calling TB. When the TB
604 spans two pages, we cannot safely do a direct
609 (env
->kqemu_enabled
!= 2) &&
611 tb
->page_addr
[1] == -1
612 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
613 && (tb
->cflags
& CF_CODE_COPY
) ==
614 (((TranslationBlock
*)(T0
& ~3))->cflags
& CF_CODE_COPY
)
618 tb_add_jump((TranslationBlock
*)(long)(T0
& ~3), T0
& 3, tb
);
619 #if defined(USE_CODE_COPY)
620 /* propagates the FP use info */
621 ((TranslationBlock
*)(T0
& ~3))->cflags
|=
622 (tb
->cflags
& CF_FP_USED
);
624 spin_unlock(&tb_lock
);
628 env
->current_tb
= tb
;
629 /* execute the generated code */
630 gen_func
= (void *)tc_ptr
;
631 #if defined(__sparc__)
632 __asm__
__volatile__("call %0\n\t"
636 : "i0", "i1", "i2", "i3", "i4", "i5",
637 "o0", "o1", "o2", "o3", "o4", "o5",
638 "l0", "l1", "l2", "l3", "l4", "l5",
640 #elif defined(__arm__)
641 asm volatile ("mov pc, %0\n\t"
642 ".global exec_loop\n\t"
646 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
647 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
649 if (!(tb
->cflags
& CF_CODE_COPY
)) {
650 if ((tb
->cflags
& CF_FP_USED
) && env
->native_fp_regs
) {
651 save_native_fp_state(env
);
655 if ((tb
->cflags
& CF_FP_USED
) && !env
->native_fp_regs
) {
656 restore_native_fp_state(env
);
658 /* we work with native eflags */
659 CC_SRC
= cc_table
[CC_OP
].compute_all();
660 CC_OP
= CC_OP_EFLAGS
;
661 asm(".globl exec_loop\n"
666 " fs movl %11, %%eax\n"
667 " andl $0x400, %%eax\n"
668 " fs orl %8, %%eax\n"
671 " fs movl %%esp, %12\n"
672 " fs movl %0, %%eax\n"
673 " fs movl %1, %%ecx\n"
674 " fs movl %2, %%edx\n"
675 " fs movl %3, %%ebx\n"
676 " fs movl %4, %%esp\n"
677 " fs movl %5, %%ebp\n"
678 " fs movl %6, %%esi\n"
679 " fs movl %7, %%edi\n"
682 " fs movl %%esp, %4\n"
683 " fs movl %12, %%esp\n"
684 " fs movl %%eax, %0\n"
685 " fs movl %%ecx, %1\n"
686 " fs movl %%edx, %2\n"
687 " fs movl %%ebx, %3\n"
688 " fs movl %%ebp, %5\n"
689 " fs movl %%esi, %6\n"
690 " fs movl %%edi, %7\n"
693 " movl %%eax, %%ecx\n"
694 " andl $0x400, %%ecx\n"
696 " andl $0x8d5, %%eax\n"
697 " fs movl %%eax, %8\n"
699 " subl %%ecx, %%eax\n"
700 " fs movl %%eax, %11\n"
701 " fs movl %9, %%ebx\n" /* get T0 value */
704 : "m" (*(uint8_t *)offsetof(CPUState
, regs
[0])),
705 "m" (*(uint8_t *)offsetof(CPUState
, regs
[1])),
706 "m" (*(uint8_t *)offsetof(CPUState
, regs
[2])),
707 "m" (*(uint8_t *)offsetof(CPUState
, regs
[3])),
708 "m" (*(uint8_t *)offsetof(CPUState
, regs
[4])),
709 "m" (*(uint8_t *)offsetof(CPUState
, regs
[5])),
710 "m" (*(uint8_t *)offsetof(CPUState
, regs
[6])),
711 "m" (*(uint8_t *)offsetof(CPUState
, regs
[7])),
712 "m" (*(uint8_t *)offsetof(CPUState
, cc_src
)),
713 "m" (*(uint8_t *)offsetof(CPUState
, tmp0
)),
715 "m" (*(uint8_t *)offsetof(CPUState
, df
)),
716 "m" (*(uint8_t *)offsetof(CPUState
, saved_esp
))
721 #elif defined(__ia64)
728 fp
.gp
= code_gen_buffer
+ 2 * (1 << 20);
729 (*(void (*)(void)) &fp
)();
733 env
->current_tb
= NULL
;
734 /* reset soft MMU for next block (it can currently
735 only be set by a memory fault) */
736 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
737 if (env
->hflags
& HF_SOFTMMU_MASK
) {
738 env
->hflags
&= ~HF_SOFTMMU_MASK
;
739 /* do not allow linking to another block */
743 #if defined(USE_KQEMU)
744 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
745 if (kqemu_is_ok(env
) &&
746 (cpu_get_time_fast() - env
->last_io_time
) >= MIN_CYCLE_BEFORE_SWITCH
) {
757 #if defined(TARGET_I386)
758 #if defined(USE_CODE_COPY)
759 if (env
->native_fp_regs
) {
760 save_native_fp_state(env
);
763 /* restore flags in standard format */
764 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
765 #elif defined(TARGET_ARM)
766 /* XXX: Save/restore host fpu exception state?. */
767 #elif defined(TARGET_SPARC)
768 #if defined(reg_REGWPTR)
769 REGWPTR
= saved_regwptr
;
771 #elif defined(TARGET_PPC)
772 #elif defined(TARGET_M68K)
773 cpu_m68k_flush_flags(env
, env
->cc_op
);
774 env
->cc_op
= CC_OP_FLAGS
;
775 env
->sr
= (env
->sr
& 0xffe0)
776 | env
->cc_dest
| (env
->cc_x
<< 4);
777 #elif defined(TARGET_MIPS)
778 #elif defined(TARGET_SH4)
781 #error unsupported target CPU
784 /* restore global registers */
785 #if defined(__sparc__) && !defined(HOST_SOLARIS)
786 asm volatile ("mov %0, %%i7" : : "r" (saved_i7
));
788 #include "hostregs_helper.h"
790 /* fail safe : never use cpu_single_env outside cpu_exec() */
791 cpu_single_env
= NULL
;
795 /* must only be called from the generated code as an exception can be
797 void tb_invalidate_page_range(target_ulong start
, target_ulong end
)
799 /* XXX: cannot enable it yet because it yields to MMU exception
800 where NIP != read address on PowerPC */
802 target_ulong phys_addr
;
803 phys_addr
= get_phys_addr_code(env
, start
);
804 tb_invalidate_phys_page_range(phys_addr
, phys_addr
+ end
- start
, 0);
808 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
810 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
)
812 CPUX86State
*saved_env
;
816 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
818 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
819 (selector
<< 4), 0xffff, 0);
821 load_seg(seg_reg
, selector
);
826 void cpu_x86_fsave(CPUX86State
*s
, uint8_t *ptr
, int data32
)
828 CPUX86State
*saved_env
;
833 helper_fsave((target_ulong
)ptr
, data32
);
838 void cpu_x86_frstor(CPUX86State
*s
, uint8_t *ptr
, int data32
)
840 CPUX86State
*saved_env
;
845 helper_frstor((target_ulong
)ptr
, data32
);
850 #endif /* TARGET_I386 */
852 #if !defined(CONFIG_SOFTMMU)
854 #if defined(TARGET_I386)
856 /* 'pc' is the host PC at which the exception was raised. 'address' is
857 the effective address of the memory exception. 'is_write' is 1 if a
858 write caused the exception and otherwise 0'. 'old_set' is the
859 signal set which should be restored */
860 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
861 int is_write
, sigset_t
*old_set
,
864 TranslationBlock
*tb
;
868 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
869 #if defined(DEBUG_SIGNAL)
870 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
871 pc
, address
, is_write
, *(unsigned long *)old_set
);
873 /* XXX: locking issue */
874 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
878 /* see if it is an MMU fault */
879 ret
= cpu_x86_handle_mmu_fault(env
, address
, is_write
,
880 ((env
->hflags
& HF_CPL_MASK
) == 3), 0);
882 return 0; /* not an MMU fault */
884 return 1; /* the MMU fault was handled without causing real CPU fault */
885 /* now we have a real cpu fault */
888 /* the PC is inside the translated code. It means that we have
889 a virtual CPU fault */
890 cpu_restore_state(tb
, env
, pc
, puc
);
894 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
895 env
->eip
, env
->cr
[2], env
->error_code
);
897 /* we restore the process signal mask as the sigreturn should
898 do it (XXX: use sigsetjmp) */
899 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
900 raise_exception_err(env
->exception_index
, env
->error_code
);
902 /* activate soft MMU for this block */
903 env
->hflags
|= HF_SOFTMMU_MASK
;
904 cpu_resume_from_signal(env
, puc
);
906 /* never comes here */
910 #elif defined(TARGET_ARM)
911 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
912 int is_write
, sigset_t
*old_set
,
915 TranslationBlock
*tb
;
919 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
920 #if defined(DEBUG_SIGNAL)
921 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
922 pc
, address
, is_write
, *(unsigned long *)old_set
);
924 /* XXX: locking issue */
925 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
928 /* see if it is an MMU fault */
929 ret
= cpu_arm_handle_mmu_fault(env
, address
, is_write
, 1, 0);
931 return 0; /* not an MMU fault */
933 return 1; /* the MMU fault was handled without causing real CPU fault */
934 /* now we have a real cpu fault */
937 /* the PC is inside the translated code. It means that we have
938 a virtual CPU fault */
939 cpu_restore_state(tb
, env
, pc
, puc
);
941 /* we restore the process signal mask as the sigreturn should
942 do it (XXX: use sigsetjmp) */
943 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
946 #elif defined(TARGET_SPARC)
947 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
948 int is_write
, sigset_t
*old_set
,
951 TranslationBlock
*tb
;
955 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
956 #if defined(DEBUG_SIGNAL)
957 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
958 pc
, address
, is_write
, *(unsigned long *)old_set
);
960 /* XXX: locking issue */
961 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
964 /* see if it is an MMU fault */
965 ret
= cpu_sparc_handle_mmu_fault(env
, address
, is_write
, 1, 0);
967 return 0; /* not an MMU fault */
969 return 1; /* the MMU fault was handled without causing real CPU fault */
970 /* now we have a real cpu fault */
973 /* the PC is inside the translated code. It means that we have
974 a virtual CPU fault */
975 cpu_restore_state(tb
, env
, pc
, puc
);
977 /* we restore the process signal mask as the sigreturn should
978 do it (XXX: use sigsetjmp) */
979 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
982 #elif defined (TARGET_PPC)
983 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
984 int is_write
, sigset_t
*old_set
,
987 TranslationBlock
*tb
;
991 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
992 #if defined(DEBUG_SIGNAL)
993 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
994 pc
, address
, is_write
, *(unsigned long *)old_set
);
996 /* XXX: locking issue */
997 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1001 /* see if it is an MMU fault */
1002 ret
= cpu_ppc_handle_mmu_fault(env
, address
, is_write
, msr_pr
, 0);
1004 return 0; /* not an MMU fault */
1006 return 1; /* the MMU fault was handled without causing real CPU fault */
1008 /* now we have a real cpu fault */
1009 tb
= tb_find_pc(pc
);
1011 /* the PC is inside the translated code. It means that we have
1012 a virtual CPU fault */
1013 cpu_restore_state(tb
, env
, pc
, puc
);
1017 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1018 env
->nip
, env
->error_code
, tb
);
1020 /* we restore the process signal mask as the sigreturn should
1021 do it (XXX: use sigsetjmp) */
1022 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1023 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1025 /* activate soft MMU for this block */
1026 cpu_resume_from_signal(env
, puc
);
1028 /* never comes here */
1032 #elif defined(TARGET_M68K)
1033 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1034 int is_write
, sigset_t
*old_set
,
1037 TranslationBlock
*tb
;
1041 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1042 #if defined(DEBUG_SIGNAL)
1043 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1044 pc
, address
, is_write
, *(unsigned long *)old_set
);
1046 /* XXX: locking issue */
1047 if (is_write
&& page_unprotect(address
, pc
, puc
)) {
1050 /* see if it is an MMU fault */
1051 ret
= cpu_m68k_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1053 return 0; /* not an MMU fault */
1055 return 1; /* the MMU fault was handled without causing real CPU fault */
1056 /* now we have a real cpu fault */
1057 tb
= tb_find_pc(pc
);
1059 /* the PC is inside the translated code. It means that we have
1060 a virtual CPU fault */
1061 cpu_restore_state(tb
, env
, pc
, puc
);
1063 /* we restore the process signal mask as the sigreturn should
1064 do it (XXX: use sigsetjmp) */
1065 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1067 /* never comes here */
1071 #elif defined (TARGET_MIPS)
1072 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1073 int is_write
, sigset_t
*old_set
,
1076 TranslationBlock
*tb
;
1080 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1081 #if defined(DEBUG_SIGNAL)
1082 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1083 pc
, address
, is_write
, *(unsigned long *)old_set
);
1085 /* XXX: locking issue */
1086 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1090 /* see if it is an MMU fault */
1091 ret
= cpu_mips_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1093 return 0; /* not an MMU fault */
1095 return 1; /* the MMU fault was handled without causing real CPU fault */
1097 /* now we have a real cpu fault */
1098 tb
= tb_find_pc(pc
);
1100 /* the PC is inside the translated code. It means that we have
1101 a virtual CPU fault */
1102 cpu_restore_state(tb
, env
, pc
, puc
);
1106 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1107 env
->nip
, env
->error_code
, tb
);
1109 /* we restore the process signal mask as the sigreturn should
1110 do it (XXX: use sigsetjmp) */
1111 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1112 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1114 /* activate soft MMU for this block */
1115 cpu_resume_from_signal(env
, puc
);
1117 /* never comes here */
1121 #elif defined (TARGET_SH4)
1122 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1123 int is_write
, sigset_t
*old_set
,
1126 TranslationBlock
*tb
;
1130 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1131 #if defined(DEBUG_SIGNAL)
1132 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1133 pc
, address
, is_write
, *(unsigned long *)old_set
);
1135 /* XXX: locking issue */
1136 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1140 /* see if it is an MMU fault */
1141 ret
= cpu_sh4_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1143 return 0; /* not an MMU fault */
1145 return 1; /* the MMU fault was handled without causing real CPU fault */
1147 /* now we have a real cpu fault */
1148 tb
= tb_find_pc(pc
);
1150 /* the PC is inside the translated code. It means that we have
1151 a virtual CPU fault */
1152 cpu_restore_state(tb
, env
, pc
, puc
);
1155 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1156 env
->nip
, env
->error_code
, tb
);
1158 /* we restore the process signal mask as the sigreturn should
1159 do it (XXX: use sigsetjmp) */
1160 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1162 /* never comes here */
1166 #error unsupported target CPU
1169 #if defined(__i386__)
1171 #if defined(__APPLE__)
1172 # include <sys/ucontext.h>
1174 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
1175 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
1176 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
1178 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
1179 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
1180 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
1183 #if defined(USE_CODE_COPY)
1184 static void cpu_send_trap(unsigned long pc
, int trap
,
1185 struct ucontext
*uc
)
1187 TranslationBlock
*tb
;
1190 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1191 /* now we have a real cpu fault */
1192 tb
= tb_find_pc(pc
);
1194 /* the PC is inside the translated code. It means that we have
1195 a virtual CPU fault */
1196 cpu_restore_state(tb
, env
, pc
, uc
);
1198 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
1199 raise_exception_err(trap
, env
->error_code
);
1203 int cpu_signal_handler(int host_signum
, void *pinfo
,
1206 siginfo_t
*info
= pinfo
;
1207 struct ucontext
*uc
= puc
;
1215 #define REG_TRAPNO TRAPNO
1218 trapno
= TRAP_sig(uc
);
1219 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1220 if (trapno
== 0x00 || trapno
== 0x05) {
1221 /* send division by zero or bound exception */
1222 cpu_send_trap(pc
, trapno
, uc
);
1226 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1228 (ERROR_sig(uc
) >> 1) & 1 : 0,
1229 &uc
->uc_sigmask
, puc
);
1232 #elif defined(__x86_64__)
1234 int cpu_signal_handler(int host_signum
, void *pinfo
,
1237 siginfo_t
*info
= pinfo
;
1238 struct ucontext
*uc
= puc
;
1241 pc
= uc
->uc_mcontext
.gregs
[REG_RIP
];
1242 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1243 uc
->uc_mcontext
.gregs
[REG_TRAPNO
] == 0xe ?
1244 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
1245 &uc
->uc_sigmask
, puc
);
1248 #elif defined(__powerpc__)
1250 /***********************************************************************
1251 * signal context platform-specific definitions
1255 /* All Registers access - only for local access */
1256 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1257 /* Gpr Registers access */
1258 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1259 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1260 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1261 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1262 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1263 # define LR_sig(context) REG_sig(link, context) /* Link register */
1264 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1265 /* Float Registers access */
1266 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1267 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1268 /* Exception Registers access */
1269 # define DAR_sig(context) REG_sig(dar, context)
1270 # define DSISR_sig(context) REG_sig(dsisr, context)
1271 # define TRAP_sig(context) REG_sig(trap, context)
1275 # include <sys/ucontext.h>
1276 typedef struct ucontext SIGCONTEXT
;
1277 /* All Registers access - only for local access */
1278 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1279 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1280 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1281 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1282 /* Gpr Registers access */
1283 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1284 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1285 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1286 # define CTR_sig(context) REG_sig(ctr, context)
1287 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1288 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1289 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1290 /* Float Registers access */
1291 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1292 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1293 /* Exception Registers access */
1294 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1295 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1296 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1297 #endif /* __APPLE__ */
1299 int cpu_signal_handler(int host_signum
, void *pinfo
,
1302 siginfo_t
*info
= pinfo
;
1303 struct ucontext
*uc
= puc
;
1311 if (DSISR_sig(uc
) & 0x00800000)
1314 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000))
1317 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1318 is_write
, &uc
->uc_sigmask
, puc
);
1321 #elif defined(__alpha__)
1323 int cpu_signal_handler(int host_signum
, void *pinfo
,
1326 siginfo_t
*info
= pinfo
;
1327 struct ucontext
*uc
= puc
;
1328 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
1329 uint32_t insn
= *pc
;
1332 /* XXX: need kernel patch to get write flag faster */
1333 switch (insn
>> 26) {
1348 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1349 is_write
, &uc
->uc_sigmask
, puc
);
1351 #elif defined(__sparc__)
1353 int cpu_signal_handler(int host_signum
, void *pinfo
,
1356 siginfo_t
*info
= pinfo
;
1357 uint32_t *regs
= (uint32_t *)(info
+ 1);
1358 void *sigmask
= (regs
+ 20);
1363 /* XXX: is there a standard glibc define ? */
1365 /* XXX: need kernel patch to get write flag faster */
1367 insn
= *(uint32_t *)pc
;
1368 if ((insn
>> 30) == 3) {
1369 switch((insn
>> 19) & 0x3f) {
1381 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1382 is_write
, sigmask
, NULL
);
1385 #elif defined(__arm__)
1387 int cpu_signal_handler(int host_signum
, void *pinfo
,
1390 siginfo_t
*info
= pinfo
;
1391 struct ucontext
*uc
= puc
;
1395 pc
= uc
->uc_mcontext
.gregs
[R15
];
1396 /* XXX: compute is_write */
1398 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1400 &uc
->uc_sigmask
, puc
);
1403 #elif defined(__mc68000)
1405 int cpu_signal_handler(int host_signum
, void *pinfo
,
1408 siginfo_t
*info
= pinfo
;
1409 struct ucontext
*uc
= puc
;
1413 pc
= uc
->uc_mcontext
.gregs
[16];
1414 /* XXX: compute is_write */
1416 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1418 &uc
->uc_sigmask
, puc
);
1421 #elif defined(__ia64)
1424 /* This ought to be in <bits/siginfo.h>... */
1425 # define __ISR_VALID 1
1428 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
1430 siginfo_t
*info
= pinfo
;
1431 struct ucontext
*uc
= puc
;
1435 ip
= uc
->uc_mcontext
.sc_ip
;
1436 switch (host_signum
) {
1442 if (info
->si_code
&& (info
->si_segvflags
& __ISR_VALID
))
1443 /* ISR.W (write-access) is bit 33: */
1444 is_write
= (info
->si_isr
>> 33) & 1;
1450 return handle_cpu_signal(ip
, (unsigned long)info
->si_addr
,
1452 &uc
->uc_sigmask
, puc
);
1455 #elif defined(__s390__)
1457 int cpu_signal_handler(int host_signum
, void *pinfo
,
1460 siginfo_t
*info
= pinfo
;
1461 struct ucontext
*uc
= puc
;
1465 pc
= uc
->uc_mcontext
.psw
.addr
;
1466 /* XXX: compute is_write */
1468 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1470 &uc
->uc_sigmask
, puc
);
1475 #error host CPU specific signal handler needed
1479 #endif /* !defined(CONFIG_SOFTMMU) */