cpu-exec.c

   1 /*
   2  *  emulator main execution loop
   3  *
   4  *  Copyright (c) 2003-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include "config.h"
  20 #include "cpu.h"
  21 #include "disas.h"
  22 #include "tcg.h"
  23 #include "qemu-barrier.h"
  24 #include "qtest.h"
  25
  26 int tb_invalidated_flag;
  27
  28 //#define CONFIG_DEBUG_EXEC
  29
  30 bool qemu_cpu_has_work(CPUArchState *env)
  31 {
  32     return cpu_has_work(env);
  33 }
  34
  35 void cpu_loop_exit(CPUArchState *env)
  36 {
  37     env->current_tb = NULL;
  38     longjmp(env->jmp_env, 1);
  39 }
  40
  41 /* exit the current TB from a signal handler. The host registers are
  42    restored in a state compatible with the CPU emulator
  43  */
  44 #if defined(CONFIG_SOFTMMU)
  45 void cpu_resume_from_signal(CPUArchState *env, void *puc)
  46 {
  47     /* XXX: restore cpu registers saved in host registers */
  48
  49     env->exception_index = -1;
  50     longjmp(env->jmp_env, 1);
  51 }
  52 #endif
  53
  54 /* Execute the code without caching the generated code. An interpreter
  55    could be used if available. */
  56 static void cpu_exec_nocache(CPUArchState *env, int max_cycles,
  57                              TranslationBlock *orig_tb)
  58 {
  59     tcg_target_ulong next_tb;
  60     TranslationBlock *tb;
  61
  62     /* Should never happen.
  63        We only end up here when an existing TB is too long.  */
  64     if (max_cycles > CF_COUNT_MASK)
  65         max_cycles = CF_COUNT_MASK;
  66
  67     tb = tb_gen_code(env, orig_tb->pc, orig_tb->cs_base, orig_tb->flags,
  68                      max_cycles);
  69     env->current_tb = tb;
  70     /* execute the generated code */
  71     next_tb = tcg_qemu_tb_exec(env, tb->tc_ptr);
  72     env->current_tb = NULL;
  73
  74     if ((next_tb & 3) == 2) {
  75         /* Restore PC.  This may happen if async event occurs before
  76            the TB starts executing.  */
  77         cpu_pc_from_tb(env, tb);
  78     }
  79     tb_phys_invalidate(tb, -1);
  80     tb_free(tb);
  81 }
  82
  83 static TranslationBlock *tb_find_slow(CPUArchState *env,
  84                                       target_ulong pc,
  85                                       target_ulong cs_base,
  86                                       uint64_t flags)
  87 {
  88     TranslationBlock *tb, **ptb1;
  89     unsigned int h;
  90     tb_page_addr_t phys_pc, phys_page1;
  91     target_ulong virt_page2;
  92
  93     tb_invalidated_flag = 0;
  94
  95     /* find translated block using physical mappings */
  96     phys_pc = get_page_addr_code(env, pc);
  97     phys_page1 = phys_pc & TARGET_PAGE_MASK;
  98     h = tb_phys_hash_func(phys_pc);
  99     ptb1 = &tb_phys_hash[h];
 100     for(;;) {
 101         tb = *ptb1;
 102         if (!tb)
 103             goto not_found;
 104         if (tb->pc == pc &&
 105             tb->page_addr[0] == phys_page1 &&
 106             tb->cs_base == cs_base &&
 107             tb->flags == flags) {
 108             /* check next page if needed */
 109             if (tb->page_addr[1] != -1) {
 110                 tb_page_addr_t phys_page2;
 111
 112                 virt_page2 = (pc & TARGET_PAGE_MASK) +
 113                     TARGET_PAGE_SIZE;
 114                 phys_page2 = get_page_addr_code(env, virt_page2);
 115                 if (tb->page_addr[1] == phys_page2)
 116                     goto found;
 117             } else {
 118                 goto found;
 119             }
 120         }
 121         ptb1 = &tb->phys_hash_next;
 122     }
 123  not_found:
 124    /* if no translated code available, then translate it now */
 125     tb = tb_gen_code(env, pc, cs_base, flags, 0);
 126
 127  found:
 128     /* Move the last found TB to the head of the list */
 129     if (likely(*ptb1)) {
 130         *ptb1 = tb->phys_hash_next;
 131         tb->phys_hash_next = tb_phys_hash[h];
 132         tb_phys_hash[h] = tb;
 133     }
 134     /* we add the TB in the virtual pc hash table */
 135     env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)] = tb;
 136     return tb;
 137 }
 138
 139 static inline TranslationBlock *tb_find_fast(CPUArchState *env)
 140 {
 141     TranslationBlock *tb;
 142     target_ulong cs_base, pc;
 143     int flags;
 144
 145     /* we record a subset of the CPU state. It will
 146        always be the same before a given translated block
 147        is executed. */
 148     cpu_get_tb_cpu_state(env, &pc, &cs_base, &flags);
 149     tb = env->tb_jmp_cache[tb_jmp_cache_hash_func(pc)];
 150     if (unlikely(!tb || tb->pc != pc || tb->cs_base != cs_base ||
 151                  tb->flags != flags)) {
 152         tb = tb_find_slow(env, pc, cs_base, flags);
 153     }
 154     return tb;
 155 }
 156
 157 static CPUDebugExcpHandler *debug_excp_handler;
 158
 159 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler)
 160 {
 161     CPUDebugExcpHandler *old_handler = debug_excp_handler;
 162
 163     debug_excp_handler = handler;
 164     return old_handler;
 165 }
 166
 167 static void cpu_handle_debug_exception(CPUArchState *env)
 168 {
 169     CPUWatchpoint *wp;
 170
 171     if (!env->watchpoint_hit) {
 172         QTAILQ_FOREACH(wp, &env->watchpoints, entry) {
 173             wp->flags &= ~BP_WATCHPOINT_HIT;
 174         }
 175     }
 176     if (debug_excp_handler) {
 177         debug_excp_handler(env);
 178     }
 179 }
 180
 181 /* main execution loop */
 182
 183 volatile sig_atomic_t exit_request;
 184
 185 int cpu_exec(CPUArchState *env)
 186 {
 187 #ifdef TARGET_PPC
 188     CPUState *cpu = ENV_GET_CPU(env);
 189 #endif
 190     int ret, interrupt_request;
 191     TranslationBlock *tb;
 192     uint8_t *tc_ptr;
 193     tcg_target_ulong next_tb;
 194
 195     if (env->halted) {
 196         if (!cpu_has_work(env)) {
 197             return EXCP_HALTED;
 198         }
 199
 200         env->halted = 0;
 201     }
 202
 203     cpu_single_env = env;
 204
 205     if (unlikely(exit_request)) {
 206         env->exit_request = 1;
 207     }
 208
 209 #if defined(TARGET_I386)
 210     /* put eflags in CPU temporary format */
 211     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 212     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 213     CC_OP = CC_OP_EFLAGS;
 214     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 215 #elif defined(TARGET_SPARC)
 216 #elif defined(TARGET_M68K)
 217     env->cc_op = CC_OP_FLAGS;
 218     env->cc_dest = env->sr & 0xf;
 219     env->cc_x = (env->sr >> 4) & 1;
 220 #elif defined(TARGET_ALPHA)
 221 #elif defined(TARGET_ARM)
 222 #elif defined(TARGET_UNICORE32)
 223 #elif defined(TARGET_PPC)
 224     env->reserve_addr = -1;
 225 #elif defined(TARGET_LM32)
 226 #elif defined(TARGET_MICROBLAZE)
 227 #elif defined(TARGET_MIPS)
 228 #elif defined(TARGET_SH4)
 229 #elif defined(TARGET_CRIS)
 230 #elif defined(TARGET_S390X)
 231 #elif defined(TARGET_XTENSA)
 232     /* XXXXX */
 233 #else
 234 #error unsupported target CPU
 235 #endif
 236     env->exception_index = -1;
 237
 238     /* prepare setjmp context for exception handling */
 239     for(;;) {
 240         if (setjmp(env->jmp_env) == 0) {
 241             /* if an exception is pending, we execute it here */
 242             if (env->exception_index >= 0) {
 243                 if (env->exception_index >= EXCP_INTERRUPT) {
 244                     /* exit request from the cpu execution loop */
 245                     ret = env->exception_index;
 246                     if (ret == EXCP_DEBUG) {
 247                         cpu_handle_debug_exception(env);
 248                     }
 249                     break;
 250                 } else {
 251 #if defined(CONFIG_USER_ONLY)
 252                     /* if user mode only, we simulate a fake exception
 253                        which will be handled outside the cpu execution
 254                        loop */
 255 #if defined(TARGET_I386)
 256                     do_interrupt(env);
 257 #endif
 258                     ret = env->exception_index;
 259                     break;
 260 #else
 261                     do_interrupt(env);
 262                     env->exception_index = -1;
 263 #endif
 264                 }
 265             }
 266
 267             next_tb = 0; /* force lookup of first TB */
 268             for(;;) {
 269                 interrupt_request = env->interrupt_request;
 270                 if (unlikely(interrupt_request)) {
 271                     if (unlikely(env->singlestep_enabled & SSTEP_NOIRQ)) {
 272                         /* Mask out external interrupts for this step. */
 273                         interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
 274                     }
 275                     if (interrupt_request & CPU_INTERRUPT_DEBUG) {
 276                         env->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
 277                         env->exception_index = EXCP_DEBUG;
 278                         cpu_loop_exit(env);
 279                     }
 280 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
 281     defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
 282     defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || defined(TARGET_UNICORE32)
 283                     if (interrupt_request & CPU_INTERRUPT_HALT) {
 284                         env->interrupt_request &= ~CPU_INTERRUPT_HALT;
 285                         env->halted = 1;
 286                         env->exception_index = EXCP_HLT;
 287                         cpu_loop_exit(env);
 288                     }
 289 #endif
 290 #if defined(TARGET_I386)
 291 #if !defined(CONFIG_USER_ONLY)
 292                     if (interrupt_request & CPU_INTERRUPT_POLL) {
 293                         env->interrupt_request &= ~CPU_INTERRUPT_POLL;
 294                         apic_poll_irq(env->apic_state);
 295                     }
 296 #endif
 297                     if (interrupt_request & CPU_INTERRUPT_INIT) {
 298                             cpu_svm_check_intercept_param(env, SVM_EXIT_INIT,
 299                                                           0);
 300                             do_cpu_init(x86_env_get_cpu(env));
 301                             env->exception_index = EXCP_HALTED;
 302                             cpu_loop_exit(env);
 303                     } else if (interrupt_request & CPU_INTERRUPT_SIPI) {
 304                             do_cpu_sipi(x86_env_get_cpu(env));
 305                     } else if (env->hflags2 & HF2_GIF_MASK) {
 306                         if ((interrupt_request & CPU_INTERRUPT_SMI) &&
 307                             !(env->hflags & HF_SMM_MASK)) {
 308                             cpu_svm_check_intercept_param(env, SVM_EXIT_SMI,
 309                                                           0);
 310                             env->interrupt_request &= ~CPU_INTERRUPT_SMI;
 311                             do_smm_enter(env);
 312                             next_tb = 0;
 313                         } else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
 314                                    !(env->hflags2 & HF2_NMI_MASK)) {
 315                             env->interrupt_request &= ~CPU_INTERRUPT_NMI;
 316                             env->hflags2 |= HF2_NMI_MASK;
 317                             do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
 318                             next_tb = 0;
 319                         } else if (interrupt_request & CPU_INTERRUPT_MCE) {
 320                             env->interrupt_request &= ~CPU_INTERRUPT_MCE;
 321                             do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
 322                             next_tb = 0;
 323                         } else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 324                                    (((env->hflags2 & HF2_VINTR_MASK) &&
 325                                      (env->hflags2 & HF2_HIF_MASK)) ||
 326                                     (!(env->hflags2 & HF2_VINTR_MASK) &&
 327                                      (env->eflags & IF_MASK &&
 328                                       !(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
 329                             int intno;
 330                             cpu_svm_check_intercept_param(env, SVM_EXIT_INTR,
 331                                                           0);
 332                             env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ);
 333                             intno = cpu_get_pic_interrupt(env);
 334                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno);
 335                             do_interrupt_x86_hardirq(env, intno, 1);
 336                             /* ensure that no TB jump will be modified as
 337                                the program flow was changed */
 338                             next_tb = 0;
 339 #if !defined(CONFIG_USER_ONLY)
 340                         } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) &&
 341                                    (env->eflags & IF_MASK) &&
 342                                    !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 343                             int intno;
 344                             /* FIXME: this should respect TPR */
 345                             cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR,
 346                                                           0);
 347                             intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector));
 348                             qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno);
 349                             do_interrupt_x86_hardirq(env, intno, 1);
 350                             env->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
 351                             next_tb = 0;
 352 #endif
 353                         }
 354                     }
 355 #elif defined(TARGET_PPC)
 356                     if ((interrupt_request & CPU_INTERRUPT_RESET)) {
 357                         cpu_reset(cpu);
 358                     }
 359                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 360                         ppc_hw_interrupt(env);
 361                         if (env->pending_interrupts == 0)
 362                             env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 363                         next_tb = 0;
 364                     }
 365 #elif defined(TARGET_LM32)
 366                     if ((interrupt_request & CPU_INTERRUPT_HARD)
 367                         && (env->ie & IE_IE)) {
 368                         env->exception_index = EXCP_IRQ;
 369                         do_interrupt(env);
 370                         next_tb = 0;
 371                     }
 372 #elif defined(TARGET_MICROBLAZE)
 373                     if ((interrupt_request & CPU_INTERRUPT_HARD)
 374                         && (env->sregs[SR_MSR] & MSR_IE)
 375                         && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP))
 376                         && !(env->iflags & (D_FLAG | IMM_FLAG))) {
 377                         env->exception_index = EXCP_IRQ;
 378                         do_interrupt(env);
 379                         next_tb = 0;
 380                     }
 381 #elif defined(TARGET_MIPS)
 382                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 383                         cpu_mips_hw_interrupts_pending(env)) {
 384                         /* Raise it */
 385                         env->exception_index = EXCP_EXT_INTERRUPT;
 386                         env->error_code = 0;
 387                         do_interrupt(env);
 388                         next_tb = 0;
 389                     }
 390 #elif defined(TARGET_SPARC)
 391                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 392                         if (cpu_interrupts_enabled(env) &&
 393                             env->interrupt_index > 0) {
 394                             int pil = env->interrupt_index & 0xf;
 395                             int type = env->interrupt_index & 0xf0;
 396
 397                             if (((type == TT_EXTINT) &&
 398                                   cpu_pil_allowed(env, pil)) ||
 399                                   type != TT_EXTINT) {
 400                                 env->exception_index = env->interrupt_index;
 401                                 do_interrupt(env);
 402                                 next_tb = 0;
 403                             }
 404                         }
 405                     }
 406 #elif defined(TARGET_ARM)
 407                     if (interrupt_request & CPU_INTERRUPT_FIQ
 408                         && !(env->uncached_cpsr & CPSR_F)) {
 409                         env->exception_index = EXCP_FIQ;
 410                         do_interrupt(env);
 411                         next_tb = 0;
 412                     }
 413                     /* ARMv7-M interrupt return works by loading a magic value
 414                        into the PC.  On real hardware the load causes the
 415                        return to occur.  The qemu implementation performs the
 416                        jump normally, then does the exception return when the
 417                        CPU tries to execute code at the magic address.
 418                        This will cause the magic PC value to be pushed to
 419                        the stack if an interrupt occurred at the wrong time.
 420                        We avoid this by disabling interrupts when
 421                        pc contains a magic address.  */
 422                     if (interrupt_request & CPU_INTERRUPT_HARD
 423                         && ((IS_M(env) && env->regs[15] < 0xfffffff0)
 424                             || !(env->uncached_cpsr & CPSR_I))) {
 425                         env->exception_index = EXCP_IRQ;
 426                         do_interrupt(env);
 427                         next_tb = 0;
 428                     }
 429 #elif defined(TARGET_UNICORE32)
 430                     if (interrupt_request & CPU_INTERRUPT_HARD
 431                         && !(env->uncached_asr & ASR_I)) {
 432                         do_interrupt(env);
 433                         next_tb = 0;
 434                     }
 435 #elif defined(TARGET_SH4)
 436                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 437                         do_interrupt(env);
 438                         next_tb = 0;
 439                     }
 440 #elif defined(TARGET_ALPHA)
 441                     {
 442                         int idx = -1;
 443                         /* ??? This hard-codes the OSF/1 interrupt levels.  */
 444                         switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) {
 445                         case 0 ... 3:
 446                             if (interrupt_request & CPU_INTERRUPT_HARD) {
 447                                 idx = EXCP_DEV_INTERRUPT;
 448                             }
 449                             /* FALLTHRU */
 450                         case 4:
 451                             if (interrupt_request & CPU_INTERRUPT_TIMER) {
 452                                 idx = EXCP_CLK_INTERRUPT;
 453                             }
 454                             /* FALLTHRU */
 455                         case 5:
 456                             if (interrupt_request & CPU_INTERRUPT_SMP) {
 457                                 idx = EXCP_SMP_INTERRUPT;
 458                             }
 459                             /* FALLTHRU */
 460                         case 6:
 461                             if (interrupt_request & CPU_INTERRUPT_MCHK) {
 462                                 idx = EXCP_MCHK;
 463                             }
 464                         }
 465                         if (idx >= 0) {
 466                             env->exception_index = idx;
 467                             env->error_code = 0;
 468                             do_interrupt(env);
 469                             next_tb = 0;
 470                         }
 471                     }
 472 #elif defined(TARGET_CRIS)
 473                     if (interrupt_request & CPU_INTERRUPT_HARD
 474                         && (env->pregs[PR_CCS] & I_FLAG)
 475                         && !env->locked_irq) {
 476                         env->exception_index = EXCP_IRQ;
 477                         do_interrupt(env);
 478                         next_tb = 0;
 479                     }
 480                     if (interrupt_request & CPU_INTERRUPT_NMI) {
 481                         unsigned int m_flag_archval;
 482                         if (env->pregs[PR_VR] < 32) {
 483                             m_flag_archval = M_FLAG_V10;
 484                         } else {
 485                             m_flag_archval = M_FLAG_V32;
 486                         }
 487                         if ((env->pregs[PR_CCS] & m_flag_archval)) {
 488                             env->exception_index = EXCP_NMI;
 489                             do_interrupt(env);
 490                             next_tb = 0;
 491                         }
 492                     }
 493 #elif defined(TARGET_M68K)
 494                     if (interrupt_request & CPU_INTERRUPT_HARD
 495                         && ((env->sr & SR_I) >> SR_I_SHIFT)
 496                             < env->pending_level) {
 497                         /* Real hardware gets the interrupt vector via an
 498                            IACK cycle at this point.  Current emulated
 499                            hardware doesn't rely on this, so we
 500                            provide/save the vector when the interrupt is
 501                            first signalled.  */
 502                         env->exception_index = env->pending_vector;
 503                         do_interrupt_m68k_hardirq(env);
 504                         next_tb = 0;
 505                     }
 506 #elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY)
 507                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 508                         (env->psw.mask & PSW_MASK_EXT)) {
 509                         do_interrupt(env);
 510                         next_tb = 0;
 511                     }
 512 #elif defined(TARGET_XTENSA)
 513                     if (interrupt_request & CPU_INTERRUPT_HARD) {
 514                         env->exception_index = EXC_IRQ;
 515                         do_interrupt(env);
 516                         next_tb = 0;
 517                     }
 518 #endif
 519                    /* Don't use the cached interrupt_request value,
 520                       do_interrupt may have updated the EXITTB flag. */
 521                     if (env->interrupt_request & CPU_INTERRUPT_EXITTB) {
 522                         env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
 523                         /* ensure that no TB jump will be modified as
 524                            the program flow was changed */
 525                         next_tb = 0;
 526                     }
 527                 }
 528                 if (unlikely(env->exit_request)) {
 529                     env->exit_request = 0;
 530                     env->exception_index = EXCP_INTERRUPT;
 531                     cpu_loop_exit(env);
 532                 }
 533 #if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
 534                 if (qemu_loglevel_mask(CPU_LOG_TB_CPU)) {
 535                     /* restore flags in standard format */
 536 #if defined(TARGET_I386)
 537                     env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
 538                         | (DF & DF_MASK);
 539                     log_cpu_state(env, X86_DUMP_CCOP);
 540                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 541 #elif defined(TARGET_M68K)
 542                     cpu_m68k_flush_flags(env, env->cc_op);
 543                     env->cc_op = CC_OP_FLAGS;
 544                     env->sr = (env->sr & 0xffe0)
 545                               | env->cc_dest | (env->cc_x << 4);
 546                     log_cpu_state(env, 0);
 547 #else
 548                     log_cpu_state(env, 0);
 549 #endif
 550                 }
 551 #endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
 552                 spin_lock(&tb_lock);
 553                 tb = tb_find_fast(env);
 554                 /* Note: we do it here to avoid a gcc bug on Mac OS X when
 555                    doing it in tb_find_slow */
 556                 if (tb_invalidated_flag) {
 557                     /* as some TB could have been invalidated because
 558                        of memory exceptions while generating the code, we
 559                        must recompute the hash index here */
 560                     next_tb = 0;
 561                     tb_invalidated_flag = 0;
 562                 }
 563 #ifdef CONFIG_DEBUG_EXEC
 564                 qemu_log_mask(CPU_LOG_EXEC, "Trace %p [" TARGET_FMT_lx "] %s\n",
 565                              tb->tc_ptr, tb->pc,
 566                              lookup_symbol(tb->pc));
 567 #endif
 568                 /* see if we can patch the calling TB. When the TB
 569                    spans two pages, we cannot safely do a direct
 570                    jump. */
 571                 if (next_tb != 0 && tb->page_addr[1] == -1) {
 572                     tb_add_jump((TranslationBlock *)(next_tb & ~3), next_tb & 3, tb);
 573                 }
 574                 spin_unlock(&tb_lock);
 575
 576                 /* cpu_interrupt might be called while translating the
 577                    TB, but before it is linked into a potentially
 578                    infinite loop and becomes env->current_tb. Avoid
 579                    starting execution if there is a pending interrupt. */
 580                 env->current_tb = tb;
 581                 barrier();
 582                 if (likely(!env->exit_request)) {
 583                     tc_ptr = tb->tc_ptr;
 584                     /* execute the generated code */
 585                     next_tb = tcg_qemu_tb_exec(env, tc_ptr);
 586                     if ((next_tb & 3) == 2) {
 587                         /* Instruction counter expired.  */
 588                         int insns_left;
 589                         tb = (TranslationBlock *)(next_tb & ~3);
 590                         /* Restore PC.  */
 591                         cpu_pc_from_tb(env, tb);
 592                         insns_left = env->icount_decr.u32;
 593                         if (env->icount_extra && insns_left >= 0) {
 594                             /* Refill decrementer and continue execution.  */
 595                             env->icount_extra += insns_left;
 596                             if (env->icount_extra > 0xffff) {
 597                                 insns_left = 0xffff;
 598                             } else {
 599                                 insns_left = env->icount_extra;
 600                             }
 601                             env->icount_extra -= insns_left;
 602                             env->icount_decr.u16.low = insns_left;
 603                         } else {
 604                             if (insns_left > 0) {
 605                                 /* Execute remaining instructions.  */
 606                                 cpu_exec_nocache(env, insns_left, tb);
 607                             }
 608                             env->exception_index = EXCP_INTERRUPT;
 609                             next_tb = 0;
 610                             cpu_loop_exit(env);
 611                         }
 612                     }
 613                 }
 614                 env->current_tb = NULL;
 615                 /* reset soft MMU for next block (it can currently
 616                    only be set by a memory fault) */
 617             } /* for(;;) */
 618         } else {
 619             /* Reload env after longjmp - the compiler may have smashed all
 620              * local variables as longjmp is marked 'noreturn'. */
 621             env = cpu_single_env;
 622         }
 623     } /* for(;;) */
 624
 625
 626 #if defined(TARGET_I386)
 627     /* restore flags in standard format */
 628     env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP)
 629         | (DF & DF_MASK);
 630 #elif defined(TARGET_ARM)
 631     /* XXX: Save/restore host fpu exception state?.  */
 632 #elif defined(TARGET_UNICORE32)
 633 #elif defined(TARGET_SPARC)
 634 #elif defined(TARGET_PPC)
 635 #elif defined(TARGET_LM32)
 636 #elif defined(TARGET_M68K)
 637     cpu_m68k_flush_flags(env, env->cc_op);
 638     env->cc_op = CC_OP_FLAGS;
 639     env->sr = (env->sr & 0xffe0)
 640               | env->cc_dest | (env->cc_x << 4);
 641 #elif defined(TARGET_MICROBLAZE)
 642 #elif defined(TARGET_MIPS)
 643 #elif defined(TARGET_SH4)
 644 #elif defined(TARGET_ALPHA)
 645 #elif defined(TARGET_CRIS)
 646 #elif defined(TARGET_S390X)
 647 #elif defined(TARGET_XTENSA)
 648     /* XXXXX */
 649 #else
 650 #error unsupported target CPU
 651 #endif
 652
 653     /* fail safe : never use cpu_single_env outside cpu_exec() */
 654     cpu_single_env = NULL;
 655     return ret;
 656 }