cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #include "exec.h"
  22 #include "disas.h"
  23
  24 int tb_invalidated_flag;
  25
  26 //#define DEBUG_EXEC
  27 //#define DEBUG_SIGNAL
  28
  29 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
  30 /* XXX: unify with i386 target */
  31 void cpu_loop_exit(void)
  32 {
  33     longjmp(env->jmp_env, 1);
  34 }
  35 #endif
  36
  37 /* main execution loop */
  38
  39 int cpu_exec(CPUState *env1)
  40 {
  41     int saved_T0, saved_T1, saved_T2;
  42     CPUState *saved_env;
  43 #ifdef reg_EAX
  44     int saved_EAX;
  45 #endif
  46 #ifdef reg_ECX
  47     int saved_ECX;
  48 #endif
  49 #ifdef reg_EDX
  50     int saved_EDX;
  51 #endif
  52 #ifdef reg_EBX
  53     int saved_EBX;
  54 #endif
  55 #ifdef reg_ESP
  56     int saved_ESP;
  57 #endif
  58 #ifdef reg_EBP
  59     int saved_EBP;
  60 #endif
  61 #ifdef reg_ESI
  62     int saved_ESI;
  63 #endif
  64 #ifdef reg_EDI
  65     int saved_EDI;
  66 #endif
  67 #ifdef __sparc__
  68     int saved_i7, tmp_T0;
  69 #endif
  70     int code_gen_size, ret, interrupt_request;
  71     void (*gen_func)(void);
  72     TranslationBlock *tb, **ptb;
  73     uint8_t *tc_ptr, *cs_base, *pc;
  74     unsigned int flags;
  75
  76     /* first we save global registers */
  77     saved_T0 = T0;
  78     saved_T1 = T1;
  79     saved_T2 = T2;
  80     saved_env = env;
  81     env = env1;
  82 #ifdef __sparc__
  83     /* we also save i7 because longjmp may not restore it */
  84     asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
  85 #endif
  86
  87 #if defined(TARGET_I386)
  88 #ifdef reg_EAX
  89     saved_EAX = EAX;
  90     EAX = env->regs[R_EAX];
  91 #endif
  92 #ifdef reg_ECX
  93     saved_ECX = ECX;
  94     ECX = env->regs[R_ECX];
  95 #endif
  96 #ifdef reg_EDX
  97     saved_EDX = EDX;
  98     EDX = env->regs[R_EDX];
  99 #endif
 100 #ifdef reg_EBX
 101     saved_EBX = EBX;
 102     EBX = env->regs[R_EBX];
 103 #endif
 104 #ifdef reg_ESP
 105     saved_ESP = ESP;
 106     ESP = env->regs[R_ESP];
 107 #endif
 108 #ifdef reg_EBP
 109     saved_EBP = EBP;
 110     EBP = env->regs[R_EBP];
 111 #endif
 112 #ifdef reg_ESI
 113     saved_ESI = ESI;
 114     ESI = env->regs[R_ESI];
 115 #endif
 116 #ifdef reg_EDI
 117     saved_EDI = EDI;
 118     EDI = env->regs[R_EDI];
 119 #endif
 120
 121     /* put eflags in CPU temporary format */
 122     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 123     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 124     CC_OP = CC_OP_EFLAGS;
 125     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 126 #elif defined(TARGET_ARM)
 127     {
 128         unsigned int psr;
 129         psr = env->cpsr;
 130         env->CF = (psr >> 29) & 1;
 131         env->NZF = (psr & 0xc0000000) ^ 0x40000000;
 132         env->VF = (psr << 3) & 0x80000000;
 133         env->cpsr = psr & ~0xf0000000;
 134     }
 135 #elif defined(TARGET_SPARC)
 136 #else
 137 #error unsupported target CPU
 138 #endif
 139     env->exception_index = -1;
 140
 141     /* prepare setjmp context for exception handling */
 142     for(;;) {
 143         if (setjmp(env->jmp_env) == 0) {
 144             /* if an exception is pending, we execute it here */
 145             if (env->exception_index >= 0) {
 146                 if (env->exception_index >= EXCP_INTERRUPT) {
 147                     /* exit request from the cpu execution loop */
 148                     ret = env->exception_index;
 149                     break;
 150                 } else if (env->user_mode_only) {
 151                     /* if user mode only, we simulate a fake exception
 152                        which will be hanlded outside the cpu execution
 153                        loop */
 154 #if defined(TARGET_I386)
 155                     do_interrupt_user(env->exception_index,
 156                                       env->exception_is_int,
 157                                       env->error_code,
 158                                       env->exception_next_eip);
 159 #endif
 160                     ret = env->exception_index;
 161                     break;
 162                 } else {
 163 #if defined(TARGET_I386)
 164                     /* simulate a real cpu exception. On i386, it can
 165                        trigger new exceptions, but we do not handle
 166                        double or triple faults yet. */
 167                     do_interrupt(env->exception_index,
 168                                  env->exception_is_int,
 169                                  env->error_code,
 170                                  env->exception_next_eip, 0);
 171 #endif
 172                 }
 173                 env->exception_index = -1;
 174             }
 175             T0 = 0; /* force lookup of first TB */
 176             for(;;) {
 177 #ifdef __sparc__
 178                 /* g1 can be modified by some libc? functions */
 179                 tmp_T0 = T0;
 180 #endif
 181                 interrupt_request = env->interrupt_request;
 182                 if (__builtin_expect(interrupt_request, 0)) {
 183 #if defined(TARGET_I386)
 184                     /* if hardware interrupt pending, we execute it */
 185                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 186                         (env->eflags & IF_MASK) &&
 187                         !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
 188                         int intno;
 189                         intno = cpu_x86_get_pic_interrupt(env);
 190                         if (loglevel) {
 191                             fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
 192                         }
 193                         do_interrupt(intno, 0, 0, 0, 1);
 194                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 195                         /* ensure that no TB jump will be modified as
 196                            the program flow was changed */
 197 #ifdef __sparc__
 198                         tmp_T0 = 0;
 199 #else
 200                         T0 = 0;
 201 #endif
 202                     }
 203 #endif
 204                     if (interrupt_request & CPU_INTERRUPT_EXIT) {
 205                         env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
 206                         env->exception_index = EXCP_INTERRUPT;
 207                         cpu_loop_exit();
 208                     }
 209                 }
 210 #ifdef DEBUG_EXEC
 211                 if (loglevel) {
 212 #if defined(TARGET_I386)
 213                     /* restore flags in standard format */
 214                     env->regs[R_EAX] = EAX;
 215                     env->regs[R_EBX] = EBX;
 216                     env->regs[R_ECX] = ECX;
 217                     env->regs[R_EDX] = EDX;
 218                     env->regs[R_ESI] = ESI;
 219                     env->regs[R_EDI] = EDI;
 220                     env->regs[R_EBP] = EBP;
 221                     env->regs[R_ESP] = ESP;
 222                     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 223                     cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
 224                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 225 #elif defined(TARGET_ARM)
 226                     env->cpsr = compute_cpsr();
 227                     cpu_arm_dump_state(env, logfile, 0);
 228                     env->cpsr &= ~0xf0000000;
 229 #elif defined(TARGET_SPARC)
 230                     cpu_sparc_dump_state (env, logfile, 0);
 231 #else
 232 #error unsupported target CPU
 233 #endif
 234                 }
 235 #endif
 236                 /* we record a subset of the CPU state. It will
 237                    always be the same before a given translated block
 238                    is executed. */
 239 #if defined(TARGET_I386)
 240                 flags = env->hflags;
 241                 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
 242                 cs_base = env->segs[R_CS].base;
 243                 pc = cs_base + env->eip;
 244 #elif defined(TARGET_ARM)
 245                 flags = 0;
 246                 cs_base = 0;
 247                 pc = (uint8_t *)env->regs[15];
 248 #elif defined(TARGET_SPARC)
 249                                 flags = 0;
 250                                 cs_base = 0;
 251                                 if (env->npc) {
 252                                         env->pc = env->npc;
 253                                         env->npc = 0;
 254                                 }
 255                                 pc = (uint8_t *) env->pc;
 256 #else
 257 #error unsupported CPU
 258 #endif
 259                 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
 260                              flags);
 261                 if (!tb) {
 262                     spin_lock(&tb_lock);
 263                     /* if no translated code available, then translate it now */
 264                     tb = tb_alloc((unsigned long)pc);
 265                     if (!tb) {
 266                         /* flush must be done */
 267                         tb_flush();
 268                         /* cannot fail at this point */
 269                         tb = tb_alloc((unsigned long)pc);
 270                         /* don't forget to invalidate previous TB info */
 271                         ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 272                         T0 = 0;
 273                     }
 274                     tc_ptr = code_gen_ptr;
 275                     tb->tc_ptr = tc_ptr;
 276                     tb->cs_base = (unsigned long)cs_base;
 277                     tb->flags = flags;
 278                     tb_invalidated_flag = 0;
 279                     cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
 280                     if (tb_invalidated_flag) {
 281                         /* as some TB could have been invalidated because
 282                            of memory exceptions while generating the code, we
 283                            must recompute the hash index here */
 284                         ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 285                         while (*ptb != NULL)
 286                             ptb = &(*ptb)->hash_next;
 287                         T0 = 0;
 288                     }
 289                     *ptb = tb;
 290                     tb->hash_next = NULL;
 291                     tb_link(tb);
 292                     code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
 293                     spin_unlock(&tb_lock);
 294                 }
 295 #ifdef DEBUG_EXEC
 296                 if (loglevel) {
 297                     fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
 298                             (long)tb->tc_ptr, (long)tb->pc,
 299                             lookup_symbol((void *)tb->pc));
 300                 }
 301 #endif
 302 #ifdef __sparc__
 303                 T0 = tmp_T0;
 304 #endif
 305                 /* see if we can patch the calling TB. */
 306                 if (T0 != 0) {
 307                     spin_lock(&tb_lock);
 308                     tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
 309                     spin_unlock(&tb_lock);
 310                 }
 311                 tc_ptr = tb->tc_ptr;
 312                 env->current_tb = tb;
 313                 /* execute the generated code */
 314                 gen_func = (void *)tc_ptr;
 315 #if defined(__sparc__)
 316                 __asm__ __volatile__("call      %0\n\t"
 317                                      "mov       %%o7,%%i0"
 318                                      : /* no outputs */
 319                                      : "r" (gen_func)
 320                                      : "i0", "i1", "i2", "i3", "i4", "i5");
 321 #elif defined(__arm__)
 322                 asm volatile ("mov pc, %0\n\t"
 323                               ".global exec_loop\n\t"
 324                               "exec_loop:\n\t"
 325                               : /* no outputs */
 326                               : "r" (gen_func)
 327                               : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
 328 #else
 329                 gen_func();
 330 #endif
 331                 env->current_tb = NULL;
 332                 /* reset soft MMU for next block (it can currently
 333                    only be set by a memory fault) */
 334 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
 335                 if (env->hflags & HF_SOFTMMU_MASK) {
 336                     env->hflags &= ~HF_SOFTMMU_MASK;
 337                     /* do not allow linking to another block */
 338                     T0 = 0;
 339                 }
 340 #endif
 341             }
 342         } else {
 343         }
 344     } /* for(;;) */
 345
 346
 347 #if defined(TARGET_I386)
 348     /* restore flags in standard format */
 349     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 350
 351     /* restore global registers */
 352 #ifdef reg_EAX
 353     EAX = saved_EAX;
 354 #endif
 355 #ifdef reg_ECX
 356     ECX = saved_ECX;
 357 #endif
 358 #ifdef reg_EDX
 359     EDX = saved_EDX;
 360 #endif
 361 #ifdef reg_EBX
 362     EBX = saved_EBX;
 363 #endif
 364 #ifdef reg_ESP
 365     ESP = saved_ESP;
 366 #endif
 367 #ifdef reg_EBP
 368     EBP = saved_EBP;
 369 #endif
 370 #ifdef reg_ESI
 371     ESI = saved_ESI;
 372 #endif
 373 #ifdef reg_EDI
 374     EDI = saved_EDI;
 375 #endif
 376 #elif defined(TARGET_ARM)
 377     env->cpsr = compute_cpsr();
 378 #elif defined(TARGET_SPARC)
 379 #else
 380 #error unsupported target CPU
 381 #endif
 382 #ifdef __sparc__
 383     asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
 384 #endif
 385     T0 = saved_T0;
 386     T1 = saved_T1;
 387     T2 = saved_T2;
 388     env = saved_env;
 389     return ret;
 390 }
 391
 392 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
 393
 394 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 395 {
 396     CPUX86State *saved_env;
 397
 398     saved_env = env;
 399     env = s;
 400     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 401         selector &= 0xffff;
 402         cpu_x86_load_seg_cache(env, seg_reg, selector,
 403                                (uint8_t *)(selector << 4), 0xffff, 0);
 404     } else {
 405         load_seg(seg_reg, selector, 0);
 406     }
 407     env = saved_env;
 408 }
 409
 410 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
 411 {
 412     CPUX86State *saved_env;
 413
 414     saved_env = env;
 415     env = s;
 416
 417     helper_fsave(ptr, data32);
 418
 419     env = saved_env;
 420 }
 421
 422 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
 423 {
 424     CPUX86State *saved_env;
 425
 426     saved_env = env;
 427     env = s;
 428
 429     helper_frstor(ptr, data32);
 430
 431     env = saved_env;
 432 }
 433
 434 #endif /* TARGET_I386 */
 435
 436 #undef EAX
 437 #undef ECX
 438 #undef EDX
 439 #undef EBX
 440 #undef ESP
 441 #undef EBP
 442 #undef ESI
 443 #undef EDI
 444 #undef EIP
 445 #include <signal.h>
 446 #include <sys/ucontext.h>
 447
 448 #if defined(TARGET_I386)
 449
 450 /* 'pc' is the host PC at which the exception was raised. 'address' is
 451    the effective address of the memory exception. 'is_write' is 1 if a
 452    write caused the exception and otherwise 0'. 'old_set' is the
 453    signal set which should be restored */
 454 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 455                                     int is_write, sigset_t *old_set)
 456 {
 457     TranslationBlock *tb;
 458     int ret;
 459
 460     if (cpu_single_env)
 461         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 462 #if defined(DEBUG_SIGNAL)
 463     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 464            pc, address, is_write, *(unsigned long *)old_set);
 465 #endif
 466     /* XXX: locking issue */
 467     if (is_write && page_unprotect(address)) {
 468         return 1;
 469     }
 470     /* see if it is an MMU fault */
 471     ret = cpu_x86_handle_mmu_fault(env, address, is_write,
 472                                    ((env->hflags & HF_CPL_MASK) == 3), 0);
 473     if (ret < 0)
 474         return 0; /* not an MMU fault */
 475     if (ret == 0)
 476         return 1; /* the MMU fault was handled without causing real CPU fault */
 477     /* now we have a real cpu fault */
 478     tb = tb_find_pc(pc);
 479     if (tb) {
 480         /* the PC is inside the translated code. It means that we have
 481            a virtual CPU fault */
 482         cpu_restore_state(tb, env, pc);
 483     }
 484     if (ret == 1) {
 485 #if 0
 486         printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
 487                env->eip, env->cr[2], env->error_code);
 488 #endif
 489         /* we restore the process signal mask as the sigreturn should
 490            do it (XXX: use sigsetjmp) */
 491         sigprocmask(SIG_SETMASK, old_set, NULL);
 492         raise_exception_err(EXCP0E_PAGE, env->error_code);
 493     } else {
 494         /* activate soft MMU for this block */
 495         env->hflags |= HF_SOFTMMU_MASK;
 496         sigprocmask(SIG_SETMASK, old_set, NULL);
 497         cpu_loop_exit();
 498     }
 499     /* never comes here */
 500     return 1;
 501 }
 502
 503 #elif defined(TARGET_ARM)
 504 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 505                                     int is_write, sigset_t *old_set)
 506 {
 507     /* XXX: do more */
 508     return 0;
 509 }
 510 #elif defined(TARGET_SPARC)
 511 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 512                                     int is_write, sigset_t *old_set)
 513 {
 514         return 0;
 515 }
 516 #else
 517 #error unsupported target CPU
 518 #endif
 519
 520 #if defined(__i386__)
 521
 522 int cpu_signal_handler(int host_signum, struct siginfo *info,
 523                        void *puc)
 524 {
 525     struct ucontext *uc = puc;
 526     unsigned long pc;
 527
 528 #ifndef REG_EIP
 529 /* for glibc 2.1 */
 530 #define REG_EIP    EIP
 531 #define REG_ERR    ERR
 532 #define REG_TRAPNO TRAPNO
 533 #endif
 534     pc = uc->uc_mcontext.gregs[REG_EIP];
 535     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 536                              uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
 537                              (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 538                              &uc->uc_sigmask);
 539 }
 540
 541 #elif defined(__powerpc)
 542
 543 int cpu_signal_handler(int host_signum, struct siginfo *info,
 544                        void *puc)
 545 {
 546     struct ucontext *uc = puc;
 547     struct pt_regs *regs = uc->uc_mcontext.regs;
 548     unsigned long pc;
 549     int is_write;
 550
 551     pc = regs->nip;
 552     is_write = 0;
 553 #if 0
 554     /* ppc 4xx case */
 555     if (regs->dsisr & 0x00800000)
 556         is_write = 1;
 557 #else
 558     if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
 559         is_write = 1;
 560 #endif
 561     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 562                              is_write, &uc->uc_sigmask);
 563 }
 564
 565 #elif defined(__alpha__)
 566
 567 int cpu_signal_handler(int host_signum, struct siginfo *info,
 568                            void *puc)
 569 {
 570     struct ucontext *uc = puc;
 571     uint32_t *pc = uc->uc_mcontext.sc_pc;
 572     uint32_t insn = *pc;
 573     int is_write = 0;
 574
 575     /* XXX: need kernel patch to get write flag faster */
 576     switch (insn >> 26) {
 577     case 0x0d: // stw
 578     case 0x0e: // stb
 579     case 0x0f: // stq_u
 580     case 0x24: // stf
 581     case 0x25: // stg
 582     case 0x26: // sts
 583     case 0x27: // stt
 584     case 0x2c: // stl
 585     case 0x2d: // stq
 586     case 0x2e: // stl_c
 587     case 0x2f: // stq_c
 588         is_write = 1;
 589     }
 590
 591     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 592                              is_write, &uc->uc_sigmask);
 593 }
 594 #elif defined(__sparc__)
 595
 596 int cpu_signal_handler(int host_signum, struct siginfo *info,
 597                        void *puc)
 598 {
 599     uint32_t *regs = (uint32_t *)(info + 1);
 600     void *sigmask = (regs + 20);
 601     unsigned long pc;
 602     int is_write;
 603     uint32_t insn;
 604
 605     /* XXX: is there a standard glibc define ? */
 606     pc = regs[1];
 607     /* XXX: need kernel patch to get write flag faster */
 608     is_write = 0;
 609     insn = *(uint32_t *)pc;
 610     if ((insn >> 30) == 3) {
 611       switch((insn >> 19) & 0x3f) {
 612       case 0x05: // stb
 613       case 0x06: // sth
 614       case 0x04: // st
 615       case 0x07: // std
 616       case 0x24: // stf
 617       case 0x27: // stdf
 618       case 0x25: // stfsr
 619         is_write = 1;
 620         break;
 621       }
 622     }
 623     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 624                              is_write, sigmask);
 625 }
 626
 627 #elif defined(__arm__)
 628
 629 int cpu_signal_handler(int host_signum, struct siginfo *info,
 630                        void *puc)
 631 {
 632     struct ucontext *uc = puc;
 633     unsigned long pc;
 634     int is_write;
 635
 636     pc = uc->uc_mcontext.gregs[R15];
 637     /* XXX: compute is_write */
 638     is_write = 0;
 639     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 640                              is_write,
 641                              &uc->uc_sigmask);
 642 }
 643
 644 #elif defined(__mc68000)
 645
 646 int cpu_signal_handler(int host_signum, struct siginfo *info,
 647                        void *puc)
 648 {
 649     struct ucontext *uc = puc;
 650     unsigned long pc;
 651     int is_write;
 652
 653     pc = uc->uc_mcontext.gregs[16];
 654     /* XXX: compute is_write */
 655     is_write = 0;
 656     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 657                              is_write,
 658                              &uc->uc_sigmask);
 659 }
 660
 661 #else
 662
 663 #error host CPU specific signal handler needed
 664
 665 #endif