]>
git.proxmox.com Git - qemu.git/blob - cpu-exec.c
2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
24 #if !defined(CONFIG_SOFTMMU)
35 #include <sys/ucontext.h>
38 int tb_invalidated_flag
;
41 //#define DEBUG_SIGNAL
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
47 longjmp(env
->jmp_env
, 1);
50 #if !(defined(TARGET_SPARC) || defined(TARGET_SH4))
54 /* exit the current TB from a signal handler. The host registers are
55 restored in a state compatible with the CPU emulator
57 void cpu_resume_from_signal(CPUState
*env1
, void *puc
)
59 #if !defined(CONFIG_SOFTMMU)
60 struct ucontext
*uc
= puc
;
65 /* XXX: restore cpu registers saved in host registers */
67 #if !defined(CONFIG_SOFTMMU)
69 /* XXX: use siglongjmp ? */
70 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
73 longjmp(env
->jmp_env
, 1);
77 static TranslationBlock
*tb_find_slow(target_ulong pc
,
81 TranslationBlock
*tb
, **ptb1
;
84 target_ulong phys_pc
, phys_page1
, phys_page2
, virt_page2
;
89 tb_invalidated_flag
= 0;
91 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
93 /* find translated block using physical mappings */
94 phys_pc
= get_phys_addr_code(env
, pc
);
95 phys_page1
= phys_pc
& TARGET_PAGE_MASK
;
97 h
= tb_phys_hash_func(phys_pc
);
98 ptb1
= &tb_phys_hash
[h
];
104 tb
->page_addr
[0] == phys_page1
&&
105 tb
->cs_base
== cs_base
&&
106 tb
->flags
== flags
) {
107 /* check next page if needed */
108 if (tb
->page_addr
[1] != -1) {
109 virt_page2
= (pc
& TARGET_PAGE_MASK
) +
111 phys_page2
= get_phys_addr_code(env
, virt_page2
);
112 if (tb
->page_addr
[1] == phys_page2
)
118 ptb1
= &tb
->phys_hash_next
;
121 /* if no translated code available, then translate it now */
124 /* flush must be done */
126 /* cannot fail at this point */
128 /* don't forget to invalidate previous TB info */
129 tb_invalidated_flag
= 1;
131 tc_ptr
= code_gen_ptr
;
133 tb
->cs_base
= cs_base
;
135 cpu_gen_code(env
, tb
, CODE_GEN_MAX_SIZE
, &code_gen_size
);
136 code_gen_ptr
= (void *)(((unsigned long)code_gen_ptr
+ code_gen_size
+ CODE_GEN_ALIGN
- 1) & ~(CODE_GEN_ALIGN
- 1));
138 /* check next page if needed */
139 virt_page2
= (pc
+ tb
->size
- 1) & TARGET_PAGE_MASK
;
141 if ((pc
& TARGET_PAGE_MASK
) != virt_page2
) {
142 phys_page2
= get_phys_addr_code(env
, virt_page2
);
144 tb_link_phys(tb
, phys_pc
, phys_page2
);
147 /* we add the TB in the virtual pc hash table */
148 env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)] = tb
;
149 spin_unlock(&tb_lock
);
153 static inline TranslationBlock
*tb_find_fast(void)
155 TranslationBlock
*tb
;
156 target_ulong cs_base
, pc
;
159 /* we record a subset of the CPU state. It will
160 always be the same before a given translated block
162 #if defined(TARGET_I386)
164 flags
|= (env
->eflags
& (IOPL_MASK
| TF_MASK
| VM_MASK
));
165 cs_base
= env
->segs
[R_CS
].base
;
166 pc
= cs_base
+ env
->eip
;
167 #elif defined(TARGET_ARM)
168 flags
= env
->thumb
| (env
->vfp
.vec_len
<< 1)
169 | (env
->vfp
.vec_stride
<< 4);
170 if ((env
->uncached_cpsr
& CPSR_M
) != ARM_CPU_MODE_USR
)
172 if (env
->vfp
.xregs
[ARM_VFP_FPEXC
] & (1 << 30))
176 #elif defined(TARGET_SPARC)
177 #ifdef TARGET_SPARC64
178 // Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
179 flags
= (((env
->pstate
& PS_PEF
) >> 1) | ((env
->fprs
& FPRS_FEF
) << 2))
180 | (env
->pstate
& PS_PRIV
) | ((env
->lsu
& (DMMU_E
| IMMU_E
)) >> 2);
182 // FPU enable . MMU enabled . MMU no-fault . Supervisor
183 flags
= (env
->psref
<< 3) | ((env
->mmuregs
[0] & (MMU_E
| MMU_NF
)) << 1)
188 #elif defined(TARGET_PPC)
189 flags
= (msr_pr
<< MSR_PR
) | (msr_fp
<< MSR_FP
) |
190 (msr_se
<< MSR_SE
) | (msr_le
<< MSR_LE
);
193 #elif defined(TARGET_MIPS)
194 flags
= env
->hflags
& (MIPS_HFLAG_TMASK
| MIPS_HFLAG_BMASK
);
197 #elif defined(TARGET_SH4)
198 flags
= env
->sr
& (SR_MD
| SR_RB
);
199 cs_base
= 0; /* XXXXX */
202 #error unsupported CPU
204 tb
= env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)];
205 if (__builtin_expect(!tb
|| tb
->pc
!= pc
|| tb
->cs_base
!= cs_base
||
206 tb
->flags
!= flags
, 0)) {
207 tb
= tb_find_slow(pc
, cs_base
, flags
);
208 /* Note: we do it here to avoid a gcc bug on Mac OS X when
209 doing it in tb_find_slow */
210 if (tb_invalidated_flag
) {
211 /* as some TB could have been invalidated because
212 of memory exceptions while generating the code, we
213 must recompute the hash index here */
221 /* main execution loop */
223 int cpu_exec(CPUState
*env1
)
225 int saved_T0
, saved_T1
;
230 #if defined(TARGET_I386)
255 #elif defined(TARGET_SPARC)
256 #if defined(reg_REGWPTR)
257 uint32_t *saved_regwptr
;
260 #if defined(__sparc__) && !defined(HOST_SOLARIS)
261 int saved_i7
, tmp_T0
;
263 int ret
, interrupt_request
;
264 void (*gen_func
)(void);
265 TranslationBlock
*tb
;
268 #if defined(TARGET_I386)
269 /* handle exit of HALTED state */
270 if (env1
->hflags
& HF_HALTED_MASK
) {
271 /* disable halt condition */
272 if ((env1
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
273 (env1
->eflags
& IF_MASK
)) {
274 env1
->hflags
&= ~HF_HALTED_MASK
;
279 #elif defined(TARGET_PPC)
281 if (env1
->msr
[MSR_EE
] &&
282 (env1
->interrupt_request
&
283 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
))) {
289 #elif defined(TARGET_SPARC)
291 if ((env1
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
292 (env1
->psret
!= 0)) {
298 #elif defined(TARGET_ARM)
300 /* An interrupt wakes the CPU even if the I and F CPSR bits are
302 if (env1
->interrupt_request
303 & (CPU_INTERRUPT_FIQ
| CPU_INTERRUPT_HARD
)) {
309 #elif defined(TARGET_MIPS)
311 if (env1
->interrupt_request
&
312 (CPU_INTERRUPT_HARD
| CPU_INTERRUPT_TIMER
)) {
320 cpu_single_env
= env1
;
322 /* first we save global registers */
330 #if defined(__sparc__) && !defined(HOST_SOLARIS)
331 /* we also save i7 because longjmp may not restore it */
332 asm volatile ("mov %%i7, %0" : "=r" (saved_i7
));
335 #if defined(TARGET_I386)
362 /* put eflags in CPU temporary format */
363 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
364 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
365 CC_OP
= CC_OP_EFLAGS
;
366 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
367 #elif defined(TARGET_ARM)
368 #elif defined(TARGET_SPARC)
369 #if defined(reg_REGWPTR)
370 saved_regwptr
= REGWPTR
;
372 #elif defined(TARGET_PPC)
373 #elif defined(TARGET_MIPS)
374 #elif defined(TARGET_SH4)
377 #error unsupported target CPU
379 env
->exception_index
= -1;
381 /* prepare setjmp context for exception handling */
383 if (setjmp(env
->jmp_env
) == 0) {
384 env
->current_tb
= NULL
;
385 /* if an exception is pending, we execute it here */
386 if (env
->exception_index
>= 0) {
387 if (env
->exception_index
>= EXCP_INTERRUPT
) {
388 /* exit request from the cpu execution loop */
389 ret
= env
->exception_index
;
391 } else if (env
->user_mode_only
) {
392 /* if user mode only, we simulate a fake exception
393 which will be hanlded outside the cpu execution
395 #if defined(TARGET_I386)
396 do_interrupt_user(env
->exception_index
,
397 env
->exception_is_int
,
399 env
->exception_next_eip
);
401 ret
= env
->exception_index
;
404 #if defined(TARGET_I386)
405 /* simulate a real cpu exception. On i386, it can
406 trigger new exceptions, but we do not handle
407 double or triple faults yet. */
408 do_interrupt(env
->exception_index
,
409 env
->exception_is_int
,
411 env
->exception_next_eip
, 0);
412 #elif defined(TARGET_PPC)
414 #elif defined(TARGET_MIPS)
416 #elif defined(TARGET_SPARC)
417 do_interrupt(env
->exception_index
);
418 #elif defined(TARGET_ARM)
420 #elif defined(TARGET_SH4)
424 env
->exception_index
= -1;
427 if (kqemu_is_ok(env
) && env
->interrupt_request
== 0) {
429 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
430 ret
= kqemu_cpu_exec(env
);
431 /* put eflags in CPU temporary format */
432 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
433 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
434 CC_OP
= CC_OP_EFLAGS
;
435 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
438 longjmp(env
->jmp_env
, 1);
439 } else if (ret
== 2) {
440 /* softmmu execution needed */
442 if (env
->interrupt_request
!= 0) {
443 /* hardware interrupt will be executed just after */
445 /* otherwise, we restart */
446 longjmp(env
->jmp_env
, 1);
452 T0
= 0; /* force lookup of first TB */
454 #if defined(__sparc__) && !defined(HOST_SOLARIS)
455 /* g1 can be modified by some libc? functions */
458 interrupt_request
= env
->interrupt_request
;
459 if (__builtin_expect(interrupt_request
, 0)) {
460 #if defined(TARGET_I386)
461 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
462 !(env
->hflags
& HF_SMM_MASK
)) {
463 env
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
465 #if defined(__sparc__) && !defined(HOST_SOLARIS)
470 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
471 (env
->eflags
& IF_MASK
) &&
472 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
474 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
475 intno
= cpu_get_pic_interrupt(env
);
476 if (loglevel
& CPU_LOG_TB_IN_ASM
) {
477 fprintf(logfile
, "Servicing hardware INT=0x%02x\n", intno
);
479 do_interrupt(intno
, 0, 0, 0, 1);
480 /* ensure that no TB jump will be modified as
481 the program flow was changed */
482 #if defined(__sparc__) && !defined(HOST_SOLARIS)
488 #elif defined(TARGET_PPC)
490 if ((interrupt_request
& CPU_INTERRUPT_RESET
)) {
495 if ((interrupt_request
& CPU_INTERRUPT_HARD
)) {
497 env
->exception_index
= EXCP_EXTERNAL
;
500 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
501 #if defined(__sparc__) && !defined(HOST_SOLARIS)
506 } else if ((interrupt_request
& CPU_INTERRUPT_TIMER
)) {
508 env
->exception_index
= EXCP_DECR
;
511 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
512 #if defined(__sparc__) && !defined(HOST_SOLARIS)
519 #elif defined(TARGET_MIPS)
520 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
521 (env
->CP0_Status
& (1 << CP0St_IE
)) &&
522 (env
->CP0_Status
& env
->CP0_Cause
& 0x0000FF00) &&
523 !(env
->hflags
& MIPS_HFLAG_EXL
) &&
524 !(env
->hflags
& MIPS_HFLAG_ERL
) &&
525 !(env
->hflags
& MIPS_HFLAG_DM
)) {
527 env
->exception_index
= EXCP_EXT_INTERRUPT
;
530 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
531 #if defined(__sparc__) && !defined(HOST_SOLARIS)
537 #elif defined(TARGET_SPARC)
538 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
540 int pil
= env
->interrupt_index
& 15;
541 int type
= env
->interrupt_index
& 0xf0;
543 if (((type
== TT_EXTINT
) &&
544 (pil
== 15 || pil
> env
->psrpil
)) ||
546 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
547 do_interrupt(env
->interrupt_index
);
548 env
->interrupt_index
= 0;
549 #if defined(__sparc__) && !defined(HOST_SOLARIS)
555 } else if (interrupt_request
& CPU_INTERRUPT_TIMER
) {
556 //do_interrupt(0, 0, 0, 0, 0);
557 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
558 } else if (interrupt_request
& CPU_INTERRUPT_HALT
) {
559 env
->interrupt_request
&= ~CPU_INTERRUPT_HALT
;
561 env
->exception_index
= EXCP_HLT
;
564 #elif defined(TARGET_ARM)
565 if (interrupt_request
& CPU_INTERRUPT_FIQ
566 && !(env
->uncached_cpsr
& CPSR_F
)) {
567 env
->exception_index
= EXCP_FIQ
;
570 if (interrupt_request
& CPU_INTERRUPT_HARD
571 && !(env
->uncached_cpsr
& CPSR_I
)) {
572 env
->exception_index
= EXCP_IRQ
;
575 #elif defined(TARGET_SH4)
578 /* Don't use the cached interupt_request value,
579 do_interrupt may have updated the EXITTB flag. */
580 if (env
->interrupt_request
& CPU_INTERRUPT_EXITTB
) {
581 env
->interrupt_request
&= ~CPU_INTERRUPT_EXITTB
;
582 /* ensure that no TB jump will be modified as
583 the program flow was changed */
584 #if defined(__sparc__) && !defined(HOST_SOLARIS)
590 if (interrupt_request
& CPU_INTERRUPT_EXIT
) {
591 env
->interrupt_request
&= ~CPU_INTERRUPT_EXIT
;
592 env
->exception_index
= EXCP_INTERRUPT
;
597 if ((loglevel
& CPU_LOG_TB_CPU
)) {
598 #if defined(TARGET_I386)
599 /* restore flags in standard format */
601 env
->regs
[R_EAX
] = EAX
;
604 env
->regs
[R_EBX
] = EBX
;
607 env
->regs
[R_ECX
] = ECX
;
610 env
->regs
[R_EDX
] = EDX
;
613 env
->regs
[R_ESI
] = ESI
;
616 env
->regs
[R_EDI
] = EDI
;
619 env
->regs
[R_EBP
] = EBP
;
622 env
->regs
[R_ESP
] = ESP
;
624 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
625 cpu_dump_state(env
, logfile
, fprintf
, X86_DUMP_CCOP
);
626 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
627 #elif defined(TARGET_ARM)
628 cpu_dump_state(env
, logfile
, fprintf
, 0);
629 #elif defined(TARGET_SPARC)
630 REGWPTR
= env
->regbase
+ (env
->cwp
* 16);
631 env
->regwptr
= REGWPTR
;
632 cpu_dump_state(env
, logfile
, fprintf
, 0);
633 #elif defined(TARGET_PPC)
634 cpu_dump_state(env
, logfile
, fprintf
, 0);
635 #elif defined(TARGET_MIPS)
636 cpu_dump_state(env
, logfile
, fprintf
, 0);
637 #elif defined(TARGET_SH4)
638 cpu_dump_state(env
, logfile
, fprintf
, 0);
640 #error unsupported target CPU
646 if ((loglevel
& CPU_LOG_EXEC
)) {
647 fprintf(logfile
, "Trace 0x%08lx [" TARGET_FMT_lx
"] %s\n",
648 (long)tb
->tc_ptr
, tb
->pc
,
649 lookup_symbol(tb
->pc
));
652 #if defined(__sparc__) && !defined(HOST_SOLARIS)
655 /* see if we can patch the calling TB. When the TB
656 spans two pages, we cannot safely do a direct
661 (env
->kqemu_enabled
!= 2) &&
663 tb
->page_addr
[1] == -1
664 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
665 && (tb
->cflags
& CF_CODE_COPY
) ==
666 (((TranslationBlock
*)(T0
& ~3))->cflags
& CF_CODE_COPY
)
670 tb_add_jump((TranslationBlock
*)(long)(T0
& ~3), T0
& 3, tb
);
671 #if defined(USE_CODE_COPY)
672 /* propagates the FP use info */
673 ((TranslationBlock
*)(T0
& ~3))->cflags
|=
674 (tb
->cflags
& CF_FP_USED
);
676 spin_unlock(&tb_lock
);
680 env
->current_tb
= tb
;
681 /* execute the generated code */
682 gen_func
= (void *)tc_ptr
;
683 #if defined(__sparc__)
684 __asm__
__volatile__("call %0\n\t"
688 : "i0", "i1", "i2", "i3", "i4", "i5",
689 "l0", "l1", "l2", "l3", "l4", "l5",
691 #elif defined(__arm__)
692 asm volatile ("mov pc, %0\n\t"
693 ".global exec_loop\n\t"
697 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
698 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
700 if (!(tb
->cflags
& CF_CODE_COPY
)) {
701 if ((tb
->cflags
& CF_FP_USED
) && env
->native_fp_regs
) {
702 save_native_fp_state(env
);
706 if ((tb
->cflags
& CF_FP_USED
) && !env
->native_fp_regs
) {
707 restore_native_fp_state(env
);
709 /* we work with native eflags */
710 CC_SRC
= cc_table
[CC_OP
].compute_all();
711 CC_OP
= CC_OP_EFLAGS
;
712 asm(".globl exec_loop\n"
717 " fs movl %11, %%eax\n"
718 " andl $0x400, %%eax\n"
719 " fs orl %8, %%eax\n"
722 " fs movl %%esp, %12\n"
723 " fs movl %0, %%eax\n"
724 " fs movl %1, %%ecx\n"
725 " fs movl %2, %%edx\n"
726 " fs movl %3, %%ebx\n"
727 " fs movl %4, %%esp\n"
728 " fs movl %5, %%ebp\n"
729 " fs movl %6, %%esi\n"
730 " fs movl %7, %%edi\n"
733 " fs movl %%esp, %4\n"
734 " fs movl %12, %%esp\n"
735 " fs movl %%eax, %0\n"
736 " fs movl %%ecx, %1\n"
737 " fs movl %%edx, %2\n"
738 " fs movl %%ebx, %3\n"
739 " fs movl %%ebp, %5\n"
740 " fs movl %%esi, %6\n"
741 " fs movl %%edi, %7\n"
744 " movl %%eax, %%ecx\n"
745 " andl $0x400, %%ecx\n"
747 " andl $0x8d5, %%eax\n"
748 " fs movl %%eax, %8\n"
750 " subl %%ecx, %%eax\n"
751 " fs movl %%eax, %11\n"
752 " fs movl %9, %%ebx\n" /* get T0 value */
755 : "m" (*(uint8_t *)offsetof(CPUState
, regs
[0])),
756 "m" (*(uint8_t *)offsetof(CPUState
, regs
[1])),
757 "m" (*(uint8_t *)offsetof(CPUState
, regs
[2])),
758 "m" (*(uint8_t *)offsetof(CPUState
, regs
[3])),
759 "m" (*(uint8_t *)offsetof(CPUState
, regs
[4])),
760 "m" (*(uint8_t *)offsetof(CPUState
, regs
[5])),
761 "m" (*(uint8_t *)offsetof(CPUState
, regs
[6])),
762 "m" (*(uint8_t *)offsetof(CPUState
, regs
[7])),
763 "m" (*(uint8_t *)offsetof(CPUState
, cc_src
)),
764 "m" (*(uint8_t *)offsetof(CPUState
, tmp0
)),
766 "m" (*(uint8_t *)offsetof(CPUState
, df
)),
767 "m" (*(uint8_t *)offsetof(CPUState
, saved_esp
))
772 #elif defined(__ia64)
779 fp
.gp
= code_gen_buffer
+ 2 * (1 << 20);
780 (*(void (*)(void)) &fp
)();
784 env
->current_tb
= NULL
;
785 /* reset soft MMU for next block (it can currently
786 only be set by a memory fault) */
787 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
788 if (env
->hflags
& HF_SOFTMMU_MASK
) {
789 env
->hflags
&= ~HF_SOFTMMU_MASK
;
790 /* do not allow linking to another block */
794 #if defined(USE_KQEMU)
795 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000)
796 if (kqemu_is_ok(env
) &&
797 (cpu_get_time_fast() - env
->last_io_time
) >= MIN_CYCLE_BEFORE_SWITCH
) {
808 #if defined(TARGET_I386)
809 #if defined(USE_CODE_COPY)
810 if (env
->native_fp_regs
) {
811 save_native_fp_state(env
);
814 /* restore flags in standard format */
815 env
->eflags
= env
->eflags
| cc_table
[CC_OP
].compute_all() | (DF
& DF_MASK
);
817 /* restore global registers */
842 #elif defined(TARGET_ARM)
843 /* XXX: Save/restore host fpu exception state?. */
844 #elif defined(TARGET_SPARC)
845 #if defined(reg_REGWPTR)
846 REGWPTR
= saved_regwptr
;
848 #elif defined(TARGET_PPC)
849 #elif defined(TARGET_MIPS)
850 #elif defined(TARGET_SH4)
853 #error unsupported target CPU
855 #if defined(__sparc__) && !defined(HOST_SOLARIS)
856 asm volatile ("mov %0, %%i7" : : "r" (saved_i7
));
864 /* fail safe : never use cpu_single_env outside cpu_exec() */
865 cpu_single_env
= NULL
;
869 /* must only be called from the generated code as an exception can be
871 void tb_invalidate_page_range(target_ulong start
, target_ulong end
)
873 /* XXX: cannot enable it yet because it yields to MMU exception
874 where NIP != read address on PowerPC */
876 target_ulong phys_addr
;
877 phys_addr
= get_phys_addr_code(env
, start
);
878 tb_invalidate_phys_page_range(phys_addr
, phys_addr
+ end
- start
, 0);
882 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
884 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
)
886 CPUX86State
*saved_env
;
890 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
892 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
893 (selector
<< 4), 0xffff, 0);
895 load_seg(seg_reg
, selector
);
900 void cpu_x86_fsave(CPUX86State
*s
, uint8_t *ptr
, int data32
)
902 CPUX86State
*saved_env
;
907 helper_fsave((target_ulong
)ptr
, data32
);
912 void cpu_x86_frstor(CPUX86State
*s
, uint8_t *ptr
, int data32
)
914 CPUX86State
*saved_env
;
919 helper_frstor((target_ulong
)ptr
, data32
);
924 #endif /* TARGET_I386 */
926 #if !defined(CONFIG_SOFTMMU)
928 #if defined(TARGET_I386)
930 /* 'pc' is the host PC at which the exception was raised. 'address' is
931 the effective address of the memory exception. 'is_write' is 1 if a
932 write caused the exception and otherwise 0'. 'old_set' is the
933 signal set which should be restored */
934 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
935 int is_write
, sigset_t
*old_set
,
938 TranslationBlock
*tb
;
942 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
943 #if defined(DEBUG_SIGNAL)
944 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
945 pc
, address
, is_write
, *(unsigned long *)old_set
);
947 /* XXX: locking issue */
948 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
952 /* see if it is an MMU fault */
953 ret
= cpu_x86_handle_mmu_fault(env
, address
, is_write
,
954 ((env
->hflags
& HF_CPL_MASK
) == 3), 0);
956 return 0; /* not an MMU fault */
958 return 1; /* the MMU fault was handled without causing real CPU fault */
959 /* now we have a real cpu fault */
962 /* the PC is inside the translated code. It means that we have
963 a virtual CPU fault */
964 cpu_restore_state(tb
, env
, pc
, puc
);
968 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
969 env
->eip
, env
->cr
[2], env
->error_code
);
971 /* we restore the process signal mask as the sigreturn should
972 do it (XXX: use sigsetjmp) */
973 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
974 raise_exception_err(env
->exception_index
, env
->error_code
);
976 /* activate soft MMU for this block */
977 env
->hflags
|= HF_SOFTMMU_MASK
;
978 cpu_resume_from_signal(env
, puc
);
980 /* never comes here */
984 #elif defined(TARGET_ARM)
985 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
986 int is_write
, sigset_t
*old_set
,
989 TranslationBlock
*tb
;
993 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
994 #if defined(DEBUG_SIGNAL)
995 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
996 pc
, address
, is_write
, *(unsigned long *)old_set
);
998 /* XXX: locking issue */
999 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1002 /* see if it is an MMU fault */
1003 ret
= cpu_arm_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1005 return 0; /* not an MMU fault */
1007 return 1; /* the MMU fault was handled without causing real CPU fault */
1008 /* now we have a real cpu fault */
1009 tb
= tb_find_pc(pc
);
1011 /* the PC is inside the translated code. It means that we have
1012 a virtual CPU fault */
1013 cpu_restore_state(tb
, env
, pc
, puc
);
1015 /* we restore the process signal mask as the sigreturn should
1016 do it (XXX: use sigsetjmp) */
1017 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1020 #elif defined(TARGET_SPARC)
1021 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1022 int is_write
, sigset_t
*old_set
,
1025 TranslationBlock
*tb
;
1029 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1030 #if defined(DEBUG_SIGNAL)
1031 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1032 pc
, address
, is_write
, *(unsigned long *)old_set
);
1034 /* XXX: locking issue */
1035 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1038 /* see if it is an MMU fault */
1039 ret
= cpu_sparc_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1041 return 0; /* not an MMU fault */
1043 return 1; /* the MMU fault was handled without causing real CPU fault */
1044 /* now we have a real cpu fault */
1045 tb
= tb_find_pc(pc
);
1047 /* the PC is inside the translated code. It means that we have
1048 a virtual CPU fault */
1049 cpu_restore_state(tb
, env
, pc
, puc
);
1051 /* we restore the process signal mask as the sigreturn should
1052 do it (XXX: use sigsetjmp) */
1053 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1056 #elif defined (TARGET_PPC)
1057 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1058 int is_write
, sigset_t
*old_set
,
1061 TranslationBlock
*tb
;
1065 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1066 #if defined(DEBUG_SIGNAL)
1067 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1068 pc
, address
, is_write
, *(unsigned long *)old_set
);
1070 /* XXX: locking issue */
1071 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1075 /* see if it is an MMU fault */
1076 ret
= cpu_ppc_handle_mmu_fault(env
, address
, is_write
, msr_pr
, 0);
1078 return 0; /* not an MMU fault */
1080 return 1; /* the MMU fault was handled without causing real CPU fault */
1082 /* now we have a real cpu fault */
1083 tb
= tb_find_pc(pc
);
1085 /* the PC is inside the translated code. It means that we have
1086 a virtual CPU fault */
1087 cpu_restore_state(tb
, env
, pc
, puc
);
1091 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1092 env
->nip
, env
->error_code
, tb
);
1094 /* we restore the process signal mask as the sigreturn should
1095 do it (XXX: use sigsetjmp) */
1096 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1097 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1099 /* activate soft MMU for this block */
1100 cpu_resume_from_signal(env
, puc
);
1102 /* never comes here */
1106 #elif defined (TARGET_MIPS)
1107 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1108 int is_write
, sigset_t
*old_set
,
1111 TranslationBlock
*tb
;
1115 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1116 #if defined(DEBUG_SIGNAL)
1117 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1118 pc
, address
, is_write
, *(unsigned long *)old_set
);
1120 /* XXX: locking issue */
1121 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1125 /* see if it is an MMU fault */
1126 ret
= cpu_mips_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1128 return 0; /* not an MMU fault */
1130 return 1; /* the MMU fault was handled without causing real CPU fault */
1132 /* now we have a real cpu fault */
1133 tb
= tb_find_pc(pc
);
1135 /* the PC is inside the translated code. It means that we have
1136 a virtual CPU fault */
1137 cpu_restore_state(tb
, env
, pc
, puc
);
1141 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1142 env
->nip
, env
->error_code
, tb
);
1144 /* we restore the process signal mask as the sigreturn should
1145 do it (XXX: use sigsetjmp) */
1146 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1147 do_raise_exception_err(env
->exception_index
, env
->error_code
);
1149 /* activate soft MMU for this block */
1150 cpu_resume_from_signal(env
, puc
);
1152 /* never comes here */
1156 #elif defined (TARGET_SH4)
1157 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
1158 int is_write
, sigset_t
*old_set
,
1161 TranslationBlock
*tb
;
1165 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1166 #if defined(DEBUG_SIGNAL)
1167 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
1168 pc
, address
, is_write
, *(unsigned long *)old_set
);
1170 /* XXX: locking issue */
1171 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
1175 /* see if it is an MMU fault */
1176 ret
= cpu_sh4_handle_mmu_fault(env
, address
, is_write
, 1, 0);
1178 return 0; /* not an MMU fault */
1180 return 1; /* the MMU fault was handled without causing real CPU fault */
1182 /* now we have a real cpu fault */
1183 tb
= tb_find_pc(pc
);
1185 /* the PC is inside the translated code. It means that we have
1186 a virtual CPU fault */
1187 cpu_restore_state(tb
, env
, pc
, puc
);
1190 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
1191 env
->nip
, env
->error_code
, tb
);
1193 /* we restore the process signal mask as the sigreturn should
1194 do it (XXX: use sigsetjmp) */
1195 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
1197 /* never comes here */
1201 #error unsupported target CPU
1204 #if defined(__i386__)
1206 #if defined(USE_CODE_COPY)
1207 static void cpu_send_trap(unsigned long pc
, int trap
,
1208 struct ucontext
*uc
)
1210 TranslationBlock
*tb
;
1213 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
1214 /* now we have a real cpu fault */
1215 tb
= tb_find_pc(pc
);
1217 /* the PC is inside the translated code. It means that we have
1218 a virtual CPU fault */
1219 cpu_restore_state(tb
, env
, pc
, uc
);
1221 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
1222 raise_exception_err(trap
, env
->error_code
);
1226 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1229 struct ucontext
*uc
= puc
;
1237 #define REG_TRAPNO TRAPNO
1239 pc
= uc
->uc_mcontext
.gregs
[REG_EIP
];
1240 trapno
= uc
->uc_mcontext
.gregs
[REG_TRAPNO
];
1241 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
1242 if (trapno
== 0x00 || trapno
== 0x05) {
1243 /* send division by zero or bound exception */
1244 cpu_send_trap(pc
, trapno
, uc
);
1248 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1250 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
1251 &uc
->uc_sigmask
, puc
);
1254 #elif defined(__x86_64__)
1256 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1259 struct ucontext
*uc
= puc
;
1262 pc
= uc
->uc_mcontext
.gregs
[REG_RIP
];
1263 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1264 uc
->uc_mcontext
.gregs
[REG_TRAPNO
] == 0xe ?
1265 (uc
->uc_mcontext
.gregs
[REG_ERR
] >> 1) & 1 : 0,
1266 &uc
->uc_sigmask
, puc
);
1269 #elif defined(__powerpc__)
1271 /***********************************************************************
1272 * signal context platform-specific definitions
1276 /* All Registers access - only for local access */
1277 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
1278 /* Gpr Registers access */
1279 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
1280 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
1281 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
1282 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
1283 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
1284 # define LR_sig(context) REG_sig(link, context) /* Link register */
1285 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
1286 /* Float Registers access */
1287 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
1288 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
1289 /* Exception Registers access */
1290 # define DAR_sig(context) REG_sig(dar, context)
1291 # define DSISR_sig(context) REG_sig(dsisr, context)
1292 # define TRAP_sig(context) REG_sig(trap, context)
1296 # include <sys/ucontext.h>
1297 typedef struct ucontext SIGCONTEXT
;
1298 /* All Registers access - only for local access */
1299 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
1300 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
1301 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
1302 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
1303 /* Gpr Registers access */
1304 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
1305 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
1306 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
1307 # define CTR_sig(context) REG_sig(ctr, context)
1308 # define XER_sig(context) REG_sig(xer, context) /* Link register */
1309 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
1310 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
1311 /* Float Registers access */
1312 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
1313 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
1314 /* Exception Registers access */
1315 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
1316 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
1317 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
1318 #endif /* __APPLE__ */
1320 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1323 struct ucontext
*uc
= puc
;
1331 if (DSISR_sig(uc
) & 0x00800000)
1334 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000))
1337 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1338 is_write
, &uc
->uc_sigmask
, puc
);
1341 #elif defined(__alpha__)
1343 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1346 struct ucontext
*uc
= puc
;
1347 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
1348 uint32_t insn
= *pc
;
1351 /* XXX: need kernel patch to get write flag faster */
1352 switch (insn
>> 26) {
1367 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1368 is_write
, &uc
->uc_sigmask
, puc
);
1370 #elif defined(__sparc__)
1372 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1375 uint32_t *regs
= (uint32_t *)(info
+ 1);
1376 void *sigmask
= (regs
+ 20);
1381 /* XXX: is there a standard glibc define ? */
1383 /* XXX: need kernel patch to get write flag faster */
1385 insn
= *(uint32_t *)pc
;
1386 if ((insn
>> 30) == 3) {
1387 switch((insn
>> 19) & 0x3f) {
1399 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1400 is_write
, sigmask
, NULL
);
1403 #elif defined(__arm__)
1405 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1408 struct ucontext
*uc
= puc
;
1412 pc
= uc
->uc_mcontext
.gregs
[R15
];
1413 /* XXX: compute is_write */
1415 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1417 &uc
->uc_sigmask
, puc
);
1420 #elif defined(__mc68000)
1422 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1425 struct ucontext
*uc
= puc
;
1429 pc
= uc
->uc_mcontext
.gregs
[16];
1430 /* XXX: compute is_write */
1432 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1434 &uc
->uc_sigmask
, puc
);
1437 #elif defined(__ia64)
1440 /* This ought to be in <bits/siginfo.h>... */
1441 # define __ISR_VALID 1
1444 int cpu_signal_handler(int host_signum
, struct siginfo
*info
, void *puc
)
1446 struct ucontext
*uc
= puc
;
1450 ip
= uc
->uc_mcontext
.sc_ip
;
1451 switch (host_signum
) {
1457 if (info
->si_code
&& (info
->si_segvflags
& __ISR_VALID
))
1458 /* ISR.W (write-access) is bit 33: */
1459 is_write
= (info
->si_isr
>> 33) & 1;
1465 return handle_cpu_signal(ip
, (unsigned long)info
->si_addr
,
1467 &uc
->uc_sigmask
, puc
);
1470 #elif defined(__s390__)
1472 int cpu_signal_handler(int host_signum
, struct siginfo
*info
,
1475 struct ucontext
*uc
= puc
;
1479 pc
= uc
->uc_mcontext
.psw
.addr
;
1480 /* XXX: compute is_write */
1482 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1484 &uc
->uc_sigmask
, puc
);
1489 #error host CPU specific signal handler needed
1493 #endif /* !defined(CONFIG_SOFTMMU) */