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1 /*
2 * i386 emulator main execution loop
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 */
20 #include "config.h"
21 #include "exec.h"
22 #include "disas.h"
23
24 #if !defined(CONFIG_SOFTMMU)
25 #undef EAX
26 #undef ECX
27 #undef EDX
28 #undef EBX
29 #undef ESP
30 #undef EBP
31 #undef ESI
32 #undef EDI
33 #undef EIP
34 #include <signal.h>
35 #include <sys/ucontext.h>
36 #endif
37
38 int tb_invalidated_flag;
39
40 //#define DEBUG_EXEC
41 //#define DEBUG_SIGNAL
42
43 #if defined(TARGET_ARM) || defined(TARGET_SPARC)
44 /* XXX: unify with i386 target */
45 void cpu_loop_exit(void)
46 {
47 longjmp(env->jmp_env, 1);
48 }
49 #endif
50
51 /* exit the current TB from a signal handler. The host registers are
52 restored in a state compatible with the CPU emulator
53 */
54 void cpu_resume_from_signal(CPUState *env1, void *puc)
55 {
56 #if !defined(CONFIG_SOFTMMU)
57 struct ucontext *uc = puc;
58 #endif
59
60 env = env1;
61
62 /* XXX: restore cpu registers saved in host registers */
63
64 #if !defined(CONFIG_SOFTMMU)
65 if (puc) {
66 /* XXX: use siglongjmp ? */
67 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
68 }
69 #endif
70 longjmp(env->jmp_env, 1);
71 }
72
73 /* main execution loop */
74
75 int cpu_exec(CPUState *env1)
76 {
77 int saved_T0, saved_T1, saved_T2;
78 CPUState *saved_env;
79 #ifdef reg_EAX
80 int saved_EAX;
81 #endif
82 #ifdef reg_ECX
83 int saved_ECX;
84 #endif
85 #ifdef reg_EDX
86 int saved_EDX;
87 #endif
88 #ifdef reg_EBX
89 int saved_EBX;
90 #endif
91 #ifdef reg_ESP
92 int saved_ESP;
93 #endif
94 #ifdef reg_EBP
95 int saved_EBP;
96 #endif
97 #ifdef reg_ESI
98 int saved_ESI;
99 #endif
100 #ifdef reg_EDI
101 int saved_EDI;
102 #endif
103 #ifdef __sparc__
104 int saved_i7, tmp_T0;
105 #endif
106 int code_gen_size, ret, interrupt_request;
107 void (*gen_func)(void);
108 TranslationBlock *tb, **ptb;
109 target_ulong cs_base, pc;
110 uint8_t *tc_ptr;
111 unsigned int flags;
112
113 /* first we save global registers */
114 saved_env = env;
115 env = env1;
116 saved_T0 = T0;
117 saved_T1 = T1;
118 saved_T2 = T2;
119 #ifdef __sparc__
120 /* we also save i7 because longjmp may not restore it */
121 asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
122 #endif
123
124 #if defined(TARGET_I386)
125 #ifdef reg_EAX
126 saved_EAX = EAX;
127 #endif
128 #ifdef reg_ECX
129 saved_ECX = ECX;
130 #endif
131 #ifdef reg_EDX
132 saved_EDX = EDX;
133 #endif
134 #ifdef reg_EBX
135 saved_EBX = EBX;
136 #endif
137 #ifdef reg_ESP
138 saved_ESP = ESP;
139 #endif
140 #ifdef reg_EBP
141 saved_EBP = EBP;
142 #endif
143 #ifdef reg_ESI
144 saved_ESI = ESI;
145 #endif
146 #ifdef reg_EDI
147 saved_EDI = EDI;
148 #endif
149
150 env_to_regs();
151 /* put eflags in CPU temporary format */
152 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
153 DF = 1 - (2 * ((env->eflags >> 10) & 1));
154 CC_OP = CC_OP_EFLAGS;
155 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
156 #elif defined(TARGET_ARM)
157 {
158 unsigned int psr;
159 psr = env->cpsr;
160 env->CF = (psr >> 29) & 1;
161 env->NZF = (psr & 0xc0000000) ^ 0x40000000;
162 env->VF = (psr << 3) & 0x80000000;
163 env->QF = (psr >> 27) & 1;
164 env->cpsr = psr & ~CACHED_CPSR_BITS;
165 }
166 #elif defined(TARGET_SPARC)
167 #elif defined(TARGET_PPC)
168 #else
169 #error unsupported target CPU
170 #endif
171 env->exception_index = -1;
172
173 /* prepare setjmp context for exception handling */
174 for(;;) {
175 if (setjmp(env->jmp_env) == 0) {
176 env->current_tb = NULL;
177 /* if an exception is pending, we execute it here */
178 if (env->exception_index >= 0) {
179 if (env->exception_index >= EXCP_INTERRUPT) {
180 /* exit request from the cpu execution loop */
181 ret = env->exception_index;
182 break;
183 } else if (env->user_mode_only) {
184 /* if user mode only, we simulate a fake exception
185 which will be hanlded outside the cpu execution
186 loop */
187 #if defined(TARGET_I386)
188 do_interrupt_user(env->exception_index,
189 env->exception_is_int,
190 env->error_code,
191 env->exception_next_eip);
192 #endif
193 ret = env->exception_index;
194 break;
195 } else {
196 #if defined(TARGET_I386)
197 /* simulate a real cpu exception. On i386, it can
198 trigger new exceptions, but we do not handle
199 double or triple faults yet. */
200 do_interrupt(env->exception_index,
201 env->exception_is_int,
202 env->error_code,
203 env->exception_next_eip, 0);
204 #elif defined(TARGET_PPC)
205 do_interrupt(env);
206 #elif defined(TARGET_SPARC)
207 do_interrupt(env->exception_index,
208 env->error_code);
209 #endif
210 }
211 env->exception_index = -1;
212 }
213 #ifdef USE_KQEMU
214 if (kqemu_is_ok(env) && env->interrupt_request == 0) {
215 int ret;
216 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
217 ret = kqemu_cpu_exec(env);
218 /* put eflags in CPU temporary format */
219 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
220 DF = 1 - (2 * ((env->eflags >> 10) & 1));
221 CC_OP = CC_OP_EFLAGS;
222 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
223 if (ret == 1) {
224 /* exception */
225 longjmp(env->jmp_env, 1);
226 } else if (ret == 2) {
227 /* softmmu execution needed */
228 } else {
229 if (env->interrupt_request != 0) {
230 /* hardware interrupt will be executed just after */
231 } else {
232 /* otherwise, we restart */
233 longjmp(env->jmp_env, 1);
234 }
235 }
236 }
237 #endif
238
239 T0 = 0; /* force lookup of first TB */
240 for(;;) {
241 #ifdef __sparc__
242 /* g1 can be modified by some libc? functions */
243 tmp_T0 = T0;
244 #endif
245 interrupt_request = env->interrupt_request;
246 if (__builtin_expect(interrupt_request, 0)) {
247 #if defined(TARGET_I386)
248 /* if hardware interrupt pending, we execute it */
249 if ((interrupt_request & CPU_INTERRUPT_HARD) &&
250 (env->eflags & IF_MASK) &&
251 !(env->hflags & HF_INHIBIT_IRQ_MASK)) {
252 int intno;
253 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
254 intno = cpu_get_pic_interrupt(env);
255 if (loglevel & CPU_LOG_TB_IN_ASM) {
256 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
257 }
258 do_interrupt(intno, 0, 0, 0, 1);
259 /* ensure that no TB jump will be modified as
260 the program flow was changed */
261 #ifdef __sparc__
262 tmp_T0 = 0;
263 #else
264 T0 = 0;
265 #endif
266 }
267 #elif defined(TARGET_PPC)
268 #if 0
269 if ((interrupt_request & CPU_INTERRUPT_RESET)) {
270 cpu_ppc_reset(env);
271 }
272 #endif
273 if (msr_ee != 0) {
274 if ((interrupt_request & CPU_INTERRUPT_HARD)) {
275 /* Raise it */
276 env->exception_index = EXCP_EXTERNAL;
277 env->error_code = 0;
278 do_interrupt(env);
279 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
280 } else if ((interrupt_request & CPU_INTERRUPT_TIMER)) {
281 /* Raise it */
282 env->exception_index = EXCP_DECR;
283 env->error_code = 0;
284 do_interrupt(env);
285 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
286 }
287 }
288 #elif defined(TARGET_SPARC)
289 if (interrupt_request & CPU_INTERRUPT_HARD) {
290 do_interrupt(env->interrupt_index, 0);
291 env->interrupt_request &= ~CPU_INTERRUPT_HARD;
292 } else if (interrupt_request & CPU_INTERRUPT_TIMER) {
293 //do_interrupt(0, 0, 0, 0, 0);
294 env->interrupt_request &= ~CPU_INTERRUPT_TIMER;
295 }
296 #endif
297 if (interrupt_request & CPU_INTERRUPT_EXITTB) {
298 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
299 /* ensure that no TB jump will be modified as
300 the program flow was changed */
301 #ifdef __sparc__
302 tmp_T0 = 0;
303 #else
304 T0 = 0;
305 #endif
306 }
307 if (interrupt_request & CPU_INTERRUPT_EXIT) {
308 env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
309 env->exception_index = EXCP_INTERRUPT;
310 cpu_loop_exit();
311 }
312 }
313 #ifdef DEBUG_EXEC
314 if ((loglevel & CPU_LOG_EXEC)) {
315 #if defined(TARGET_I386)
316 /* restore flags in standard format */
317 env->regs[R_EAX] = EAX;
318 env->regs[R_EBX] = EBX;
319 env->regs[R_ECX] = ECX;
320 env->regs[R_EDX] = EDX;
321 env->regs[R_ESI] = ESI;
322 env->regs[R_EDI] = EDI;
323 env->regs[R_EBP] = EBP;
324 env->regs[R_ESP] = ESP;
325 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
326 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP);
327 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
328 #elif defined(TARGET_ARM)
329 env->cpsr = compute_cpsr();
330 cpu_dump_state(env, logfile, fprintf, 0);
331 env->cpsr &= ~CACHED_CPSR_BITS;
332 #elif defined(TARGET_SPARC)
333 cpu_dump_state (env, logfile, fprintf, 0);
334 #elif defined(TARGET_PPC)
335 cpu_dump_state(env, logfile, fprintf, 0);
336 #else
337 #error unsupported target CPU
338 #endif
339 }
340 #endif
341 /* we record a subset of the CPU state. It will
342 always be the same before a given translated block
343 is executed. */
344 #if defined(TARGET_I386)
345 flags = env->hflags;
346 flags |= (env->eflags & (IOPL_MASK | TF_MASK | VM_MASK));
347 cs_base = env->segs[R_CS].base;
348 pc = cs_base + env->eip;
349 #elif defined(TARGET_ARM)
350 flags = env->thumb;
351 cs_base = 0;
352 pc = env->regs[15];
353 #elif defined(TARGET_SPARC)
354 flags = 0;
355 cs_base = env->npc;
356 pc = env->pc;
357 #elif defined(TARGET_PPC)
358 flags = 0;
359 cs_base = 0;
360 pc = env->nip;
361 #else
362 #error unsupported CPU
363 #endif
364 tb = tb_find(&ptb, pc, cs_base,
365 flags);
366 if (!tb) {
367 TranslationBlock **ptb1;
368 unsigned int h;
369 target_ulong phys_pc, phys_page1, phys_page2, virt_page2;
370
371
372 spin_lock(&tb_lock);
373
374 tb_invalidated_flag = 0;
375
376 regs_to_env(); /* XXX: do it just before cpu_gen_code() */
377
378 /* find translated block using physical mappings */
379 phys_pc = get_phys_addr_code(env, pc);
380 phys_page1 = phys_pc & TARGET_PAGE_MASK;
381 phys_page2 = -1;
382 h = tb_phys_hash_func(phys_pc);
383 ptb1 = &tb_phys_hash[h];
384 for(;;) {
385 tb = *ptb1;
386 if (!tb)
387 goto not_found;
388 if (tb->pc == pc &&
389 tb->page_addr[0] == phys_page1 &&
390 tb->cs_base == cs_base &&
391 tb->flags == flags) {
392 /* check next page if needed */
393 if (tb->page_addr[1] != -1) {
394 virt_page2 = (pc & TARGET_PAGE_MASK) +
395 TARGET_PAGE_SIZE;
396 phys_page2 = get_phys_addr_code(env, virt_page2);
397 if (tb->page_addr[1] == phys_page2)
398 goto found;
399 } else {
400 goto found;
401 }
402 }
403 ptb1 = &tb->phys_hash_next;
404 }
405 not_found:
406 /* if no translated code available, then translate it now */
407 tb = tb_alloc(pc);
408 if (!tb) {
409 /* flush must be done */
410 tb_flush(env);
411 /* cannot fail at this point */
412 tb = tb_alloc(pc);
413 /* don't forget to invalidate previous TB info */
414 ptb = &tb_hash[tb_hash_func(pc)];
415 T0 = 0;
416 }
417 tc_ptr = code_gen_ptr;
418 tb->tc_ptr = tc_ptr;
419 tb->cs_base = cs_base;
420 tb->flags = flags;
421 cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
422 code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
423
424 /* check next page if needed */
425 virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
426 phys_page2 = -1;
427 if ((pc & TARGET_PAGE_MASK) != virt_page2) {
428 phys_page2 = get_phys_addr_code(env, virt_page2);
429 }
430 tb_link_phys(tb, phys_pc, phys_page2);
431
432 found:
433 if (tb_invalidated_flag) {
434 /* as some TB could have been invalidated because
435 of memory exceptions while generating the code, we
436 must recompute the hash index here */
437 ptb = &tb_hash[tb_hash_func(pc)];
438 while (*ptb != NULL)
439 ptb = &(*ptb)->hash_next;
440 T0 = 0;
441 }
442 /* we add the TB in the virtual pc hash table */
443 *ptb = tb;
444 tb->hash_next = NULL;
445 tb_link(tb);
446 spin_unlock(&tb_lock);
447 }
448 #ifdef DEBUG_EXEC
449 if ((loglevel & CPU_LOG_EXEC)) {
450 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n",
451 (long)tb->tc_ptr, tb->pc,
452 lookup_symbol(tb->pc));
453 }
454 #endif
455 #ifdef __sparc__
456 T0 = tmp_T0;
457 #endif
458 /* see if we can patch the calling TB. */
459 {
460 if (T0 != 0
461 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
462 && (tb->cflags & CF_CODE_COPY) ==
463 (((TranslationBlock *)(T0 & ~3))->cflags & CF_CODE_COPY)
464 #endif
465 ) {
466 spin_lock(&tb_lock);
467 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb);
468 #if defined(USE_CODE_COPY)
469 /* propagates the FP use info */
470 ((TranslationBlock *)(T0 & ~3))->cflags |=
471 (tb->cflags & CF_FP_USED);
472 #endif
473 spin_unlock(&tb_lock);
474 }
475 }
476 tc_ptr = tb->tc_ptr;
477 env->current_tb = tb;
478 /* execute the generated code */
479 gen_func = (void *)tc_ptr;
480 #if defined(__sparc__)
481 __asm__ __volatile__("call %0\n\t"
482 "mov %%o7,%%i0"
483 : /* no outputs */
484 : "r" (gen_func)
485 : "i0", "i1", "i2", "i3", "i4", "i5");
486 #elif defined(__arm__)
487 asm volatile ("mov pc, %0\n\t"
488 ".global exec_loop\n\t"
489 "exec_loop:\n\t"
490 : /* no outputs */
491 : "r" (gen_func)
492 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
493 #elif defined(TARGET_I386) && defined(USE_CODE_COPY)
494 {
495 if (!(tb->cflags & CF_CODE_COPY)) {
496 if ((tb->cflags & CF_FP_USED) && env->native_fp_regs) {
497 save_native_fp_state(env);
498 }
499 gen_func();
500 } else {
501 if ((tb->cflags & CF_FP_USED) && !env->native_fp_regs) {
502 restore_native_fp_state(env);
503 }
504 /* we work with native eflags */
505 CC_SRC = cc_table[CC_OP].compute_all();
506 CC_OP = CC_OP_EFLAGS;
507 asm(".globl exec_loop\n"
508 "\n"
509 "debug1:\n"
510 " pushl %%ebp\n"
511 " fs movl %10, %9\n"
512 " fs movl %11, %%eax\n"
513 " andl $0x400, %%eax\n"
514 " fs orl %8, %%eax\n"
515 " pushl %%eax\n"
516 " popf\n"
517 " fs movl %%esp, %12\n"
518 " fs movl %0, %%eax\n"
519 " fs movl %1, %%ecx\n"
520 " fs movl %2, %%edx\n"
521 " fs movl %3, %%ebx\n"
522 " fs movl %4, %%esp\n"
523 " fs movl %5, %%ebp\n"
524 " fs movl %6, %%esi\n"
525 " fs movl %7, %%edi\n"
526 " fs jmp *%9\n"
527 "exec_loop:\n"
528 " fs movl %%esp, %4\n"
529 " fs movl %12, %%esp\n"
530 " fs movl %%eax, %0\n"
531 " fs movl %%ecx, %1\n"
532 " fs movl %%edx, %2\n"
533 " fs movl %%ebx, %3\n"
534 " fs movl %%ebp, %5\n"
535 " fs movl %%esi, %6\n"
536 " fs movl %%edi, %7\n"
537 " pushf\n"
538 " popl %%eax\n"
539 " movl %%eax, %%ecx\n"
540 " andl $0x400, %%ecx\n"
541 " shrl $9, %%ecx\n"
542 " andl $0x8d5, %%eax\n"
543 " fs movl %%eax, %8\n"
544 " movl $1, %%eax\n"
545 " subl %%ecx, %%eax\n"
546 " fs movl %%eax, %11\n"
547 " fs movl %9, %%ebx\n" /* get T0 value */
548 " popl %%ebp\n"
549 :
550 : "m" (*(uint8_t *)offsetof(CPUState, regs[0])),
551 "m" (*(uint8_t *)offsetof(CPUState, regs[1])),
552 "m" (*(uint8_t *)offsetof(CPUState, regs[2])),
553 "m" (*(uint8_t *)offsetof(CPUState, regs[3])),
554 "m" (*(uint8_t *)offsetof(CPUState, regs[4])),
555 "m" (*(uint8_t *)offsetof(CPUState, regs[5])),
556 "m" (*(uint8_t *)offsetof(CPUState, regs[6])),
557 "m" (*(uint8_t *)offsetof(CPUState, regs[7])),
558 "m" (*(uint8_t *)offsetof(CPUState, cc_src)),
559 "m" (*(uint8_t *)offsetof(CPUState, tmp0)),
560 "a" (gen_func),
561 "m" (*(uint8_t *)offsetof(CPUState, df)),
562 "m" (*(uint8_t *)offsetof(CPUState, saved_esp))
563 : "%ecx", "%edx"
564 );
565 }
566 }
567 #else
568 gen_func();
569 #endif
570 env->current_tb = NULL;
571 /* reset soft MMU for next block (it can currently
572 only be set by a memory fault) */
573 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
574 if (env->hflags & HF_SOFTMMU_MASK) {
575 env->hflags &= ~HF_SOFTMMU_MASK;
576 /* do not allow linking to another block */
577 T0 = 0;
578 }
579 #endif
580 }
581 } else {
582 env_to_regs();
583 }
584 } /* for(;;) */
585
586
587 #if defined(TARGET_I386)
588 #if defined(USE_CODE_COPY)
589 if (env->native_fp_regs) {
590 save_native_fp_state(env);
591 }
592 #endif
593 /* restore flags in standard format */
594 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
595
596 /* restore global registers */
597 #ifdef reg_EAX
598 EAX = saved_EAX;
599 #endif
600 #ifdef reg_ECX
601 ECX = saved_ECX;
602 #endif
603 #ifdef reg_EDX
604 EDX = saved_EDX;
605 #endif
606 #ifdef reg_EBX
607 EBX = saved_EBX;
608 #endif
609 #ifdef reg_ESP
610 ESP = saved_ESP;
611 #endif
612 #ifdef reg_EBP
613 EBP = saved_EBP;
614 #endif
615 #ifdef reg_ESI
616 ESI = saved_ESI;
617 #endif
618 #ifdef reg_EDI
619 EDI = saved_EDI;
620 #endif
621 #elif defined(TARGET_ARM)
622 env->cpsr = compute_cpsr();
623 #elif defined(TARGET_SPARC)
624 #elif defined(TARGET_PPC)
625 #else
626 #error unsupported target CPU
627 #endif
628 #ifdef __sparc__
629 asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
630 #endif
631 T0 = saved_T0;
632 T1 = saved_T1;
633 T2 = saved_T2;
634 env = saved_env;
635 return ret;
636 }
637
638 /* must only be called from the generated code as an exception can be
639 generated */
640 void tb_invalidate_page_range(target_ulong start, target_ulong end)
641 {
642 /* XXX: cannot enable it yet because it yields to MMU exception
643 where NIP != read address on PowerPC */
644 #if 0
645 target_ulong phys_addr;
646 phys_addr = get_phys_addr_code(env, start);
647 tb_invalidate_phys_page_range(phys_addr, phys_addr + end - start, 0);
648 #endif
649 }
650
651 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
652
653 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
654 {
655 CPUX86State *saved_env;
656
657 saved_env = env;
658 env = s;
659 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
660 selector &= 0xffff;
661 cpu_x86_load_seg_cache(env, seg_reg, selector,
662 (selector << 4), 0xffff, 0);
663 } else {
664 load_seg(seg_reg, selector);
665 }
666 env = saved_env;
667 }
668
669 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
670 {
671 CPUX86State *saved_env;
672
673 saved_env = env;
674 env = s;
675
676 helper_fsave((target_ulong)ptr, data32);
677
678 env = saved_env;
679 }
680
681 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
682 {
683 CPUX86State *saved_env;
684
685 saved_env = env;
686 env = s;
687
688 helper_frstor((target_ulong)ptr, data32);
689
690 env = saved_env;
691 }
692
693 #endif /* TARGET_I386 */
694
695 #if !defined(CONFIG_SOFTMMU)
696
697 #if defined(TARGET_I386)
698
699 /* 'pc' is the host PC at which the exception was raised. 'address' is
700 the effective address of the memory exception. 'is_write' is 1 if a
701 write caused the exception and otherwise 0'. 'old_set' is the
702 signal set which should be restored */
703 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
704 int is_write, sigset_t *old_set,
705 void *puc)
706 {
707 TranslationBlock *tb;
708 int ret;
709
710 if (cpu_single_env)
711 env = cpu_single_env; /* XXX: find a correct solution for multithread */
712 #if defined(DEBUG_SIGNAL)
713 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
714 pc, address, is_write, *(unsigned long *)old_set);
715 #endif
716 /* XXX: locking issue */
717 if (is_write && page_unprotect(address, pc, puc)) {
718 return 1;
719 }
720
721 /* see if it is an MMU fault */
722 ret = cpu_x86_handle_mmu_fault(env, address, is_write,
723 ((env->hflags & HF_CPL_MASK) == 3), 0);
724 if (ret < 0)
725 return 0; /* not an MMU fault */
726 if (ret == 0)
727 return 1; /* the MMU fault was handled without causing real CPU fault */
728 /* now we have a real cpu fault */
729 tb = tb_find_pc(pc);
730 if (tb) {
731 /* the PC is inside the translated code. It means that we have
732 a virtual CPU fault */
733 cpu_restore_state(tb, env, pc, puc);
734 }
735 if (ret == 1) {
736 #if 0
737 printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
738 env->eip, env->cr[2], env->error_code);
739 #endif
740 /* we restore the process signal mask as the sigreturn should
741 do it (XXX: use sigsetjmp) */
742 sigprocmask(SIG_SETMASK, old_set, NULL);
743 raise_exception_err(EXCP0E_PAGE, env->error_code);
744 } else {
745 /* activate soft MMU for this block */
746 env->hflags |= HF_SOFTMMU_MASK;
747 cpu_resume_from_signal(env, puc);
748 }
749 /* never comes here */
750 return 1;
751 }
752
753 #elif defined(TARGET_ARM)
754 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
755 int is_write, sigset_t *old_set,
756 void *puc)
757 {
758 TranslationBlock *tb;
759 int ret;
760
761 if (cpu_single_env)
762 env = cpu_single_env; /* XXX: find a correct solution for multithread */
763 #if defined(DEBUG_SIGNAL)
764 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
765 pc, address, is_write, *(unsigned long *)old_set);
766 #endif
767 /* XXX: locking issue */
768 if (is_write && page_unprotect(address, pc, puc)) {
769 return 1;
770 }
771 /* see if it is an MMU fault */
772 ret = cpu_arm_handle_mmu_fault(env, address, is_write, 1, 0);
773 if (ret < 0)
774 return 0; /* not an MMU fault */
775 if (ret == 0)
776 return 1; /* the MMU fault was handled without causing real CPU fault */
777 /* now we have a real cpu fault */
778 tb = tb_find_pc(pc);
779 if (tb) {
780 /* the PC is inside the translated code. It means that we have
781 a virtual CPU fault */
782 cpu_restore_state(tb, env, pc, puc);
783 }
784 /* we restore the process signal mask as the sigreturn should
785 do it (XXX: use sigsetjmp) */
786 sigprocmask(SIG_SETMASK, old_set, NULL);
787 cpu_loop_exit();
788 }
789 #elif defined(TARGET_SPARC)
790 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
791 int is_write, sigset_t *old_set,
792 void *puc)
793 {
794 TranslationBlock *tb;
795 int ret;
796
797 if (cpu_single_env)
798 env = cpu_single_env; /* XXX: find a correct solution for multithread */
799 #if defined(DEBUG_SIGNAL)
800 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
801 pc, address, is_write, *(unsigned long *)old_set);
802 #endif
803 /* XXX: locking issue */
804 if (is_write && page_unprotect(address, pc, puc)) {
805 return 1;
806 }
807 /* see if it is an MMU fault */
808 ret = cpu_sparc_handle_mmu_fault(env, address, is_write, 1, 0);
809 if (ret < 0)
810 return 0; /* not an MMU fault */
811 if (ret == 0)
812 return 1; /* the MMU fault was handled without causing real CPU fault */
813 /* now we have a real cpu fault */
814 tb = tb_find_pc(pc);
815 if (tb) {
816 /* the PC is inside the translated code. It means that we have
817 a virtual CPU fault */
818 cpu_restore_state(tb, env, pc, puc);
819 }
820 /* we restore the process signal mask as the sigreturn should
821 do it (XXX: use sigsetjmp) */
822 sigprocmask(SIG_SETMASK, old_set, NULL);
823 cpu_loop_exit();
824 }
825 #elif defined (TARGET_PPC)
826 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
827 int is_write, sigset_t *old_set,
828 void *puc)
829 {
830 TranslationBlock *tb;
831 int ret;
832
833 if (cpu_single_env)
834 env = cpu_single_env; /* XXX: find a correct solution for multithread */
835 #if defined(DEBUG_SIGNAL)
836 printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
837 pc, address, is_write, *(unsigned long *)old_set);
838 #endif
839 /* XXX: locking issue */
840 if (is_write && page_unprotect(address, pc, puc)) {
841 return 1;
842 }
843
844 /* see if it is an MMU fault */
845 ret = cpu_ppc_handle_mmu_fault(env, address, is_write, msr_pr, 0);
846 if (ret < 0)
847 return 0; /* not an MMU fault */
848 if (ret == 0)
849 return 1; /* the MMU fault was handled without causing real CPU fault */
850
851 /* now we have a real cpu fault */
852 tb = tb_find_pc(pc);
853 if (tb) {
854 /* the PC is inside the translated code. It means that we have
855 a virtual CPU fault */
856 cpu_restore_state(tb, env, pc, puc);
857 }
858 if (ret == 1) {
859 #if 0
860 printf("PF exception: NIP=0x%08x error=0x%x %p\n",
861 env->nip, env->error_code, tb);
862 #endif
863 /* we restore the process signal mask as the sigreturn should
864 do it (XXX: use sigsetjmp) */
865 sigprocmask(SIG_SETMASK, old_set, NULL);
866 do_raise_exception_err(env->exception_index, env->error_code);
867 } else {
868 /* activate soft MMU for this block */
869 cpu_resume_from_signal(env, puc);
870 }
871 /* never comes here */
872 return 1;
873 }
874 #else
875 #error unsupported target CPU
876 #endif
877
878 #if defined(__i386__)
879
880 #if defined(USE_CODE_COPY)
881 static void cpu_send_trap(unsigned long pc, int trap,
882 struct ucontext *uc)
883 {
884 TranslationBlock *tb;
885
886 if (cpu_single_env)
887 env = cpu_single_env; /* XXX: find a correct solution for multithread */
888 /* now we have a real cpu fault */
889 tb = tb_find_pc(pc);
890 if (tb) {
891 /* the PC is inside the translated code. It means that we have
892 a virtual CPU fault */
893 cpu_restore_state(tb, env, pc, uc);
894 }
895 sigprocmask(SIG_SETMASK, &uc->uc_sigmask, NULL);
896 raise_exception_err(trap, env->error_code);
897 }
898 #endif
899
900 int cpu_signal_handler(int host_signum, struct siginfo *info,
901 void *puc)
902 {
903 struct ucontext *uc = puc;
904 unsigned long pc;
905 int trapno;
906
907 #ifndef REG_EIP
908 /* for glibc 2.1 */
909 #define REG_EIP EIP
910 #define REG_ERR ERR
911 #define REG_TRAPNO TRAPNO
912 #endif
913 pc = uc->uc_mcontext.gregs[REG_EIP];
914 trapno = uc->uc_mcontext.gregs[REG_TRAPNO];
915 #if defined(TARGET_I386) && defined(USE_CODE_COPY)
916 if (trapno == 0x00 || trapno == 0x05) {
917 /* send division by zero or bound exception */
918 cpu_send_trap(pc, trapno, uc);
919 return 1;
920 } else
921 #endif
922 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
923 trapno == 0xe ?
924 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
925 &uc->uc_sigmask, puc);
926 }
927
928 #elif defined(__x86_64__)
929
930 int cpu_signal_handler(int host_signum, struct siginfo *info,
931 void *puc)
932 {
933 struct ucontext *uc = puc;
934 unsigned long pc;
935
936 pc = uc->uc_mcontext.gregs[REG_RIP];
937 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
938 uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
939 (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
940 &uc->uc_sigmask, puc);
941 }
942
943 #elif defined(__powerpc__)
944
945 /***********************************************************************
946 * signal context platform-specific definitions
947 * From Wine
948 */
949 #ifdef linux
950 /* All Registers access - only for local access */
951 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
952 /* Gpr Registers access */
953 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
954 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
955 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
956 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
957 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
958 # define LR_sig(context) REG_sig(link, context) /* Link register */
959 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
960 /* Float Registers access */
961 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
962 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
963 /* Exception Registers access */
964 # define DAR_sig(context) REG_sig(dar, context)
965 # define DSISR_sig(context) REG_sig(dsisr, context)
966 # define TRAP_sig(context) REG_sig(trap, context)
967 #endif /* linux */
968
969 #ifdef __APPLE__
970 # include <sys/ucontext.h>
971 typedef struct ucontext SIGCONTEXT;
972 /* All Registers access - only for local access */
973 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
974 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
975 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
976 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
977 /* Gpr Registers access */
978 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
979 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
980 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
981 # define CTR_sig(context) REG_sig(ctr, context)
982 # define XER_sig(context) REG_sig(xer, context) /* Link register */
983 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
984 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
985 /* Float Registers access */
986 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
987 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
988 /* Exception Registers access */
989 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
990 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
991 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
992 #endif /* __APPLE__ */
993
994 int cpu_signal_handler(int host_signum, struct siginfo *info,
995 void *puc)
996 {
997 struct ucontext *uc = puc;
998 unsigned long pc;
999 int is_write;
1000
1001 pc = IAR_sig(uc);
1002 is_write = 0;
1003 #if 0
1004 /* ppc 4xx case */
1005 if (DSISR_sig(uc) & 0x00800000)
1006 is_write = 1;
1007 #else
1008 if (TRAP_sig(uc) != 0x400 && (DSISR_sig(uc) & 0x02000000))
1009 is_write = 1;
1010 #endif
1011 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1012 is_write, &uc->uc_sigmask, puc);
1013 }
1014
1015 #elif defined(__alpha__)
1016
1017 int cpu_signal_handler(int host_signum, struct siginfo *info,
1018 void *puc)
1019 {
1020 struct ucontext *uc = puc;
1021 uint32_t *pc = uc->uc_mcontext.sc_pc;
1022 uint32_t insn = *pc;
1023 int is_write = 0;
1024
1025 /* XXX: need kernel patch to get write flag faster */
1026 switch (insn >> 26) {
1027 case 0x0d: // stw
1028 case 0x0e: // stb
1029 case 0x0f: // stq_u
1030 case 0x24: // stf
1031 case 0x25: // stg
1032 case 0x26: // sts
1033 case 0x27: // stt
1034 case 0x2c: // stl
1035 case 0x2d: // stq
1036 case 0x2e: // stl_c
1037 case 0x2f: // stq_c
1038 is_write = 1;
1039 }
1040
1041 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1042 is_write, &uc->uc_sigmask, puc);
1043 }
1044 #elif defined(__sparc__)
1045
1046 int cpu_signal_handler(int host_signum, struct siginfo *info,
1047 void *puc)
1048 {
1049 uint32_t *regs = (uint32_t *)(info + 1);
1050 void *sigmask = (regs + 20);
1051 unsigned long pc;
1052 int is_write;
1053 uint32_t insn;
1054
1055 /* XXX: is there a standard glibc define ? */
1056 pc = regs[1];
1057 /* XXX: need kernel patch to get write flag faster */
1058 is_write = 0;
1059 insn = *(uint32_t *)pc;
1060 if ((insn >> 30) == 3) {
1061 switch((insn >> 19) & 0x3f) {
1062 case 0x05: // stb
1063 case 0x06: // sth
1064 case 0x04: // st
1065 case 0x07: // std
1066 case 0x24: // stf
1067 case 0x27: // stdf
1068 case 0x25: // stfsr
1069 is_write = 1;
1070 break;
1071 }
1072 }
1073 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1074 is_write, sigmask, NULL);
1075 }
1076
1077 #elif defined(__arm__)
1078
1079 int cpu_signal_handler(int host_signum, struct siginfo *info,
1080 void *puc)
1081 {
1082 struct ucontext *uc = puc;
1083 unsigned long pc;
1084 int is_write;
1085
1086 pc = uc->uc_mcontext.gregs[R15];
1087 /* XXX: compute is_write */
1088 is_write = 0;
1089 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1090 is_write,
1091 &uc->uc_sigmask);
1092 }
1093
1094 #elif defined(__mc68000)
1095
1096 int cpu_signal_handler(int host_signum, struct siginfo *info,
1097 void *puc)
1098 {
1099 struct ucontext *uc = puc;
1100 unsigned long pc;
1101 int is_write;
1102
1103 pc = uc->uc_mcontext.gregs[16];
1104 /* XXX: compute is_write */
1105 is_write = 0;
1106 return handle_cpu_signal(pc, (unsigned long)info->si_addr,
1107 is_write,
1108 &uc->uc_sigmask, puc);
1109 }
1110
1111 #else
1112
1113 #error host CPU specific signal handler needed
1114
1115 #endif
1116
1117 #endif /* !defined(CONFIG_SOFTMMU) */
Qemu copy for testing