cpu-exec.c

   1 /*
   2  *  i386 emulator main execution loop
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #include "config.h"
  21 #ifdef TARGET_I386
  22 #include "exec-i386.h"
  23 #endif
  24 #ifdef TARGET_ARM
  25 #include "exec-arm.h"
  26 #endif
  27
  28 #include "disas.h"
  29
  30 //#define DEBUG_EXEC
  31 //#define DEBUG_SIGNAL
  32
  33 #if defined(TARGET_ARM)
  34 /* XXX: unify with i386 target */
  35 void cpu_loop_exit(void)
  36 {
  37     longjmp(env->jmp_env, 1);
  38 }
  39 #endif
  40
  41 /* main execution loop */
  42
  43 int cpu_exec(CPUState *env1)
  44 {
  45     int saved_T0, saved_T1, saved_T2;
  46     CPUState *saved_env;
  47 #ifdef reg_EAX
  48     int saved_EAX;
  49 #endif
  50 #ifdef reg_ECX
  51     int saved_ECX;
  52 #endif
  53 #ifdef reg_EDX
  54     int saved_EDX;
  55 #endif
  56 #ifdef reg_EBX
  57     int saved_EBX;
  58 #endif
  59 #ifdef reg_ESP
  60     int saved_ESP;
  61 #endif
  62 #ifdef reg_EBP
  63     int saved_EBP;
  64 #endif
  65 #ifdef reg_ESI
  66     int saved_ESI;
  67 #endif
  68 #ifdef reg_EDI
  69     int saved_EDI;
  70 #endif
  71 #ifdef __sparc__
  72     int saved_i7, tmp_T0;
  73 #endif
  74     int code_gen_size, ret, interrupt_request;
  75     void (*gen_func)(void);
  76     TranslationBlock *tb, **ptb;
  77     uint8_t *tc_ptr, *cs_base, *pc;
  78     unsigned int flags;
  79
  80     /* first we save global registers */
  81     saved_T0 = T0;
  82     saved_T1 = T1;
  83     saved_T2 = T2;
  84     saved_env = env;
  85     env = env1;
  86 #ifdef __sparc__
  87     /* we also save i7 because longjmp may not restore it */
  88     asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
  89 #endif
  90
  91 #if defined(TARGET_I386)
  92 #ifdef reg_EAX
  93     saved_EAX = EAX;
  94     EAX = env->regs[R_EAX];
  95 #endif
  96 #ifdef reg_ECX
  97     saved_ECX = ECX;
  98     ECX = env->regs[R_ECX];
  99 #endif
 100 #ifdef reg_EDX
 101     saved_EDX = EDX;
 102     EDX = env->regs[R_EDX];
 103 #endif
 104 #ifdef reg_EBX
 105     saved_EBX = EBX;
 106     EBX = env->regs[R_EBX];
 107 #endif
 108 #ifdef reg_ESP
 109     saved_ESP = ESP;
 110     ESP = env->regs[R_ESP];
 111 #endif
 112 #ifdef reg_EBP
 113     saved_EBP = EBP;
 114     EBP = env->regs[R_EBP];
 115 #endif
 116 #ifdef reg_ESI
 117     saved_ESI = ESI;
 118     ESI = env->regs[R_ESI];
 119 #endif
 120 #ifdef reg_EDI
 121     saved_EDI = EDI;
 122     EDI = env->regs[R_EDI];
 123 #endif
 124
 125     /* put eflags in CPU temporary format */
 126     CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 127     DF = 1 - (2 * ((env->eflags >> 10) & 1));
 128     CC_OP = CC_OP_EFLAGS;
 129     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 130 #elif defined(TARGET_ARM)
 131     {
 132         unsigned int psr;
 133         psr = env->cpsr;
 134         env->CF = (psr >> 29) & 1;
 135         env->NZF = (psr & 0xc0000000) ^ 0x40000000;
 136         env->VF = (psr << 3) & 0x80000000;
 137         env->cpsr = psr & ~0xf0000000;
 138     }
 139 #else
 140 #error unsupported target CPU
 141 #endif
 142     env->exception_index = -1;
 143
 144     /* prepare setjmp context for exception handling */
 145     for(;;) {
 146         if (setjmp(env->jmp_env) == 0) {
 147             /* if an exception is pending, we execute it here */
 148             if (env->exception_index >= 0) {
 149                 if (env->exception_index >= EXCP_INTERRUPT) {
 150                     /* exit request from the cpu execution loop */
 151                     ret = env->exception_index;
 152                     break;
 153                 } else if (env->user_mode_only) {
 154                     /* if user mode only, we simulate a fake exception
 155                        which will be hanlded outside the cpu execution
 156                        loop */
 157 #if defined(TARGET_I386)
 158                     do_interrupt_user(env->exception_index,
 159                                       env->exception_is_int,
 160                                       env->error_code,
 161                                       env->exception_next_eip);
 162 #endif
 163                     ret = env->exception_index;
 164                     break;
 165                 } else {
 166 #if defined(TARGET_I386)
 167                     /* simulate a real cpu exception. On i386, it can
 168                        trigger new exceptions, but we do not handle
 169                        double or triple faults yet. */
 170                     do_interrupt(env->exception_index,
 171                                  env->exception_is_int,
 172                                  env->error_code,
 173                                  env->exception_next_eip, 0);
 174 #endif
 175                 }
 176                 env->exception_index = -1;
 177             }
 178             T0 = 0; /* force lookup of first TB */
 179             for(;;) {
 180 #ifdef __sparc__
 181                 /* g1 can be modified by some libc? functions */
 182                 tmp_T0 = T0;
 183 #endif
 184                 interrupt_request = env->interrupt_request;
 185                 if (interrupt_request) {
 186 #if defined(TARGET_I386)
 187                     /* if hardware interrupt pending, we execute it */
 188                     if ((interrupt_request & CPU_INTERRUPT_HARD) &&
 189                         (env->eflags & IF_MASK)) {
 190                         int intno;
 191                         intno = cpu_x86_get_pic_interrupt(env);
 192                         if (loglevel) {
 193                             fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno);
 194                         }
 195                         do_interrupt(intno, 0, 0, 0, 1);
 196                         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
 197                         /* ensure that no TB jump will be modified as
 198                            the program flow was changed */
 199 #ifdef __sparc__
 200                         tmp_T0 = 0;
 201 #else
 202                         T0 = 0;
 203 #endif
 204                     }
 205 #endif
 206                     if (interrupt_request & CPU_INTERRUPT_EXIT) {
 207                         env->interrupt_request &= ~CPU_INTERRUPT_EXIT;
 208                         env->exception_index = EXCP_INTERRUPT;
 209                         cpu_loop_exit();
 210                     }
 211                 }
 212 #ifdef DEBUG_EXEC
 213                 if (loglevel) {
 214 #if defined(TARGET_I386)
 215                     /* restore flags in standard format */
 216                     env->regs[R_EAX] = EAX;
 217                     env->regs[R_EBX] = EBX;
 218                     env->regs[R_ECX] = ECX;
 219                     env->regs[R_EDX] = EDX;
 220                     env->regs[R_ESI] = ESI;
 221                     env->regs[R_EDI] = EDI;
 222                     env->regs[R_EBP] = EBP;
 223                     env->regs[R_ESP] = ESP;
 224                     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 225                     cpu_x86_dump_state(env, logfile, X86_DUMP_CCOP);
 226                     env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
 227 #elif defined(TARGET_ARM)
 228                     env->cpsr = compute_cpsr();
 229                     cpu_arm_dump_state(env, logfile, 0);
 230                     env->cpsr &= ~0xf0000000;
 231 #else
 232 #error unsupported target CPU
 233 #endif
 234                 }
 235 #endif
 236                 /* we compute the CPU state. We assume it will not
 237                    change during the whole generated block. */
 238 #if defined(TARGET_I386)
 239                 flags = (env->segs[R_CS].flags & DESC_B_MASK)
 240                     >> (DESC_B_SHIFT - GEN_FLAG_CODE32_SHIFT);
 241                 flags |= (env->segs[R_SS].flags & DESC_B_MASK)
 242                     >> (DESC_B_SHIFT - GEN_FLAG_SS32_SHIFT);
 243                 flags |= (((unsigned long)env->segs[R_DS].base |
 244                            (unsigned long)env->segs[R_ES].base |
 245                            (unsigned long)env->segs[R_SS].base) != 0) <<
 246                     GEN_FLAG_ADDSEG_SHIFT;
 247                 flags |= env->cpl << GEN_FLAG_CPL_SHIFT;
 248                 flags |= env->soft_mmu << GEN_FLAG_SOFT_MMU_SHIFT;
 249                 flags |= (env->eflags & VM_MASK) >> (17 - GEN_FLAG_VM_SHIFT);
 250                 flags |= (env->eflags & (IOPL_MASK | TF_MASK));
 251                 cs_base = env->segs[R_CS].base;
 252                 pc = cs_base + env->eip;
 253 #elif defined(TARGET_ARM)
 254                 flags = 0;
 255                 cs_base = 0;
 256                 pc = (uint8_t *)env->regs[15];
 257 #else
 258 #error unsupported CPU
 259 #endif
 260                 tb = tb_find(&ptb, (unsigned long)pc, (unsigned long)cs_base,
 261                              flags);
 262                 if (!tb) {
 263                     spin_lock(&tb_lock);
 264                     /* if no translated code available, then translate it now */
 265                     tb = tb_alloc((unsigned long)pc);
 266                     if (!tb) {
 267                         /* flush must be done */
 268                         tb_flush();
 269                         /* cannot fail at this point */
 270                         tb = tb_alloc((unsigned long)pc);
 271                         /* don't forget to invalidate previous TB info */
 272                         ptb = &tb_hash[tb_hash_func((unsigned long)pc)];
 273                         T0 = 0;
 274                     }
 275                     tc_ptr = code_gen_ptr;
 276                     tb->tc_ptr = tc_ptr;
 277                     tb->cs_base = (unsigned long)cs_base;
 278                     tb->flags = flags;
 279                     ret = cpu_gen_code(env, tb, CODE_GEN_MAX_SIZE, &code_gen_size);
 280 #if defined(TARGET_I386)
 281                     /* XXX: suppress that, this is incorrect */
 282                     /* if invalid instruction, signal it */
 283                     if (ret != 0) {
 284                         /* NOTE: the tb is allocated but not linked, so we
 285                            can leave it */
 286                         spin_unlock(&tb_lock);
 287                         raise_exception(EXCP06_ILLOP);
 288                     }
 289 #endif
 290                     *ptb = tb;
 291                     tb->hash_next = NULL;
 292                     tb_link(tb);
 293                     code_gen_ptr = (void *)(((unsigned long)code_gen_ptr + code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
 294                     spin_unlock(&tb_lock);
 295                 }
 296 #ifdef DEBUG_EXEC
 297                 if (loglevel) {
 298                     fprintf(logfile, "Trace 0x%08lx [0x%08lx] %s\n",
 299                             (long)tb->tc_ptr, (long)tb->pc,
 300                             lookup_symbol((void *)tb->pc));
 301                 }
 302 #endif
 303 #ifdef __sparc__
 304                 T0 = tmp_T0;
 305 #endif
 306                 /* see if we can patch the calling TB. XXX: remove TF test */
 307                 if (T0 != 0
 308 #if defined(TARGET_I386)
 309                     && !(env->eflags & TF_MASK)
 310 #endif
 311                     ) {
 312                     spin_lock(&tb_lock);
 313                     tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
 314                     spin_unlock(&tb_lock);
 315                 }
 316                 tc_ptr = tb->tc_ptr;
 317                 env->current_tb = tb;
 318                 /* execute the generated code */
 319                 gen_func = (void *)tc_ptr;
 320 #if defined(__sparc__)
 321                 __asm__ __volatile__("call      %0\n\t"
 322                                      "mov       %%o7,%%i0"
 323                                      : /* no outputs */
 324                                      : "r" (gen_func)
 325                                      : "i0", "i1", "i2", "i3", "i4", "i5");
 326 #elif defined(__arm__)
 327                 asm volatile ("mov pc, %0\n\t"
 328                               ".global exec_loop\n\t"
 329                               "exec_loop:\n\t"
 330                               : /* no outputs */
 331                               : "r" (gen_func)
 332                               : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
 333 #else
 334                 gen_func();
 335 #endif
 336                 env->current_tb = NULL;
 337                 /* reset soft MMU for next block (it can currently
 338                    only be set by a memory fault) */
 339 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU)
 340                 if (env->soft_mmu) {
 341                     env->soft_mmu = 0;
 342                     /* do not allow linking to another block */
 343                     T0 = 0;
 344                 }
 345 #endif
 346             }
 347         } else {
 348         }
 349     } /* for(;;) */
 350
 351
 352 #if defined(TARGET_I386)
 353     /* restore flags in standard format */
 354     env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK);
 355
 356     /* restore global registers */
 357 #ifdef reg_EAX
 358     EAX = saved_EAX;
 359 #endif
 360 #ifdef reg_ECX
 361     ECX = saved_ECX;
 362 #endif
 363 #ifdef reg_EDX
 364     EDX = saved_EDX;
 365 #endif
 366 #ifdef reg_EBX
 367     EBX = saved_EBX;
 368 #endif
 369 #ifdef reg_ESP
 370     ESP = saved_ESP;
 371 #endif
 372 #ifdef reg_EBP
 373     EBP = saved_EBP;
 374 #endif
 375 #ifdef reg_ESI
 376     ESI = saved_ESI;
 377 #endif
 378 #ifdef reg_EDI
 379     EDI = saved_EDI;
 380 #endif
 381 #elif defined(TARGET_ARM)
 382     env->cpsr = compute_cpsr();
 383 #else
 384 #error unsupported target CPU
 385 #endif
 386 #ifdef __sparc__
 387     asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
 388 #endif
 389     T0 = saved_T0;
 390     T1 = saved_T1;
 391     T2 = saved_T2;
 392     env = saved_env;
 393     return ret;
 394 }
 395
 396 #if defined(TARGET_I386)
 397
 398 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector)
 399 {
 400     CPUX86State *saved_env;
 401
 402     saved_env = env;
 403     env = s;
 404     if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 405         SegmentCache *sc;
 406         selector &= 0xffff;
 407         sc = &env->segs[seg_reg];
 408         sc->base = (void *)(selector << 4);
 409         sc->limit = 0xffff;
 410         sc->flags = 0;
 411         sc->selector = selector;
 412     } else {
 413         load_seg(seg_reg, selector, 0);
 414     }
 415     env = saved_env;
 416 }
 417
 418 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32)
 419 {
 420     CPUX86State *saved_env;
 421
 422     saved_env = env;
 423     env = s;
 424
 425     helper_fsave(ptr, data32);
 426
 427     env = saved_env;
 428 }
 429
 430 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32)
 431 {
 432     CPUX86State *saved_env;
 433
 434     saved_env = env;
 435     env = s;
 436
 437     helper_frstor(ptr, data32);
 438
 439     env = saved_env;
 440 }
 441
 442 #endif /* TARGET_I386 */
 443
 444 #undef EAX
 445 #undef ECX
 446 #undef EDX
 447 #undef EBX
 448 #undef ESP
 449 #undef EBP
 450 #undef ESI
 451 #undef EDI
 452 #undef EIP
 453 #include <signal.h>
 454 #include <sys/ucontext.h>
 455
 456 #if defined(TARGET_I386)
 457
 458 /* 'pc' is the host PC at which the exception was raised. 'address' is
 459    the effective address of the memory exception. 'is_write' is 1 if a
 460    write caused the exception and otherwise 0'. 'old_set' is the
 461    signal set which should be restored */
 462 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 463                                     int is_write, sigset_t *old_set)
 464 {
 465     TranslationBlock *tb;
 466     int ret;
 467
 468     if (cpu_single_env)
 469         env = cpu_single_env; /* XXX: find a correct solution for multithread */
 470 #if defined(DEBUG_SIGNAL)
 471     printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
 472            pc, address, is_write, *(unsigned long *)old_set);
 473 #endif
 474     /* XXX: locking issue */
 475     if (is_write && page_unprotect(address)) {
 476         return 1;
 477     }
 478     /* see if it is an MMU fault */
 479     ret = cpu_x86_handle_mmu_fault(env, address, is_write);
 480     if (ret < 0)
 481         return 0; /* not an MMU fault */
 482     if (ret == 0)
 483         return 1; /* the MMU fault was handled without causing real CPU fault */
 484     /* now we have a real cpu fault */
 485     tb = tb_find_pc(pc);
 486     if (tb) {
 487         /* the PC is inside the translated code. It means that we have
 488            a virtual CPU fault */
 489         cpu_restore_state(tb, env, pc);
 490     }
 491     if (ret == 1) {
 492 #if 0
 493         printf("PF exception: EIP=0x%08x CR2=0x%08x error=0x%x\n",
 494                env->eip, env->cr[2], env->error_code);
 495 #endif
 496         /* we restore the process signal mask as the sigreturn should
 497            do it (XXX: use sigsetjmp) */
 498         sigprocmask(SIG_SETMASK, old_set, NULL);
 499         raise_exception_err(EXCP0E_PAGE, env->error_code);
 500     } else {
 501         /* activate soft MMU for this block */
 502         env->soft_mmu = 1;
 503         sigprocmask(SIG_SETMASK, old_set, NULL);
 504         cpu_loop_exit();
 505     }
 506     /* never comes here */
 507     return 1;
 508 }
 509
 510 #elif defined(TARGET_ARM)
 511 static inline int handle_cpu_signal(unsigned long pc, unsigned long address,
 512                                     int is_write, sigset_t *old_set)
 513 {
 514     /* XXX: do more */
 515     return 0;
 516 }
 517 #else
 518 #error unsupported target CPU
 519 #endif
 520
 521 #if defined(__i386__)
 522
 523 int cpu_signal_handler(int host_signum, struct siginfo *info,
 524                        void *puc)
 525 {
 526     struct ucontext *uc = puc;
 527     unsigned long pc;
 528
 529 #ifndef REG_EIP
 530 /* for glibc 2.1 */
 531 #define REG_EIP    EIP
 532 #define REG_ERR    ERR
 533 #define REG_TRAPNO TRAPNO
 534 #endif
 535     pc = uc->uc_mcontext.gregs[REG_EIP];
 536     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 537                              uc->uc_mcontext.gregs[REG_TRAPNO] == 0xe ?
 538                              (uc->uc_mcontext.gregs[REG_ERR] >> 1) & 1 : 0,
 539                              &uc->uc_sigmask);
 540 }
 541
 542 #elif defined(__powerpc)
 543
 544 int cpu_signal_handler(int host_signum, struct siginfo *info,
 545                        void *puc)
 546 {
 547     struct ucontext *uc = puc;
 548     struct pt_regs *regs = uc->uc_mcontext.regs;
 549     unsigned long pc;
 550     int is_write;
 551
 552     pc = regs->nip;
 553     is_write = 0;
 554 #if 0
 555     /* ppc 4xx case */
 556     if (regs->dsisr & 0x00800000)
 557         is_write = 1;
 558 #else
 559     if (regs->trap != 0x400 && (regs->dsisr & 0x02000000))
 560         is_write = 1;
 561 #endif
 562     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 563                              is_write, &uc->uc_sigmask);
 564 }
 565
 566 #elif defined(__alpha__)
 567
 568 int cpu_signal_handler(int host_signum, struct siginfo *info,
 569                            void *puc)
 570 {
 571     struct ucontext *uc = puc;
 572     uint32_t *pc = uc->uc_mcontext.sc_pc;
 573     uint32_t insn = *pc;
 574     int is_write = 0;
 575
 576     /* XXX: need kernel patch to get write flag faster */
 577     switch (insn >> 26) {
 578     case 0x0d: // stw
 579     case 0x0e: // stb
 580     case 0x0f: // stq_u
 581     case 0x24: // stf
 582     case 0x25: // stg
 583     case 0x26: // sts
 584     case 0x27: // stt
 585     case 0x2c: // stl
 586     case 0x2d: // stq
 587     case 0x2e: // stl_c
 588     case 0x2f: // stq_c
 589         is_write = 1;
 590     }
 591
 592     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 593                              is_write, &uc->uc_sigmask);
 594 }
 595 #elif defined(__sparc__)
 596
 597 int cpu_signal_handler(int host_signum, struct siginfo *info,
 598                        void *puc)
 599 {
 600     uint32_t *regs = (uint32_t *)(info + 1);
 601     void *sigmask = (regs + 20);
 602     unsigned long pc;
 603     int is_write;
 604     uint32_t insn;
 605
 606     /* XXX: is there a standard glibc define ? */
 607     pc = regs[1];
 608     /* XXX: need kernel patch to get write flag faster */
 609     is_write = 0;
 610     insn = *(uint32_t *)pc;
 611     if ((insn >> 30) == 3) {
 612       switch((insn >> 19) & 0x3f) {
 613       case 0x05: // stb
 614       case 0x06: // sth
 615       case 0x04: // st
 616       case 0x07: // std
 617       case 0x24: // stf
 618       case 0x27: // stdf
 619       case 0x25: // stfsr
 620         is_write = 1;
 621         break;
 622       }
 623     }
 624     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 625                              is_write, sigmask);
 626 }
 627
 628 #elif defined(__arm__)
 629
 630 int cpu_signal_handler(int host_signum, struct siginfo *info,
 631                        void *puc)
 632 {
 633     struct ucontext *uc = puc;
 634     unsigned long pc;
 635     int is_write;
 636
 637     pc = uc->uc_mcontext.gregs[R15];
 638     /* XXX: compute is_write */
 639     is_write = 0;
 640     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 641                              is_write,
 642                              &uc->uc_sigmask);
 643 }
 644
 645 #elif defined(__mc68000)
 646
 647 int cpu_signal_handler(int host_signum, struct siginfo *info,
 648                        void *puc)
 649 {
 650     struct ucontext *uc = puc;
 651     unsigned long pc;
 652     int is_write;
 653
 654     pc = uc->uc_mcontext.gregs[16];
 655     /* XXX: compute is_write */
 656     is_write = 0;
 657     return handle_cpu_signal(pc, (unsigned long)info->si_addr,
 658                              is_write,
 659                              &uc->uc_sigmask);
 660 }
 661
 662 #else
 663
 664 #error host CPU specific signal handler needed
 665
 666 #endif