cpu-i386.h

   1 /*
   2  * i386 virtual CPU header
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20 #ifndef CPU_I386_H
  21 #define CPU_I386_H
  22
  23 #include "config.h"
  24 #include <setjmp.h>
  25
  26 #define R_EAX 0
  27 #define R_ECX 1
  28 #define R_EDX 2
  29 #define R_EBX 3
  30 #define R_ESP 4
  31 #define R_EBP 5
  32 #define R_ESI 6
  33 #define R_EDI 7
  34
  35 #define R_AL 0
  36 #define R_CL 1
  37 #define R_DL 2
  38 #define R_BL 3
  39 #define R_AH 4
  40 #define R_CH 5
  41 #define R_DH 6
  42 #define R_BH 7
  43
  44 #define R_ES 0
  45 #define R_CS 1
  46 #define R_SS 2
  47 #define R_DS 3
  48 #define R_FS 4
  49 #define R_GS 5
  50
  51 /* segment descriptor fields */
  52 #define DESC_G_MASK     (1 << 23)
  53 #define DESC_B_SHIFT    22
  54 #define DESC_B_MASK     (1 << DESC_B_SHIFT)
  55 #define DESC_AVL_MASK   (1 << 20)
  56 #define DESC_P_MASK     (1 << 15)
  57 #define DESC_DPL_SHIFT  13
  58 #define DESC_S_MASK     (1 << 12)
  59 #define DESC_TYPE_SHIFT 8
  60 #define DESC_A_MASK     (1 << 8)
  61
  62 #define DESC_CS_MASK    (1 << 11)
  63 #define DESC_C_MASK     (1 << 10)
  64 #define DESC_R_MASK     (1 << 9)
  65
  66 #define DESC_E_MASK     (1 << 10)
  67 #define DESC_W_MASK     (1 << 9)
  68
  69 /* eflags masks */
  70 #define CC_C    0x0001
  71 #define CC_P    0x0004
  72 #define CC_A    0x0010
  73 #define CC_Z    0x0040
  74 #define CC_S    0x0080
  75 #define CC_O    0x0800
  76
  77 #define TF_MASK                 0x00000100
  78 #define IF_MASK                 0x00000200
  79 #define DF_MASK                 0x00000400
  80 #define IOPL_MASK               0x00003000
  81 #define NT_MASK                 0x00004000
  82 #define RF_MASK                 0x00010000
  83 #define VM_MASK                 0x00020000
  84 #define AC_MASK                 0x00040000
  85 #define VIF_MASK                0x00080000
  86 #define VIP_MASK                0x00100000
  87 #define ID_MASK                 0x00200000
  88
  89 #define CR0_PE_MASK  (1 << 0)
  90 #define CR0_TS_MASK  (1 << 3)
  91 #define CR0_WP_MASK  (1 << 16)
  92 #define CR0_AM_MASK  (1 << 18)
  93 #define CR0_PG_MASK  (1 << 31)
  94
  95 #define CR4_VME_MASK  (1 << 0)
  96 #define CR4_PVI_MASK  (1 << 1)
  97 #define CR4_TSD_MASK  (1 << 2)
  98 #define CR4_DE_MASK   (1 << 3)
  99 #define CR4_PSE_MASK  (1 << 4)
 100
 101 #define PG_PRESENT_BIT  0
 102 #define PG_RW_BIT       1
 103 #define PG_USER_BIT     2
 104 #define PG_PWT_BIT      3
 105 #define PG_PCD_BIT      4
 106 #define PG_ACCESSED_BIT 5
 107 #define PG_DIRTY_BIT    6
 108 #define PG_PSE_BIT      7
 109 #define PG_GLOBAL_BIT   8
 110
 111 #define PG_PRESENT_MASK  (1 << PG_PRESENT_BIT)
 112 #define PG_RW_MASK       (1 << PG_RW_BIT)
 113 #define PG_USER_MASK     (1 << PG_USER_BIT)
 114 #define PG_PWT_MASK      (1 << PG_PWT_BIT)
 115 #define PG_PCD_MASK      (1 << PG_PCD_BIT)
 116 #define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 117 #define PG_DIRTY_MASK    (1 << PG_DIRTY_BIT)
 118 #define PG_PSE_MASK      (1 << PG_PSE_BIT)
 119 #define PG_GLOBAL_MASK   (1 << PG_GLOBAL_BIT)
 120
 121 #define PG_ERROR_W_BIT     1
 122
 123 #define PG_ERROR_P_MASK    0x01
 124 #define PG_ERROR_W_MASK    (1 << PG_ERROR_W_BIT)
 125 #define PG_ERROR_U_MASK    0x04
 126 #define PG_ERROR_RSVD_MASK 0x08
 127
 128 #define MSR_IA32_APICBASE               0x1b
 129 #define MSR_IA32_APICBASE_BSP           (1<<8)
 130 #define MSR_IA32_APICBASE_ENABLE        (1<<11)
 131 #define MSR_IA32_APICBASE_BASE          (0xfffff<<12)
 132
 133 #define MSR_IA32_SYSENTER_CS            0x174
 134 #define MSR_IA32_SYSENTER_ESP           0x175
 135 #define MSR_IA32_SYSENTER_EIP           0x176
 136
 137 #define EXCP00_DIVZ     0
 138 #define EXCP01_SSTP     1
 139 #define EXCP02_NMI      2
 140 #define EXCP03_INT3     3
 141 #define EXCP04_INTO     4
 142 #define EXCP05_BOUND    5
 143 #define EXCP06_ILLOP    6
 144 #define EXCP07_PREX     7
 145 #define EXCP08_DBLE     8
 146 #define EXCP09_XERR     9
 147 #define EXCP0A_TSS      10
 148 #define EXCP0B_NOSEG    11
 149 #define EXCP0C_STACK    12
 150 #define EXCP0D_GPF      13
 151 #define EXCP0E_PAGE     14
 152 #define EXCP10_COPR     16
 153 #define EXCP11_ALGN     17
 154 #define EXCP12_MCHK     18
 155
 156 #define EXCP_INTERRUPT  256 /* async interruption */
 157 #define EXCP_HLT        257 /* hlt instruction reached */
 158 #define EXCP_DEBUG      258 /* cpu stopped after a breakpoint or singlestep */
 159
 160 #define MAX_BREAKPOINTS 32
 161
 162 enum {
 163     CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 164     CC_OP_EFLAGS,  /* all cc are explicitely computed, CC_SRC = flags */
 165     CC_OP_MUL, /* modify all flags, C, O = (CC_SRC != 0) */
 166
 167     CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 168     CC_OP_ADDW,
 169     CC_OP_ADDL,
 170
 171     CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 172     CC_OP_ADCW,
 173     CC_OP_ADCL,
 174
 175     CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 176     CC_OP_SUBW,
 177     CC_OP_SUBL,
 178
 179     CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */
 180     CC_OP_SBBW,
 181     CC_OP_SBBL,
 182
 183     CC_OP_LOGICB, /* modify all flags, CC_DST = res */
 184     CC_OP_LOGICW,
 185     CC_OP_LOGICL,
 186
 187     CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */
 188     CC_OP_INCW,
 189     CC_OP_INCL,
 190
 191     CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C  */
 192     CC_OP_DECW,
 193     CC_OP_DECL,
 194
 195     CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 196     CC_OP_SHLW,
 197     CC_OP_SHLL,
 198
 199     CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */
 200     CC_OP_SARW,
 201     CC_OP_SARL,
 202
 203     CC_OP_NB,
 204 };
 205
 206 #ifdef __i386__
 207 #define USE_X86LDOUBLE
 208 #endif
 209
 210 #ifdef USE_X86LDOUBLE
 211 typedef long double CPU86_LDouble;
 212 #else
 213 typedef double CPU86_LDouble;
 214 #endif
 215
 216 typedef struct SegmentCache {
 217     uint32_t selector;
 218     uint8_t *base;
 219     uint32_t limit;
 220     uint32_t flags;
 221 } SegmentCache;
 222
 223 typedef struct CPUX86State {
 224     /* standard registers */
 225     uint32_t regs[8];
 226     uint32_t eip;
 227     uint32_t eflags; /* eflags register. During CPU emulation, CC
 228                         flags and DF are set to zero because they are
 229                         stored elsewhere */
 230
 231     /* emulator internal eflags handling */
 232     uint32_t cc_src;
 233     uint32_t cc_dst;
 234     uint32_t cc_op;
 235     int32_t df; /* D flag : 1 if D = 0, -1 if D = 1 */
 236
 237     /* FPU state */
 238     unsigned int fpstt; /* top of stack index */
 239     unsigned int fpus;
 240     unsigned int fpuc;
 241     uint8_t fptags[8];   /* 0 = valid, 1 = empty */
 242     CPU86_LDouble fpregs[8];
 243
 244     /* emulator internal variables */
 245     CPU86_LDouble ft0;
 246     union {
 247         float f;
 248         double d;
 249         int i32;
 250         int64_t i64;
 251     } fp_convert;
 252
 253     /* segments */
 254     SegmentCache segs[6]; /* selector values */
 255     SegmentCache ldt;
 256     SegmentCache tr;
 257     SegmentCache gdt; /* only base and limit are used */
 258     SegmentCache idt; /* only base and limit are used */
 259     int cpl;          /* current cpl */
 260
 261     /* sysenter registers */
 262     uint32_t sysenter_cs;
 263     uint32_t sysenter_esp;
 264     uint32_t sysenter_eip;
 265
 266     /* exception/interrupt handling */
 267     jmp_buf jmp_env;
 268     int exception_index;
 269     int error_code;
 270     int exception_is_int;
 271     int exception_next_eip;
 272     struct TranslationBlock *current_tb; /* currently executing TB */
 273     uint32_t cr[5]; /* NOTE: cr1 is unused */
 274     uint32_t dr[8]; /* debug registers */
 275     int interrupt_request;
 276     int user_mode_only; /* user mode only simulation */
 277
 278     uint32_t breakpoints[MAX_BREAKPOINTS];
 279     int nb_breakpoints;
 280     int singlestep_enabled;
 281
 282     /* user data */
 283     void *opaque;
 284 } CPUX86State;
 285
 286 #ifndef IN_OP_I386
 287 void cpu_x86_outb(CPUX86State *env, int addr, int val);
 288 void cpu_x86_outw(CPUX86State *env, int addr, int val);
 289 void cpu_x86_outl(CPUX86State *env, int addr, int val);
 290 int cpu_x86_inb(CPUX86State *env, int addr);
 291 int cpu_x86_inw(CPUX86State *env, int addr);
 292 int cpu_x86_inl(CPUX86State *env, int addr);
 293 #endif
 294
 295 CPUX86State *cpu_x86_init(void);
 296 int cpu_x86_exec(CPUX86State *s);
 297 void cpu_x86_close(CPUX86State *s);
 298 int cpu_x86_get_pic_interrupt(CPUX86State *s);
 299
 300 /* needed to load some predefinied segment registers */
 301 void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
 302
 303 /* wrapper, just in case memory mappings must be changed */
 304 static inline void cpu_x86_set_cpl(CPUX86State *s, int cpl)
 305 {
 306     s->cpl = cpl;
 307 }
 308
 309 /* simulate fsave/frstor */
 310 void cpu_x86_fsave(CPUX86State *s, uint8_t *ptr, int data32);
 311 void cpu_x86_frstor(CPUX86State *s, uint8_t *ptr, int data32);
 312
 313 /* you can call this signal handler from your SIGBUS and SIGSEGV
 314    signal handlers to inform the virtual CPU of exceptions. non zero
 315    is returned if the signal was handled by the virtual CPU.  */
 316 struct siginfo;
 317 int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
 318                            void *puc);
 319
 320 /* MMU defines */
 321 void cpu_x86_init_mmu(CPUX86State *env);
 322 extern int phys_ram_size;
 323 extern int phys_ram_fd;
 324 extern uint8_t *phys_ram_base;
 325
 326 /* used to debug */
 327 #define X86_DUMP_FPU  0x0001 /* dump FPU state too */
 328 #define X86_DUMP_CCOP 0x0002 /* dump qemu flag cache */
 329 void cpu_x86_dump_state(CPUX86State *env, FILE *f, int flags);
 330
 331 #define TARGET_PAGE_BITS 12
 332 #include "cpu-all.h"
 333
 334 #endif /* CPU_I386_H */