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1 /* Disassembler code for CRIS.
2 Copyright 2000, 2001, 2002, 2004, 2005, 2006 Free Software Foundation, Inc.
3 Contributed by Axis Communications AB, Lund, Sweden.
4 Written by Hans-Peter Nilsson.
5
6 This file is part of the GNU binutils and GDB, the GNU debugger.
7
8 This program is free software; you can redistribute it and/or modify it
9 under the terms of the GNU General Public License as published by the
10 Free Software Foundation; either version 2, or (at your option) any later
11 version.
12
13 This program is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
16 more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; if not, see <http://www.gnu.org/licenses/>. */
20
21 #include "qemu-common.h"
22 #include "dis-asm.h"
23 //#include "sysdep.h"
24 #include "target-cris/opcode-cris.h"
25 //#include "libiberty.h"
26
27 #define CONST_STRNEQ(STR1,STR2) (strncmp ((STR1), (STR2), sizeof (STR2) - 1) == 0)
28
29 /* cris-opc.c -- Table of opcodes for the CRIS processor.
30 Copyright 2000, 2001, 2004 Free Software Foundation, Inc.
31 Contributed by Axis Communications AB, Lund, Sweden.
32 Originally written for GAS 1.38.1 by Mikael Asker.
33 Reorganized by Hans-Peter Nilsson.
34
35 This file is part of GAS, GDB and the GNU binutils.
36
37 GAS, GDB, and GNU binutils is free software; you can redistribute it
38 and/or modify it under the terms of the GNU General Public License as
39 published by the Free Software Foundation; either version 2, or (at your
40 option) any later version.
41
42 GAS, GDB, and GNU binutils are distributed in the hope that they will be
43 useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
44 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
45 GNU General Public License for more details.
46
47 You should have received a copy of the GNU General Public License
48 along with this program; if not, see <http://www.gnu.org/licenses/>. */
49
50 #ifndef NULL
51 #define NULL (0)
52 #endif
53
54 /* This table isn't used for CRISv32 and the size of immediate operands. */
55 const struct cris_spec_reg
56 cris_spec_regs[] =
57 {
58 {"bz", 0, 1, cris_ver_v32p, NULL},
59 {"p0", 0, 1, 0, NULL},
60 {"vr", 1, 1, 0, NULL},
61 {"p1", 1, 1, 0, NULL},
62 {"pid", 2, 1, cris_ver_v32p, NULL},
63 {"p2", 2, 1, cris_ver_v32p, NULL},
64 {"p2", 2, 1, cris_ver_warning, NULL},
65 {"srs", 3, 1, cris_ver_v32p, NULL},
66 {"p3", 3, 1, cris_ver_v32p, NULL},
67 {"p3", 3, 1, cris_ver_warning, NULL},
68 {"wz", 4, 2, cris_ver_v32p, NULL},
69 {"p4", 4, 2, 0, NULL},
70 {"ccr", 5, 2, cris_ver_v0_10, NULL},
71 {"exs", 5, 4, cris_ver_v32p, NULL},
72 {"p5", 5, 2, cris_ver_v0_10, NULL},
73 {"p5", 5, 4, cris_ver_v32p, NULL},
74 {"dcr0",6, 2, cris_ver_v0_3, NULL},
75 {"eda", 6, 4, cris_ver_v32p, NULL},
76 {"p6", 6, 2, cris_ver_v0_3, NULL},
77 {"p6", 6, 4, cris_ver_v32p, NULL},
78 {"dcr1/mof", 7, 4, cris_ver_v10p,
79 "Register `dcr1/mof' with ambiguous size specified. Guessing 4 bytes"},
80 {"dcr1/mof", 7, 2, cris_ver_v0_3,
81 "Register `dcr1/mof' with ambiguous size specified. Guessing 2 bytes"},
82 {"mof", 7, 4, cris_ver_v10p, NULL},
83 {"dcr1",7, 2, cris_ver_v0_3, NULL},
84 {"p7", 7, 4, cris_ver_v10p, NULL},
85 {"p7", 7, 2, cris_ver_v0_3, NULL},
86 {"dz", 8, 4, cris_ver_v32p, NULL},
87 {"p8", 8, 4, 0, NULL},
88 {"ibr", 9, 4, cris_ver_v0_10, NULL},
89 {"ebp", 9, 4, cris_ver_v32p, NULL},
90 {"p9", 9, 4, 0, NULL},
91 {"irp", 10, 4, cris_ver_v0_10, NULL},
92 {"erp", 10, 4, cris_ver_v32p, NULL},
93 {"p10", 10, 4, 0, NULL},
94 {"srp", 11, 4, 0, NULL},
95 {"p11", 11, 4, 0, NULL},
96 /* For disassembly use only. Accept at assembly with a warning. */
97 {"bar/dtp0", 12, 4, cris_ver_warning,
98 "Ambiguous register `bar/dtp0' specified"},
99 {"nrp", 12, 4, cris_ver_v32p, NULL},
100 {"bar", 12, 4, cris_ver_v8_10, NULL},
101 {"dtp0",12, 4, cris_ver_v0_3, NULL},
102 {"p12", 12, 4, 0, NULL},
103 /* For disassembly use only. Accept at assembly with a warning. */
104 {"dccr/dtp1",13, 4, cris_ver_warning,
105 "Ambiguous register `dccr/dtp1' specified"},
106 {"ccs", 13, 4, cris_ver_v32p, NULL},
107 {"dccr",13, 4, cris_ver_v8_10, NULL},
108 {"dtp1",13, 4, cris_ver_v0_3, NULL},
109 {"p13", 13, 4, 0, NULL},
110 {"brp", 14, 4, cris_ver_v3_10, NULL},
111 {"usp", 14, 4, cris_ver_v32p, NULL},
112 {"p14", 14, 4, cris_ver_v3p, NULL},
113 {"usp", 15, 4, cris_ver_v10, NULL},
114 {"spc", 15, 4, cris_ver_v32p, NULL},
115 {"p15", 15, 4, cris_ver_v10p, NULL},
116 {NULL, 0, 0, cris_ver_version_all, NULL}
117 };
118
119 /* Add version specifiers to this table when necessary.
120 The (now) regular coding of register names suggests a simpler
121 implementation. */
122 const struct cris_support_reg cris_support_regs[] =
123 {
124 {"s0", 0},
125 {"s1", 1},
126 {"s2", 2},
127 {"s3", 3},
128 {"s4", 4},
129 {"s5", 5},
130 {"s6", 6},
131 {"s7", 7},
132 {"s8", 8},
133 {"s9", 9},
134 {"s10", 10},
135 {"s11", 11},
136 {"s12", 12},
137 {"s13", 13},
138 {"s14", 14},
139 {"s15", 15},
140 {NULL, 0}
141 };
142
143 /* All CRIS opcodes are 16 bits.
144
145 - The match component is a mask saying which bits must match a
146 particular opcode in order for an instruction to be an instance
147 of that opcode.
148
149 - The args component is a string containing characters symbolically
150 matching the operands of an instruction. Used for both assembly
151 and disassembly.
152
153 Operand-matching characters:
154 [ ] , space
155 Verbatim.
156 A The string "ACR" (case-insensitive).
157 B Not really an operand. It causes a "BDAP -size,SP" prefix to be
158 output for the PUSH alias-instructions and recognizes a push-
159 prefix at disassembly. This letter isn't recognized for v32.
160 Must be followed by a R or P letter.
161 ! Non-match pattern, will not match if there's a prefix insn.
162 b Non-matching operand, used for branches with 16-bit
163 displacement. Only recognized by the disassembler.
164 c 5-bit unsigned immediate in bits <4:0>.
165 C 4-bit unsigned immediate in bits <3:0>.
166 d At assembly, optionally (as in put other cases before this one)
167 ".d" or ".D" at the start of the operands, followed by one space
168 character. At disassembly, nothing.
169 D General register in bits <15:12> and <3:0>.
170 f List of flags in bits <15:12> and <3:0>.
171 i 6-bit signed immediate in bits <5:0>.
172 I 6-bit unsigned immediate in bits <5:0>.
173 M Size modifier (B, W or D) for CLEAR instructions.
174 m Size modifier (B, W or D) in bits <5:4>
175 N A 32-bit dword, like in the difference between s and y.
176 This has no effect on bits in the opcode. Can also be expressed
177 as "[pc+]" in input.
178 n As N, but PC-relative (to the start of the instruction).
179 o [-128..127] word offset in bits <7:1> and <0>. Used by 8-bit
180 branch instructions.
181 O [-128..127] offset in bits <7:0>. Also matches a comma and a
182 general register after the expression, in bits <15:12>. Used
183 only for the BDAP prefix insn (in v32 the ADDOQ insn; same opcode).
184 P Special register in bits <15:12>.
185 p Indicates that the insn is a prefix insn. Must be first
186 character.
187 Q As O, but don't relax; force an 8-bit offset.
188 R General register in bits <15:12>.
189 r General register in bits <3:0>.
190 S Source operand in bit <10> and a prefix; a 3-operand prefix
191 without side-effect.
192 s Source operand in bits <10> and <3:0>, optionally with a
193 side-effect prefix, except [pc] (the name, not R15 as in ACR)
194 isn't allowed for v32 and higher.
195 T Support register in bits <15:12>.
196 u 4-bit (PC-relative) unsigned immediate word offset in bits <3:0>.
197 U Relaxes to either u or n, instruction is assumed LAPCQ or LAPC.
198 Not recognized at disassembly.
199 x Register-dot-modifier, for example "r5.w" in bits <15:12> and <5:4>.
200 y Like 's' but do not allow an integer at assembly.
201 Y The difference s-y; only an integer is allowed.
202 z Size modifier (B or W) in bit <4>. */
203
204
205 /* Please note the order of the opcodes in this table is significant.
206 The assembler requires that all instances of the same mnemonic must
207 be consecutive. If they aren't, the assembler might not recognize
208 them, or may indicate an internal error.
209
210 The disassembler should not normally care about the order of the
211 opcodes, but will prefer an earlier alternative if the "match-score"
212 (see cris-dis.c) is computed as equal.
213
214 It should not be significant for proper execution that this table is
215 in alphabetical order, but please follow that convention for an easy
216 overview. */
217
218 const struct cris_opcode
219 cris_opcodes[] =
220 {
221 {"abs", 0x06B0, 0x0940, "r,R", 0, SIZE_NONE, 0,
222 cris_abs_op},
223
224 {"add", 0x0600, 0x09c0, "m r,R", 0, SIZE_NONE, 0,
225 cris_reg_mode_add_sub_cmp_and_or_move_op},
226
227 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD, 0,
228 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
229
230 {"add", 0x0A00, 0x01c0, "m S,D", 0, SIZE_NONE,
231 cris_ver_v0_10,
232 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
233
234 {"add", 0x0a00, 0x05c0, "m S,R,r", 0, SIZE_NONE,
235 cris_ver_v0_10,
236 cris_three_operand_add_sub_cmp_and_or_op},
237
238 {"add", 0x0A00, 0x01c0, "m s,R", 0, SIZE_FIELD,
239 cris_ver_v32p,
240 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
241
242 {"addc", 0x0570, 0x0A80, "r,R", 0, SIZE_FIX_32,
243 cris_ver_v32p,
244 cris_not_implemented_op},
245
246 {"addc", 0x09A0, 0x0250, "s,R", 0, SIZE_FIX_32,
247 cris_ver_v32p,
248 cris_not_implemented_op},
249
250 {"addi", 0x0540, 0x0A80, "x,r,A", 0, SIZE_NONE,
251 cris_ver_v32p,
252 cris_addi_op},
253
254 {"addi", 0x0500, 0x0Ac0, "x,r", 0, SIZE_NONE, 0,
255 cris_addi_op},
256
257 /* This collates after "addo", but we want to disassemble as "addoq",
258 not "addo". */
259 {"addoq", 0x0100, 0x0E00, "Q,A", 0, SIZE_NONE,
260 cris_ver_v32p,
261 cris_not_implemented_op},
262
263 {"addo", 0x0940, 0x0280, "m s,R,A", 0, SIZE_FIELD_SIGNED,
264 cris_ver_v32p,
265 cris_not_implemented_op},
266
267 /* This must be located after the insn above, lest we misinterpret
268 "addo.b -1,r0,acr" as "addo .b-1,r0,acr". FIXME: Sounds like a
269 parser bug. */
270 {"addo", 0x0100, 0x0E00, "O,A", 0, SIZE_NONE,
271 cris_ver_v32p,
272 cris_not_implemented_op},
273
274 {"addq", 0x0200, 0x0Dc0, "I,R", 0, SIZE_NONE, 0,
275 cris_quick_mode_add_sub_op},
276
277 {"adds", 0x0420, 0x0Bc0, "z r,R", 0, SIZE_NONE, 0,
278 cris_reg_mode_add_sub_cmp_and_or_move_op},
279
280 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
281 {"adds", 0x0820, 0x03c0, "z s,R", 0, SIZE_FIELD, 0,
282 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
283
284 {"adds", 0x0820, 0x03c0, "z S,D", 0, SIZE_NONE,
285 cris_ver_v0_10,
286 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
287
288 {"adds", 0x0820, 0x07c0, "z S,R,r", 0, SIZE_NONE,
289 cris_ver_v0_10,
290 cris_three_operand_add_sub_cmp_and_or_op},
291
292 {"addu", 0x0400, 0x0be0, "z r,R", 0, SIZE_NONE, 0,
293 cris_reg_mode_add_sub_cmp_and_or_move_op},
294
295 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
296 {"addu", 0x0800, 0x03e0, "z s,R", 0, SIZE_FIELD, 0,
297 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
298
299 {"addu", 0x0800, 0x03e0, "z S,D", 0, SIZE_NONE,
300 cris_ver_v0_10,
301 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
302
303 {"addu", 0x0800, 0x07e0, "z S,R,r", 0, SIZE_NONE,
304 cris_ver_v0_10,
305 cris_three_operand_add_sub_cmp_and_or_op},
306
307 {"and", 0x0700, 0x08C0, "m r,R", 0, SIZE_NONE, 0,
308 cris_reg_mode_add_sub_cmp_and_or_move_op},
309
310 {"and", 0x0B00, 0x00C0, "m s,R", 0, SIZE_FIELD, 0,
311 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
312
313 {"and", 0x0B00, 0x00C0, "m S,D", 0, SIZE_NONE,
314 cris_ver_v0_10,
315 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
316
317 {"and", 0x0B00, 0x04C0, "m S,R,r", 0, SIZE_NONE,
318 cris_ver_v0_10,
319 cris_three_operand_add_sub_cmp_and_or_op},
320
321 {"andq", 0x0300, 0x0CC0, "i,R", 0, SIZE_NONE, 0,
322 cris_quick_mode_and_cmp_move_or_op},
323
324 {"asr", 0x0780, 0x0840, "m r,R", 0, SIZE_NONE, 0,
325 cris_asr_op},
326
327 {"asrq", 0x03a0, 0x0c40, "c,R", 0, SIZE_NONE, 0,
328 cris_asrq_op},
329
330 {"ax", 0x15B0, 0xEA4F, "", 0, SIZE_NONE, 0,
331 cris_ax_ei_setf_op},
332
333 /* FIXME: Should use branch #defines. */
334 {"b", 0x0dff, 0x0200, "b", 1, SIZE_NONE, 0,
335 cris_sixteen_bit_offset_branch_op},
336
337 {"ba",
338 BA_QUICK_OPCODE,
339 0x0F00+(0xF-CC_A)*0x1000, "o", 1, SIZE_NONE, 0,
340 cris_eight_bit_offset_branch_op},
341
342 /* Needs to come after the usual "ba o", which might be relaxed to
343 this one. */
344 {"ba", BA_DWORD_OPCODE,
345 0xffff & (~BA_DWORD_OPCODE), "n", 0, SIZE_FIX_32,
346 cris_ver_v32p,
347 cris_none_reg_mode_jump_op},
348
349 {"bas", 0x0EBF, 0x0140, "n,P", 0, SIZE_FIX_32,
350 cris_ver_v32p,
351 cris_none_reg_mode_jump_op},
352
353 {"basc", 0x0EFF, 0x0100, "n,P", 0, SIZE_FIX_32,
354 cris_ver_v32p,
355 cris_none_reg_mode_jump_op},
356
357 {"bcc",
358 BRANCH_QUICK_OPCODE+CC_CC*0x1000,
359 0x0f00+(0xF-CC_CC)*0x1000, "o", 1, SIZE_NONE, 0,
360 cris_eight_bit_offset_branch_op},
361
362 {"bcs",
363 BRANCH_QUICK_OPCODE+CC_CS*0x1000,
364 0x0f00+(0xF-CC_CS)*0x1000, "o", 1, SIZE_NONE, 0,
365 cris_eight_bit_offset_branch_op},
366
367 {"bdap",
368 BDAP_INDIR_OPCODE, BDAP_INDIR_Z_BITS, "pm s,R", 0, SIZE_FIELD_SIGNED,
369 cris_ver_v0_10,
370 cris_bdap_prefix},
371
372 {"bdap",
373 BDAP_QUICK_OPCODE, BDAP_QUICK_Z_BITS, "pO", 0, SIZE_NONE,
374 cris_ver_v0_10,
375 cris_quick_mode_bdap_prefix},
376
377 {"beq",
378 BRANCH_QUICK_OPCODE+CC_EQ*0x1000,
379 0x0f00+(0xF-CC_EQ)*0x1000, "o", 1, SIZE_NONE, 0,
380 cris_eight_bit_offset_branch_op},
381
382 /* This is deliberately put before "bext" to trump it, even though not
383 in alphabetical order, since we don't do excluding version checks
384 for v0..v10. */
385 {"bwf",
386 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
387 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
388 cris_ver_v10,
389 cris_eight_bit_offset_branch_op},
390
391 {"bext",
392 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
393 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
394 cris_ver_v0_3,
395 cris_eight_bit_offset_branch_op},
396
397 {"bge",
398 BRANCH_QUICK_OPCODE+CC_GE*0x1000,
399 0x0f00+(0xF-CC_GE)*0x1000, "o", 1, SIZE_NONE, 0,
400 cris_eight_bit_offset_branch_op},
401
402 {"bgt",
403 BRANCH_QUICK_OPCODE+CC_GT*0x1000,
404 0x0f00+(0xF-CC_GT)*0x1000, "o", 1, SIZE_NONE, 0,
405 cris_eight_bit_offset_branch_op},
406
407 {"bhi",
408 BRANCH_QUICK_OPCODE+CC_HI*0x1000,
409 0x0f00+(0xF-CC_HI)*0x1000, "o", 1, SIZE_NONE, 0,
410 cris_eight_bit_offset_branch_op},
411
412 {"bhs",
413 BRANCH_QUICK_OPCODE+CC_HS*0x1000,
414 0x0f00+(0xF-CC_HS)*0x1000, "o", 1, SIZE_NONE, 0,
415 cris_eight_bit_offset_branch_op},
416
417 {"biap", BIAP_OPCODE, BIAP_Z_BITS, "pm r,R", 0, SIZE_NONE,
418 cris_ver_v0_10,
419 cris_biap_prefix},
420
421 {"ble",
422 BRANCH_QUICK_OPCODE+CC_LE*0x1000,
423 0x0f00+(0xF-CC_LE)*0x1000, "o", 1, SIZE_NONE, 0,
424 cris_eight_bit_offset_branch_op},
425
426 {"blo",
427 BRANCH_QUICK_OPCODE+CC_LO*0x1000,
428 0x0f00+(0xF-CC_LO)*0x1000, "o", 1, SIZE_NONE, 0,
429 cris_eight_bit_offset_branch_op},
430
431 {"bls",
432 BRANCH_QUICK_OPCODE+CC_LS*0x1000,
433 0x0f00+(0xF-CC_LS)*0x1000, "o", 1, SIZE_NONE, 0,
434 cris_eight_bit_offset_branch_op},
435
436 {"blt",
437 BRANCH_QUICK_OPCODE+CC_LT*0x1000,
438 0x0f00+(0xF-CC_LT)*0x1000, "o", 1, SIZE_NONE, 0,
439 cris_eight_bit_offset_branch_op},
440
441 {"bmi",
442 BRANCH_QUICK_OPCODE+CC_MI*0x1000,
443 0x0f00+(0xF-CC_MI)*0x1000, "o", 1, SIZE_NONE, 0,
444 cris_eight_bit_offset_branch_op},
445
446 {"bmod", 0x0ab0, 0x0140, "s,R", 0, SIZE_FIX_32,
447 cris_ver_sim_v0_10,
448 cris_not_implemented_op},
449
450 {"bmod", 0x0ab0, 0x0140, "S,D", 0, SIZE_NONE,
451 cris_ver_sim_v0_10,
452 cris_not_implemented_op},
453
454 {"bmod", 0x0ab0, 0x0540, "S,R,r", 0, SIZE_NONE,
455 cris_ver_sim_v0_10,
456 cris_not_implemented_op},
457
458 {"bne",
459 BRANCH_QUICK_OPCODE+CC_NE*0x1000,
460 0x0f00+(0xF-CC_NE)*0x1000, "o", 1, SIZE_NONE, 0,
461 cris_eight_bit_offset_branch_op},
462
463 {"bound", 0x05c0, 0x0A00, "m r,R", 0, SIZE_NONE, 0,
464 cris_two_operand_bound_op},
465 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
466 {"bound", 0x09c0, 0x0200, "m s,R", 0, SIZE_FIELD,
467 cris_ver_v0_10,
468 cris_two_operand_bound_op},
469 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
470 {"bound", 0x0dcf, 0x0200, "m Y,R", 0, SIZE_FIELD, 0,
471 cris_two_operand_bound_op},
472 {"bound", 0x09c0, 0x0200, "m S,D", 0, SIZE_NONE,
473 cris_ver_v0_10,
474 cris_two_operand_bound_op},
475 {"bound", 0x09c0, 0x0600, "m S,R,r", 0, SIZE_NONE,
476 cris_ver_v0_10,
477 cris_three_operand_bound_op},
478
479 {"bpl",
480 BRANCH_QUICK_OPCODE+CC_PL*0x1000,
481 0x0f00+(0xF-CC_PL)*0x1000, "o", 1, SIZE_NONE, 0,
482 cris_eight_bit_offset_branch_op},
483
484 {"break", 0xe930, 0x16c0, "C", 0, SIZE_NONE,
485 cris_ver_v3p,
486 cris_break_op},
487
488 {"bsb",
489 BRANCH_QUICK_OPCODE+CC_EXT*0x1000,
490 0x0f00+(0xF-CC_EXT)*0x1000, "o", 1, SIZE_NONE,
491 cris_ver_v32p,
492 cris_eight_bit_offset_branch_op},
493
494 {"bsr", 0xBEBF, 0x4140, "n", 0, SIZE_FIX_32,
495 cris_ver_v32p,
496 cris_none_reg_mode_jump_op},
497
498 {"bsrc", 0xBEFF, 0x4100, "n", 0, SIZE_FIX_32,
499 cris_ver_v32p,
500 cris_none_reg_mode_jump_op},
501
502 {"bstore", 0x0af0, 0x0100, "s,R", 0, SIZE_FIX_32,
503 cris_ver_warning,
504 cris_not_implemented_op},
505
506 {"bstore", 0x0af0, 0x0100, "S,D", 0, SIZE_NONE,
507 cris_ver_warning,
508 cris_not_implemented_op},
509
510 {"bstore", 0x0af0, 0x0500, "S,R,r", 0, SIZE_NONE,
511 cris_ver_warning,
512 cris_not_implemented_op},
513
514 {"btst", 0x04F0, 0x0B00, "r,R", 0, SIZE_NONE, 0,
515 cris_btst_nop_op},
516 {"btstq", 0x0380, 0x0C60, "c,R", 0, SIZE_NONE, 0,
517 cris_btst_nop_op},
518
519 {"bvc",
520 BRANCH_QUICK_OPCODE+CC_VC*0x1000,
521 0x0f00+(0xF-CC_VC)*0x1000, "o", 1, SIZE_NONE, 0,
522 cris_eight_bit_offset_branch_op},
523
524 {"bvs",
525 BRANCH_QUICK_OPCODE+CC_VS*0x1000,
526 0x0f00+(0xF-CC_VS)*0x1000, "o", 1, SIZE_NONE, 0,
527 cris_eight_bit_offset_branch_op},
528
529 {"clear", 0x0670, 0x3980, "M r", 0, SIZE_NONE, 0,
530 cris_reg_mode_clear_op},
531
532 {"clear", 0x0A70, 0x3180, "M y", 0, SIZE_NONE, 0,
533 cris_none_reg_mode_clear_test_op},
534
535 {"clear", 0x0A70, 0x3180, "M S", 0, SIZE_NONE,
536 cris_ver_v0_10,
537 cris_none_reg_mode_clear_test_op},
538
539 {"clearf", 0x05F0, 0x0A00, "f", 0, SIZE_NONE, 0,
540 cris_clearf_di_op},
541
542 {"cmp", 0x06C0, 0x0900, "m r,R", 0, SIZE_NONE, 0,
543 cris_reg_mode_add_sub_cmp_and_or_move_op},
544
545 {"cmp", 0x0Ac0, 0x0100, "m s,R", 0, SIZE_FIELD, 0,
546 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
547
548 {"cmp", 0x0Ac0, 0x0100, "m S,D", 0, SIZE_NONE,
549 cris_ver_v0_10,
550 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
551
552 {"cmpq", 0x02C0, 0x0D00, "i,R", 0, SIZE_NONE, 0,
553 cris_quick_mode_and_cmp_move_or_op},
554
555 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
556 {"cmps", 0x08e0, 0x0300, "z s,R", 0, SIZE_FIELD, 0,
557 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
558
559 {"cmps", 0x08e0, 0x0300, "z S,D", 0, SIZE_NONE,
560 cris_ver_v0_10,
561 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
562
563 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
564 {"cmpu", 0x08c0, 0x0320, "z s,R" , 0, SIZE_FIELD, 0,
565 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
566
567 {"cmpu", 0x08c0, 0x0320, "z S,D", 0, SIZE_NONE,
568 cris_ver_v0_10,
569 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
570
571 {"di", 0x25F0, 0xDA0F, "", 0, SIZE_NONE, 0,
572 cris_clearf_di_op},
573
574 {"dip", DIP_OPCODE, DIP_Z_BITS, "ps", 0, SIZE_FIX_32,
575 cris_ver_v0_10,
576 cris_dip_prefix},
577
578 {"div", 0x0980, 0x0640, "m R,r", 0, SIZE_FIELD, 0,
579 cris_not_implemented_op},
580
581 {"dstep", 0x06f0, 0x0900, "r,R", 0, SIZE_NONE, 0,
582 cris_dstep_logshift_mstep_neg_not_op},
583
584 {"ei", 0x25B0, 0xDA4F, "", 0, SIZE_NONE, 0,
585 cris_ax_ei_setf_op},
586
587 {"fidxd", 0x0ab0, 0xf540, "[r]", 0, SIZE_NONE,
588 cris_ver_v32p,
589 cris_not_implemented_op},
590
591 {"fidxi", 0x0d30, 0xF2C0, "[r]", 0, SIZE_NONE,
592 cris_ver_v32p,
593 cris_not_implemented_op},
594
595 {"ftagd", 0x1AB0, 0xE540, "[r]", 0, SIZE_NONE,
596 cris_ver_v32p,
597 cris_not_implemented_op},
598
599 {"ftagi", 0x1D30, 0xE2C0, "[r]", 0, SIZE_NONE,
600 cris_ver_v32p,
601 cris_not_implemented_op},
602
603 {"halt", 0xF930, 0x06CF, "", 0, SIZE_NONE,
604 cris_ver_v32p,
605 cris_not_implemented_op},
606
607 {"jas", 0x09B0, 0x0640, "r,P", 0, SIZE_NONE,
608 cris_ver_v32p,
609 cris_reg_mode_jump_op},
610
611 {"jas", 0x0DBF, 0x0240, "N,P", 0, SIZE_FIX_32,
612 cris_ver_v32p,
613 cris_reg_mode_jump_op},
614
615 {"jasc", 0x0B30, 0x04C0, "r,P", 0, SIZE_NONE,
616 cris_ver_v32p,
617 cris_reg_mode_jump_op},
618
619 {"jasc", 0x0F3F, 0x00C0, "N,P", 0, SIZE_FIX_32,
620 cris_ver_v32p,
621 cris_reg_mode_jump_op},
622
623 {"jbrc", 0x69b0, 0x9640, "r", 0, SIZE_NONE,
624 cris_ver_v8_10,
625 cris_reg_mode_jump_op},
626
627 {"jbrc", 0x6930, 0x92c0, "s", 0, SIZE_FIX_32,
628 cris_ver_v8_10,
629 cris_none_reg_mode_jump_op},
630
631 {"jbrc", 0x6930, 0x92c0, "S", 0, SIZE_NONE,
632 cris_ver_v8_10,
633 cris_none_reg_mode_jump_op},
634
635 {"jir", 0xA9b0, 0x5640, "r", 0, SIZE_NONE,
636 cris_ver_v8_10,
637 cris_reg_mode_jump_op},
638
639 {"jir", 0xA930, 0x52c0, "s", 0, SIZE_FIX_32,
640 cris_ver_v8_10,
641 cris_none_reg_mode_jump_op},
642
643 {"jir", 0xA930, 0x52c0, "S", 0, SIZE_NONE,
644 cris_ver_v8_10,
645 cris_none_reg_mode_jump_op},
646
647 {"jirc", 0x29b0, 0xd640, "r", 0, SIZE_NONE,
648 cris_ver_v8_10,
649 cris_reg_mode_jump_op},
650
651 {"jirc", 0x2930, 0xd2c0, "s", 0, SIZE_FIX_32,
652 cris_ver_v8_10,
653 cris_none_reg_mode_jump_op},
654
655 {"jirc", 0x2930, 0xd2c0, "S", 0, SIZE_NONE,
656 cris_ver_v8_10,
657 cris_none_reg_mode_jump_op},
658
659 {"jsr", 0xB9b0, 0x4640, "r", 0, SIZE_NONE, 0,
660 cris_reg_mode_jump_op},
661
662 {"jsr", 0xB930, 0x42c0, "s", 0, SIZE_FIX_32,
663 cris_ver_v0_10,
664 cris_none_reg_mode_jump_op},
665
666 {"jsr", 0xBDBF, 0x4240, "N", 0, SIZE_FIX_32,
667 cris_ver_v32p,
668 cris_none_reg_mode_jump_op},
669
670 {"jsr", 0xB930, 0x42c0, "S", 0, SIZE_NONE,
671 cris_ver_v0_10,
672 cris_none_reg_mode_jump_op},
673
674 {"jsrc", 0x39b0, 0xc640, "r", 0, SIZE_NONE,
675 cris_ver_v8_10,
676 cris_reg_mode_jump_op},
677
678 {"jsrc", 0x3930, 0xc2c0, "s", 0, SIZE_FIX_32,
679 cris_ver_v8_10,
680 cris_none_reg_mode_jump_op},
681
682 {"jsrc", 0x3930, 0xc2c0, "S", 0, SIZE_NONE,
683 cris_ver_v8_10,
684 cris_none_reg_mode_jump_op},
685
686 {"jsrc", 0xBB30, 0x44C0, "r", 0, SIZE_NONE,
687 cris_ver_v32p,
688 cris_reg_mode_jump_op},
689
690 {"jsrc", 0xBF3F, 0x40C0, "N", 0, SIZE_FIX_32,
691 cris_ver_v32p,
692 cris_reg_mode_jump_op},
693
694 {"jump", 0x09b0, 0xF640, "r", 0, SIZE_NONE, 0,
695 cris_reg_mode_jump_op},
696
697 {"jump",
698 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "s", 0, SIZE_FIX_32,
699 cris_ver_v0_10,
700 cris_none_reg_mode_jump_op},
701
702 {"jump",
703 JUMP_INDIR_OPCODE, JUMP_INDIR_Z_BITS, "S", 0, SIZE_NONE,
704 cris_ver_v0_10,
705 cris_none_reg_mode_jump_op},
706
707 {"jump", 0x09F0, 0x060F, "P", 0, SIZE_NONE,
708 cris_ver_v32p,
709 cris_none_reg_mode_jump_op},
710
711 {"jump",
712 JUMP_PC_INCR_OPCODE_V32,
713 (0xffff & ~JUMP_PC_INCR_OPCODE_V32), "N", 0, SIZE_FIX_32,
714 cris_ver_v32p,
715 cris_none_reg_mode_jump_op},
716
717 {"jmpu", 0x8930, 0x72c0, "s", 0, SIZE_FIX_32,
718 cris_ver_v10,
719 cris_none_reg_mode_jump_op},
720
721 {"jmpu", 0x8930, 0x72c0, "S", 0, SIZE_NONE,
722 cris_ver_v10,
723 cris_none_reg_mode_jump_op},
724
725 {"lapc", 0x0970, 0x0680, "U,R", 0, SIZE_NONE,
726 cris_ver_v32p,
727 cris_not_implemented_op},
728
729 {"lapc", 0x0D7F, 0x0280, "dn,R", 0, SIZE_FIX_32,
730 cris_ver_v32p,
731 cris_not_implemented_op},
732
733 {"lapcq", 0x0970, 0x0680, "u,R", 0, SIZE_NONE,
734 cris_ver_v32p,
735 cris_addi_op},
736
737 {"lsl", 0x04C0, 0x0B00, "m r,R", 0, SIZE_NONE, 0,
738 cris_dstep_logshift_mstep_neg_not_op},
739
740 {"lslq", 0x03c0, 0x0C20, "c,R", 0, SIZE_NONE, 0,
741 cris_dstep_logshift_mstep_neg_not_op},
742
743 {"lsr", 0x07C0, 0x0800, "m r,R", 0, SIZE_NONE, 0,
744 cris_dstep_logshift_mstep_neg_not_op},
745
746 {"lsrq", 0x03e0, 0x0C00, "c,R", 0, SIZE_NONE, 0,
747 cris_dstep_logshift_mstep_neg_not_op},
748
749 {"lz", 0x0730, 0x08C0, "r,R", 0, SIZE_NONE,
750 cris_ver_v3p,
751 cris_not_implemented_op},
752
753 {"mcp", 0x07f0, 0x0800, "P,r", 0, SIZE_NONE,
754 cris_ver_v32p,
755 cris_not_implemented_op},
756
757 {"move", 0x0640, 0x0980, "m r,R", 0, SIZE_NONE, 0,
758 cris_reg_mode_add_sub_cmp_and_or_move_op},
759
760 {"move", 0x0A40, 0x0180, "m s,R", 0, SIZE_FIELD, 0,
761 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
762
763 {"move", 0x0A40, 0x0180, "m S,D", 0, SIZE_NONE,
764 cris_ver_v0_10,
765 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
766
767 {"move", 0x0630, 0x09c0, "r,P", 0, SIZE_NONE, 0,
768 cris_move_to_preg_op},
769
770 {"move", 0x0670, 0x0980, "P,r", 0, SIZE_NONE, 0,
771 cris_reg_mode_move_from_preg_op},
772
773 {"move", 0x0BC0, 0x0000, "m R,y", 0, SIZE_FIELD, 0,
774 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
775
776 {"move", 0x0BC0, 0x0000, "m D,S", 0, SIZE_NONE,
777 cris_ver_v0_10,
778 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
779
780 {"move",
781 MOVE_M_TO_PREG_OPCODE, MOVE_M_TO_PREG_ZBITS,
782 "s,P", 0, SIZE_SPEC_REG, 0,
783 cris_move_to_preg_op},
784
785 {"move", 0x0A30, 0x01c0, "S,P", 0, SIZE_NONE,
786 cris_ver_v0_10,
787 cris_move_to_preg_op},
788
789 {"move", 0x0A70, 0x0180, "P,y", 0, SIZE_SPEC_REG, 0,
790 cris_none_reg_mode_move_from_preg_op},
791
792 {"move", 0x0A70, 0x0180, "P,S", 0, SIZE_NONE,
793 cris_ver_v0_10,
794 cris_none_reg_mode_move_from_preg_op},
795
796 {"move", 0x0B70, 0x0480, "r,T", 0, SIZE_NONE,
797 cris_ver_v32p,
798 cris_not_implemented_op},
799
800 {"move", 0x0F70, 0x0080, "T,r", 0, SIZE_NONE,
801 cris_ver_v32p,
802 cris_not_implemented_op},
803
804 {"movem", 0x0BF0, 0x0000, "R,y", 0, SIZE_FIX_32, 0,
805 cris_move_reg_to_mem_movem_op},
806
807 {"movem", 0x0BF0, 0x0000, "D,S", 0, SIZE_NONE,
808 cris_ver_v0_10,
809 cris_move_reg_to_mem_movem_op},
810
811 {"movem", 0x0BB0, 0x0040, "s,R", 0, SIZE_FIX_32, 0,
812 cris_move_mem_to_reg_movem_op},
813
814 {"movem", 0x0BB0, 0x0040, "S,D", 0, SIZE_NONE,
815 cris_ver_v0_10,
816 cris_move_mem_to_reg_movem_op},
817
818 {"moveq", 0x0240, 0x0D80, "i,R", 0, SIZE_NONE, 0,
819 cris_quick_mode_and_cmp_move_or_op},
820
821 {"movs", 0x0460, 0x0B80, "z r,R", 0, SIZE_NONE, 0,
822 cris_reg_mode_add_sub_cmp_and_or_move_op},
823
824 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
825 {"movs", 0x0860, 0x0380, "z s,R", 0, SIZE_FIELD, 0,
826 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
827
828 {"movs", 0x0860, 0x0380, "z S,D", 0, SIZE_NONE,
829 cris_ver_v0_10,
830 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
831
832 {"movu", 0x0440, 0x0Ba0, "z r,R", 0, SIZE_NONE, 0,
833 cris_reg_mode_add_sub_cmp_and_or_move_op},
834
835 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
836 {"movu", 0x0840, 0x03a0, "z s,R", 0, SIZE_FIELD, 0,
837 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
838
839 {"movu", 0x0840, 0x03a0, "z S,D", 0, SIZE_NONE,
840 cris_ver_v0_10,
841 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
842
843 {"mstep", 0x07f0, 0x0800, "r,R", 0, SIZE_NONE,
844 cris_ver_v0_10,
845 cris_dstep_logshift_mstep_neg_not_op},
846
847 {"muls", 0x0d00, 0x02c0, "m r,R", 0, SIZE_NONE,
848 cris_ver_v10p,
849 cris_muls_op},
850
851 {"mulu", 0x0900, 0x06c0, "m r,R", 0, SIZE_NONE,
852 cris_ver_v10p,
853 cris_mulu_op},
854
855 {"neg", 0x0580, 0x0A40, "m r,R", 0, SIZE_NONE, 0,
856 cris_dstep_logshift_mstep_neg_not_op},
857
858 {"nop", NOP_OPCODE, NOP_Z_BITS, "", 0, SIZE_NONE,
859 cris_ver_v0_10,
860 cris_btst_nop_op},
861
862 {"nop", NOP_OPCODE_V32, NOP_Z_BITS_V32, "", 0, SIZE_NONE,
863 cris_ver_v32p,
864 cris_btst_nop_op},
865
866 {"not", 0x8770, 0x7880, "r", 0, SIZE_NONE, 0,
867 cris_dstep_logshift_mstep_neg_not_op},
868
869 {"or", 0x0740, 0x0880, "m r,R", 0, SIZE_NONE, 0,
870 cris_reg_mode_add_sub_cmp_and_or_move_op},
871
872 {"or", 0x0B40, 0x0080, "m s,R", 0, SIZE_FIELD, 0,
873 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
874
875 {"or", 0x0B40, 0x0080, "m S,D", 0, SIZE_NONE,
876 cris_ver_v0_10,
877 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
878
879 {"or", 0x0B40, 0x0480, "m S,R,r", 0, SIZE_NONE,
880 cris_ver_v0_10,
881 cris_three_operand_add_sub_cmp_and_or_op},
882
883 {"orq", 0x0340, 0x0C80, "i,R", 0, SIZE_NONE, 0,
884 cris_quick_mode_and_cmp_move_or_op},
885
886 {"pop", 0x0E6E, 0x0191, "!R", 0, SIZE_NONE,
887 cris_ver_v0_10,
888 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
889
890 {"pop", 0x0e3e, 0x01c1, "!P", 0, SIZE_NONE,
891 cris_ver_v0_10,
892 cris_none_reg_mode_move_from_preg_op},
893
894 {"push", 0x0FEE, 0x0011, "BR", 0, SIZE_NONE,
895 cris_ver_v0_10,
896 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
897
898 {"push", 0x0E7E, 0x0181, "BP", 0, SIZE_NONE,
899 cris_ver_v0_10,
900 cris_move_to_preg_op},
901
902 {"rbf", 0x3b30, 0xc0c0, "y", 0, SIZE_NONE,
903 cris_ver_v10,
904 cris_not_implemented_op},
905
906 {"rbf", 0x3b30, 0xc0c0, "S", 0, SIZE_NONE,
907 cris_ver_v10,
908 cris_not_implemented_op},
909
910 {"rfe", 0x2930, 0xD6CF, "", 0, SIZE_NONE,
911 cris_ver_v32p,
912 cris_not_implemented_op},
913
914 {"rfg", 0x4930, 0xB6CF, "", 0, SIZE_NONE,
915 cris_ver_v32p,
916 cris_not_implemented_op},
917
918 {"rfn", 0x5930, 0xA6CF, "", 0, SIZE_NONE,
919 cris_ver_v32p,
920 cris_not_implemented_op},
921
922 {"ret", 0xB67F, 0x4980, "", 1, SIZE_NONE,
923 cris_ver_v0_10,
924 cris_reg_mode_move_from_preg_op},
925
926 {"ret", 0xB9F0, 0x460F, "", 1, SIZE_NONE,
927 cris_ver_v32p,
928 cris_reg_mode_move_from_preg_op},
929
930 {"retb", 0xe67f, 0x1980, "", 1, SIZE_NONE,
931 cris_ver_v0_10,
932 cris_reg_mode_move_from_preg_op},
933
934 {"rete", 0xA9F0, 0x560F, "", 1, SIZE_NONE,
935 cris_ver_v32p,
936 cris_reg_mode_move_from_preg_op},
937
938 {"reti", 0xA67F, 0x5980, "", 1, SIZE_NONE,
939 cris_ver_v0_10,
940 cris_reg_mode_move_from_preg_op},
941
942 {"retn", 0xC9F0, 0x360F, "", 1, SIZE_NONE,
943 cris_ver_v32p,
944 cris_reg_mode_move_from_preg_op},
945
946 {"sbfs", 0x3b70, 0xc080, "y", 0, SIZE_NONE,
947 cris_ver_v10,
948 cris_not_implemented_op},
949
950 {"sbfs", 0x3b70, 0xc080, "S", 0, SIZE_NONE,
951 cris_ver_v10,
952 cris_not_implemented_op},
953
954 {"sa",
955 0x0530+CC_A*0x1000,
956 0x0AC0+(0xf-CC_A)*0x1000, "r", 0, SIZE_NONE, 0,
957 cris_scc_op},
958
959 {"ssb",
960 0x0530+CC_EXT*0x1000,
961 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
962 cris_ver_v32p,
963 cris_scc_op},
964
965 {"scc",
966 0x0530+CC_CC*0x1000,
967 0x0AC0+(0xf-CC_CC)*0x1000, "r", 0, SIZE_NONE, 0,
968 cris_scc_op},
969
970 {"scs",
971 0x0530+CC_CS*0x1000,
972 0x0AC0+(0xf-CC_CS)*0x1000, "r", 0, SIZE_NONE, 0,
973 cris_scc_op},
974
975 {"seq",
976 0x0530+CC_EQ*0x1000,
977 0x0AC0+(0xf-CC_EQ)*0x1000, "r", 0, SIZE_NONE, 0,
978 cris_scc_op},
979
980 {"setf", 0x05b0, 0x0A40, "f", 0, SIZE_NONE, 0,
981 cris_ax_ei_setf_op},
982
983 {"sfe", 0x3930, 0xC6CF, "", 0, SIZE_NONE,
984 cris_ver_v32p,
985 cris_not_implemented_op},
986
987 /* Need to have "swf" in front of "sext" so it is the one displayed in
988 disassembly. */
989 {"swf",
990 0x0530+CC_EXT*0x1000,
991 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
992 cris_ver_v10,
993 cris_scc_op},
994
995 {"sext",
996 0x0530+CC_EXT*0x1000,
997 0x0AC0+(0xf-CC_EXT)*0x1000, "r", 0, SIZE_NONE,
998 cris_ver_v0_3,
999 cris_scc_op},
1000
1001 {"sge",
1002 0x0530+CC_GE*0x1000,
1003 0x0AC0+(0xf-CC_GE)*0x1000, "r", 0, SIZE_NONE, 0,
1004 cris_scc_op},
1005
1006 {"sgt",
1007 0x0530+CC_GT*0x1000,
1008 0x0AC0+(0xf-CC_GT)*0x1000, "r", 0, SIZE_NONE, 0,
1009 cris_scc_op},
1010
1011 {"shi",
1012 0x0530+CC_HI*0x1000,
1013 0x0AC0+(0xf-CC_HI)*0x1000, "r", 0, SIZE_NONE, 0,
1014 cris_scc_op},
1015
1016 {"shs",
1017 0x0530+CC_HS*0x1000,
1018 0x0AC0+(0xf-CC_HS)*0x1000, "r", 0, SIZE_NONE, 0,
1019 cris_scc_op},
1020
1021 {"sle",
1022 0x0530+CC_LE*0x1000,
1023 0x0AC0+(0xf-CC_LE)*0x1000, "r", 0, SIZE_NONE, 0,
1024 cris_scc_op},
1025
1026 {"slo",
1027 0x0530+CC_LO*0x1000,
1028 0x0AC0+(0xf-CC_LO)*0x1000, "r", 0, SIZE_NONE, 0,
1029 cris_scc_op},
1030
1031 {"sls",
1032 0x0530+CC_LS*0x1000,
1033 0x0AC0+(0xf-CC_LS)*0x1000, "r", 0, SIZE_NONE, 0,
1034 cris_scc_op},
1035
1036 {"slt",
1037 0x0530+CC_LT*0x1000,
1038 0x0AC0+(0xf-CC_LT)*0x1000, "r", 0, SIZE_NONE, 0,
1039 cris_scc_op},
1040
1041 {"smi",
1042 0x0530+CC_MI*0x1000,
1043 0x0AC0+(0xf-CC_MI)*0x1000, "r", 0, SIZE_NONE, 0,
1044 cris_scc_op},
1045
1046 {"sne",
1047 0x0530+CC_NE*0x1000,
1048 0x0AC0+(0xf-CC_NE)*0x1000, "r", 0, SIZE_NONE, 0,
1049 cris_scc_op},
1050
1051 {"spl",
1052 0x0530+CC_PL*0x1000,
1053 0x0AC0+(0xf-CC_PL)*0x1000, "r", 0, SIZE_NONE, 0,
1054 cris_scc_op},
1055
1056 {"sub", 0x0680, 0x0940, "m r,R", 0, SIZE_NONE, 0,
1057 cris_reg_mode_add_sub_cmp_and_or_move_op},
1058
1059 {"sub", 0x0a80, 0x0140, "m s,R", 0, SIZE_FIELD, 0,
1060 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1061
1062 {"sub", 0x0a80, 0x0140, "m S,D", 0, SIZE_NONE,
1063 cris_ver_v0_10,
1064 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1065
1066 {"sub", 0x0a80, 0x0540, "m S,R,r", 0, SIZE_NONE,
1067 cris_ver_v0_10,
1068 cris_three_operand_add_sub_cmp_and_or_op},
1069
1070 {"subq", 0x0280, 0x0d40, "I,R", 0, SIZE_NONE, 0,
1071 cris_quick_mode_add_sub_op},
1072
1073 {"subs", 0x04a0, 0x0b40, "z r,R", 0, SIZE_NONE, 0,
1074 cris_reg_mode_add_sub_cmp_and_or_move_op},
1075
1076 /* FIXME: SIZE_FIELD_SIGNED and all necessary changes. */
1077 {"subs", 0x08a0, 0x0340, "z s,R", 0, SIZE_FIELD, 0,
1078 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1079
1080 {"subs", 0x08a0, 0x0340, "z S,D", 0, SIZE_NONE,
1081 cris_ver_v0_10,
1082 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1083
1084 {"subs", 0x08a0, 0x0740, "z S,R,r", 0, SIZE_NONE,
1085 cris_ver_v0_10,
1086 cris_three_operand_add_sub_cmp_and_or_op},
1087
1088 {"subu", 0x0480, 0x0b60, "z r,R", 0, SIZE_NONE, 0,
1089 cris_reg_mode_add_sub_cmp_and_or_move_op},
1090
1091 /* FIXME: SIZE_FIELD_UNSIGNED and all necessary changes. */
1092 {"subu", 0x0880, 0x0360, "z s,R", 0, SIZE_FIELD, 0,
1093 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1094
1095 {"subu", 0x0880, 0x0360, "z S,D", 0, SIZE_NONE,
1096 cris_ver_v0_10,
1097 cris_none_reg_mode_add_sub_cmp_and_or_move_op},
1098
1099 {"subu", 0x0880, 0x0760, "z S,R,r", 0, SIZE_NONE,
1100 cris_ver_v0_10,
1101 cris_three_operand_add_sub_cmp_and_or_op},
1102
1103 {"svc",
1104 0x0530+CC_VC*0x1000,
1105 0x0AC0+(0xf-CC_VC)*0x1000, "r", 0, SIZE_NONE, 0,
1106 cris_scc_op},
1107
1108 {"svs",
1109 0x0530+CC_VS*0x1000,
1110 0x0AC0+(0xf-CC_VS)*0x1000, "r", 0, SIZE_NONE, 0,
1111 cris_scc_op},
1112
1113 /* The insn "swapn" is the same as "not" and will be disassembled as
1114 such, but the swap* family of mnmonics are generally v8-and-higher
1115 only, so count it in. */
1116 {"swapn", 0x8770, 0x7880, "r", 0, SIZE_NONE,
1117 cris_ver_v8p,
1118 cris_not_implemented_op},
1119
1120 {"swapw", 0x4770, 0xb880, "r", 0, SIZE_NONE,
1121 cris_ver_v8p,
1122 cris_not_implemented_op},
1123
1124 {"swapnw", 0xc770, 0x3880, "r", 0, SIZE_NONE,
1125 cris_ver_v8p,
1126 cris_not_implemented_op},
1127
1128 {"swapb", 0x2770, 0xd880, "r", 0, SIZE_NONE,
1129 cris_ver_v8p,
1130 cris_not_implemented_op},
1131
1132 {"swapnb", 0xA770, 0x5880, "r", 0, SIZE_NONE,
1133 cris_ver_v8p,
1134 cris_not_implemented_op},
1135
1136 {"swapwb", 0x6770, 0x9880, "r", 0, SIZE_NONE,
1137 cris_ver_v8p,
1138 cris_not_implemented_op},
1139
1140 {"swapnwb", 0xE770, 0x1880, "r", 0, SIZE_NONE,
1141 cris_ver_v8p,
1142 cris_not_implemented_op},
1143
1144 {"swapr", 0x1770, 0xe880, "r", 0, SIZE_NONE,
1145 cris_ver_v8p,
1146 cris_not_implemented_op},
1147
1148 {"swapnr", 0x9770, 0x6880, "r", 0, SIZE_NONE,
1149 cris_ver_v8p,
1150 cris_not_implemented_op},
1151
1152 {"swapwr", 0x5770, 0xa880, "r", 0, SIZE_NONE,
1153 cris_ver_v8p,
1154 cris_not_implemented_op},
1155
1156 {"swapnwr", 0xd770, 0x2880, "r", 0, SIZE_NONE,
1157 cris_ver_v8p,
1158 cris_not_implemented_op},
1159
1160 {"swapbr", 0x3770, 0xc880, "r", 0, SIZE_NONE,
1161 cris_ver_v8p,
1162 cris_not_implemented_op},
1163
1164 {"swapnbr", 0xb770, 0x4880, "r", 0, SIZE_NONE,
1165 cris_ver_v8p,
1166 cris_not_implemented_op},
1167
1168 {"swapwbr", 0x7770, 0x8880, "r", 0, SIZE_NONE,
1169 cris_ver_v8p,
1170 cris_not_implemented_op},
1171
1172 {"swapnwbr", 0xf770, 0x0880, "r", 0, SIZE_NONE,
1173 cris_ver_v8p,
1174 cris_not_implemented_op},
1175
1176 {"test", 0x0640, 0x0980, "m D", 0, SIZE_NONE,
1177 cris_ver_v0_10,
1178 cris_reg_mode_test_op},
1179
1180 {"test", 0x0b80, 0xf040, "m y", 0, SIZE_FIELD, 0,
1181 cris_none_reg_mode_clear_test_op},
1182
1183 {"test", 0x0b80, 0xf040, "m S", 0, SIZE_NONE,
1184 cris_ver_v0_10,
1185 cris_none_reg_mode_clear_test_op},
1186
1187 {"xor", 0x07B0, 0x0840, "r,R", 0, SIZE_NONE, 0,
1188 cris_xor_op},
1189
1190 {NULL, 0, 0, NULL, 0, 0, 0, cris_not_implemented_op}
1191 };
1192
1193 /* Condition-names, indexed by the CC_* numbers as found in cris.h. */
1194 const char * const
1195 cris_cc_strings[] =
1196 {
1197 "hs",
1198 "lo",
1199 "ne",
1200 "eq",
1201 "vc",
1202 "vs",
1203 "pl",
1204 "mi",
1205 "ls",
1206 "hi",
1207 "ge",
1208 "lt",
1209 "gt",
1210 "le",
1211 "a",
1212 /* This is a placeholder. In v0, this would be "ext". In v32, this
1213 is "sb". See cris_conds15. */
1214 "wf"
1215 };
1216
1217 /* Different names and semantics for condition 1111 (0xf). */
1218 const struct cris_cond15 cris_cond15s[] =
1219 {
1220 /* FIXME: In what version did condition "ext" disappear? */
1221 {"ext", cris_ver_v0_3},
1222 {"wf", cris_ver_v10},
1223 {"sb", cris_ver_v32p},
1224 {NULL, 0}
1225 };
1226
1227
1228 /*
1229 * Local variables:
1230 * eval: (c-set-style "gnu")
1231 * indent-tabs-mode: t
1232 * End:
1233 */
1234
1235
1236 /* No instruction will be disassembled longer than this. In theory, and
1237 in silicon, address prefixes can be cascaded. In practice, cascading
1238 is not used by GCC, and not supported by the assembler. */
1239 #ifndef MAX_BYTES_PER_CRIS_INSN
1240 #define MAX_BYTES_PER_CRIS_INSN 8
1241 #endif
1242
1243 /* Whether or not to decode prefixes, folding it into the following
1244 instruction. FIXME: Make this optional later. */
1245 #ifndef PARSE_PREFIX
1246 #define PARSE_PREFIX 1
1247 #endif
1248
1249 /* Sometimes we prefix all registers with this character. */
1250 #define REGISTER_PREFIX_CHAR '$'
1251
1252 /* Whether or not to trace the following sequence:
1253 sub* X,r%d
1254 bound* Y,r%d
1255 adds.w [pc+r%d.w],pc
1256
1257 This is the assembly form of a switch-statement in C.
1258 The "sub is optional. If there is none, then X will be zero.
1259 X is the value of the first case,
1260 Y is the number of cases (including default).
1261
1262 This results in case offsets printed on the form:
1263 case N: -> case_address
1264 where N is an estimation on the corresponding 'case' operand in C,
1265 and case_address is where execution of that case continues after the
1266 sequence presented above.
1267
1268 The old style of output was to print the offsets as instructions,
1269 which made it hard to follow "case"-constructs in the disassembly,
1270 and caused a lot of annoying warnings about undefined instructions.
1271
1272 FIXME: Make this optional later. */
1273 #ifndef TRACE_CASE
1274 #define TRACE_CASE (disdata->trace_case)
1275 #endif
1276
1277 enum cris_disass_family
1278 { cris_dis_v0_v10, cris_dis_common_v10_v32, cris_dis_v32 };
1279
1280 /* Stored in the disasm_info->private_data member. */
1281 struct cris_disasm_data
1282 {
1283 /* Whether to print something less confusing if we find something
1284 matching a switch-construct. */
1285 bfd_boolean trace_case;
1286
1287 /* Whether this code is flagged as crisv32. FIXME: Should be an enum
1288 that includes "compatible". */
1289 enum cris_disass_family distype;
1290 };
1291
1292 /* Value of first element in switch. */
1293 static long case_offset = 0;
1294
1295 /* How many more case-offsets to print. */
1296 static long case_offset_counter = 0;
1297
1298 /* Number of case offsets. */
1299 static long no_of_case_offsets = 0;
1300
1301 /* Candidate for next case_offset. */
1302 static long last_immediate = 0;
1303
1304 static int cris_constraint
1305 (const char *, unsigned, unsigned, struct cris_disasm_data *);
1306
1307 /* Parse disassembler options and store state in info. FIXME: For the
1308 time being, we abuse static variables. */
1309
1310 static bfd_boolean
1311 cris_parse_disassembler_options (disassemble_info *info,
1312 enum cris_disass_family distype)
1313 {
1314 struct cris_disasm_data *disdata;
1315
1316 info->private_data = calloc (1, sizeof (struct cris_disasm_data));
1317 disdata = (struct cris_disasm_data *) info->private_data;
1318 if (disdata == NULL)
1319 return false;
1320
1321 /* Default true. */
1322 disdata->trace_case
1323 = (info->disassembler_options == NULL
1324 || (strcmp (info->disassembler_options, "nocase") != 0));
1325
1326 disdata->distype = distype;
1327 return true;
1328 }
1329
1330 static const struct cris_spec_reg *
1331 spec_reg_info (unsigned int sreg, enum cris_disass_family distype)
1332 {
1333 int i;
1334
1335 for (i = 0; cris_spec_regs[i].name != NULL; i++)
1336 {
1337 if (cris_spec_regs[i].number == sreg)
1338 {
1339 if (distype == cris_dis_v32)
1340 switch (cris_spec_regs[i].applicable_version)
1341 {
1342 case cris_ver_warning:
1343 case cris_ver_version_all:
1344 case cris_ver_v3p:
1345 case cris_ver_v8p:
1346 case cris_ver_v10p:
1347 case cris_ver_v32p:
1348 /* No ambiguous sizes or register names with CRISv32. */
1349 if (cris_spec_regs[i].warning == NULL)
1350 return &cris_spec_regs[i];
1351 default:
1352 ;
1353 }
1354 else if (cris_spec_regs[i].applicable_version != cris_ver_v32p)
1355 return &cris_spec_regs[i];
1356 }
1357 }
1358
1359 return NULL;
1360 }
1361
1362 /* Return the number of bits in the argument. */
1363
1364 static int
1365 number_of_bits (unsigned int val)
1366 {
1367 int bits;
1368
1369 for (bits = 0; val != 0; val &= val - 1)
1370 bits++;
1371
1372 return bits;
1373 }
1374
1375 /* Get an entry in the opcode-table. */
1376
1377 static const struct cris_opcode *
1378 get_opcode_entry (unsigned int insn,
1379 unsigned int prefix_insn,
1380 struct cris_disasm_data *disdata)
1381 {
1382 /* For non-prefixed insns, we keep a table of pointers, indexed by the
1383 insn code. Each entry is initialized when found to be NULL. */
1384 static const struct cris_opcode **opc_table = NULL;
1385
1386 const struct cris_opcode *max_matchedp = NULL;
1387 const struct cris_opcode **prefix_opc_table = NULL;
1388
1389 /* We hold a table for each prefix that need to be handled differently. */
1390 static const struct cris_opcode **dip_prefixes = NULL;
1391 static const struct cris_opcode **bdapq_m1_prefixes = NULL;
1392 static const struct cris_opcode **bdapq_m2_prefixes = NULL;
1393 static const struct cris_opcode **bdapq_m4_prefixes = NULL;
1394 static const struct cris_opcode **rest_prefixes = NULL;
1395
1396 /* Allocate and clear the opcode-table. */
1397 if (opc_table == NULL)
1398 {
1399 opc_table = g_new0(const struct cris_opcode *, 65536);
1400 dip_prefixes = g_new0(const struct cris_opcode *, 65536);
1401 bdapq_m1_prefixes = g_new0(const struct cris_opcode *, 65536);
1402 bdapq_m2_prefixes = g_new0(const struct cris_opcode *, 65536);
1403 bdapq_m4_prefixes = g_new0(const struct cris_opcode *, 65536);
1404 rest_prefixes = g_new0(const struct cris_opcode *, 65536);
1405 }
1406
1407 /* Get the right table if this is a prefix.
1408 This code is connected to cris_constraints in that it knows what
1409 prefixes play a role in recognition of patterns; the necessary
1410 state is reflected by which table is used. If constraints
1411 involving match or non-match of prefix insns are changed, then this
1412 probably needs changing too. */
1413 if (prefix_insn != NO_CRIS_PREFIX)
1414 {
1415 const struct cris_opcode *popcodep
1416 = (opc_table[prefix_insn] != NULL
1417 ? opc_table[prefix_insn]
1418 : get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata));
1419
1420 if (popcodep == NULL)
1421 return NULL;
1422
1423 if (popcodep->match == BDAP_QUICK_OPCODE)
1424 {
1425 /* Since some offsets are recognized with "push" macros, we
1426 have to have different tables for them. */
1427 int offset = (prefix_insn & 255);
1428
1429 if (offset > 127)
1430 offset -= 256;
1431
1432 switch (offset)
1433 {
1434 case -4:
1435 prefix_opc_table = bdapq_m4_prefixes;
1436 break;
1437
1438 case -2:
1439 prefix_opc_table = bdapq_m2_prefixes;
1440 break;
1441
1442 case -1:
1443 prefix_opc_table = bdapq_m1_prefixes;
1444 break;
1445
1446 default:
1447 prefix_opc_table = rest_prefixes;
1448 break;
1449 }
1450 }
1451 else if (popcodep->match == DIP_OPCODE)
1452 /* We don't allow postincrement when the prefix is DIP, so use a
1453 different table for DIP. */
1454 prefix_opc_table = dip_prefixes;
1455 else
1456 prefix_opc_table = rest_prefixes;
1457 }
1458
1459 if (prefix_insn != NO_CRIS_PREFIX
1460 && prefix_opc_table[insn] != NULL)
1461 max_matchedp = prefix_opc_table[insn];
1462 else if (prefix_insn == NO_CRIS_PREFIX && opc_table[insn] != NULL)
1463 max_matchedp = opc_table[insn];
1464 else
1465 {
1466 const struct cris_opcode *opcodep;
1467 int max_level_of_match = -1;
1468
1469 for (opcodep = cris_opcodes;
1470 opcodep->name != NULL;
1471 opcodep++)
1472 {
1473 int level_of_match;
1474
1475 if (disdata->distype == cris_dis_v32)
1476 {
1477 switch (opcodep->applicable_version)
1478 {
1479 case cris_ver_version_all:
1480 break;
1481
1482 case cris_ver_v0_3:
1483 case cris_ver_v0_10:
1484 case cris_ver_v3_10:
1485 case cris_ver_sim_v0_10:
1486 case cris_ver_v8_10:
1487 case cris_ver_v10:
1488 case cris_ver_warning:
1489 continue;
1490
1491 case cris_ver_v3p:
1492 case cris_ver_v8p:
1493 case cris_ver_v10p:
1494 case cris_ver_v32p:
1495 break;
1496
1497 case cris_ver_v8:
1498 abort ();
1499 default:
1500 abort ();
1501 }
1502 }
1503 else
1504 {
1505 switch (opcodep->applicable_version)
1506 {
1507 case cris_ver_version_all:
1508 case cris_ver_v0_3:
1509 case cris_ver_v3p:
1510 case cris_ver_v0_10:
1511 case cris_ver_v8p:
1512 case cris_ver_v8_10:
1513 case cris_ver_v10:
1514 case cris_ver_sim_v0_10:
1515 case cris_ver_v10p:
1516 case cris_ver_warning:
1517 break;
1518
1519 case cris_ver_v32p:
1520 continue;
1521
1522 case cris_ver_v8:
1523 abort ();
1524 default:
1525 abort ();
1526 }
1527 }
1528
1529 /* We give a double lead for bits matching the template in
1530 cris_opcodes. Not even, because then "move p8,r10" would
1531 be given 2 bits lead over "clear.d r10". When there's a
1532 tie, the first entry in the table wins. This is
1533 deliberate, to avoid a more complicated recognition
1534 formula. */
1535 if ((opcodep->match & insn) == opcodep->match
1536 && (opcodep->lose & insn) == 0
1537 && ((level_of_match
1538 = cris_constraint (opcodep->args,
1539 insn,
1540 prefix_insn,
1541 disdata))
1542 >= 0)
1543 && ((level_of_match
1544 += 2 * number_of_bits (opcodep->match
1545 | opcodep->lose))
1546 > max_level_of_match))
1547 {
1548 max_matchedp = opcodep;
1549 max_level_of_match = level_of_match;
1550
1551 /* If there was a full match, never mind looking
1552 further. */
1553 if (level_of_match >= 2 * 16)
1554 break;
1555 }
1556 }
1557 /* Fill in the new entry.
1558
1559 If there are changes to the opcode-table involving prefixes, and
1560 disassembly then does not work correctly, try removing the
1561 else-clause below that fills in the prefix-table. If that
1562 helps, you need to change the prefix_opc_table setting above, or
1563 something related. */
1564 if (prefix_insn == NO_CRIS_PREFIX)
1565 opc_table[insn] = max_matchedp;
1566 else
1567 prefix_opc_table[insn] = max_matchedp;
1568 }
1569
1570 return max_matchedp;
1571 }
1572
1573 /* Return -1 if the constraints of a bitwise-matched instruction say
1574 that there is no match. Otherwise return a nonnegative number
1575 indicating the confidence in the match (higher is better). */
1576
1577 static int
1578 cris_constraint (const char *cs,
1579 unsigned int insn,
1580 unsigned int prefix_insn,
1581 struct cris_disasm_data *disdata)
1582 {
1583 int retval = 0;
1584 int tmp;
1585 int prefix_ok = 0;
1586 const char *s;
1587
1588 for (s = cs; *s; s++)
1589 switch (*s)
1590 {
1591 case '!':
1592 /* Do not recognize "pop" if there's a prefix and then only for
1593 v0..v10. */
1594 if (prefix_insn != NO_CRIS_PREFIX
1595 || disdata->distype != cris_dis_v0_v10)
1596 return -1;
1597 break;
1598
1599 case 'U':
1600 /* Not recognized at disassembly. */
1601 return -1;
1602
1603 case 'M':
1604 /* Size modifier for "clear", i.e. special register 0, 4 or 8.
1605 Check that it is one of them. Only special register 12 could
1606 be mismatched, but checking for matches is more logical than
1607 checking for mismatches when there are only a few cases. */
1608 tmp = ((insn >> 12) & 0xf);
1609 if (tmp != 0 && tmp != 4 && tmp != 8)
1610 return -1;
1611 break;
1612
1613 case 'm':
1614 if ((insn & 0x30) == 0x30)
1615 return -1;
1616 break;
1617
1618 case 'S':
1619 /* A prefix operand without side-effect. */
1620 if (prefix_insn != NO_CRIS_PREFIX && (insn & 0x400) == 0)
1621 {
1622 prefix_ok = 1;
1623 break;
1624 }
1625 else
1626 return -1;
1627
1628 case 's':
1629 case 'y':
1630 case 'Y':
1631 /* If this is a prefixed insn with postincrement (side-effect),
1632 the prefix must not be DIP. */
1633 if (prefix_insn != NO_CRIS_PREFIX)
1634 {
1635 if (insn & 0x400)
1636 {
1637 const struct cris_opcode *prefix_opcodep
1638 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1639
1640 if (prefix_opcodep->match == DIP_OPCODE)
1641 return -1;
1642 }
1643
1644 prefix_ok = 1;
1645 }
1646 break;
1647
1648 case 'B':
1649 /* If we don't fall through, then the prefix is ok. */
1650 prefix_ok = 1;
1651
1652 /* A "push" prefix. Check for valid "push" size.
1653 In case of special register, it may be != 4. */
1654 if (prefix_insn != NO_CRIS_PREFIX)
1655 {
1656 /* Match the prefix insn to BDAPQ. */
1657 const struct cris_opcode *prefix_opcodep
1658 = get_opcode_entry (prefix_insn, NO_CRIS_PREFIX, disdata);
1659
1660 if (prefix_opcodep->match == BDAP_QUICK_OPCODE)
1661 {
1662 int pushsize = (prefix_insn & 255);
1663
1664 if (pushsize > 127)
1665 pushsize -= 256;
1666
1667 if (s[1] == 'P')
1668 {
1669 unsigned int spec_reg = (insn >> 12) & 15;
1670 const struct cris_spec_reg *sregp
1671 = spec_reg_info (spec_reg, disdata->distype);
1672
1673 /* For a special-register, the "prefix size" must
1674 match the size of the register. */
1675 if (sregp && sregp->reg_size == (unsigned int) -pushsize)
1676 break;
1677 }
1678 else if (s[1] == 'R')
1679 {
1680 if ((insn & 0x30) == 0x20 && pushsize == -4)
1681 break;
1682 }
1683 /* FIXME: Should abort here; next constraint letter
1684 *must* be 'P' or 'R'. */
1685 }
1686 }
1687 return -1;
1688
1689 case 'D':
1690 retval = (((insn >> 12) & 15) == (insn & 15));
1691 if (!retval)
1692 return -1;
1693 else
1694 retval += 4;
1695 break;
1696
1697 case 'P':
1698 {
1699 const struct cris_spec_reg *sregp
1700 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
1701
1702 /* Since we match four bits, we will give a value of 4-1 = 3
1703 in a match. If there is a corresponding exact match of a
1704 special register in another pattern, it will get a value of
1705 4, which will be higher. This should be correct in that an
1706 exact pattern would match better than a general pattern.
1707
1708 Note that there is a reason for not returning zero; the
1709 pattern for "clear" is partly matched in the bit-pattern
1710 (the two lower bits must be zero), while the bit-pattern
1711 for a move from a special register is matched in the
1712 register constraint. */
1713
1714 if (sregp != NULL)
1715 {
1716 retval += 3;
1717 break;
1718 }
1719 else
1720 return -1;
1721 }
1722 }
1723
1724 if (prefix_insn != NO_CRIS_PREFIX && ! prefix_ok)
1725 return -1;
1726
1727 return retval;
1728 }
1729
1730 /* Format number as hex with a leading "0x" into outbuffer. */
1731
1732 static char *
1733 format_hex (unsigned long number,
1734 char *outbuffer,
1735 struct cris_disasm_data *disdata)
1736 {
1737 /* Truncate negative numbers on >32-bit hosts. */
1738 number &= 0xffffffff;
1739
1740 sprintf (outbuffer, "0x%lx", number);
1741
1742 /* Save this value for the "case" support. */
1743 if (TRACE_CASE)
1744 last_immediate = number;
1745
1746 return outbuffer + strlen (outbuffer);
1747 }
1748
1749 /* Format number as decimal into outbuffer. Parameter signedp says
1750 whether the number should be formatted as signed (!= 0) or
1751 unsigned (== 0). */
1752
1753 static char *
1754 format_dec (long number, char *outbuffer, int signedp)
1755 {
1756 last_immediate = number;
1757 sprintf (outbuffer, signedp ? "%ld" : "%lu", number);
1758
1759 return outbuffer + strlen (outbuffer);
1760 }
1761
1762 /* Format the name of the general register regno into outbuffer. */
1763
1764 static char *
1765 format_reg (struct cris_disasm_data *disdata,
1766 int regno,
1767 char *outbuffer_start,
1768 bfd_boolean with_reg_prefix)
1769 {
1770 char *outbuffer = outbuffer_start;
1771
1772 if (with_reg_prefix)
1773 *outbuffer++ = REGISTER_PREFIX_CHAR;
1774
1775 switch (regno)
1776 {
1777 case 15:
1778 /* For v32, there is no context in which we output PC. */
1779 if (disdata->distype == cris_dis_v32)
1780 strcpy (outbuffer, "acr");
1781 else
1782 strcpy (outbuffer, "pc");
1783 break;
1784
1785 case 14:
1786 strcpy (outbuffer, "sp");
1787 break;
1788
1789 default:
1790 sprintf (outbuffer, "r%d", regno);
1791 break;
1792 }
1793
1794 return outbuffer_start + strlen (outbuffer_start);
1795 }
1796
1797 /* Format the name of a support register into outbuffer. */
1798
1799 static char *
1800 format_sup_reg (unsigned int regno,
1801 char *outbuffer_start,
1802 bfd_boolean with_reg_prefix)
1803 {
1804 char *outbuffer = outbuffer_start;
1805 int i;
1806
1807 if (with_reg_prefix)
1808 *outbuffer++ = REGISTER_PREFIX_CHAR;
1809
1810 for (i = 0; cris_support_regs[i].name != NULL; i++)
1811 if (cris_support_regs[i].number == regno)
1812 {
1813 sprintf (outbuffer, "%s", cris_support_regs[i].name);
1814 return outbuffer_start + strlen (outbuffer_start);
1815 }
1816
1817 /* There's supposed to be register names covering all numbers, though
1818 some may be generic names. */
1819 sprintf (outbuffer, "format_sup_reg-BUG");
1820 return outbuffer_start + strlen (outbuffer_start);
1821 }
1822
1823 /* Return the length of an instruction. */
1824
1825 static unsigned
1826 bytes_to_skip (unsigned int insn,
1827 const struct cris_opcode *matchedp,
1828 enum cris_disass_family distype,
1829 const struct cris_opcode *prefix_matchedp)
1830 {
1831 /* Each insn is a word plus "immediate" operands. */
1832 unsigned to_skip = 2;
1833 const char *template = matchedp->args;
1834 const char *s;
1835
1836 for (s = template; *s; s++)
1837 if ((*s == 's' || *s == 'N' || *s == 'Y')
1838 && (insn & 0x400) && (insn & 15) == 15
1839 && prefix_matchedp == NULL)
1840 {
1841 /* Immediate via [pc+], so we have to check the size of the
1842 operand. */
1843 int mode_size = 1 << ((insn >> 4) & (*template == 'z' ? 1 : 3));
1844
1845 if (matchedp->imm_oprnd_size == SIZE_FIX_32)
1846 to_skip += 4;
1847 else if (matchedp->imm_oprnd_size == SIZE_SPEC_REG)
1848 {
1849 const struct cris_spec_reg *sregp
1850 = spec_reg_info ((insn >> 12) & 15, distype);
1851
1852 /* FIXME: Improve error handling; should have been caught
1853 earlier. */
1854 if (sregp == NULL)
1855 return 2;
1856
1857 /* PC is incremented by two, not one, for a byte. Except on
1858 CRISv32, where constants are always DWORD-size for
1859 special registers. */
1860 to_skip +=
1861 distype == cris_dis_v32 ? 4 : (sregp->reg_size + 1) & ~1;
1862 }
1863 else
1864 to_skip += (mode_size + 1) & ~1;
1865 }
1866 else if (*s == 'n')
1867 to_skip += 4;
1868 else if (*s == 'b')
1869 to_skip += 2;
1870
1871 return to_skip;
1872 }
1873
1874 /* Print condition code flags. */
1875
1876 static char *
1877 print_flags (struct cris_disasm_data *disdata, unsigned int insn, char *cp)
1878 {
1879 /* Use the v8 (Etrax 100) flag definitions for disassembly.
1880 The differences with v0 (Etrax 1..4) vs. Svinto are:
1881 v0 'd' <=> v8 'm'
1882 v0 'e' <=> v8 'b'.
1883 FIXME: Emit v0..v3 flag names somehow. */
1884 static const char v8_fnames[] = "cvznxibm";
1885 static const char v32_fnames[] = "cvznxiup";
1886 const char *fnames
1887 = disdata->distype == cris_dis_v32 ? v32_fnames : v8_fnames;
1888
1889 unsigned char flagbits = (((insn >> 8) & 0xf0) | (insn & 15));
1890 int i;
1891
1892 for (i = 0; i < 8; i++)
1893 if (flagbits & (1 << i))
1894 *cp++ = fnames[i];
1895
1896 return cp;
1897 }
1898
1899 /* Print out an insn with its operands, and update the info->insn_type
1900 fields. The prefix_opcodep and the rest hold a prefix insn that is
1901 supposed to be output as an address mode. */
1902
1903 static void
1904 print_with_operands (const struct cris_opcode *opcodep,
1905 unsigned int insn,
1906 unsigned char *buffer,
1907 bfd_vma addr,
1908 disassemble_info *info,
1909 /* If a prefix insn was before this insn (and is supposed
1910 to be output as an address), here is a description of
1911 it. */
1912 const struct cris_opcode *prefix_opcodep,
1913 unsigned int prefix_insn,
1914 unsigned char *prefix_buffer,
1915 bfd_boolean with_reg_prefix)
1916 {
1917 /* Get a buffer of somewhat reasonable size where we store
1918 intermediate parts of the insn. */
1919 char temp[sizeof (".d [$r13=$r12-2147483648],$r10") * 2];
1920 char *tp = temp;
1921 static const char mode_char[] = "bwd?";
1922 const char *s;
1923 const char *cs;
1924 struct cris_disasm_data *disdata
1925 = (struct cris_disasm_data *) info->private_data;
1926
1927 /* Print out the name first thing we do. */
1928 (*info->fprintf_func) (info->stream, "%s", opcodep->name);
1929
1930 cs = opcodep->args;
1931 s = cs;
1932
1933 /* Ignore any prefix indicator. */
1934 if (*s == 'p')
1935 s++;
1936
1937 if (*s == 'm' || *s == 'M' || *s == 'z')
1938 {
1939 *tp++ = '.';
1940
1941 /* Get the size-letter. */
1942 *tp++ = *s == 'M'
1943 ? (insn & 0x8000 ? 'd'
1944 : insn & 0x4000 ? 'w' : 'b')
1945 : mode_char[(insn >> 4) & (*s == 'z' ? 1 : 3)];
1946
1947 /* Ignore the size and the space character that follows. */
1948 s += 2;
1949 }
1950
1951 /* Add a space if this isn't a long-branch, because for those will add
1952 the condition part of the name later. */
1953 if (opcodep->match != (BRANCH_PC_LOW + BRANCH_INCR_HIGH * 256))
1954 *tp++ = ' ';
1955
1956 /* Fill in the insn-type if deducible from the name (and there's no
1957 better way). */
1958 if (opcodep->name[0] == 'j')
1959 {
1960 if (CONST_STRNEQ (opcodep->name, "jsr"))
1961 /* It's "jsr" or "jsrc". */
1962 info->insn_type = dis_jsr;
1963 else
1964 /* Any other jump-type insn is considered a branch. */
1965 info->insn_type = dis_branch;
1966 }
1967
1968 /* We might know some more fields right now. */
1969 info->branch_delay_insns = opcodep->delayed;
1970
1971 /* Handle operands. */
1972 for (; *s; s++)
1973 {
1974 switch (*s)
1975 {
1976 case 'T':
1977 tp = format_sup_reg ((insn >> 12) & 15, tp, with_reg_prefix);
1978 break;
1979
1980 case 'A':
1981 if (with_reg_prefix)
1982 *tp++ = REGISTER_PREFIX_CHAR;
1983 *tp++ = 'a';
1984 *tp++ = 'c';
1985 *tp++ = 'r';
1986 break;
1987
1988 case '[':
1989 case ']':
1990 case ',':
1991 *tp++ = *s;
1992 break;
1993
1994 case '!':
1995 /* Ignore at this point; used at earlier stages to avoid
1996 recognition if there's a prefix at something that in other
1997 ways looks like a "pop". */
1998 break;
1999
2000 case 'd':
2001 /* Ignore. This is an optional ".d " on the large one of
2002 relaxable insns. */
2003 break;
2004
2005 case 'B':
2006 /* This was the prefix that made this a "push". We've already
2007 handled it by recognizing it, so signal that the prefix is
2008 handled by setting it to NULL. */
2009 prefix_opcodep = NULL;
2010 break;
2011
2012 case 'D':
2013 case 'r':
2014 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2015 break;
2016
2017 case 'R':
2018 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2019 break;
2020
2021 case 'n':
2022 {
2023 /* Like N but pc-relative to the start of the insn. */
2024 unsigned long number
2025 = (buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2026 + buffer[5] * 0x1000000 + addr);
2027
2028 /* Finish off and output previous formatted bytes. */
2029 *tp = 0;
2030 if (temp[0])
2031 (*info->fprintf_func) (info->stream, "%s", temp);
2032 tp = temp;
2033
2034 (*info->print_address_func) ((bfd_vma) number, info);
2035 }
2036 break;
2037
2038 case 'u':
2039 {
2040 /* Like n but the offset is bits <3:0> in the instruction. */
2041 unsigned long number = (buffer[0] & 0xf) * 2 + addr;
2042
2043 /* Finish off and output previous formatted bytes. */
2044 *tp = 0;
2045 if (temp[0])
2046 (*info->fprintf_func) (info->stream, "%s", temp);
2047 tp = temp;
2048
2049 (*info->print_address_func) ((bfd_vma) number, info);
2050 }
2051 break;
2052
2053 case 'N':
2054 case 'y':
2055 case 'Y':
2056 case 'S':
2057 case 's':
2058 /* Any "normal" memory operand. */
2059 if ((insn & 0x400) && (insn & 15) == 15 && prefix_opcodep == NULL)
2060 {
2061 /* We're looking at [pc+], i.e. we need to output an immediate
2062 number, where the size can depend on different things. */
2063 long number;
2064 int signedp
2065 = ((*cs == 'z' && (insn & 0x20))
2066 || opcodep->match == BDAP_QUICK_OPCODE);
2067 int nbytes;
2068
2069 if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2070 nbytes = 4;
2071 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2072 {
2073 const struct cris_spec_reg *sregp
2074 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2075
2076 /* A NULL return should have been as a non-match earlier,
2077 so catch it as an internal error in the error-case
2078 below. */
2079 if (sregp == NULL)
2080 /* Whatever non-valid size. */
2081 nbytes = 42;
2082 else
2083 /* PC is always incremented by a multiple of two.
2084 For CRISv32, immediates are always 4 bytes for
2085 special registers. */
2086 nbytes = disdata->distype == cris_dis_v32
2087 ? 4 : (sregp->reg_size + 1) & ~1;
2088 }
2089 else
2090 {
2091 int mode_size = 1 << ((insn >> 4) & (*cs == 'z' ? 1 : 3));
2092
2093 if (mode_size == 1)
2094 nbytes = 2;
2095 else
2096 nbytes = mode_size;
2097 }
2098
2099 switch (nbytes)
2100 {
2101 case 1:
2102 number = buffer[2];
2103 if (signedp && number > 127)
2104 number -= 256;
2105 break;
2106
2107 case 2:
2108 number = buffer[2] + buffer[3] * 256;
2109 if (signedp && number > 32767)
2110 number -= 65536;
2111 break;
2112
2113 case 4:
2114 number
2115 = buffer[2] + buffer[3] * 256 + buffer[4] * 65536
2116 + buffer[5] * 0x1000000;
2117 break;
2118
2119 default:
2120 strcpy (tp, "bug");
2121 tp += 3;
2122 number = 42;
2123 }
2124
2125 if ((*cs == 'z' && (insn & 0x20))
2126 || (opcodep->match == BDAP_QUICK_OPCODE
2127 && (nbytes <= 2 || buffer[1 + nbytes] == 0)))
2128 tp = format_dec (number, tp, signedp);
2129 else
2130 {
2131 unsigned int highbyte = (number >> 24) & 0xff;
2132
2133 /* Either output this as an address or as a number. If it's
2134 a dword with the same high-byte as the address of the
2135 insn, assume it's an address, and also if it's a non-zero
2136 non-0xff high-byte. If this is a jsr or a jump, then
2137 it's definitely an address. */
2138 if (nbytes == 4
2139 && (highbyte == ((addr >> 24) & 0xff)
2140 || (highbyte != 0 && highbyte != 0xff)
2141 || info->insn_type == dis_branch
2142 || info->insn_type == dis_jsr))
2143 {
2144 /* Finish off and output previous formatted bytes. */
2145 *tp = 0;
2146 tp = temp;
2147 if (temp[0])
2148 (*info->fprintf_func) (info->stream, "%s", temp);
2149
2150 (*info->print_address_func) ((bfd_vma) number, info);
2151
2152 info->target = number;
2153 }
2154 else
2155 tp = format_hex (number, tp, disdata);
2156 }
2157 }
2158 else
2159 {
2160 /* Not an immediate number. Then this is a (possibly
2161 prefixed) memory operand. */
2162 if (info->insn_type != dis_nonbranch)
2163 {
2164 int mode_size
2165 = 1 << ((insn >> 4)
2166 & (opcodep->args[0] == 'z' ? 1 : 3));
2167 int size;
2168 info->insn_type = dis_dref;
2169 info->flags |= CRIS_DIS_FLAG_MEMREF;
2170
2171 if (opcodep->imm_oprnd_size == SIZE_FIX_32)
2172 size = 4;
2173 else if (opcodep->imm_oprnd_size == SIZE_SPEC_REG)
2174 {
2175 const struct cris_spec_reg *sregp
2176 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2177
2178 /* FIXME: Improve error handling; should have been caught
2179 earlier. */
2180 if (sregp == NULL)
2181 size = 4;
2182 else
2183 size = sregp->reg_size;
2184 }
2185 else
2186 size = mode_size;
2187
2188 info->data_size = size;
2189 }
2190
2191 *tp++ = '[';
2192
2193 if (prefix_opcodep
2194 /* We don't match dip with a postincremented field
2195 as a side-effect address mode. */
2196 && ((insn & 0x400) == 0
2197 || prefix_opcodep->match != DIP_OPCODE))
2198 {
2199 if (insn & 0x400)
2200 {
2201 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2202 *tp++ = '=';
2203 }
2204
2205
2206 /* We mainly ignore the prefix format string when the
2207 address-mode syntax is output. */
2208 switch (prefix_opcodep->match)
2209 {
2210 case DIP_OPCODE:
2211 /* It's [r], [r+] or [pc+]. */
2212 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2213 {
2214 /* It's [pc+]. This cannot possibly be anything
2215 but an address. */
2216 unsigned long number
2217 = prefix_buffer[2] + prefix_buffer[3] * 256
2218 + prefix_buffer[4] * 65536
2219 + prefix_buffer[5] * 0x1000000;
2220
2221 info->target = (bfd_vma) number;
2222
2223 /* Finish off and output previous formatted
2224 data. */
2225 *tp = 0;
2226 tp = temp;
2227 if (temp[0])
2228 (*info->fprintf_func) (info->stream, "%s", temp);
2229
2230 (*info->print_address_func) ((bfd_vma) number, info);
2231 }
2232 else
2233 {
2234 /* For a memref in an address, we use target2.
2235 In this case, target is zero. */
2236 info->flags
2237 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2238 | CRIS_DIS_FLAG_MEM_TARGET2_MEM);
2239
2240 info->target2 = prefix_insn & 15;
2241
2242 *tp++ = '[';
2243 tp = format_reg (disdata, prefix_insn & 15, tp,
2244 with_reg_prefix);
2245 if (prefix_insn & 0x400)
2246 *tp++ = '+';
2247 *tp++ = ']';
2248 }
2249 break;
2250
2251 case BDAP_QUICK_OPCODE:
2252 {
2253 int number;
2254
2255 number = prefix_buffer[0];
2256 if (number > 127)
2257 number -= 256;
2258
2259 /* Output "reg+num" or, if num < 0, "reg-num". */
2260 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2261 with_reg_prefix);
2262 if (number >= 0)
2263 *tp++ = '+';
2264 tp = format_dec (number, tp, 1);
2265
2266 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2267 info->target = (prefix_insn >> 12) & 15;
2268 info->target2 = (bfd_vma) number;
2269 break;
2270 }
2271
2272 case BIAP_OPCODE:
2273 /* Output "r+R.m". */
2274 tp = format_reg (disdata, prefix_insn & 15, tp,
2275 with_reg_prefix);
2276 *tp++ = '+';
2277 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2278 with_reg_prefix);
2279 *tp++ = '.';
2280 *tp++ = mode_char[(prefix_insn >> 4) & 3];
2281
2282 info->flags
2283 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2284 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2285
2286 | ((prefix_insn & 0x8000)
2287 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT4
2288 : ((prefix_insn & 0x8000)
2289 ? CRIS_DIS_FLAG_MEM_TARGET2_MULT2 : 0)));
2290
2291 /* Is it the casejump? It's a "adds.w [pc+r%d.w],pc". */
2292 if (insn == 0xf83f && (prefix_insn & ~0xf000) == 0x55f)
2293 /* Then start interpreting data as offsets. */
2294 case_offset_counter = no_of_case_offsets;
2295 break;
2296
2297 case BDAP_INDIR_OPCODE:
2298 /* Output "r+s.m", or, if "s" is [pc+], "r+s" or
2299 "r-s". */
2300 tp = format_reg (disdata, (prefix_insn >> 12) & 15, tp,
2301 with_reg_prefix);
2302
2303 if ((prefix_insn & 0x400) && (prefix_insn & 15) == 15)
2304 {
2305 long number;
2306 unsigned int nbytes;
2307
2308 /* It's a value. Get its size. */
2309 int mode_size = 1 << ((prefix_insn >> 4) & 3);
2310
2311 if (mode_size == 1)
2312 nbytes = 2;
2313 else
2314 nbytes = mode_size;
2315
2316 switch (nbytes)
2317 {
2318 case 1:
2319 number = prefix_buffer[2];
2320 if (number > 127)
2321 number -= 256;
2322 break;
2323
2324 case 2:
2325 number = prefix_buffer[2] + prefix_buffer[3] * 256;
2326 if (number > 32767)
2327 number -= 65536;
2328 break;
2329
2330 case 4:
2331 number
2332 = prefix_buffer[2] + prefix_buffer[3] * 256
2333 + prefix_buffer[4] * 65536
2334 + prefix_buffer[5] * 0x1000000;
2335 break;
2336
2337 default:
2338 strcpy (tp, "bug");
2339 tp += 3;
2340 number = 42;
2341 }
2342
2343 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2344 info->target2 = (bfd_vma) number;
2345
2346 /* If the size is dword, then assume it's an
2347 address. */
2348 if (nbytes == 4)
2349 {
2350 /* Finish off and output previous formatted
2351 bytes. */
2352 *tp++ = '+';
2353 *tp = 0;
2354 tp = temp;
2355 (*info->fprintf_func) (info->stream, "%s", temp);
2356
2357 (*info->print_address_func) ((bfd_vma) number, info);
2358 }
2359 else
2360 {
2361 if (number >= 0)
2362 *tp++ = '+';
2363 tp = format_dec (number, tp, 1);
2364 }
2365 }
2366 else
2367 {
2368 /* Output "r+[R].m" or "r+[R+].m". */
2369 *tp++ = '+';
2370 *tp++ = '[';
2371 tp = format_reg (disdata, prefix_insn & 15, tp,
2372 with_reg_prefix);
2373 if (prefix_insn & 0x400)
2374 *tp++ = '+';
2375 *tp++ = ']';
2376 *tp++ = '.';
2377 *tp++ = mode_char[(prefix_insn >> 4) & 3];
2378
2379 info->flags
2380 |= (CRIS_DIS_FLAG_MEM_TARGET2_IS_REG
2381 | CRIS_DIS_FLAG_MEM_TARGET2_MEM
2382 | CRIS_DIS_FLAG_MEM_TARGET_IS_REG
2383
2384 | (((prefix_insn >> 4) == 2)
2385 ? 0
2386 : (((prefix_insn >> 4) & 3) == 1
2387 ? CRIS_DIS_FLAG_MEM_TARGET2_MEM_WORD
2388 : CRIS_DIS_FLAG_MEM_TARGET2_MEM_BYTE)));
2389 }
2390 break;
2391
2392 default:
2393 (*info->fprintf_func) (info->stream, "?prefix-bug");
2394 }
2395
2396 /* To mark that the prefix is used, reset it. */
2397 prefix_opcodep = NULL;
2398 }
2399 else
2400 {
2401 tp = format_reg (disdata, insn & 15, tp, with_reg_prefix);
2402
2403 info->flags |= CRIS_DIS_FLAG_MEM_TARGET_IS_REG;
2404 info->target = insn & 15;
2405
2406 if (insn & 0x400)
2407 *tp++ = '+';
2408 }
2409 *tp++ = ']';
2410 }
2411 break;
2412
2413 case 'x':
2414 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2415 *tp++ = '.';
2416 *tp++ = mode_char[(insn >> 4) & 3];
2417 break;
2418
2419 case 'I':
2420 tp = format_dec (insn & 63, tp, 0);
2421 break;
2422
2423 case 'b':
2424 {
2425 int where = buffer[2] + buffer[3] * 256;
2426
2427 if (where > 32767)
2428 where -= 65536;
2429
2430 where += addr + ((disdata->distype == cris_dis_v32) ? 0 : 4);
2431
2432 if (insn == BA_PC_INCR_OPCODE)
2433 info->insn_type = dis_branch;
2434 else
2435 info->insn_type = dis_condbranch;
2436
2437 info->target = (bfd_vma) where;
2438
2439 *tp = 0;
2440 tp = temp;
2441 (*info->fprintf_func) (info->stream, "%s%s ",
2442 temp, cris_cc_strings[insn >> 12]);
2443
2444 (*info->print_address_func) ((bfd_vma) where, info);
2445 }
2446 break;
2447
2448 case 'c':
2449 tp = format_dec (insn & 31, tp, 0);
2450 break;
2451
2452 case 'C':
2453 tp = format_dec (insn & 15, tp, 0);
2454 break;
2455
2456 case 'o':
2457 {
2458 long offset = insn & 0xfe;
2459 bfd_vma target;
2460
2461 if (insn & 1)
2462 offset |= ~0xff;
2463
2464 if (opcodep->match == BA_QUICK_OPCODE)
2465 info->insn_type = dis_branch;
2466 else
2467 info->insn_type = dis_condbranch;
2468
2469 target = addr + ((disdata->distype == cris_dis_v32) ? 0 : 2) + offset;
2470 info->target = target;
2471 *tp = 0;
2472 tp = temp;
2473 (*info->fprintf_func) (info->stream, "%s", temp);
2474 (*info->print_address_func) (target, info);
2475 }
2476 break;
2477
2478 case 'Q':
2479 case 'O':
2480 {
2481 long number = buffer[0];
2482
2483 if (number > 127)
2484 number = number - 256;
2485
2486 tp = format_dec (number, tp, 1);
2487 *tp++ = ',';
2488 tp = format_reg (disdata, (insn >> 12) & 15, tp, with_reg_prefix);
2489 }
2490 break;
2491
2492 case 'f':
2493 tp = print_flags (disdata, insn, tp);
2494 break;
2495
2496 case 'i':
2497 tp = format_dec ((insn & 32) ? (insn & 31) | ~31L : insn & 31, tp, 1);
2498 break;
2499
2500 case 'P':
2501 {
2502 const struct cris_spec_reg *sregp
2503 = spec_reg_info ((insn >> 12) & 15, disdata->distype);
2504
2505 if (sregp->name == NULL)
2506 /* Should have been caught as a non-match eariler. */
2507 *tp++ = '?';
2508 else
2509 {
2510 if (with_reg_prefix)
2511 *tp++ = REGISTER_PREFIX_CHAR;
2512 strcpy (tp, sregp->name);
2513 tp += strlen (tp);
2514 }
2515 }
2516 break;
2517
2518 default:
2519 strcpy (tp, "???");
2520 tp += 3;
2521 }
2522 }
2523
2524 *tp = 0;
2525
2526 if (prefix_opcodep)
2527 (*info->fprintf_func) (info->stream, " (OOPS unused prefix \"%s: %s\")",
2528 prefix_opcodep->name, prefix_opcodep->args);
2529
2530 (*info->fprintf_func) (info->stream, "%s", temp);
2531
2532 /* Get info for matching case-tables, if we don't have any active.
2533 We assume that the last constant seen is used; either in the insn
2534 itself or in a "move.d const,rN, sub.d rN,rM"-like sequence. */
2535 if (TRACE_CASE && case_offset_counter == 0)
2536 {
2537 if (CONST_STRNEQ (opcodep->name, "sub"))
2538 case_offset = last_immediate;
2539
2540 /* It could also be an "add", if there are negative case-values. */
2541 else if (CONST_STRNEQ (opcodep->name, "add"))
2542 /* The first case is the negated operand to the add. */
2543 case_offset = -last_immediate;
2544
2545 /* A bound insn will tell us the number of cases. */
2546 else if (CONST_STRNEQ (opcodep->name, "bound"))
2547 no_of_case_offsets = last_immediate + 1;
2548
2549 /* A jump or jsr or branch breaks the chain of insns for a
2550 case-table, so assume default first-case again. */
2551 else if (info->insn_type == dis_jsr
2552 || info->insn_type == dis_branch
2553 || info->insn_type == dis_condbranch)
2554 case_offset = 0;
2555 }
2556 }
2557
2558
2559 /* Print the CRIS instruction at address memaddr on stream. Returns
2560 length of the instruction, in bytes. Prefix register names with `$' if
2561 WITH_REG_PREFIX. */
2562
2563 static int
2564 print_insn_cris_generic (bfd_vma memaddr,
2565 disassemble_info *info,
2566 bfd_boolean with_reg_prefix)
2567 {
2568 int nbytes;
2569 unsigned int insn;
2570 const struct cris_opcode *matchedp;
2571 int advance = 0;
2572 struct cris_disasm_data *disdata
2573 = (struct cris_disasm_data *) info->private_data;
2574
2575 /* No instruction will be disassembled as longer than this number of
2576 bytes; stacked prefixes will not be expanded. */
2577 unsigned char buffer[MAX_BYTES_PER_CRIS_INSN];
2578 unsigned char *bufp;
2579 int status = 0;
2580 bfd_vma addr;
2581
2582 /* There will be an "out of range" error after the last instruction.
2583 Reading pairs of bytes in decreasing number, we hope that we will get
2584 at least the amount that we will consume.
2585
2586 If we can't get any data, or we do not get enough data, we print
2587 the error message. */
2588
2589 nbytes = info->buffer_length;
2590 if (nbytes > MAX_BYTES_PER_CRIS_INSN)
2591 nbytes = MAX_BYTES_PER_CRIS_INSN;
2592 status = (*info->read_memory_func) (memaddr, buffer, nbytes, info);
2593
2594 /* If we did not get all we asked for, then clear the rest.
2595 Hopefully this makes a reproducible result in case of errors. */
2596 if (nbytes != MAX_BYTES_PER_CRIS_INSN)
2597 memset (buffer + nbytes, 0, MAX_BYTES_PER_CRIS_INSN - nbytes);
2598
2599 addr = memaddr;
2600 bufp = buffer;
2601
2602 /* Set some defaults for the insn info. */
2603 info->insn_info_valid = 1;
2604 info->branch_delay_insns = 0;
2605 info->data_size = 0;
2606 info->insn_type = dis_nonbranch;
2607 info->flags = 0;
2608 info->target = 0;
2609 info->target2 = 0;
2610
2611 /* If we got any data, disassemble it. */
2612 if (nbytes != 0)
2613 {
2614 matchedp = NULL;
2615
2616 insn = bufp[0] + bufp[1] * 256;
2617
2618 /* If we're in a case-table, don't disassemble the offsets. */
2619 if (TRACE_CASE && case_offset_counter != 0)
2620 {
2621 info->insn_type = dis_noninsn;
2622 advance += 2;
2623
2624 /* If to print data as offsets, then shortcut here. */
2625 (*info->fprintf_func) (info->stream, "case %ld%s: -> ",
2626 case_offset + no_of_case_offsets
2627 - case_offset_counter,
2628 case_offset_counter == 1 ? "/default" :
2629 "");
2630
2631 (*info->print_address_func) ((bfd_vma)
2632 ((short) (insn)
2633 + (long) (addr
2634 - (no_of_case_offsets
2635 - case_offset_counter)
2636 * 2)), info);
2637 case_offset_counter--;
2638
2639 /* The default case start (without a "sub" or "add") must be
2640 zero. */
2641 if (case_offset_counter == 0)
2642 case_offset = 0;
2643 }
2644 else if (insn == 0)
2645 {
2646 /* We're often called to disassemble zeroes. While this is a
2647 valid "bcc .+2" insn, it is also useless enough and enough
2648 of a nuiscance that we will just output "bcc .+2" for it
2649 and signal it as a noninsn. */
2650 (*info->fprintf_func) (info->stream,
2651 disdata->distype == cris_dis_v32
2652 ? "bcc ." : "bcc .+2");
2653 info->insn_type = dis_noninsn;
2654 advance += 2;
2655 }
2656 else
2657 {
2658 const struct cris_opcode *prefix_opcodep = NULL;
2659 unsigned char *prefix_buffer = bufp;
2660 unsigned int prefix_insn = insn;
2661 int prefix_size = 0;
2662
2663 matchedp = get_opcode_entry (insn, NO_CRIS_PREFIX, disdata);
2664
2665 /* Check if we're supposed to write out prefixes as address
2666 modes and if this was a prefix. */
2667 if (matchedp != NULL && PARSE_PREFIX && matchedp->args[0] == 'p')
2668 {
2669 /* If it's a prefix, put it into the prefix vars and get the
2670 main insn. */
2671 prefix_size = bytes_to_skip (prefix_insn, matchedp,
2672 disdata->distype, NULL);
2673 prefix_opcodep = matchedp;
2674
2675 insn = bufp[prefix_size] + bufp[prefix_size + 1] * 256;
2676 matchedp = get_opcode_entry (insn, prefix_insn, disdata);
2677
2678 if (matchedp != NULL)
2679 {
2680 addr += prefix_size;
2681 bufp += prefix_size;
2682 advance += prefix_size;
2683 }
2684 else
2685 {
2686 /* The "main" insn wasn't valid, at least not when
2687 prefixed. Put back things enough to output the
2688 prefix insn only, as a normal insn. */
2689 matchedp = prefix_opcodep;
2690 insn = prefix_insn;
2691 prefix_opcodep = NULL;
2692 }
2693 }
2694
2695 if (matchedp == NULL)
2696 {
2697 (*info->fprintf_func) (info->stream, "??0x%x", insn);
2698 advance += 2;
2699
2700 info->insn_type = dis_noninsn;
2701 }
2702 else
2703 {
2704 advance
2705 += bytes_to_skip (insn, matchedp, disdata->distype,
2706 prefix_opcodep);
2707
2708 /* The info_type and assorted fields will be set according
2709 to the operands. */
2710 print_with_operands (matchedp, insn, bufp, addr, info,
2711 prefix_opcodep, prefix_insn,
2712 prefix_buffer, with_reg_prefix);
2713 }
2714 }
2715 }
2716 else
2717 info->insn_type = dis_noninsn;
2718
2719 /* If we read less than MAX_BYTES_PER_CRIS_INSN, i.e. we got an error
2720 status when reading that much, and the insn decoding indicated a
2721 length exceeding what we read, there is an error. */
2722 if (status != 0 && (nbytes == 0 || advance > nbytes))
2723 {
2724 (*info->memory_error_func) (status, memaddr, info);
2725 return -1;
2726 }
2727
2728 /* Max supported insn size with one folded prefix insn. */
2729 info->bytes_per_line = MAX_BYTES_PER_CRIS_INSN;
2730
2731 /* I would like to set this to a fixed value larger than the actual
2732 number of bytes to print in order to avoid spaces between bytes,
2733 but objdump.c (2.9.1) does not like that, so we print 16-bit
2734 chunks, which is the next choice. */
2735 info->bytes_per_chunk = 2;
2736
2737 /* Printing bytes in order of increasing addresses makes sense,
2738 especially on a little-endian target.
2739 This is completely the opposite of what you think; setting this to
2740 BFD_ENDIAN_LITTLE will print bytes in order N..0 rather than the 0..N
2741 we want. */
2742 info->display_endian = BFD_ENDIAN_BIG;
2743
2744 return advance;
2745 }
2746
2747 /* Disassemble, prefixing register names with `$'. CRIS v0..v10. */
2748 static int
2749 print_insn_cris_with_register_prefix (bfd_vma vma,
2750 disassemble_info *info)
2751 {
2752 if (info->private_data == NULL
2753 && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2754 return -1;
2755 return print_insn_cris_generic (vma, info, true);
2756 }
2757 /* Disassemble, prefixing register names with `$'. CRIS v32. */
2758
2759 static int
2760 print_insn_crisv32_with_register_prefix (bfd_vma vma,
2761 disassemble_info *info)
2762 {
2763 if (info->private_data == NULL
2764 && !cris_parse_disassembler_options (info, cris_dis_v32))
2765 return -1;
2766 return print_insn_cris_generic (vma, info, true);
2767 }
2768
2769 #if 0
2770 /* Disassemble, prefixing register names with `$'.
2771 Common v10 and v32 subset. */
2772
2773 static int
2774 print_insn_crisv10_v32_with_register_prefix (bfd_vma vma,
2775 disassemble_info *info)
2776 {
2777 if (info->private_data == NULL
2778 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2779 return -1;
2780 return print_insn_cris_generic (vma, info, true);
2781 }
2782
2783 /* Disassemble, no prefixes on register names. CRIS v0..v10. */
2784
2785 static int
2786 print_insn_cris_without_register_prefix (bfd_vma vma,
2787 disassemble_info *info)
2788 {
2789 if (info->private_data == NULL
2790 && !cris_parse_disassembler_options (info, cris_dis_v0_v10))
2791 return -1;
2792 return print_insn_cris_generic (vma, info, false);
2793 }
2794
2795 /* Disassemble, no prefixes on register names. CRIS v32. */
2796
2797 static int
2798 print_insn_crisv32_without_register_prefix (bfd_vma vma,
2799 disassemble_info *info)
2800 {
2801 if (info->private_data == NULL
2802 && !cris_parse_disassembler_options (info, cris_dis_v32))
2803 return -1;
2804 return print_insn_cris_generic (vma, info, false);
2805 }
2806
2807 /* Disassemble, no prefixes on register names.
2808 Common v10 and v32 subset. */
2809
2810 static int
2811 print_insn_crisv10_v32_without_register_prefix (bfd_vma vma,
2812 disassemble_info *info)
2813 {
2814 if (info->private_data == NULL
2815 && !cris_parse_disassembler_options (info, cris_dis_common_v10_v32))
2816 return -1;
2817 return print_insn_cris_generic (vma, info, false);
2818 }
2819 #endif
2820
2821 int
2822 print_insn_crisv10 (bfd_vma vma,
2823 disassemble_info *info)
2824 {
2825 return print_insn_cris_with_register_prefix(vma, info);
2826 }
2827
2828 int
2829 print_insn_crisv32 (bfd_vma vma,
2830 disassemble_info *info)
2831 {
2832 return print_insn_crisv32_with_register_prefix(vma, info);
2833 }
2834
2835 /* Return a disassembler-function that prints registers with a `$' prefix,
2836 or one that prints registers without a prefix.
2837 FIXME: We should improve the solution to avoid the multitude of
2838 functions seen above. */
2839 #if 0
2840 disassembler_ftype
2841 cris_get_disassembler (bfd *abfd)
2842 {
2843 /* If there's no bfd in sight, we return what is valid as input in all
2844 contexts if fed back to the assembler: disassembly *with* register
2845 prefix. Unfortunately this will be totally wrong for v32. */
2846 if (abfd == NULL)
2847 return print_insn_cris_with_register_prefix;
2848
2849 if (bfd_get_symbol_leading_char (abfd) == 0)
2850 {
2851 if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2852 return print_insn_crisv32_with_register_prefix;
2853 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2854 return print_insn_crisv10_v32_with_register_prefix;
2855
2856 /* We default to v10. This may be specifically specified in the
2857 bfd mach, but is also the default setting. */
2858 return print_insn_cris_with_register_prefix;
2859 }
2860
2861 if (bfd_get_mach (abfd) == bfd_mach_cris_v32)
2862 return print_insn_crisv32_without_register_prefix;
2863 if (bfd_get_mach (abfd) == bfd_mach_cris_v10_v32)
2864 return print_insn_crisv10_v32_without_register_prefix;
2865 return print_insn_cris_without_register_prefix;
2866 }
2867 #endif
2868 /* Local variables:
2869 eval: (c-set-style "gnu")
2870 indent-tabs-mode: t
2871 End: */
Qemu copy for testing