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add fixes for intel MDS CVEs
[pve-qemu.git] / debian / patches / extra / 0007-x86-define-a-new-MSR-based-feature-word-FEATURE_WORD.patch
1 From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001
2 From: Robert Hoo <robert.hu@linux.intel.com>
3 Date: Mon, 15 Oct 2018 12:47:25 +0800
4 Subject: [PATCH 7/9] x86: define a new MSR based feature word --
5 FEATURE_WORDS_ARCH_CAPABILITIES
6
7 Note RSBA is specially treated -- no matter host support it or not, qemu
8 pretends it is supported.
9
10 Signed-off-by: Robert Hoo <robert.hu@linux.intel.com>
11 Message-Id: <1539578845-37944-4-git-send-email-robert.hu@linux.intel.com>
12 [ehabkost: removed automatic enabling of RSBA]
13 Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
14 Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
15 ---
16 target/i386/cpu.c | 24 +++++++++++++++++++++++-
17 target/i386/cpu.h | 8 ++++++++
18 target/i386/kvm.c | 11 +++++++++++
19 3 files changed, 42 insertions(+), 1 deletion(-)
20
21 diff --git a/target/i386/cpu.c b/target/i386/cpu.c
22 index d2985144a3..a64aa8793e 100644
23 --- a/target/i386/cpu.c
24 +++ b/target/i386/cpu.c
25 @@ -1141,6 +1141,27 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
26 },
27 .tcg_features = ~0U,
28 },
29 + /*Below are MSR exposed features*/
30 + [FEAT_ARCH_CAPABILITIES] = {
31 + .type = MSR_FEATURE_WORD,
32 + .feat_names = {
33 + "rdctl-no", "ibrs-all", "rsba", "skip-l1dfl-vmentry",
34 + "ssb-no", NULL, NULL, NULL,
35 + NULL, NULL, NULL, NULL,
36 + NULL, NULL, NULL, NULL,
37 + NULL, NULL, NULL, NULL,
38 + NULL, NULL, NULL, NULL,
39 + NULL, NULL, NULL, NULL,
40 + NULL, NULL, NULL, NULL,
41 + },
42 + .msr = {
43 + .index = MSR_IA32_ARCH_CAPABILITIES,
44 + .cpuid_dep = {
45 + FEAT_7_0_EDX,
46 + CPUID_7_0_EDX_ARCH_CAPABILITIES
47 + }
48 + },
49 + },
50 };
51
52 typedef struct X86RegisterInfo32 {
53 @@ -3581,7 +3602,8 @@ static uint32_t x86_cpu_get_supported_feature_word(FeatureWord w,
54 wi->cpuid.reg);
55 break;
56 case MSR_FEATURE_WORD:
57 - r = kvm_arch_get_supported_msr_feature(kvm_state, wi->msr.index);
58 + r = kvm_arch_get_supported_msr_feature(kvm_state,
59 + wi->msr.index);
60 break;
61 }
62 } else if (hvf_enabled()) {
63 diff --git a/target/i386/cpu.h b/target/i386/cpu.h
64 index fb2f5f6ebc..ae54a98249 100644
65 --- a/target/i386/cpu.h
66 +++ b/target/i386/cpu.h
67 @@ -502,6 +502,7 @@ typedef enum FeatureWord {
68 FEAT_6_EAX, /* CPUID[6].EAX */
69 FEAT_XSAVE_COMP_LO, /* CPUID[EAX=0xd,ECX=0].EAX */
70 FEAT_XSAVE_COMP_HI, /* CPUID[EAX=0xd,ECX=0].EDX */
71 + FEAT_ARCH_CAPABILITIES,
72 FEATURE_WORDS,
73 } FeatureWord;
74
75 @@ -727,6 +728,13 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS];
76 #define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
77 #define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
78
79 +/* MSR Feature Bits */
80 +#define MSR_ARCH_CAP_RDCL_NO (1U << 0)
81 +#define MSR_ARCH_CAP_IBRS_ALL (1U << 1)
82 +#define MSR_ARCH_CAP_RSBA (1U << 2)
83 +#define MSR_ARCH_CAP_SKIP_L1DFL_VMENTRY (1U << 3)
84 +#define MSR_ARCH_CAP_SSB_NO (1U << 4)
85 +
86 #ifndef HYPERV_SPINLOCK_NEVER_RETRY
87 #define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
88 #endif
89 diff --git a/target/i386/kvm.c b/target/i386/kvm.c
90 index cd45c79169..0b7fcb4f7f 100644
91 --- a/target/i386/kvm.c
92 +++ b/target/i386/kvm.c
93 @@ -1936,6 +1936,17 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
94 }
95 #endif
96
97 + /* If host supports feature MSR, write down. */
98 + if (kvm_feature_msrs) {
99 + int i;
100 + for (i = 0; i < kvm_feature_msrs->nmsrs; i++)
101 + if (kvm_feature_msrs->indices[i] == MSR_IA32_ARCH_CAPABILITIES) {
102 + kvm_msr_entry_add(cpu, MSR_IA32_ARCH_CAPABILITIES,
103 + env->features[FEAT_ARCH_CAPABILITIES]);
104 + break;
105 + }
106 + }
107 +
108 /*
109 * The following MSRs have side effects on the guest or are too heavy
110 * for normal writeback. Limit them to reset or full state updates.
111 --
112 2.20.1
113