2 * Copyright 2008 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Jerome Glisse <glisse@freedesktop.org>
27 #include <linux/pagemap.h>
29 #include <drm/amdgpu_drm.h>
30 #include <drm/drm_syncobj.h>
32 #include "amdgpu_trace.h"
34 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser
*p
,
35 struct drm_amdgpu_cs_chunk_fence
*data
,
38 struct drm_gem_object
*gobj
;
41 gobj
= drm_gem_object_lookup(p
->filp
, data
->handle
);
45 p
->uf_entry
.robj
= amdgpu_bo_ref(gem_to_amdgpu_bo(gobj
));
46 p
->uf_entry
.priority
= 0;
47 p
->uf_entry
.tv
.bo
= &p
->uf_entry
.robj
->tbo
;
48 p
->uf_entry
.tv
.shared
= true;
49 p
->uf_entry
.user_pages
= NULL
;
51 size
= amdgpu_bo_size(p
->uf_entry
.robj
);
52 if (size
!= PAGE_SIZE
|| (data
->offset
+ 8) > size
)
55 *offset
= data
->offset
;
57 drm_gem_object_put_unlocked(gobj
);
59 if (amdgpu_ttm_tt_get_usermm(p
->uf_entry
.robj
->tbo
.ttm
)) {
60 amdgpu_bo_unref(&p
->uf_entry
.robj
);
67 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser
*p
, void *data
)
69 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
70 struct amdgpu_vm
*vm
= &fpriv
->vm
;
71 union drm_amdgpu_cs
*cs
= data
;
72 uint64_t *chunk_array_user
;
73 uint64_t *chunk_array
;
74 unsigned size
, num_ibs
= 0;
75 uint32_t uf_offset
= 0;
79 if (cs
->in
.num_chunks
== 0)
82 chunk_array
= kmalloc_array(cs
->in
.num_chunks
, sizeof(uint64_t), GFP_KERNEL
);
86 p
->ctx
= amdgpu_ctx_get(fpriv
, cs
->in
.ctx_id
);
93 chunk_array_user
= u64_to_user_ptr(cs
->in
.chunks
);
94 if (copy_from_user(chunk_array
, chunk_array_user
,
95 sizeof(uint64_t)*cs
->in
.num_chunks
)) {
100 p
->nchunks
= cs
->in
.num_chunks
;
101 p
->chunks
= kmalloc_array(p
->nchunks
, sizeof(struct amdgpu_cs_chunk
),
108 for (i
= 0; i
< p
->nchunks
; i
++) {
109 struct drm_amdgpu_cs_chunk __user
**chunk_ptr
= NULL
;
110 struct drm_amdgpu_cs_chunk user_chunk
;
111 uint32_t __user
*cdata
;
113 chunk_ptr
= u64_to_user_ptr(chunk_array
[i
]);
114 if (copy_from_user(&user_chunk
, chunk_ptr
,
115 sizeof(struct drm_amdgpu_cs_chunk
))) {
118 goto free_partial_kdata
;
120 p
->chunks
[i
].chunk_id
= user_chunk
.chunk_id
;
121 p
->chunks
[i
].length_dw
= user_chunk
.length_dw
;
123 size
= p
->chunks
[i
].length_dw
;
124 cdata
= u64_to_user_ptr(user_chunk
.chunk_data
);
126 p
->chunks
[i
].kdata
= kvmalloc_array(size
, sizeof(uint32_t), GFP_KERNEL
);
127 if (p
->chunks
[i
].kdata
== NULL
) {
130 goto free_partial_kdata
;
132 size
*= sizeof(uint32_t);
133 if (copy_from_user(p
->chunks
[i
].kdata
, cdata
, size
)) {
135 goto free_partial_kdata
;
138 switch (p
->chunks
[i
].chunk_id
) {
139 case AMDGPU_CHUNK_ID_IB
:
143 case AMDGPU_CHUNK_ID_FENCE
:
144 size
= sizeof(struct drm_amdgpu_cs_chunk_fence
);
145 if (p
->chunks
[i
].length_dw
* sizeof(uint32_t) < size
) {
147 goto free_partial_kdata
;
150 ret
= amdgpu_cs_user_fence_chunk(p
, p
->chunks
[i
].kdata
,
153 goto free_partial_kdata
;
157 case AMDGPU_CHUNK_ID_DEPENDENCIES
:
158 case AMDGPU_CHUNK_ID_SYNCOBJ_IN
:
159 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT
:
164 goto free_partial_kdata
;
168 ret
= amdgpu_job_alloc(p
->adev
, num_ibs
, &p
->job
, vm
);
172 if (p
->uf_entry
.robj
)
173 p
->job
->uf_addr
= uf_offset
;
181 kvfree(p
->chunks
[i
].kdata
);
186 amdgpu_ctx_put(p
->ctx
);
193 /* Convert microseconds to bytes. */
194 static u64
us_to_bytes(struct amdgpu_device
*adev
, s64 us
)
196 if (us
<= 0 || !adev
->mm_stats
.log2_max_MBps
)
199 /* Since accum_us is incremented by a million per second, just
200 * multiply it by the number of MB/s to get the number of bytes.
202 return us
<< adev
->mm_stats
.log2_max_MBps
;
205 static s64
bytes_to_us(struct amdgpu_device
*adev
, u64 bytes
)
207 if (!adev
->mm_stats
.log2_max_MBps
)
210 return bytes
>> adev
->mm_stats
.log2_max_MBps
;
213 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
214 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
215 * which means it can go over the threshold once. If that happens, the driver
216 * will be in debt and no other buffer migrations can be done until that debt
219 * This approach allows moving a buffer of any size (it's important to allow
222 * The currency is simply time in microseconds and it increases as the clock
223 * ticks. The accumulated microseconds (us) are converted to bytes and
226 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device
*adev
,
230 s64 time_us
, increment_us
;
231 u64 free_vram
, total_vram
, used_vram
;
233 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
236 * It means that in order to get full max MBps, at least 5 IBs per
237 * second must be submitted and not more than 200ms apart from each
240 const s64 us_upper_bound
= 200000;
242 if (!adev
->mm_stats
.log2_max_MBps
) {
248 total_vram
= adev
->mc
.real_vram_size
- adev
->vram_pin_size
;
249 used_vram
= amdgpu_vram_mgr_usage(&adev
->mman
.bdev
.man
[TTM_PL_VRAM
]);
250 free_vram
= used_vram
>= total_vram
? 0 : total_vram
- used_vram
;
252 spin_lock(&adev
->mm_stats
.lock
);
254 /* Increase the amount of accumulated us. */
255 time_us
= ktime_to_us(ktime_get());
256 increment_us
= time_us
- adev
->mm_stats
.last_update_us
;
257 adev
->mm_stats
.last_update_us
= time_us
;
258 adev
->mm_stats
.accum_us
= min(adev
->mm_stats
.accum_us
+ increment_us
,
261 /* This prevents the short period of low performance when the VRAM
262 * usage is low and the driver is in debt or doesn't have enough
263 * accumulated us to fill VRAM quickly.
265 * The situation can occur in these cases:
266 * - a lot of VRAM is freed by userspace
267 * - the presence of a big buffer causes a lot of evictions
268 * (solution: split buffers into smaller ones)
270 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
271 * accum_us to a positive number.
273 if (free_vram
>= 128 * 1024 * 1024 || free_vram
>= total_vram
/ 8) {
276 /* Be more aggresive on dGPUs. Try to fill a portion of free
279 if (!(adev
->flags
& AMD_IS_APU
))
280 min_us
= bytes_to_us(adev
, free_vram
/ 4);
282 min_us
= 0; /* Reset accum_us on APUs. */
284 adev
->mm_stats
.accum_us
= max(min_us
, adev
->mm_stats
.accum_us
);
287 /* This is set to 0 if the driver is in debt to disallow (optional)
290 *max_bytes
= us_to_bytes(adev
, adev
->mm_stats
.accum_us
);
292 /* Do the same for visible VRAM if half of it is free */
293 if (adev
->mc
.visible_vram_size
< adev
->mc
.real_vram_size
) {
294 u64 total_vis_vram
= adev
->mc
.visible_vram_size
;
296 amdgpu_vram_mgr_vis_usage(&adev
->mman
.bdev
.man
[TTM_PL_VRAM
]);
298 if (used_vis_vram
< total_vis_vram
) {
299 u64 free_vis_vram
= total_vis_vram
- used_vis_vram
;
300 adev
->mm_stats
.accum_us_vis
= min(adev
->mm_stats
.accum_us_vis
+
301 increment_us
, us_upper_bound
);
303 if (free_vis_vram
>= total_vis_vram
/ 2)
304 adev
->mm_stats
.accum_us_vis
=
305 max(bytes_to_us(adev
, free_vis_vram
/ 2),
306 adev
->mm_stats
.accum_us_vis
);
309 *max_vis_bytes
= us_to_bytes(adev
, adev
->mm_stats
.accum_us_vis
);
314 spin_unlock(&adev
->mm_stats
.lock
);
317 /* Report how many bytes have really been moved for the last command
318 * submission. This can result in a debt that can stop buffer migrations
321 void amdgpu_cs_report_moved_bytes(struct amdgpu_device
*adev
, u64 num_bytes
,
324 spin_lock(&adev
->mm_stats
.lock
);
325 adev
->mm_stats
.accum_us
-= bytes_to_us(adev
, num_bytes
);
326 adev
->mm_stats
.accum_us_vis
-= bytes_to_us(adev
, num_vis_bytes
);
327 spin_unlock(&adev
->mm_stats
.lock
);
330 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser
*p
,
331 struct amdgpu_bo
*bo
)
333 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->tbo
.bdev
);
334 u64 initial_bytes_moved
, bytes_moved
;
341 /* Don't move this buffer if we have depleted our allowance
342 * to move it. Don't move anything if the threshold is zero.
344 if (p
->bytes_moved
< p
->bytes_moved_threshold
) {
345 if (adev
->mc
.visible_vram_size
< adev
->mc
.real_vram_size
&&
346 (bo
->flags
& AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED
)) {
347 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
348 * visible VRAM if we've depleted our allowance to do
351 if (p
->bytes_moved_vis
< p
->bytes_moved_vis_threshold
)
352 domain
= bo
->preferred_domains
;
354 domain
= bo
->allowed_domains
;
356 domain
= bo
->preferred_domains
;
359 domain
= bo
->allowed_domains
;
363 amdgpu_ttm_placement_from_domain(bo
, domain
);
364 initial_bytes_moved
= atomic64_read(&adev
->num_bytes_moved
);
365 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
366 bytes_moved
= atomic64_read(&adev
->num_bytes_moved
) -
368 p
->bytes_moved
+= bytes_moved
;
369 if (adev
->mc
.visible_vram_size
< adev
->mc
.real_vram_size
&&
370 bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
&&
371 bo
->tbo
.mem
.start
< adev
->mc
.visible_vram_size
>> PAGE_SHIFT
)
372 p
->bytes_moved_vis
+= bytes_moved
;
374 if (unlikely(r
== -ENOMEM
) && domain
!= bo
->allowed_domains
) {
375 domain
= bo
->allowed_domains
;
382 /* Last resort, try to evict something from the current working set */
383 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser
*p
,
384 struct amdgpu_bo
*validated
)
386 uint32_t domain
= validated
->allowed_domains
;
392 for (;&p
->evictable
->tv
.head
!= &p
->validated
;
393 p
->evictable
= list_prev_entry(p
->evictable
, tv
.head
)) {
395 struct amdgpu_bo_list_entry
*candidate
= p
->evictable
;
396 struct amdgpu_bo
*bo
= candidate
->robj
;
397 struct amdgpu_device
*adev
= amdgpu_ttm_adev(bo
->tbo
.bdev
);
398 u64 initial_bytes_moved
, bytes_moved
;
399 bool update_bytes_moved_vis
;
402 /* If we reached our current BO we can forget it */
403 if (candidate
->robj
== validated
)
406 other
= amdgpu_mem_type_to_domain(bo
->tbo
.mem
.mem_type
);
408 /* Check if this BO is in one of the domains we need space for */
409 if (!(other
& domain
))
412 /* Check if we can move this BO somewhere else */
413 other
= bo
->allowed_domains
& ~domain
;
417 /* Good we can try to move this BO somewhere else */
418 amdgpu_ttm_placement_from_domain(bo
, other
);
419 update_bytes_moved_vis
=
420 adev
->mc
.visible_vram_size
< adev
->mc
.real_vram_size
&&
421 bo
->tbo
.mem
.mem_type
== TTM_PL_VRAM
&&
422 bo
->tbo
.mem
.start
< adev
->mc
.visible_vram_size
>> PAGE_SHIFT
;
423 initial_bytes_moved
= atomic64_read(&adev
->num_bytes_moved
);
424 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, true, false);
425 bytes_moved
= atomic64_read(&adev
->num_bytes_moved
) -
427 p
->bytes_moved
+= bytes_moved
;
428 if (update_bytes_moved_vis
)
429 p
->bytes_moved_vis
+= bytes_moved
;
434 p
->evictable
= list_prev_entry(p
->evictable
, tv
.head
);
435 list_move(&candidate
->tv
.head
, &p
->validated
);
443 static int amdgpu_cs_validate(void *param
, struct amdgpu_bo
*bo
)
445 struct amdgpu_cs_parser
*p
= param
;
449 r
= amdgpu_cs_bo_validate(p
, bo
);
450 } while (r
== -ENOMEM
&& amdgpu_cs_try_evict(p
, bo
));
455 r
= amdgpu_cs_bo_validate(p
, bo
->shadow
);
460 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser
*p
,
461 struct list_head
*validated
)
463 struct amdgpu_bo_list_entry
*lobj
;
466 list_for_each_entry(lobj
, validated
, tv
.head
) {
467 struct amdgpu_bo
*bo
= lobj
->robj
;
468 bool binding_userptr
= false;
469 struct mm_struct
*usermm
;
471 usermm
= amdgpu_ttm_tt_get_usermm(bo
->tbo
.ttm
);
472 if (usermm
&& usermm
!= current
->mm
)
475 /* Check if we have user pages and nobody bound the BO already */
476 if (lobj
->user_pages
&& bo
->tbo
.ttm
->state
!= tt_bound
) {
477 amdgpu_ttm_tt_set_user_pages(bo
->tbo
.ttm
,
479 binding_userptr
= true;
482 if (p
->evictable
== lobj
)
485 r
= amdgpu_cs_validate(p
, bo
);
489 if (binding_userptr
) {
490 kvfree(lobj
->user_pages
);
491 lobj
->user_pages
= NULL
;
497 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser
*p
,
498 union drm_amdgpu_cs
*cs
)
500 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
501 struct amdgpu_bo_list_entry
*e
;
502 struct list_head duplicates
;
503 bool need_mmap_lock
= false;
504 unsigned i
, tries
= 10;
507 INIT_LIST_HEAD(&p
->validated
);
509 p
->bo_list
= amdgpu_bo_list_get(fpriv
, cs
->in
.bo_list_handle
);
511 need_mmap_lock
= p
->bo_list
->first_userptr
!=
512 p
->bo_list
->num_entries
;
513 amdgpu_bo_list_get_list(p
->bo_list
, &p
->validated
);
516 INIT_LIST_HEAD(&duplicates
);
517 amdgpu_vm_get_pd_bo(&fpriv
->vm
, &p
->validated
, &p
->vm_pd
);
519 if (p
->uf_entry
.robj
)
520 list_add(&p
->uf_entry
.tv
.head
, &p
->validated
);
523 down_read(¤t
->mm
->mmap_sem
);
526 struct list_head need_pages
;
529 r
= ttm_eu_reserve_buffers(&p
->ticket
, &p
->validated
, true,
531 if (unlikely(r
!= 0)) {
532 if (r
!= -ERESTARTSYS
)
533 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
534 goto error_free_pages
;
537 /* Without a BO list we don't have userptr BOs */
541 INIT_LIST_HEAD(&need_pages
);
542 for (i
= p
->bo_list
->first_userptr
;
543 i
< p
->bo_list
->num_entries
; ++i
) {
545 e
= &p
->bo_list
->array
[i
];
547 if (amdgpu_ttm_tt_userptr_invalidated(e
->robj
->tbo
.ttm
,
548 &e
->user_invalidated
) && e
->user_pages
) {
550 /* We acquired a page array, but somebody
551 * invalidated it. Free it and try again
553 release_pages(e
->user_pages
,
554 e
->robj
->tbo
.ttm
->num_pages
,
556 kvfree(e
->user_pages
);
557 e
->user_pages
= NULL
;
560 if (e
->robj
->tbo
.ttm
->state
!= tt_bound
&&
562 list_del(&e
->tv
.head
);
563 list_add(&e
->tv
.head
, &need_pages
);
565 amdgpu_bo_unreserve(e
->robj
);
569 if (list_empty(&need_pages
))
572 /* Unreserve everything again. */
573 ttm_eu_backoff_reservation(&p
->ticket
, &p
->validated
);
575 /* We tried too many times, just abort */
578 DRM_ERROR("deadlock in %s\n", __func__
);
579 goto error_free_pages
;
582 /* Fill the page arrays for all userptrs. */
583 list_for_each_entry(e
, &need_pages
, tv
.head
) {
584 struct ttm_tt
*ttm
= e
->robj
->tbo
.ttm
;
586 e
->user_pages
= kvmalloc_array(ttm
->num_pages
,
587 sizeof(struct page
*),
588 GFP_KERNEL
| __GFP_ZERO
);
589 if (!e
->user_pages
) {
591 DRM_ERROR("calloc failure in %s\n", __func__
);
592 goto error_free_pages
;
595 r
= amdgpu_ttm_tt_get_user_pages(ttm
, e
->user_pages
);
597 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
598 kvfree(e
->user_pages
);
599 e
->user_pages
= NULL
;
600 goto error_free_pages
;
605 list_splice(&need_pages
, &p
->validated
);
608 amdgpu_cs_get_threshold_for_moves(p
->adev
, &p
->bytes_moved_threshold
,
609 &p
->bytes_moved_vis_threshold
);
611 p
->bytes_moved_vis
= 0;
612 p
->evictable
= list_last_entry(&p
->validated
,
613 struct amdgpu_bo_list_entry
,
616 r
= amdgpu_vm_validate_pt_bos(p
->adev
, &fpriv
->vm
,
617 amdgpu_cs_validate
, p
);
619 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
623 r
= amdgpu_cs_list_validate(p
, &duplicates
);
625 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
629 r
= amdgpu_cs_list_validate(p
, &p
->validated
);
631 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
635 amdgpu_cs_report_moved_bytes(p
->adev
, p
->bytes_moved
,
638 struct amdgpu_bo
*gds
= p
->bo_list
->gds_obj
;
639 struct amdgpu_bo
*gws
= p
->bo_list
->gws_obj
;
640 struct amdgpu_bo
*oa
= p
->bo_list
->oa_obj
;
641 struct amdgpu_vm
*vm
= &fpriv
->vm
;
644 for (i
= 0; i
< p
->bo_list
->num_entries
; i
++) {
645 struct amdgpu_bo
*bo
= p
->bo_list
->array
[i
].robj
;
647 p
->bo_list
->array
[i
].bo_va
= amdgpu_vm_bo_find(vm
, bo
);
651 p
->job
->gds_base
= amdgpu_bo_gpu_offset(gds
);
652 p
->job
->gds_size
= amdgpu_bo_size(gds
);
655 p
->job
->gws_base
= amdgpu_bo_gpu_offset(gws
);
656 p
->job
->gws_size
= amdgpu_bo_size(gws
);
659 p
->job
->oa_base
= amdgpu_bo_gpu_offset(oa
);
660 p
->job
->oa_size
= amdgpu_bo_size(oa
);
664 if (!r
&& p
->uf_entry
.robj
) {
665 struct amdgpu_bo
*uf
= p
->uf_entry
.robj
;
667 r
= amdgpu_ttm_bind(&uf
->tbo
, &uf
->tbo
.mem
);
668 p
->job
->uf_addr
+= amdgpu_bo_gpu_offset(uf
);
673 ttm_eu_backoff_reservation(&p
->ticket
, &p
->validated
);
678 up_read(¤t
->mm
->mmap_sem
);
681 for (i
= p
->bo_list
->first_userptr
;
682 i
< p
->bo_list
->num_entries
; ++i
) {
683 e
= &p
->bo_list
->array
[i
];
688 release_pages(e
->user_pages
,
689 e
->robj
->tbo
.ttm
->num_pages
,
691 kvfree(e
->user_pages
);
698 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser
*p
)
700 struct amdgpu_bo_list_entry
*e
;
703 list_for_each_entry(e
, &p
->validated
, tv
.head
) {
704 struct reservation_object
*resv
= e
->robj
->tbo
.resv
;
705 r
= amdgpu_sync_resv(p
->adev
, &p
->job
->sync
, resv
, p
->filp
);
714 * cs_parser_fini() - clean parser states
715 * @parser: parser structure holding parsing context.
716 * @error: error number
718 * If error is set than unvalidate buffer, otherwise just free memory
719 * used by parsing context.
721 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser
*parser
, int error
,
727 ttm_eu_fence_buffer_objects(&parser
->ticket
,
731 ttm_eu_backoff_reservation(&parser
->ticket
,
734 for (i
= 0; i
< parser
->num_post_dep_syncobjs
; i
++)
735 drm_syncobj_put(parser
->post_dep_syncobjs
[i
]);
736 kfree(parser
->post_dep_syncobjs
);
738 dma_fence_put(parser
->fence
);
741 amdgpu_ctx_put(parser
->ctx
);
743 amdgpu_bo_list_put(parser
->bo_list
);
745 for (i
= 0; i
< parser
->nchunks
; i
++)
746 kvfree(parser
->chunks
[i
].kdata
);
747 kfree(parser
->chunks
);
749 amdgpu_job_free(parser
->job
);
750 amdgpu_bo_unref(&parser
->uf_entry
.robj
);
753 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser
*p
)
755 struct amdgpu_device
*adev
= p
->adev
;
756 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
757 struct amdgpu_vm
*vm
= &fpriv
->vm
;
758 struct amdgpu_bo_va
*bo_va
;
759 struct amdgpu_bo
*bo
;
762 r
= amdgpu_vm_update_directories(adev
, vm
);
766 r
= amdgpu_sync_fence(adev
, &p
->job
->sync
, vm
->last_dir_update
);
770 r
= amdgpu_vm_clear_freed(adev
, vm
, NULL
);
774 r
= amdgpu_vm_bo_update(adev
, fpriv
->prt_va
, false);
778 r
= amdgpu_sync_fence(adev
, &p
->job
->sync
,
779 fpriv
->prt_va
->last_pt_update
);
783 if (amdgpu_sriov_vf(adev
)) {
786 bo_va
= fpriv
->csa_va
;
788 r
= amdgpu_vm_bo_update(adev
, bo_va
, false);
792 f
= bo_va
->last_pt_update
;
793 r
= amdgpu_sync_fence(adev
, &p
->job
->sync
, f
);
799 for (i
= 0; i
< p
->bo_list
->num_entries
; i
++) {
802 /* ignore duplicates */
803 bo
= p
->bo_list
->array
[i
].robj
;
807 bo_va
= p
->bo_list
->array
[i
].bo_va
;
811 r
= amdgpu_vm_bo_update(adev
, bo_va
, false);
815 f
= bo_va
->last_pt_update
;
816 r
= amdgpu_sync_fence(adev
, &p
->job
->sync
, f
);
823 r
= amdgpu_vm_handle_moved(adev
, vm
, &p
->job
->sync
);
825 if (amdgpu_vm_debug
&& p
->bo_list
) {
826 /* Invalidate all BOs to test for userspace bugs */
827 for (i
= 0; i
< p
->bo_list
->num_entries
; i
++) {
828 /* ignore duplicates */
829 bo
= p
->bo_list
->array
[i
].robj
;
833 amdgpu_vm_bo_invalidate(adev
, bo
, false);
840 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device
*adev
,
841 struct amdgpu_cs_parser
*p
)
843 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
844 struct amdgpu_vm
*vm
= &fpriv
->vm
;
845 struct amdgpu_ring
*ring
= p
->job
->ring
;
848 /* Only for UVD/VCE VM emulation */
849 if (ring
->funcs
->parse_cs
) {
850 for (i
= 0; i
< p
->job
->num_ibs
; i
++) {
851 r
= amdgpu_ring_parse_cs(ring
, p
, i
);
858 p
->job
->vm_pd_addr
= amdgpu_bo_gpu_offset(vm
->root
.base
.bo
);
860 r
= amdgpu_bo_vm_update_pte(p
);
865 return amdgpu_cs_sync_rings(p
);
868 static int amdgpu_cs_ib_fill(struct amdgpu_device
*adev
,
869 struct amdgpu_cs_parser
*parser
)
871 struct amdgpu_fpriv
*fpriv
= parser
->filp
->driver_priv
;
872 struct amdgpu_vm
*vm
= &fpriv
->vm
;
874 int r
, ce_preempt
= 0, de_preempt
= 0;
876 for (i
= 0, j
= 0; i
< parser
->nchunks
&& j
< parser
->job
->num_ibs
; i
++) {
877 struct amdgpu_cs_chunk
*chunk
;
878 struct amdgpu_ib
*ib
;
879 struct drm_amdgpu_cs_chunk_ib
*chunk_ib
;
880 struct amdgpu_ring
*ring
;
882 chunk
= &parser
->chunks
[i
];
883 ib
= &parser
->job
->ibs
[j
];
884 chunk_ib
= (struct drm_amdgpu_cs_chunk_ib
*)chunk
->kdata
;
886 if (chunk
->chunk_id
!= AMDGPU_CHUNK_ID_IB
)
889 if (chunk_ib
->ip_type
== AMDGPU_HW_IP_GFX
&& amdgpu_sriov_vf(adev
)) {
890 if (chunk_ib
->flags
& AMDGPU_IB_FLAG_PREEMPT
) {
891 if (chunk_ib
->flags
& AMDGPU_IB_FLAG_CE
)
897 /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
898 if (ce_preempt
> 1 || de_preempt
> 1)
902 r
= amdgpu_queue_mgr_map(adev
, &parser
->ctx
->queue_mgr
, chunk_ib
->ip_type
,
903 chunk_ib
->ip_instance
, chunk_ib
->ring
, &ring
);
907 if (chunk_ib
->flags
& AMDGPU_IB_FLAG_PREAMBLE
) {
908 parser
->job
->preamble_status
|= AMDGPU_PREAMBLE_IB_PRESENT
;
909 if (!parser
->ctx
->preamble_presented
) {
910 parser
->job
->preamble_status
|= AMDGPU_PREAMBLE_IB_PRESENT_FIRST
;
911 parser
->ctx
->preamble_presented
= true;
915 if (parser
->job
->ring
&& parser
->job
->ring
!= ring
)
918 parser
->job
->ring
= ring
;
920 if (ring
->funcs
->parse_cs
) {
921 struct amdgpu_bo_va_mapping
*m
;
922 struct amdgpu_bo
*aobj
= NULL
;
926 m
= amdgpu_cs_find_mapping(parser
, chunk_ib
->va_start
,
929 DRM_ERROR("IB va_start is invalid\n");
933 if ((chunk_ib
->va_start
+ chunk_ib
->ib_bytes
) >
934 (m
->last
+ 1) * AMDGPU_GPU_PAGE_SIZE
) {
935 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
939 /* the IB should be reserved at this point */
940 r
= amdgpu_bo_kmap(aobj
, (void **)&kptr
);
945 offset
= m
->start
* AMDGPU_GPU_PAGE_SIZE
;
946 kptr
+= chunk_ib
->va_start
- offset
;
948 r
= amdgpu_ib_get(adev
, vm
, chunk_ib
->ib_bytes
, ib
);
950 DRM_ERROR("Failed to get ib !\n");
954 memcpy(ib
->ptr
, kptr
, chunk_ib
->ib_bytes
);
955 amdgpu_bo_kunmap(aobj
);
957 r
= amdgpu_ib_get(adev
, vm
, 0, ib
);
959 DRM_ERROR("Failed to get ib !\n");
965 ib
->gpu_addr
= chunk_ib
->va_start
;
966 ib
->length_dw
= chunk_ib
->ib_bytes
/ 4;
967 ib
->flags
= chunk_ib
->flags
;
971 /* UVD & VCE fw doesn't support user fences */
972 if (parser
->job
->uf_addr
&& (
973 parser
->job
->ring
->funcs
->type
== AMDGPU_RING_TYPE_UVD
||
974 parser
->job
->ring
->funcs
->type
== AMDGPU_RING_TYPE_VCE
))
980 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser
*p
,
981 struct amdgpu_cs_chunk
*chunk
)
983 struct amdgpu_fpriv
*fpriv
= p
->filp
->driver_priv
;
986 struct drm_amdgpu_cs_chunk_dep
*deps
;
988 deps
= (struct drm_amdgpu_cs_chunk_dep
*)chunk
->kdata
;
989 num_deps
= chunk
->length_dw
* 4 /
990 sizeof(struct drm_amdgpu_cs_chunk_dep
);
992 for (i
= 0; i
< num_deps
; ++i
) {
993 struct amdgpu_ring
*ring
;
994 struct amdgpu_ctx
*ctx
;
995 struct dma_fence
*fence
;
997 ctx
= amdgpu_ctx_get(fpriv
, deps
[i
].ctx_id
);
1001 r
= amdgpu_queue_mgr_map(p
->adev
, &ctx
->queue_mgr
,
1003 deps
[i
].ip_instance
,
1004 deps
[i
].ring
, &ring
);
1006 amdgpu_ctx_put(ctx
);
1010 fence
= amdgpu_ctx_get_fence(ctx
, ring
,
1012 if (IS_ERR(fence
)) {
1014 amdgpu_ctx_put(ctx
);
1017 r
= amdgpu_sync_fence(p
->adev
, &p
->job
->sync
,
1019 dma_fence_put(fence
);
1020 amdgpu_ctx_put(ctx
);
1028 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser
*p
,
1032 struct dma_fence
*fence
;
1033 r
= drm_syncobj_find_fence(p
->filp
, handle
, &fence
);
1037 r
= amdgpu_sync_fence(p
->adev
, &p
->job
->sync
, fence
);
1038 dma_fence_put(fence
);
1043 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser
*p
,
1044 struct amdgpu_cs_chunk
*chunk
)
1048 struct drm_amdgpu_cs_chunk_sem
*deps
;
1050 deps
= (struct drm_amdgpu_cs_chunk_sem
*)chunk
->kdata
;
1051 num_deps
= chunk
->length_dw
* 4 /
1052 sizeof(struct drm_amdgpu_cs_chunk_sem
);
1054 for (i
= 0; i
< num_deps
; ++i
) {
1055 r
= amdgpu_syncobj_lookup_and_add_to_sync(p
, deps
[i
].handle
);
1062 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser
*p
,
1063 struct amdgpu_cs_chunk
*chunk
)
1067 struct drm_amdgpu_cs_chunk_sem
*deps
;
1068 deps
= (struct drm_amdgpu_cs_chunk_sem
*)chunk
->kdata
;
1069 num_deps
= chunk
->length_dw
* 4 /
1070 sizeof(struct drm_amdgpu_cs_chunk_sem
);
1072 p
->post_dep_syncobjs
= kmalloc_array(num_deps
,
1073 sizeof(struct drm_syncobj
*),
1075 p
->num_post_dep_syncobjs
= 0;
1077 if (!p
->post_dep_syncobjs
)
1080 for (i
= 0; i
< num_deps
; ++i
) {
1081 p
->post_dep_syncobjs
[i
] = drm_syncobj_find(p
->filp
, deps
[i
].handle
);
1082 if (!p
->post_dep_syncobjs
[i
])
1084 p
->num_post_dep_syncobjs
++;
1089 static int amdgpu_cs_dependencies(struct amdgpu_device
*adev
,
1090 struct amdgpu_cs_parser
*p
)
1094 for (i
= 0; i
< p
->nchunks
; ++i
) {
1095 struct amdgpu_cs_chunk
*chunk
;
1097 chunk
= &p
->chunks
[i
];
1099 if (chunk
->chunk_id
== AMDGPU_CHUNK_ID_DEPENDENCIES
) {
1100 r
= amdgpu_cs_process_fence_dep(p
, chunk
);
1103 } else if (chunk
->chunk_id
== AMDGPU_CHUNK_ID_SYNCOBJ_IN
) {
1104 r
= amdgpu_cs_process_syncobj_in_dep(p
, chunk
);
1107 } else if (chunk
->chunk_id
== AMDGPU_CHUNK_ID_SYNCOBJ_OUT
) {
1108 r
= amdgpu_cs_process_syncobj_out_dep(p
, chunk
);
1117 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser
*p
)
1121 for (i
= 0; i
< p
->num_post_dep_syncobjs
; ++i
)
1122 drm_syncobj_replace_fence(p
->post_dep_syncobjs
[i
], p
->fence
);
1125 static int amdgpu_cs_submit(struct amdgpu_cs_parser
*p
,
1126 union drm_amdgpu_cs
*cs
)
1128 struct amdgpu_ring
*ring
= p
->job
->ring
;
1129 struct amd_sched_entity
*entity
= &p
->ctx
->rings
[ring
->idx
].entity
;
1130 struct amdgpu_job
*job
;
1136 r
= amd_sched_job_init(&job
->base
, &ring
->sched
, entity
, p
->filp
);
1138 amdgpu_job_free(job
);
1142 job
->owner
= p
->filp
;
1143 job
->fence_ctx
= entity
->fence_context
;
1144 p
->fence
= dma_fence_get(&job
->base
.s_fence
->finished
);
1146 amdgpu_cs_post_dependencies(p
);
1148 cs
->out
.handle
= amdgpu_ctx_add_fence(p
->ctx
, ring
, p
->fence
);
1149 job
->uf_sequence
= cs
->out
.handle
;
1150 amdgpu_job_free_resources(job
);
1151 amdgpu_cs_parser_fini(p
, 0, true);
1153 trace_amdgpu_cs_ioctl(job
);
1154 amd_sched_entity_push_job(&job
->base
);
1158 int amdgpu_cs_ioctl(struct drm_device
*dev
, void *data
, struct drm_file
*filp
)
1160 struct amdgpu_device
*adev
= dev
->dev_private
;
1161 struct amdgpu_fpriv
*fpriv
= filp
->driver_priv
;
1162 union drm_amdgpu_cs
*cs
= data
;
1163 struct amdgpu_cs_parser parser
= {};
1164 bool reserved_buffers
= false;
1167 if (!adev
->accel_working
)
1169 if (amdgpu_kms_vram_lost(adev
, fpriv
))
1175 r
= amdgpu_cs_parser_init(&parser
, data
);
1177 DRM_ERROR("Failed to initialize parser !\n");
1181 r
= amdgpu_cs_parser_bos(&parser
, data
);
1184 DRM_ERROR("Not enough memory for command submission!\n");
1185 else if (r
!= -ERESTARTSYS
)
1186 DRM_ERROR("Failed to process the buffer list %d!\n", r
);
1190 reserved_buffers
= true;
1191 r
= amdgpu_cs_ib_fill(adev
, &parser
);
1195 r
= amdgpu_cs_dependencies(adev
, &parser
);
1197 DRM_ERROR("Failed in the dependencies handling %d!\n", r
);
1201 for (i
= 0; i
< parser
.job
->num_ibs
; i
++)
1202 trace_amdgpu_cs(&parser
, i
);
1204 r
= amdgpu_cs_ib_vm_chunk(adev
, &parser
);
1208 r
= amdgpu_cs_submit(&parser
, cs
);
1214 amdgpu_cs_parser_fini(&parser
, r
, reserved_buffers
);
1219 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1222 * @data: data from userspace
1223 * @filp: file private
1225 * Wait for the command submission identified by handle to finish.
1227 int amdgpu_cs_wait_ioctl(struct drm_device
*dev
, void *data
,
1228 struct drm_file
*filp
)
1230 union drm_amdgpu_wait_cs
*wait
= data
;
1231 struct amdgpu_device
*adev
= dev
->dev_private
;
1232 struct amdgpu_fpriv
*fpriv
= filp
->driver_priv
;
1233 unsigned long timeout
= amdgpu_gem_timeout(wait
->in
.timeout
);
1234 struct amdgpu_ring
*ring
= NULL
;
1235 struct amdgpu_ctx
*ctx
;
1236 struct dma_fence
*fence
;
1239 if (amdgpu_kms_vram_lost(adev
, fpriv
))
1242 ctx
= amdgpu_ctx_get(filp
->driver_priv
, wait
->in
.ctx_id
);
1246 r
= amdgpu_queue_mgr_map(adev
, &ctx
->queue_mgr
,
1247 wait
->in
.ip_type
, wait
->in
.ip_instance
,
1248 wait
->in
.ring
, &ring
);
1250 amdgpu_ctx_put(ctx
);
1254 fence
= amdgpu_ctx_get_fence(ctx
, ring
, wait
->in
.handle
);
1258 r
= dma_fence_wait_timeout(fence
, true, timeout
);
1259 dma_fence_put(fence
);
1263 amdgpu_ctx_put(ctx
);
1267 memset(wait
, 0, sizeof(*wait
));
1268 wait
->out
.status
= (r
== 0);
1274 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1276 * @adev: amdgpu device
1277 * @filp: file private
1278 * @user: drm_amdgpu_fence copied from user space
1280 static struct dma_fence
*amdgpu_cs_get_fence(struct amdgpu_device
*adev
,
1281 struct drm_file
*filp
,
1282 struct drm_amdgpu_fence
*user
)
1284 struct amdgpu_ring
*ring
;
1285 struct amdgpu_ctx
*ctx
;
1286 struct dma_fence
*fence
;
1289 ctx
= amdgpu_ctx_get(filp
->driver_priv
, user
->ctx_id
);
1291 return ERR_PTR(-EINVAL
);
1293 r
= amdgpu_queue_mgr_map(adev
, &ctx
->queue_mgr
, user
->ip_type
,
1294 user
->ip_instance
, user
->ring
, &ring
);
1296 amdgpu_ctx_put(ctx
);
1300 fence
= amdgpu_ctx_get_fence(ctx
, ring
, user
->seq_no
);
1301 amdgpu_ctx_put(ctx
);
1307 * amdgpu_cs_wait_all_fence - wait on all fences to signal
1309 * @adev: amdgpu device
1310 * @filp: file private
1311 * @wait: wait parameters
1312 * @fences: array of drm_amdgpu_fence
1314 static int amdgpu_cs_wait_all_fences(struct amdgpu_device
*adev
,
1315 struct drm_file
*filp
,
1316 union drm_amdgpu_wait_fences
*wait
,
1317 struct drm_amdgpu_fence
*fences
)
1319 uint32_t fence_count
= wait
->in
.fence_count
;
1323 for (i
= 0; i
< fence_count
; i
++) {
1324 struct dma_fence
*fence
;
1325 unsigned long timeout
= amdgpu_gem_timeout(wait
->in
.timeout_ns
);
1327 fence
= amdgpu_cs_get_fence(adev
, filp
, &fences
[i
]);
1329 return PTR_ERR(fence
);
1333 r
= dma_fence_wait_timeout(fence
, true, timeout
);
1334 dma_fence_put(fence
);
1342 memset(wait
, 0, sizeof(*wait
));
1343 wait
->out
.status
= (r
> 0);
1349 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1351 * @adev: amdgpu device
1352 * @filp: file private
1353 * @wait: wait parameters
1354 * @fences: array of drm_amdgpu_fence
1356 static int amdgpu_cs_wait_any_fence(struct amdgpu_device
*adev
,
1357 struct drm_file
*filp
,
1358 union drm_amdgpu_wait_fences
*wait
,
1359 struct drm_amdgpu_fence
*fences
)
1361 unsigned long timeout
= amdgpu_gem_timeout(wait
->in
.timeout_ns
);
1362 uint32_t fence_count
= wait
->in
.fence_count
;
1363 uint32_t first
= ~0;
1364 struct dma_fence
**array
;
1368 /* Prepare the fence array */
1369 array
= kcalloc(fence_count
, sizeof(struct dma_fence
*), GFP_KERNEL
);
1374 for (i
= 0; i
< fence_count
; i
++) {
1375 struct dma_fence
*fence
;
1377 fence
= amdgpu_cs_get_fence(adev
, filp
, &fences
[i
]);
1378 if (IS_ERR(fence
)) {
1380 goto err_free_fence_array
;
1383 } else { /* NULL, the fence has been already signaled */
1390 r
= dma_fence_wait_any_timeout(array
, fence_count
, true, timeout
,
1393 goto err_free_fence_array
;
1396 memset(wait
, 0, sizeof(*wait
));
1397 wait
->out
.status
= (r
> 0);
1398 wait
->out
.first_signaled
= first
;
1399 /* set return value 0 to indicate success */
1402 err_free_fence_array
:
1403 for (i
= 0; i
< fence_count
; i
++)
1404 dma_fence_put(array
[i
]);
1411 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1414 * @data: data from userspace
1415 * @filp: file private
1417 int amdgpu_cs_wait_fences_ioctl(struct drm_device
*dev
, void *data
,
1418 struct drm_file
*filp
)
1420 struct amdgpu_device
*adev
= dev
->dev_private
;
1421 struct amdgpu_fpriv
*fpriv
= filp
->driver_priv
;
1422 union drm_amdgpu_wait_fences
*wait
= data
;
1423 uint32_t fence_count
= wait
->in
.fence_count
;
1424 struct drm_amdgpu_fence
*fences_user
;
1425 struct drm_amdgpu_fence
*fences
;
1428 if (amdgpu_kms_vram_lost(adev
, fpriv
))
1430 /* Get the fences from userspace */
1431 fences
= kmalloc_array(fence_count
, sizeof(struct drm_amdgpu_fence
),
1436 fences_user
= u64_to_user_ptr(wait
->in
.fences
);
1437 if (copy_from_user(fences
, fences_user
,
1438 sizeof(struct drm_amdgpu_fence
) * fence_count
)) {
1440 goto err_free_fences
;
1443 if (wait
->in
.wait_all
)
1444 r
= amdgpu_cs_wait_all_fences(adev
, filp
, wait
, fences
);
1446 r
= amdgpu_cs_wait_any_fence(adev
, filp
, wait
, fences
);
1455 * amdgpu_cs_find_bo_va - find bo_va for VM address
1457 * @parser: command submission parser context
1459 * @bo: resulting BO of the mapping found
1461 * Search the buffer objects in the command submission context for a certain
1462 * virtual memory address. Returns allocation structure when found, NULL
1465 struct amdgpu_bo_va_mapping
*
1466 amdgpu_cs_find_mapping(struct amdgpu_cs_parser
*parser
,
1467 uint64_t addr
, struct amdgpu_bo
**bo
)
1469 struct amdgpu_bo_va_mapping
*mapping
;
1472 if (!parser
->bo_list
)
1475 addr
/= AMDGPU_GPU_PAGE_SIZE
;
1477 for (i
= 0; i
< parser
->bo_list
->num_entries
; i
++) {
1478 struct amdgpu_bo_list_entry
*lobj
;
1480 lobj
= &parser
->bo_list
->array
[i
];
1484 list_for_each_entry(mapping
, &lobj
->bo_va
->valids
, list
) {
1485 if (mapping
->start
> addr
||
1486 addr
> mapping
->last
)
1489 *bo
= lobj
->bo_va
->base
.bo
;
1493 list_for_each_entry(mapping
, &lobj
->bo_va
->invalids
, list
) {
1494 if (mapping
->start
> addr
||
1495 addr
> mapping
->last
)
1498 *bo
= lobj
->bo_va
->base
.bo
;
1507 * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
1509 * @parser: command submission parser context
1511 * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
1513 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser
*parser
)
1518 if (!parser
->bo_list
)
1521 for (i
= 0; i
< parser
->bo_list
->num_entries
; i
++) {
1522 struct amdgpu_bo
*bo
= parser
->bo_list
->array
[i
].robj
;
1524 r
= amdgpu_ttm_bind(&bo
->tbo
, &bo
->tbo
.mem
);
1528 if (bo
->flags
& AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
)
1531 bo
->flags
|= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS
;
1532 amdgpu_ttm_placement_from_domain(bo
, bo
->allowed_domains
);
1533 r
= ttm_bo_validate(&bo
->tbo
, &bo
->placement
, false, false);