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drm/amdgpu: fix userptr put_page handling
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_cs.c
1 /*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27 #include <linux/pagemap.h>
28 #include <drm/drmP.h>
29 #include <drm/amdgpu_drm.h>
30 #include <drm/drm_syncobj.h>
31 #include "amdgpu.h"
32 #include "amdgpu_trace.h"
33
34 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
35 struct drm_amdgpu_cs_chunk_fence *data,
36 uint32_t *offset)
37 {
38 struct drm_gem_object *gobj;
39 unsigned long size;
40
41 gobj = drm_gem_object_lookup(p->filp, data->handle);
42 if (gobj == NULL)
43 return -EINVAL;
44
45 p->uf_entry.robj = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
46 p->uf_entry.priority = 0;
47 p->uf_entry.tv.bo = &p->uf_entry.robj->tbo;
48 p->uf_entry.tv.shared = true;
49 p->uf_entry.user_pages = NULL;
50
51 size = amdgpu_bo_size(p->uf_entry.robj);
52 if (size != PAGE_SIZE || (data->offset + 8) > size)
53 return -EINVAL;
54
55 *offset = data->offset;
56
57 drm_gem_object_put_unlocked(gobj);
58
59 if (amdgpu_ttm_tt_get_usermm(p->uf_entry.robj->tbo.ttm)) {
60 amdgpu_bo_unref(&p->uf_entry.robj);
61 return -EINVAL;
62 }
63
64 return 0;
65 }
66
67 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
68 {
69 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
70 struct amdgpu_vm *vm = &fpriv->vm;
71 union drm_amdgpu_cs *cs = data;
72 uint64_t *chunk_array_user;
73 uint64_t *chunk_array;
74 unsigned size, num_ibs = 0;
75 uint32_t uf_offset = 0;
76 int i;
77 int ret;
78
79 if (cs->in.num_chunks == 0)
80 return 0;
81
82 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
83 if (!chunk_array)
84 return -ENOMEM;
85
86 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
87 if (!p->ctx) {
88 ret = -EINVAL;
89 goto free_chunk;
90 }
91
92 /* get chunks */
93 chunk_array_user = u64_to_user_ptr(cs->in.chunks);
94 if (copy_from_user(chunk_array, chunk_array_user,
95 sizeof(uint64_t)*cs->in.num_chunks)) {
96 ret = -EFAULT;
97 goto put_ctx;
98 }
99
100 p->nchunks = cs->in.num_chunks;
101 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
102 GFP_KERNEL);
103 if (!p->chunks) {
104 ret = -ENOMEM;
105 goto put_ctx;
106 }
107
108 for (i = 0; i < p->nchunks; i++) {
109 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
110 struct drm_amdgpu_cs_chunk user_chunk;
111 uint32_t __user *cdata;
112
113 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
114 if (copy_from_user(&user_chunk, chunk_ptr,
115 sizeof(struct drm_amdgpu_cs_chunk))) {
116 ret = -EFAULT;
117 i--;
118 goto free_partial_kdata;
119 }
120 p->chunks[i].chunk_id = user_chunk.chunk_id;
121 p->chunks[i].length_dw = user_chunk.length_dw;
122
123 size = p->chunks[i].length_dw;
124 cdata = u64_to_user_ptr(user_chunk.chunk_data);
125
126 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
127 if (p->chunks[i].kdata == NULL) {
128 ret = -ENOMEM;
129 i--;
130 goto free_partial_kdata;
131 }
132 size *= sizeof(uint32_t);
133 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
134 ret = -EFAULT;
135 goto free_partial_kdata;
136 }
137
138 switch (p->chunks[i].chunk_id) {
139 case AMDGPU_CHUNK_ID_IB:
140 ++num_ibs;
141 break;
142
143 case AMDGPU_CHUNK_ID_FENCE:
144 size = sizeof(struct drm_amdgpu_cs_chunk_fence);
145 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
146 ret = -EINVAL;
147 goto free_partial_kdata;
148 }
149
150 ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
151 &uf_offset);
152 if (ret)
153 goto free_partial_kdata;
154
155 break;
156
157 case AMDGPU_CHUNK_ID_DEPENDENCIES:
158 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
159 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
160 break;
161
162 default:
163 ret = -EINVAL;
164 goto free_partial_kdata;
165 }
166 }
167
168 ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
169 if (ret)
170 goto free_all_kdata;
171
172 if (p->uf_entry.robj)
173 p->job->uf_addr = uf_offset;
174 kfree(chunk_array);
175 return 0;
176
177 free_all_kdata:
178 i = p->nchunks - 1;
179 free_partial_kdata:
180 for (; i >= 0; i--)
181 kvfree(p->chunks[i].kdata);
182 kfree(p->chunks);
183 p->chunks = NULL;
184 p->nchunks = 0;
185 put_ctx:
186 amdgpu_ctx_put(p->ctx);
187 free_chunk:
188 kfree(chunk_array);
189
190 return ret;
191 }
192
193 /* Convert microseconds to bytes. */
194 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
195 {
196 if (us <= 0 || !adev->mm_stats.log2_max_MBps)
197 return 0;
198
199 /* Since accum_us is incremented by a million per second, just
200 * multiply it by the number of MB/s to get the number of bytes.
201 */
202 return us << adev->mm_stats.log2_max_MBps;
203 }
204
205 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
206 {
207 if (!adev->mm_stats.log2_max_MBps)
208 return 0;
209
210 return bytes >> adev->mm_stats.log2_max_MBps;
211 }
212
213 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
214 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
215 * which means it can go over the threshold once. If that happens, the driver
216 * will be in debt and no other buffer migrations can be done until that debt
217 * is repaid.
218 *
219 * This approach allows moving a buffer of any size (it's important to allow
220 * that).
221 *
222 * The currency is simply time in microseconds and it increases as the clock
223 * ticks. The accumulated microseconds (us) are converted to bytes and
224 * returned.
225 */
226 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
227 u64 *max_bytes,
228 u64 *max_vis_bytes)
229 {
230 s64 time_us, increment_us;
231 u64 free_vram, total_vram, used_vram;
232
233 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
234 * throttling.
235 *
236 * It means that in order to get full max MBps, at least 5 IBs per
237 * second must be submitted and not more than 200ms apart from each
238 * other.
239 */
240 const s64 us_upper_bound = 200000;
241
242 if (!adev->mm_stats.log2_max_MBps) {
243 *max_bytes = 0;
244 *max_vis_bytes = 0;
245 return;
246 }
247
248 total_vram = adev->mc.real_vram_size - adev->vram_pin_size;
249 used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
250 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
251
252 spin_lock(&adev->mm_stats.lock);
253
254 /* Increase the amount of accumulated us. */
255 time_us = ktime_to_us(ktime_get());
256 increment_us = time_us - adev->mm_stats.last_update_us;
257 adev->mm_stats.last_update_us = time_us;
258 adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
259 us_upper_bound);
260
261 /* This prevents the short period of low performance when the VRAM
262 * usage is low and the driver is in debt or doesn't have enough
263 * accumulated us to fill VRAM quickly.
264 *
265 * The situation can occur in these cases:
266 * - a lot of VRAM is freed by userspace
267 * - the presence of a big buffer causes a lot of evictions
268 * (solution: split buffers into smaller ones)
269 *
270 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
271 * accum_us to a positive number.
272 */
273 if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
274 s64 min_us;
275
276 /* Be more aggresive on dGPUs. Try to fill a portion of free
277 * VRAM now.
278 */
279 if (!(adev->flags & AMD_IS_APU))
280 min_us = bytes_to_us(adev, free_vram / 4);
281 else
282 min_us = 0; /* Reset accum_us on APUs. */
283
284 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
285 }
286
287 /* This is set to 0 if the driver is in debt to disallow (optional)
288 * buffer moves.
289 */
290 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
291
292 /* Do the same for visible VRAM if half of it is free */
293 if (adev->mc.visible_vram_size < adev->mc.real_vram_size) {
294 u64 total_vis_vram = adev->mc.visible_vram_size;
295 u64 used_vis_vram =
296 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
297
298 if (used_vis_vram < total_vis_vram) {
299 u64 free_vis_vram = total_vis_vram - used_vis_vram;
300 adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
301 increment_us, us_upper_bound);
302
303 if (free_vis_vram >= total_vis_vram / 2)
304 adev->mm_stats.accum_us_vis =
305 max(bytes_to_us(adev, free_vis_vram / 2),
306 adev->mm_stats.accum_us_vis);
307 }
308
309 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
310 } else {
311 *max_vis_bytes = 0;
312 }
313
314 spin_unlock(&adev->mm_stats.lock);
315 }
316
317 /* Report how many bytes have really been moved for the last command
318 * submission. This can result in a debt that can stop buffer migrations
319 * temporarily.
320 */
321 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
322 u64 num_vis_bytes)
323 {
324 spin_lock(&adev->mm_stats.lock);
325 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
326 adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
327 spin_unlock(&adev->mm_stats.lock);
328 }
329
330 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
331 struct amdgpu_bo *bo)
332 {
333 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
334 u64 initial_bytes_moved, bytes_moved;
335 uint32_t domain;
336 int r;
337
338 if (bo->pin_count)
339 return 0;
340
341 /* Don't move this buffer if we have depleted our allowance
342 * to move it. Don't move anything if the threshold is zero.
343 */
344 if (p->bytes_moved < p->bytes_moved_threshold) {
345 if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
346 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
347 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
348 * visible VRAM if we've depleted our allowance to do
349 * that.
350 */
351 if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
352 domain = bo->preferred_domains;
353 else
354 domain = bo->allowed_domains;
355 } else {
356 domain = bo->preferred_domains;
357 }
358 } else {
359 domain = bo->allowed_domains;
360 }
361
362 retry:
363 amdgpu_ttm_placement_from_domain(bo, domain);
364 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
365 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
366 bytes_moved = atomic64_read(&adev->num_bytes_moved) -
367 initial_bytes_moved;
368 p->bytes_moved += bytes_moved;
369 if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
370 bo->tbo.mem.mem_type == TTM_PL_VRAM &&
371 bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
372 p->bytes_moved_vis += bytes_moved;
373
374 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
375 domain = bo->allowed_domains;
376 goto retry;
377 }
378
379 return r;
380 }
381
382 /* Last resort, try to evict something from the current working set */
383 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
384 struct amdgpu_bo *validated)
385 {
386 uint32_t domain = validated->allowed_domains;
387 int r;
388
389 if (!p->evictable)
390 return false;
391
392 for (;&p->evictable->tv.head != &p->validated;
393 p->evictable = list_prev_entry(p->evictable, tv.head)) {
394
395 struct amdgpu_bo_list_entry *candidate = p->evictable;
396 struct amdgpu_bo *bo = candidate->robj;
397 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
398 u64 initial_bytes_moved, bytes_moved;
399 bool update_bytes_moved_vis;
400 uint32_t other;
401
402 /* If we reached our current BO we can forget it */
403 if (candidate->robj == validated)
404 break;
405
406 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
407
408 /* Check if this BO is in one of the domains we need space for */
409 if (!(other & domain))
410 continue;
411
412 /* Check if we can move this BO somewhere else */
413 other = bo->allowed_domains & ~domain;
414 if (!other)
415 continue;
416
417 /* Good we can try to move this BO somewhere else */
418 amdgpu_ttm_placement_from_domain(bo, other);
419 update_bytes_moved_vis =
420 adev->mc.visible_vram_size < adev->mc.real_vram_size &&
421 bo->tbo.mem.mem_type == TTM_PL_VRAM &&
422 bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT;
423 initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
424 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
425 bytes_moved = atomic64_read(&adev->num_bytes_moved) -
426 initial_bytes_moved;
427 p->bytes_moved += bytes_moved;
428 if (update_bytes_moved_vis)
429 p->bytes_moved_vis += bytes_moved;
430
431 if (unlikely(r))
432 break;
433
434 p->evictable = list_prev_entry(p->evictable, tv.head);
435 list_move(&candidate->tv.head, &p->validated);
436
437 return true;
438 }
439
440 return false;
441 }
442
443 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
444 {
445 struct amdgpu_cs_parser *p = param;
446 int r;
447
448 do {
449 r = amdgpu_cs_bo_validate(p, bo);
450 } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
451 if (r)
452 return r;
453
454 if (bo->shadow)
455 r = amdgpu_cs_bo_validate(p, bo->shadow);
456
457 return r;
458 }
459
460 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
461 struct list_head *validated)
462 {
463 struct amdgpu_bo_list_entry *lobj;
464 int r;
465
466 list_for_each_entry(lobj, validated, tv.head) {
467 struct amdgpu_bo *bo = lobj->robj;
468 bool binding_userptr = false;
469 struct mm_struct *usermm;
470
471 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
472 if (usermm && usermm != current->mm)
473 return -EPERM;
474
475 /* Check if we have user pages and nobody bound the BO already */
476 if (lobj->user_pages && bo->tbo.ttm->state != tt_bound) {
477 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
478 lobj->user_pages);
479 binding_userptr = true;
480 }
481
482 if (p->evictable == lobj)
483 p->evictable = NULL;
484
485 r = amdgpu_cs_validate(p, bo);
486 if (r)
487 return r;
488
489 if (binding_userptr) {
490 kvfree(lobj->user_pages);
491 lobj->user_pages = NULL;
492 }
493 }
494 return 0;
495 }
496
497 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
498 union drm_amdgpu_cs *cs)
499 {
500 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
501 struct amdgpu_bo_list_entry *e;
502 struct list_head duplicates;
503 bool need_mmap_lock = false;
504 unsigned i, tries = 10;
505 int r;
506
507 INIT_LIST_HEAD(&p->validated);
508
509 p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
510 if (p->bo_list) {
511 need_mmap_lock = p->bo_list->first_userptr !=
512 p->bo_list->num_entries;
513 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
514 }
515
516 INIT_LIST_HEAD(&duplicates);
517 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
518
519 if (p->uf_entry.robj)
520 list_add(&p->uf_entry.tv.head, &p->validated);
521
522 if (need_mmap_lock)
523 down_read(&current->mm->mmap_sem);
524
525 while (1) {
526 struct list_head need_pages;
527 unsigned i;
528
529 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
530 &duplicates);
531 if (unlikely(r != 0)) {
532 if (r != -ERESTARTSYS)
533 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
534 goto error_free_pages;
535 }
536
537 /* Without a BO list we don't have userptr BOs */
538 if (!p->bo_list)
539 break;
540
541 INIT_LIST_HEAD(&need_pages);
542 for (i = p->bo_list->first_userptr;
543 i < p->bo_list->num_entries; ++i) {
544
545 e = &p->bo_list->array[i];
546
547 if (amdgpu_ttm_tt_userptr_invalidated(e->robj->tbo.ttm,
548 &e->user_invalidated) && e->user_pages) {
549
550 /* We acquired a page array, but somebody
551 * invalidated it. Free it and try again
552 */
553 release_pages(e->user_pages,
554 e->robj->tbo.ttm->num_pages,
555 false);
556 kvfree(e->user_pages);
557 e->user_pages = NULL;
558 }
559
560 if (e->robj->tbo.ttm->state != tt_bound &&
561 !e->user_pages) {
562 list_del(&e->tv.head);
563 list_add(&e->tv.head, &need_pages);
564
565 amdgpu_bo_unreserve(e->robj);
566 }
567 }
568
569 if (list_empty(&need_pages))
570 break;
571
572 /* Unreserve everything again. */
573 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
574
575 /* We tried too many times, just abort */
576 if (!--tries) {
577 r = -EDEADLK;
578 DRM_ERROR("deadlock in %s\n", __func__);
579 goto error_free_pages;
580 }
581
582 /* Fill the page arrays for all userptrs. */
583 list_for_each_entry(e, &need_pages, tv.head) {
584 struct ttm_tt *ttm = e->robj->tbo.ttm;
585
586 e->user_pages = kvmalloc_array(ttm->num_pages,
587 sizeof(struct page*),
588 GFP_KERNEL | __GFP_ZERO);
589 if (!e->user_pages) {
590 r = -ENOMEM;
591 DRM_ERROR("calloc failure in %s\n", __func__);
592 goto error_free_pages;
593 }
594
595 r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
596 if (r) {
597 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
598 kvfree(e->user_pages);
599 e->user_pages = NULL;
600 goto error_free_pages;
601 }
602 }
603
604 /* And try again. */
605 list_splice(&need_pages, &p->validated);
606 }
607
608 amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
609 &p->bytes_moved_vis_threshold);
610 p->bytes_moved = 0;
611 p->bytes_moved_vis = 0;
612 p->evictable = list_last_entry(&p->validated,
613 struct amdgpu_bo_list_entry,
614 tv.head);
615
616 r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
617 amdgpu_cs_validate, p);
618 if (r) {
619 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
620 goto error_validate;
621 }
622
623 r = amdgpu_cs_list_validate(p, &duplicates);
624 if (r) {
625 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
626 goto error_validate;
627 }
628
629 r = amdgpu_cs_list_validate(p, &p->validated);
630 if (r) {
631 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
632 goto error_validate;
633 }
634
635 amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
636 p->bytes_moved_vis);
637 if (p->bo_list) {
638 struct amdgpu_bo *gds = p->bo_list->gds_obj;
639 struct amdgpu_bo *gws = p->bo_list->gws_obj;
640 struct amdgpu_bo *oa = p->bo_list->oa_obj;
641 struct amdgpu_vm *vm = &fpriv->vm;
642 unsigned i;
643
644 for (i = 0; i < p->bo_list->num_entries; i++) {
645 struct amdgpu_bo *bo = p->bo_list->array[i].robj;
646
647 p->bo_list->array[i].bo_va = amdgpu_vm_bo_find(vm, bo);
648 }
649
650 if (gds) {
651 p->job->gds_base = amdgpu_bo_gpu_offset(gds);
652 p->job->gds_size = amdgpu_bo_size(gds);
653 }
654 if (gws) {
655 p->job->gws_base = amdgpu_bo_gpu_offset(gws);
656 p->job->gws_size = amdgpu_bo_size(gws);
657 }
658 if (oa) {
659 p->job->oa_base = amdgpu_bo_gpu_offset(oa);
660 p->job->oa_size = amdgpu_bo_size(oa);
661 }
662 }
663
664 if (!r && p->uf_entry.robj) {
665 struct amdgpu_bo *uf = p->uf_entry.robj;
666
667 r = amdgpu_ttm_bind(&uf->tbo, &uf->tbo.mem);
668 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
669 }
670
671 error_validate:
672 if (r)
673 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
674
675 error_free_pages:
676
677 if (need_mmap_lock)
678 up_read(&current->mm->mmap_sem);
679
680 if (p->bo_list) {
681 for (i = p->bo_list->first_userptr;
682 i < p->bo_list->num_entries; ++i) {
683 e = &p->bo_list->array[i];
684
685 if (!e->user_pages)
686 continue;
687
688 release_pages(e->user_pages,
689 e->robj->tbo.ttm->num_pages,
690 false);
691 kvfree(e->user_pages);
692 }
693 }
694
695 return r;
696 }
697
698 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
699 {
700 struct amdgpu_bo_list_entry *e;
701 int r;
702
703 list_for_each_entry(e, &p->validated, tv.head) {
704 struct reservation_object *resv = e->robj->tbo.resv;
705 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp);
706
707 if (r)
708 return r;
709 }
710 return 0;
711 }
712
713 /**
714 * cs_parser_fini() - clean parser states
715 * @parser: parser structure holding parsing context.
716 * @error: error number
717 *
718 * If error is set than unvalidate buffer, otherwise just free memory
719 * used by parsing context.
720 **/
721 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
722 bool backoff)
723 {
724 unsigned i;
725
726 if (!error)
727 ttm_eu_fence_buffer_objects(&parser->ticket,
728 &parser->validated,
729 parser->fence);
730 else if (backoff)
731 ttm_eu_backoff_reservation(&parser->ticket,
732 &parser->validated);
733
734 for (i = 0; i < parser->num_post_dep_syncobjs; i++)
735 drm_syncobj_put(parser->post_dep_syncobjs[i]);
736 kfree(parser->post_dep_syncobjs);
737
738 dma_fence_put(parser->fence);
739
740 if (parser->ctx)
741 amdgpu_ctx_put(parser->ctx);
742 if (parser->bo_list)
743 amdgpu_bo_list_put(parser->bo_list);
744
745 for (i = 0; i < parser->nchunks; i++)
746 kvfree(parser->chunks[i].kdata);
747 kfree(parser->chunks);
748 if (parser->job)
749 amdgpu_job_free(parser->job);
750 amdgpu_bo_unref(&parser->uf_entry.robj);
751 }
752
753 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
754 {
755 struct amdgpu_device *adev = p->adev;
756 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
757 struct amdgpu_vm *vm = &fpriv->vm;
758 struct amdgpu_bo_va *bo_va;
759 struct amdgpu_bo *bo;
760 int i, r;
761
762 r = amdgpu_vm_update_directories(adev, vm);
763 if (r)
764 return r;
765
766 r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_dir_update);
767 if (r)
768 return r;
769
770 r = amdgpu_vm_clear_freed(adev, vm, NULL);
771 if (r)
772 return r;
773
774 r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
775 if (r)
776 return r;
777
778 r = amdgpu_sync_fence(adev, &p->job->sync,
779 fpriv->prt_va->last_pt_update);
780 if (r)
781 return r;
782
783 if (amdgpu_sriov_vf(adev)) {
784 struct dma_fence *f;
785
786 bo_va = fpriv->csa_va;
787 BUG_ON(!bo_va);
788 r = amdgpu_vm_bo_update(adev, bo_va, false);
789 if (r)
790 return r;
791
792 f = bo_va->last_pt_update;
793 r = amdgpu_sync_fence(adev, &p->job->sync, f);
794 if (r)
795 return r;
796 }
797
798 if (p->bo_list) {
799 for (i = 0; i < p->bo_list->num_entries; i++) {
800 struct dma_fence *f;
801
802 /* ignore duplicates */
803 bo = p->bo_list->array[i].robj;
804 if (!bo)
805 continue;
806
807 bo_va = p->bo_list->array[i].bo_va;
808 if (bo_va == NULL)
809 continue;
810
811 r = amdgpu_vm_bo_update(adev, bo_va, false);
812 if (r)
813 return r;
814
815 f = bo_va->last_pt_update;
816 r = amdgpu_sync_fence(adev, &p->job->sync, f);
817 if (r)
818 return r;
819 }
820
821 }
822
823 r = amdgpu_vm_handle_moved(adev, vm, &p->job->sync);
824
825 if (amdgpu_vm_debug && p->bo_list) {
826 /* Invalidate all BOs to test for userspace bugs */
827 for (i = 0; i < p->bo_list->num_entries; i++) {
828 /* ignore duplicates */
829 bo = p->bo_list->array[i].robj;
830 if (!bo)
831 continue;
832
833 amdgpu_vm_bo_invalidate(adev, bo, false);
834 }
835 }
836
837 return r;
838 }
839
840 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
841 struct amdgpu_cs_parser *p)
842 {
843 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
844 struct amdgpu_vm *vm = &fpriv->vm;
845 struct amdgpu_ring *ring = p->job->ring;
846 int i, r;
847
848 /* Only for UVD/VCE VM emulation */
849 if (ring->funcs->parse_cs) {
850 for (i = 0; i < p->job->num_ibs; i++) {
851 r = amdgpu_ring_parse_cs(ring, p, i);
852 if (r)
853 return r;
854 }
855 }
856
857 if (p->job->vm) {
858 p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
859
860 r = amdgpu_bo_vm_update_pte(p);
861 if (r)
862 return r;
863 }
864
865 return amdgpu_cs_sync_rings(p);
866 }
867
868 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
869 struct amdgpu_cs_parser *parser)
870 {
871 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
872 struct amdgpu_vm *vm = &fpriv->vm;
873 int i, j;
874 int r, ce_preempt = 0, de_preempt = 0;
875
876 for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
877 struct amdgpu_cs_chunk *chunk;
878 struct amdgpu_ib *ib;
879 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
880 struct amdgpu_ring *ring;
881
882 chunk = &parser->chunks[i];
883 ib = &parser->job->ibs[j];
884 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
885
886 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
887 continue;
888
889 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
890 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
891 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
892 ce_preempt++;
893 else
894 de_preempt++;
895 }
896
897 /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
898 if (ce_preempt > 1 || de_preempt > 1)
899 return -EINVAL;
900 }
901
902 r = amdgpu_queue_mgr_map(adev, &parser->ctx->queue_mgr, chunk_ib->ip_type,
903 chunk_ib->ip_instance, chunk_ib->ring, &ring);
904 if (r)
905 return r;
906
907 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE) {
908 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT;
909 if (!parser->ctx->preamble_presented) {
910 parser->job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
911 parser->ctx->preamble_presented = true;
912 }
913 }
914
915 if (parser->job->ring && parser->job->ring != ring)
916 return -EINVAL;
917
918 parser->job->ring = ring;
919
920 if (ring->funcs->parse_cs) {
921 struct amdgpu_bo_va_mapping *m;
922 struct amdgpu_bo *aobj = NULL;
923 uint64_t offset;
924 uint8_t *kptr;
925
926 m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
927 &aobj);
928 if (!aobj) {
929 DRM_ERROR("IB va_start is invalid\n");
930 return -EINVAL;
931 }
932
933 if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
934 (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
935 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
936 return -EINVAL;
937 }
938
939 /* the IB should be reserved at this point */
940 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
941 if (r) {
942 return r;
943 }
944
945 offset = m->start * AMDGPU_GPU_PAGE_SIZE;
946 kptr += chunk_ib->va_start - offset;
947
948 r = amdgpu_ib_get(adev, vm, chunk_ib->ib_bytes, ib);
949 if (r) {
950 DRM_ERROR("Failed to get ib !\n");
951 return r;
952 }
953
954 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
955 amdgpu_bo_kunmap(aobj);
956 } else {
957 r = amdgpu_ib_get(adev, vm, 0, ib);
958 if (r) {
959 DRM_ERROR("Failed to get ib !\n");
960 return r;
961 }
962
963 }
964
965 ib->gpu_addr = chunk_ib->va_start;
966 ib->length_dw = chunk_ib->ib_bytes / 4;
967 ib->flags = chunk_ib->flags;
968 j++;
969 }
970
971 /* UVD & VCE fw doesn't support user fences */
972 if (parser->job->uf_addr && (
973 parser->job->ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
974 parser->job->ring->funcs->type == AMDGPU_RING_TYPE_VCE))
975 return -EINVAL;
976
977 return 0;
978 }
979
980 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
981 struct amdgpu_cs_chunk *chunk)
982 {
983 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
984 unsigned num_deps;
985 int i, r;
986 struct drm_amdgpu_cs_chunk_dep *deps;
987
988 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
989 num_deps = chunk->length_dw * 4 /
990 sizeof(struct drm_amdgpu_cs_chunk_dep);
991
992 for (i = 0; i < num_deps; ++i) {
993 struct amdgpu_ring *ring;
994 struct amdgpu_ctx *ctx;
995 struct dma_fence *fence;
996
997 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
998 if (ctx == NULL)
999 return -EINVAL;
1000
1001 r = amdgpu_queue_mgr_map(p->adev, &ctx->queue_mgr,
1002 deps[i].ip_type,
1003 deps[i].ip_instance,
1004 deps[i].ring, &ring);
1005 if (r) {
1006 amdgpu_ctx_put(ctx);
1007 return r;
1008 }
1009
1010 fence = amdgpu_ctx_get_fence(ctx, ring,
1011 deps[i].handle);
1012 if (IS_ERR(fence)) {
1013 r = PTR_ERR(fence);
1014 amdgpu_ctx_put(ctx);
1015 return r;
1016 } else if (fence) {
1017 r = amdgpu_sync_fence(p->adev, &p->job->sync,
1018 fence);
1019 dma_fence_put(fence);
1020 amdgpu_ctx_put(ctx);
1021 if (r)
1022 return r;
1023 }
1024 }
1025 return 0;
1026 }
1027
1028 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1029 uint32_t handle)
1030 {
1031 int r;
1032 struct dma_fence *fence;
1033 r = drm_syncobj_find_fence(p->filp, handle, &fence);
1034 if (r)
1035 return r;
1036
1037 r = amdgpu_sync_fence(p->adev, &p->job->sync, fence);
1038 dma_fence_put(fence);
1039
1040 return r;
1041 }
1042
1043 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1044 struct amdgpu_cs_chunk *chunk)
1045 {
1046 unsigned num_deps;
1047 int i, r;
1048 struct drm_amdgpu_cs_chunk_sem *deps;
1049
1050 deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1051 num_deps = chunk->length_dw * 4 /
1052 sizeof(struct drm_amdgpu_cs_chunk_sem);
1053
1054 for (i = 0; i < num_deps; ++i) {
1055 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1056 if (r)
1057 return r;
1058 }
1059 return 0;
1060 }
1061
1062 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1063 struct amdgpu_cs_chunk *chunk)
1064 {
1065 unsigned num_deps;
1066 int i;
1067 struct drm_amdgpu_cs_chunk_sem *deps;
1068 deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1069 num_deps = chunk->length_dw * 4 /
1070 sizeof(struct drm_amdgpu_cs_chunk_sem);
1071
1072 p->post_dep_syncobjs = kmalloc_array(num_deps,
1073 sizeof(struct drm_syncobj *),
1074 GFP_KERNEL);
1075 p->num_post_dep_syncobjs = 0;
1076
1077 if (!p->post_dep_syncobjs)
1078 return -ENOMEM;
1079
1080 for (i = 0; i < num_deps; ++i) {
1081 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1082 if (!p->post_dep_syncobjs[i])
1083 return -EINVAL;
1084 p->num_post_dep_syncobjs++;
1085 }
1086 return 0;
1087 }
1088
1089 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1090 struct amdgpu_cs_parser *p)
1091 {
1092 int i, r;
1093
1094 for (i = 0; i < p->nchunks; ++i) {
1095 struct amdgpu_cs_chunk *chunk;
1096
1097 chunk = &p->chunks[i];
1098
1099 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1100 r = amdgpu_cs_process_fence_dep(p, chunk);
1101 if (r)
1102 return r;
1103 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1104 r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1105 if (r)
1106 return r;
1107 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1108 r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1109 if (r)
1110 return r;
1111 }
1112 }
1113
1114 return 0;
1115 }
1116
1117 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1118 {
1119 int i;
1120
1121 for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1122 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1123 }
1124
1125 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1126 union drm_amdgpu_cs *cs)
1127 {
1128 struct amdgpu_ring *ring = p->job->ring;
1129 struct amd_sched_entity *entity = &p->ctx->rings[ring->idx].entity;
1130 struct amdgpu_job *job;
1131 int r;
1132
1133 job = p->job;
1134 p->job = NULL;
1135
1136 r = amd_sched_job_init(&job->base, &ring->sched, entity, p->filp);
1137 if (r) {
1138 amdgpu_job_free(job);
1139 return r;
1140 }
1141
1142 job->owner = p->filp;
1143 job->fence_ctx = entity->fence_context;
1144 p->fence = dma_fence_get(&job->base.s_fence->finished);
1145
1146 amdgpu_cs_post_dependencies(p);
1147
1148 cs->out.handle = amdgpu_ctx_add_fence(p->ctx, ring, p->fence);
1149 job->uf_sequence = cs->out.handle;
1150 amdgpu_job_free_resources(job);
1151 amdgpu_cs_parser_fini(p, 0, true);
1152
1153 trace_amdgpu_cs_ioctl(job);
1154 amd_sched_entity_push_job(&job->base);
1155 return 0;
1156 }
1157
1158 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1159 {
1160 struct amdgpu_device *adev = dev->dev_private;
1161 struct amdgpu_fpriv *fpriv = filp->driver_priv;
1162 union drm_amdgpu_cs *cs = data;
1163 struct amdgpu_cs_parser parser = {};
1164 bool reserved_buffers = false;
1165 int i, r;
1166
1167 if (!adev->accel_working)
1168 return -EBUSY;
1169 if (amdgpu_kms_vram_lost(adev, fpriv))
1170 return -ENODEV;
1171
1172 parser.adev = adev;
1173 parser.filp = filp;
1174
1175 r = amdgpu_cs_parser_init(&parser, data);
1176 if (r) {
1177 DRM_ERROR("Failed to initialize parser !\n");
1178 goto out;
1179 }
1180
1181 r = amdgpu_cs_parser_bos(&parser, data);
1182 if (r) {
1183 if (r == -ENOMEM)
1184 DRM_ERROR("Not enough memory for command submission!\n");
1185 else if (r != -ERESTARTSYS)
1186 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1187 goto out;
1188 }
1189
1190 reserved_buffers = true;
1191 r = amdgpu_cs_ib_fill(adev, &parser);
1192 if (r)
1193 goto out;
1194
1195 r = amdgpu_cs_dependencies(adev, &parser);
1196 if (r) {
1197 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1198 goto out;
1199 }
1200
1201 for (i = 0; i < parser.job->num_ibs; i++)
1202 trace_amdgpu_cs(&parser, i);
1203
1204 r = amdgpu_cs_ib_vm_chunk(adev, &parser);
1205 if (r)
1206 goto out;
1207
1208 r = amdgpu_cs_submit(&parser, cs);
1209 if (r)
1210 goto out;
1211
1212 return 0;
1213 out:
1214 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1215 return r;
1216 }
1217
1218 /**
1219 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1220 *
1221 * @dev: drm device
1222 * @data: data from userspace
1223 * @filp: file private
1224 *
1225 * Wait for the command submission identified by handle to finish.
1226 */
1227 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1228 struct drm_file *filp)
1229 {
1230 union drm_amdgpu_wait_cs *wait = data;
1231 struct amdgpu_device *adev = dev->dev_private;
1232 struct amdgpu_fpriv *fpriv = filp->driver_priv;
1233 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1234 struct amdgpu_ring *ring = NULL;
1235 struct amdgpu_ctx *ctx;
1236 struct dma_fence *fence;
1237 long r;
1238
1239 if (amdgpu_kms_vram_lost(adev, fpriv))
1240 return -ENODEV;
1241
1242 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1243 if (ctx == NULL)
1244 return -EINVAL;
1245
1246 r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr,
1247 wait->in.ip_type, wait->in.ip_instance,
1248 wait->in.ring, &ring);
1249 if (r) {
1250 amdgpu_ctx_put(ctx);
1251 return r;
1252 }
1253
1254 fence = amdgpu_ctx_get_fence(ctx, ring, wait->in.handle);
1255 if (IS_ERR(fence))
1256 r = PTR_ERR(fence);
1257 else if (fence) {
1258 r = dma_fence_wait_timeout(fence, true, timeout);
1259 dma_fence_put(fence);
1260 } else
1261 r = 1;
1262
1263 amdgpu_ctx_put(ctx);
1264 if (r < 0)
1265 return r;
1266
1267 memset(wait, 0, sizeof(*wait));
1268 wait->out.status = (r == 0);
1269
1270 return 0;
1271 }
1272
1273 /**
1274 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1275 *
1276 * @adev: amdgpu device
1277 * @filp: file private
1278 * @user: drm_amdgpu_fence copied from user space
1279 */
1280 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1281 struct drm_file *filp,
1282 struct drm_amdgpu_fence *user)
1283 {
1284 struct amdgpu_ring *ring;
1285 struct amdgpu_ctx *ctx;
1286 struct dma_fence *fence;
1287 int r;
1288
1289 ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1290 if (ctx == NULL)
1291 return ERR_PTR(-EINVAL);
1292
1293 r = amdgpu_queue_mgr_map(adev, &ctx->queue_mgr, user->ip_type,
1294 user->ip_instance, user->ring, &ring);
1295 if (r) {
1296 amdgpu_ctx_put(ctx);
1297 return ERR_PTR(r);
1298 }
1299
1300 fence = amdgpu_ctx_get_fence(ctx, ring, user->seq_no);
1301 amdgpu_ctx_put(ctx);
1302
1303 return fence;
1304 }
1305
1306 /**
1307 * amdgpu_cs_wait_all_fence - wait on all fences to signal
1308 *
1309 * @adev: amdgpu device
1310 * @filp: file private
1311 * @wait: wait parameters
1312 * @fences: array of drm_amdgpu_fence
1313 */
1314 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1315 struct drm_file *filp,
1316 union drm_amdgpu_wait_fences *wait,
1317 struct drm_amdgpu_fence *fences)
1318 {
1319 uint32_t fence_count = wait->in.fence_count;
1320 unsigned int i;
1321 long r = 1;
1322
1323 for (i = 0; i < fence_count; i++) {
1324 struct dma_fence *fence;
1325 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1326
1327 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1328 if (IS_ERR(fence))
1329 return PTR_ERR(fence);
1330 else if (!fence)
1331 continue;
1332
1333 r = dma_fence_wait_timeout(fence, true, timeout);
1334 dma_fence_put(fence);
1335 if (r < 0)
1336 return r;
1337
1338 if (r == 0)
1339 break;
1340 }
1341
1342 memset(wait, 0, sizeof(*wait));
1343 wait->out.status = (r > 0);
1344
1345 return 0;
1346 }
1347
1348 /**
1349 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1350 *
1351 * @adev: amdgpu device
1352 * @filp: file private
1353 * @wait: wait parameters
1354 * @fences: array of drm_amdgpu_fence
1355 */
1356 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1357 struct drm_file *filp,
1358 union drm_amdgpu_wait_fences *wait,
1359 struct drm_amdgpu_fence *fences)
1360 {
1361 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1362 uint32_t fence_count = wait->in.fence_count;
1363 uint32_t first = ~0;
1364 struct dma_fence **array;
1365 unsigned int i;
1366 long r;
1367
1368 /* Prepare the fence array */
1369 array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1370
1371 if (array == NULL)
1372 return -ENOMEM;
1373
1374 for (i = 0; i < fence_count; i++) {
1375 struct dma_fence *fence;
1376
1377 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1378 if (IS_ERR(fence)) {
1379 r = PTR_ERR(fence);
1380 goto err_free_fence_array;
1381 } else if (fence) {
1382 array[i] = fence;
1383 } else { /* NULL, the fence has been already signaled */
1384 r = 1;
1385 first = i;
1386 goto out;
1387 }
1388 }
1389
1390 r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1391 &first);
1392 if (r < 0)
1393 goto err_free_fence_array;
1394
1395 out:
1396 memset(wait, 0, sizeof(*wait));
1397 wait->out.status = (r > 0);
1398 wait->out.first_signaled = first;
1399 /* set return value 0 to indicate success */
1400 r = 0;
1401
1402 err_free_fence_array:
1403 for (i = 0; i < fence_count; i++)
1404 dma_fence_put(array[i]);
1405 kfree(array);
1406
1407 return r;
1408 }
1409
1410 /**
1411 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1412 *
1413 * @dev: drm device
1414 * @data: data from userspace
1415 * @filp: file private
1416 */
1417 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1418 struct drm_file *filp)
1419 {
1420 struct amdgpu_device *adev = dev->dev_private;
1421 struct amdgpu_fpriv *fpriv = filp->driver_priv;
1422 union drm_amdgpu_wait_fences *wait = data;
1423 uint32_t fence_count = wait->in.fence_count;
1424 struct drm_amdgpu_fence *fences_user;
1425 struct drm_amdgpu_fence *fences;
1426 int r;
1427
1428 if (amdgpu_kms_vram_lost(adev, fpriv))
1429 return -ENODEV;
1430 /* Get the fences from userspace */
1431 fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1432 GFP_KERNEL);
1433 if (fences == NULL)
1434 return -ENOMEM;
1435
1436 fences_user = u64_to_user_ptr(wait->in.fences);
1437 if (copy_from_user(fences, fences_user,
1438 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1439 r = -EFAULT;
1440 goto err_free_fences;
1441 }
1442
1443 if (wait->in.wait_all)
1444 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1445 else
1446 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1447
1448 err_free_fences:
1449 kfree(fences);
1450
1451 return r;
1452 }
1453
1454 /**
1455 * amdgpu_cs_find_bo_va - find bo_va for VM address
1456 *
1457 * @parser: command submission parser context
1458 * @addr: VM address
1459 * @bo: resulting BO of the mapping found
1460 *
1461 * Search the buffer objects in the command submission context for a certain
1462 * virtual memory address. Returns allocation structure when found, NULL
1463 * otherwise.
1464 */
1465 struct amdgpu_bo_va_mapping *
1466 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1467 uint64_t addr, struct amdgpu_bo **bo)
1468 {
1469 struct amdgpu_bo_va_mapping *mapping;
1470 unsigned i;
1471
1472 if (!parser->bo_list)
1473 return NULL;
1474
1475 addr /= AMDGPU_GPU_PAGE_SIZE;
1476
1477 for (i = 0; i < parser->bo_list->num_entries; i++) {
1478 struct amdgpu_bo_list_entry *lobj;
1479
1480 lobj = &parser->bo_list->array[i];
1481 if (!lobj->bo_va)
1482 continue;
1483
1484 list_for_each_entry(mapping, &lobj->bo_va->valids, list) {
1485 if (mapping->start > addr ||
1486 addr > mapping->last)
1487 continue;
1488
1489 *bo = lobj->bo_va->base.bo;
1490 return mapping;
1491 }
1492
1493 list_for_each_entry(mapping, &lobj->bo_va->invalids, list) {
1494 if (mapping->start > addr ||
1495 addr > mapping->last)
1496 continue;
1497
1498 *bo = lobj->bo_va->base.bo;
1499 return mapping;
1500 }
1501 }
1502
1503 return NULL;
1504 }
1505
1506 /**
1507 * amdgpu_cs_sysvm_access_required - make BOs accessible by the system VM
1508 *
1509 * @parser: command submission parser context
1510 *
1511 * Helper for UVD/VCE VM emulation, make sure BOs are accessible by the system VM.
1512 */
1513 int amdgpu_cs_sysvm_access_required(struct amdgpu_cs_parser *parser)
1514 {
1515 unsigned i;
1516 int r;
1517
1518 if (!parser->bo_list)
1519 return 0;
1520
1521 for (i = 0; i < parser->bo_list->num_entries; i++) {
1522 struct amdgpu_bo *bo = parser->bo_list->array[i].robj;
1523
1524 r = amdgpu_ttm_bind(&bo->tbo, &bo->tbo.mem);
1525 if (unlikely(r))
1526 return r;
1527
1528 if (bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
1529 continue;
1530
1531 bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1532 amdgpu_ttm_placement_from_domain(bo, bo->allowed_domains);
1533 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
1534 if (unlikely(r))
1535 return r;
1536 }
1537
1538 return 0;
1539 }
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