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Merge branches 'acpi-pci', 'acpi-power' and 'acpi-misc'
[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / amd / amdgpu / amdgpu_cs.c
1 /*
2 * Copyright 2008 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Jerome Glisse <glisse@freedesktop.org>
26 */
27 #include <linux/pagemap.h>
28 #include <linux/sync_file.h>
29 #include <drm/drmP.h>
30 #include <drm/amdgpu_drm.h>
31 #include <drm/drm_syncobj.h>
32 #include "amdgpu.h"
33 #include "amdgpu_trace.h"
34 #include "amdgpu_gmc.h"
35 #include "amdgpu_gem.h"
36
37 static int amdgpu_cs_user_fence_chunk(struct amdgpu_cs_parser *p,
38 struct drm_amdgpu_cs_chunk_fence *data,
39 uint32_t *offset)
40 {
41 struct drm_gem_object *gobj;
42 struct amdgpu_bo *bo;
43 unsigned long size;
44 int r;
45
46 gobj = drm_gem_object_lookup(p->filp, data->handle);
47 if (gobj == NULL)
48 return -EINVAL;
49
50 bo = amdgpu_bo_ref(gem_to_amdgpu_bo(gobj));
51 p->uf_entry.priority = 0;
52 p->uf_entry.tv.bo = &bo->tbo;
53 /* One for TTM and one for the CS job */
54 p->uf_entry.tv.num_shared = 2;
55 p->uf_entry.user_pages = NULL;
56
57 drm_gem_object_put_unlocked(gobj);
58
59 size = amdgpu_bo_size(bo);
60 if (size != PAGE_SIZE || (data->offset + 8) > size) {
61 r = -EINVAL;
62 goto error_unref;
63 }
64
65 if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
66 r = -EINVAL;
67 goto error_unref;
68 }
69
70 *offset = data->offset;
71
72 return 0;
73
74 error_unref:
75 amdgpu_bo_unref(&bo);
76 return r;
77 }
78
79 static int amdgpu_cs_bo_handles_chunk(struct amdgpu_cs_parser *p,
80 struct drm_amdgpu_bo_list_in *data)
81 {
82 int r;
83 struct drm_amdgpu_bo_list_entry *info = NULL;
84
85 r = amdgpu_bo_create_list_entry_array(data, &info);
86 if (r)
87 return r;
88
89 r = amdgpu_bo_list_create(p->adev, p->filp, info, data->bo_number,
90 &p->bo_list);
91 if (r)
92 goto error_free;
93
94 kvfree(info);
95 return 0;
96
97 error_free:
98 if (info)
99 kvfree(info);
100
101 return r;
102 }
103
104 static int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, union drm_amdgpu_cs *cs)
105 {
106 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
107 struct amdgpu_vm *vm = &fpriv->vm;
108 uint64_t *chunk_array_user;
109 uint64_t *chunk_array;
110 unsigned size, num_ibs = 0;
111 uint32_t uf_offset = 0;
112 int i;
113 int ret;
114
115 if (cs->in.num_chunks == 0)
116 return 0;
117
118 chunk_array = kmalloc_array(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
119 if (!chunk_array)
120 return -ENOMEM;
121
122 p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
123 if (!p->ctx) {
124 ret = -EINVAL;
125 goto free_chunk;
126 }
127
128 mutex_lock(&p->ctx->lock);
129
130 /* skip guilty context job */
131 if (atomic_read(&p->ctx->guilty) == 1) {
132 ret = -ECANCELED;
133 goto free_chunk;
134 }
135
136 /* get chunks */
137 chunk_array_user = u64_to_user_ptr(cs->in.chunks);
138 if (copy_from_user(chunk_array, chunk_array_user,
139 sizeof(uint64_t)*cs->in.num_chunks)) {
140 ret = -EFAULT;
141 goto free_chunk;
142 }
143
144 p->nchunks = cs->in.num_chunks;
145 p->chunks = kmalloc_array(p->nchunks, sizeof(struct amdgpu_cs_chunk),
146 GFP_KERNEL);
147 if (!p->chunks) {
148 ret = -ENOMEM;
149 goto free_chunk;
150 }
151
152 for (i = 0; i < p->nchunks; i++) {
153 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
154 struct drm_amdgpu_cs_chunk user_chunk;
155 uint32_t __user *cdata;
156
157 chunk_ptr = u64_to_user_ptr(chunk_array[i]);
158 if (copy_from_user(&user_chunk, chunk_ptr,
159 sizeof(struct drm_amdgpu_cs_chunk))) {
160 ret = -EFAULT;
161 i--;
162 goto free_partial_kdata;
163 }
164 p->chunks[i].chunk_id = user_chunk.chunk_id;
165 p->chunks[i].length_dw = user_chunk.length_dw;
166
167 size = p->chunks[i].length_dw;
168 cdata = u64_to_user_ptr(user_chunk.chunk_data);
169
170 p->chunks[i].kdata = kvmalloc_array(size, sizeof(uint32_t), GFP_KERNEL);
171 if (p->chunks[i].kdata == NULL) {
172 ret = -ENOMEM;
173 i--;
174 goto free_partial_kdata;
175 }
176 size *= sizeof(uint32_t);
177 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
178 ret = -EFAULT;
179 goto free_partial_kdata;
180 }
181
182 switch (p->chunks[i].chunk_id) {
183 case AMDGPU_CHUNK_ID_IB:
184 ++num_ibs;
185 break;
186
187 case AMDGPU_CHUNK_ID_FENCE:
188 size = sizeof(struct drm_amdgpu_cs_chunk_fence);
189 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
190 ret = -EINVAL;
191 goto free_partial_kdata;
192 }
193
194 ret = amdgpu_cs_user_fence_chunk(p, p->chunks[i].kdata,
195 &uf_offset);
196 if (ret)
197 goto free_partial_kdata;
198
199 break;
200
201 case AMDGPU_CHUNK_ID_BO_HANDLES:
202 size = sizeof(struct drm_amdgpu_bo_list_in);
203 if (p->chunks[i].length_dw * sizeof(uint32_t) < size) {
204 ret = -EINVAL;
205 goto free_partial_kdata;
206 }
207
208 ret = amdgpu_cs_bo_handles_chunk(p, p->chunks[i].kdata);
209 if (ret)
210 goto free_partial_kdata;
211
212 break;
213
214 case AMDGPU_CHUNK_ID_DEPENDENCIES:
215 case AMDGPU_CHUNK_ID_SYNCOBJ_IN:
216 case AMDGPU_CHUNK_ID_SYNCOBJ_OUT:
217 break;
218
219 default:
220 ret = -EINVAL;
221 goto free_partial_kdata;
222 }
223 }
224
225 ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
226 if (ret)
227 goto free_all_kdata;
228
229 if (p->ctx->vram_lost_counter != p->job->vram_lost_counter) {
230 ret = -ECANCELED;
231 goto free_all_kdata;
232 }
233
234 if (p->uf_entry.tv.bo)
235 p->job->uf_addr = uf_offset;
236 kfree(chunk_array);
237
238 /* Use this opportunity to fill in task info for the vm */
239 amdgpu_vm_set_task_info(vm);
240
241 return 0;
242
243 free_all_kdata:
244 i = p->nchunks - 1;
245 free_partial_kdata:
246 for (; i >= 0; i--)
247 kvfree(p->chunks[i].kdata);
248 kfree(p->chunks);
249 p->chunks = NULL;
250 p->nchunks = 0;
251 free_chunk:
252 kfree(chunk_array);
253
254 return ret;
255 }
256
257 /* Convert microseconds to bytes. */
258 static u64 us_to_bytes(struct amdgpu_device *adev, s64 us)
259 {
260 if (us <= 0 || !adev->mm_stats.log2_max_MBps)
261 return 0;
262
263 /* Since accum_us is incremented by a million per second, just
264 * multiply it by the number of MB/s to get the number of bytes.
265 */
266 return us << adev->mm_stats.log2_max_MBps;
267 }
268
269 static s64 bytes_to_us(struct amdgpu_device *adev, u64 bytes)
270 {
271 if (!adev->mm_stats.log2_max_MBps)
272 return 0;
273
274 return bytes >> adev->mm_stats.log2_max_MBps;
275 }
276
277 /* Returns how many bytes TTM can move right now. If no bytes can be moved,
278 * it returns 0. If it returns non-zero, it's OK to move at least one buffer,
279 * which means it can go over the threshold once. If that happens, the driver
280 * will be in debt and no other buffer migrations can be done until that debt
281 * is repaid.
282 *
283 * This approach allows moving a buffer of any size (it's important to allow
284 * that).
285 *
286 * The currency is simply time in microseconds and it increases as the clock
287 * ticks. The accumulated microseconds (us) are converted to bytes and
288 * returned.
289 */
290 static void amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev,
291 u64 *max_bytes,
292 u64 *max_vis_bytes)
293 {
294 s64 time_us, increment_us;
295 u64 free_vram, total_vram, used_vram;
296
297 /* Allow a maximum of 200 accumulated ms. This is basically per-IB
298 * throttling.
299 *
300 * It means that in order to get full max MBps, at least 5 IBs per
301 * second must be submitted and not more than 200ms apart from each
302 * other.
303 */
304 const s64 us_upper_bound = 200000;
305
306 if (!adev->mm_stats.log2_max_MBps) {
307 *max_bytes = 0;
308 *max_vis_bytes = 0;
309 return;
310 }
311
312 total_vram = adev->gmc.real_vram_size - atomic64_read(&adev->vram_pin_size);
313 used_vram = amdgpu_vram_mgr_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
314 free_vram = used_vram >= total_vram ? 0 : total_vram - used_vram;
315
316 spin_lock(&adev->mm_stats.lock);
317
318 /* Increase the amount of accumulated us. */
319 time_us = ktime_to_us(ktime_get());
320 increment_us = time_us - adev->mm_stats.last_update_us;
321 adev->mm_stats.last_update_us = time_us;
322 adev->mm_stats.accum_us = min(adev->mm_stats.accum_us + increment_us,
323 us_upper_bound);
324
325 /* This prevents the short period of low performance when the VRAM
326 * usage is low and the driver is in debt or doesn't have enough
327 * accumulated us to fill VRAM quickly.
328 *
329 * The situation can occur in these cases:
330 * - a lot of VRAM is freed by userspace
331 * - the presence of a big buffer causes a lot of evictions
332 * (solution: split buffers into smaller ones)
333 *
334 * If 128 MB or 1/8th of VRAM is free, start filling it now by setting
335 * accum_us to a positive number.
336 */
337 if (free_vram >= 128 * 1024 * 1024 || free_vram >= total_vram / 8) {
338 s64 min_us;
339
340 /* Be more aggresive on dGPUs. Try to fill a portion of free
341 * VRAM now.
342 */
343 if (!(adev->flags & AMD_IS_APU))
344 min_us = bytes_to_us(adev, free_vram / 4);
345 else
346 min_us = 0; /* Reset accum_us on APUs. */
347
348 adev->mm_stats.accum_us = max(min_us, adev->mm_stats.accum_us);
349 }
350
351 /* This is set to 0 if the driver is in debt to disallow (optional)
352 * buffer moves.
353 */
354 *max_bytes = us_to_bytes(adev, adev->mm_stats.accum_us);
355
356 /* Do the same for visible VRAM if half of it is free */
357 if (!amdgpu_gmc_vram_full_visible(&adev->gmc)) {
358 u64 total_vis_vram = adev->gmc.visible_vram_size;
359 u64 used_vis_vram =
360 amdgpu_vram_mgr_vis_usage(&adev->mman.bdev.man[TTM_PL_VRAM]);
361
362 if (used_vis_vram < total_vis_vram) {
363 u64 free_vis_vram = total_vis_vram - used_vis_vram;
364 adev->mm_stats.accum_us_vis = min(adev->mm_stats.accum_us_vis +
365 increment_us, us_upper_bound);
366
367 if (free_vis_vram >= total_vis_vram / 2)
368 adev->mm_stats.accum_us_vis =
369 max(bytes_to_us(adev, free_vis_vram / 2),
370 adev->mm_stats.accum_us_vis);
371 }
372
373 *max_vis_bytes = us_to_bytes(adev, adev->mm_stats.accum_us_vis);
374 } else {
375 *max_vis_bytes = 0;
376 }
377
378 spin_unlock(&adev->mm_stats.lock);
379 }
380
381 /* Report how many bytes have really been moved for the last command
382 * submission. This can result in a debt that can stop buffer migrations
383 * temporarily.
384 */
385 void amdgpu_cs_report_moved_bytes(struct amdgpu_device *adev, u64 num_bytes,
386 u64 num_vis_bytes)
387 {
388 spin_lock(&adev->mm_stats.lock);
389 adev->mm_stats.accum_us -= bytes_to_us(adev, num_bytes);
390 adev->mm_stats.accum_us_vis -= bytes_to_us(adev, num_vis_bytes);
391 spin_unlock(&adev->mm_stats.lock);
392 }
393
394 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p,
395 struct amdgpu_bo *bo)
396 {
397 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
398 struct ttm_operation_ctx ctx = {
399 .interruptible = true,
400 .no_wait_gpu = false,
401 .resv = bo->tbo.resv,
402 .flags = 0
403 };
404 uint32_t domain;
405 int r;
406
407 if (bo->pin_count)
408 return 0;
409
410 /* Don't move this buffer if we have depleted our allowance
411 * to move it. Don't move anything if the threshold is zero.
412 */
413 if (p->bytes_moved < p->bytes_moved_threshold) {
414 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
415 (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
416 /* And don't move a CPU_ACCESS_REQUIRED BO to limited
417 * visible VRAM if we've depleted our allowance to do
418 * that.
419 */
420 if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
421 domain = bo->preferred_domains;
422 else
423 domain = bo->allowed_domains;
424 } else {
425 domain = bo->preferred_domains;
426 }
427 } else {
428 domain = bo->allowed_domains;
429 }
430
431 retry:
432 amdgpu_bo_placement_from_domain(bo, domain);
433 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
434
435 p->bytes_moved += ctx.bytes_moved;
436 if (!amdgpu_gmc_vram_full_visible(&adev->gmc) &&
437 amdgpu_bo_in_cpu_visible_vram(bo))
438 p->bytes_moved_vis += ctx.bytes_moved;
439
440 if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
441 domain = bo->allowed_domains;
442 goto retry;
443 }
444
445 return r;
446 }
447
448 /* Last resort, try to evict something from the current working set */
449 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p,
450 struct amdgpu_bo *validated)
451 {
452 uint32_t domain = validated->allowed_domains;
453 struct ttm_operation_ctx ctx = { true, false };
454 int r;
455
456 if (!p->evictable)
457 return false;
458
459 for (;&p->evictable->tv.head != &p->validated;
460 p->evictable = list_prev_entry(p->evictable, tv.head)) {
461
462 struct amdgpu_bo_list_entry *candidate = p->evictable;
463 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(candidate->tv.bo);
464 struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
465 bool update_bytes_moved_vis;
466 uint32_t other;
467
468 /* If we reached our current BO we can forget it */
469 if (bo == validated)
470 break;
471
472 /* We can't move pinned BOs here */
473 if (bo->pin_count)
474 continue;
475
476 other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
477
478 /* Check if this BO is in one of the domains we need space for */
479 if (!(other & domain))
480 continue;
481
482 /* Check if we can move this BO somewhere else */
483 other = bo->allowed_domains & ~domain;
484 if (!other)
485 continue;
486
487 /* Good we can try to move this BO somewhere else */
488 update_bytes_moved_vis =
489 !amdgpu_gmc_vram_full_visible(&adev->gmc) &&
490 amdgpu_bo_in_cpu_visible_vram(bo);
491 amdgpu_bo_placement_from_domain(bo, other);
492 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
493 p->bytes_moved += ctx.bytes_moved;
494 if (update_bytes_moved_vis)
495 p->bytes_moved_vis += ctx.bytes_moved;
496
497 if (unlikely(r))
498 break;
499
500 p->evictable = list_prev_entry(p->evictable, tv.head);
501 list_move(&candidate->tv.head, &p->validated);
502
503 return true;
504 }
505
506 return false;
507 }
508
509 static int amdgpu_cs_validate(void *param, struct amdgpu_bo *bo)
510 {
511 struct amdgpu_cs_parser *p = param;
512 int r;
513
514 do {
515 r = amdgpu_cs_bo_validate(p, bo);
516 } while (r == -ENOMEM && amdgpu_cs_try_evict(p, bo));
517 if (r)
518 return r;
519
520 if (bo->shadow)
521 r = amdgpu_cs_bo_validate(p, bo->shadow);
522
523 return r;
524 }
525
526 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p,
527 struct list_head *validated)
528 {
529 struct ttm_operation_ctx ctx = { true, false };
530 struct amdgpu_bo_list_entry *lobj;
531 int r;
532
533 list_for_each_entry(lobj, validated, tv.head) {
534 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(lobj->tv.bo);
535 bool binding_userptr = false;
536 struct mm_struct *usermm;
537
538 usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
539 if (usermm && usermm != current->mm)
540 return -EPERM;
541
542 /* Check if we have user pages and nobody bound the BO already */
543 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
544 lobj->user_pages) {
545 amdgpu_bo_placement_from_domain(bo,
546 AMDGPU_GEM_DOMAIN_CPU);
547 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
548 if (r)
549 return r;
550 amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm,
551 lobj->user_pages);
552 binding_userptr = true;
553 }
554
555 if (p->evictable == lobj)
556 p->evictable = NULL;
557
558 r = amdgpu_cs_validate(p, bo);
559 if (r)
560 return r;
561
562 if (binding_userptr) {
563 kvfree(lobj->user_pages);
564 lobj->user_pages = NULL;
565 }
566 }
567 return 0;
568 }
569
570 static int amdgpu_cs_parser_bos(struct amdgpu_cs_parser *p,
571 union drm_amdgpu_cs *cs)
572 {
573 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
574 struct amdgpu_vm *vm = &fpriv->vm;
575 struct amdgpu_bo_list_entry *e;
576 struct list_head duplicates;
577 struct amdgpu_bo *gds;
578 struct amdgpu_bo *gws;
579 struct amdgpu_bo *oa;
580 unsigned tries = 10;
581 int r;
582
583 INIT_LIST_HEAD(&p->validated);
584
585 /* p->bo_list could already be assigned if AMDGPU_CHUNK_ID_BO_HANDLES is present */
586 if (cs->in.bo_list_handle) {
587 if (p->bo_list)
588 return -EINVAL;
589
590 r = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle,
591 &p->bo_list);
592 if (r)
593 return r;
594 } else if (!p->bo_list) {
595 /* Create a empty bo_list when no handle is provided */
596 r = amdgpu_bo_list_create(p->adev, p->filp, NULL, 0,
597 &p->bo_list);
598 if (r)
599 return r;
600 }
601
602 /* One for TTM and one for the CS job */
603 amdgpu_bo_list_for_each_entry(e, p->bo_list)
604 e->tv.num_shared = 2;
605
606 amdgpu_bo_list_get_list(p->bo_list, &p->validated);
607 if (p->bo_list->first_userptr != p->bo_list->num_entries)
608 p->mn = amdgpu_mn_get(p->adev, AMDGPU_MN_TYPE_GFX);
609
610 INIT_LIST_HEAD(&duplicates);
611 amdgpu_vm_get_pd_bo(&fpriv->vm, &p->validated, &p->vm_pd);
612
613 if (p->uf_entry.tv.bo && !ttm_to_amdgpu_bo(p->uf_entry.tv.bo)->parent)
614 list_add(&p->uf_entry.tv.head, &p->validated);
615
616 while (1) {
617 struct list_head need_pages;
618
619 r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true,
620 &duplicates);
621 if (unlikely(r != 0)) {
622 if (r != -ERESTARTSYS)
623 DRM_ERROR("ttm_eu_reserve_buffers failed.\n");
624 goto error_free_pages;
625 }
626
627 INIT_LIST_HEAD(&need_pages);
628 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
629 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
630
631 if (amdgpu_ttm_tt_userptr_invalidated(bo->tbo.ttm,
632 &e->user_invalidated) && e->user_pages) {
633
634 /* We acquired a page array, but somebody
635 * invalidated it. Free it and try again
636 */
637 release_pages(e->user_pages,
638 bo->tbo.ttm->num_pages);
639 kvfree(e->user_pages);
640 e->user_pages = NULL;
641 }
642
643 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) &&
644 !e->user_pages) {
645 list_del(&e->tv.head);
646 list_add(&e->tv.head, &need_pages);
647
648 amdgpu_bo_unreserve(bo);
649 }
650 }
651
652 if (list_empty(&need_pages))
653 break;
654
655 /* Unreserve everything again. */
656 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
657
658 /* We tried too many times, just abort */
659 if (!--tries) {
660 r = -EDEADLK;
661 DRM_ERROR("deadlock in %s\n", __func__);
662 goto error_free_pages;
663 }
664
665 /* Fill the page arrays for all userptrs. */
666 list_for_each_entry(e, &need_pages, tv.head) {
667 struct ttm_tt *ttm = e->tv.bo->ttm;
668
669 e->user_pages = kvmalloc_array(ttm->num_pages,
670 sizeof(struct page*),
671 GFP_KERNEL | __GFP_ZERO);
672 if (!e->user_pages) {
673 r = -ENOMEM;
674 DRM_ERROR("calloc failure in %s\n", __func__);
675 goto error_free_pages;
676 }
677
678 r = amdgpu_ttm_tt_get_user_pages(ttm, e->user_pages);
679 if (r) {
680 DRM_ERROR("amdgpu_ttm_tt_get_user_pages failed.\n");
681 kvfree(e->user_pages);
682 e->user_pages = NULL;
683 goto error_free_pages;
684 }
685 }
686
687 /* And try again. */
688 list_splice(&need_pages, &p->validated);
689 }
690
691 amdgpu_cs_get_threshold_for_moves(p->adev, &p->bytes_moved_threshold,
692 &p->bytes_moved_vis_threshold);
693 p->bytes_moved = 0;
694 p->bytes_moved_vis = 0;
695 p->evictable = list_last_entry(&p->validated,
696 struct amdgpu_bo_list_entry,
697 tv.head);
698
699 r = amdgpu_vm_validate_pt_bos(p->adev, &fpriv->vm,
700 amdgpu_cs_validate, p);
701 if (r) {
702 DRM_ERROR("amdgpu_vm_validate_pt_bos() failed.\n");
703 goto error_validate;
704 }
705
706 r = amdgpu_cs_list_validate(p, &duplicates);
707 if (r) {
708 DRM_ERROR("amdgpu_cs_list_validate(duplicates) failed.\n");
709 goto error_validate;
710 }
711
712 r = amdgpu_cs_list_validate(p, &p->validated);
713 if (r) {
714 DRM_ERROR("amdgpu_cs_list_validate(validated) failed.\n");
715 goto error_validate;
716 }
717
718 amdgpu_cs_report_moved_bytes(p->adev, p->bytes_moved,
719 p->bytes_moved_vis);
720
721 gds = p->bo_list->gds_obj;
722 gws = p->bo_list->gws_obj;
723 oa = p->bo_list->oa_obj;
724
725 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
726 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
727
728 /* Make sure we use the exclusive slot for shared BOs */
729 if (bo->prime_shared_count)
730 e->tv.num_shared = 0;
731 e->bo_va = amdgpu_vm_bo_find(vm, bo);
732 }
733
734 if (gds) {
735 p->job->gds_base = amdgpu_bo_gpu_offset(gds) >> PAGE_SHIFT;
736 p->job->gds_size = amdgpu_bo_size(gds) >> PAGE_SHIFT;
737 }
738 if (gws) {
739 p->job->gws_base = amdgpu_bo_gpu_offset(gws) >> PAGE_SHIFT;
740 p->job->gws_size = amdgpu_bo_size(gws) >> PAGE_SHIFT;
741 }
742 if (oa) {
743 p->job->oa_base = amdgpu_bo_gpu_offset(oa) >> PAGE_SHIFT;
744 p->job->oa_size = amdgpu_bo_size(oa) >> PAGE_SHIFT;
745 }
746
747 if (!r && p->uf_entry.tv.bo) {
748 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(p->uf_entry.tv.bo);
749
750 r = amdgpu_ttm_alloc_gart(&uf->tbo);
751 p->job->uf_addr += amdgpu_bo_gpu_offset(uf);
752 }
753
754 error_validate:
755 if (r)
756 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
757
758 error_free_pages:
759
760 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
761 if (!e->user_pages)
762 continue;
763
764 release_pages(e->user_pages, e->tv.bo->ttm->num_pages);
765 kvfree(e->user_pages);
766 }
767
768 return r;
769 }
770
771 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
772 {
773 struct amdgpu_bo_list_entry *e;
774 int r;
775
776 list_for_each_entry(e, &p->validated, tv.head) {
777 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
778 struct reservation_object *resv = bo->tbo.resv;
779
780 r = amdgpu_sync_resv(p->adev, &p->job->sync, resv, p->filp,
781 amdgpu_bo_explicit_sync(bo));
782
783 if (r)
784 return r;
785 }
786 return 0;
787 }
788
789 /**
790 * cs_parser_fini() - clean parser states
791 * @parser: parser structure holding parsing context.
792 * @error: error number
793 *
794 * If error is set than unvalidate buffer, otherwise just free memory
795 * used by parsing context.
796 **/
797 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
798 bool backoff)
799 {
800 unsigned i;
801
802 if (error && backoff)
803 ttm_eu_backoff_reservation(&parser->ticket,
804 &parser->validated);
805
806 for (i = 0; i < parser->num_post_dep_syncobjs; i++)
807 drm_syncobj_put(parser->post_dep_syncobjs[i]);
808 kfree(parser->post_dep_syncobjs);
809
810 dma_fence_put(parser->fence);
811
812 if (parser->ctx) {
813 mutex_unlock(&parser->ctx->lock);
814 amdgpu_ctx_put(parser->ctx);
815 }
816 if (parser->bo_list)
817 amdgpu_bo_list_put(parser->bo_list);
818
819 for (i = 0; i < parser->nchunks; i++)
820 kvfree(parser->chunks[i].kdata);
821 kfree(parser->chunks);
822 if (parser->job)
823 amdgpu_job_free(parser->job);
824 if (parser->uf_entry.tv.bo) {
825 struct amdgpu_bo *uf = ttm_to_amdgpu_bo(parser->uf_entry.tv.bo);
826
827 amdgpu_bo_unref(&uf);
828 }
829 }
830
831 static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
832 {
833 struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
834 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
835 struct amdgpu_device *adev = p->adev;
836 struct amdgpu_vm *vm = &fpriv->vm;
837 struct amdgpu_bo_list_entry *e;
838 struct amdgpu_bo_va *bo_va;
839 struct amdgpu_bo *bo;
840 int r;
841
842 /* Only for UVD/VCE VM emulation */
843 if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
844 unsigned i, j;
845
846 for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
847 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
848 struct amdgpu_bo_va_mapping *m;
849 struct amdgpu_bo *aobj = NULL;
850 struct amdgpu_cs_chunk *chunk;
851 uint64_t offset, va_start;
852 struct amdgpu_ib *ib;
853 uint8_t *kptr;
854
855 chunk = &p->chunks[i];
856 ib = &p->job->ibs[j];
857 chunk_ib = chunk->kdata;
858
859 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
860 continue;
861
862 va_start = chunk_ib->va_start & AMDGPU_GMC_HOLE_MASK;
863 r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
864 if (r) {
865 DRM_ERROR("IB va_start is invalid\n");
866 return r;
867 }
868
869 if ((va_start + chunk_ib->ib_bytes) >
870 (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
871 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
872 return -EINVAL;
873 }
874
875 /* the IB should be reserved at this point */
876 r = amdgpu_bo_kmap(aobj, (void **)&kptr);
877 if (r) {
878 return r;
879 }
880
881 offset = m->start * AMDGPU_GPU_PAGE_SIZE;
882 kptr += va_start - offset;
883
884 if (ring->funcs->parse_cs) {
885 memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
886 amdgpu_bo_kunmap(aobj);
887
888 r = amdgpu_ring_parse_cs(ring, p, j);
889 if (r)
890 return r;
891 } else {
892 ib->ptr = (uint32_t *)kptr;
893 r = amdgpu_ring_patch_cs_in_place(ring, p, j);
894 amdgpu_bo_kunmap(aobj);
895 if (r)
896 return r;
897 }
898
899 j++;
900 }
901 }
902
903 if (!p->job->vm)
904 return amdgpu_cs_sync_rings(p);
905
906
907 r = amdgpu_vm_clear_freed(adev, vm, NULL);
908 if (r)
909 return r;
910
911 r = amdgpu_vm_bo_update(adev, fpriv->prt_va, false);
912 if (r)
913 return r;
914
915 r = amdgpu_sync_fence(adev, &p->job->sync,
916 fpriv->prt_va->last_pt_update, false);
917 if (r)
918 return r;
919
920 if (amdgpu_sriov_vf(adev)) {
921 struct dma_fence *f;
922
923 bo_va = fpriv->csa_va;
924 BUG_ON(!bo_va);
925 r = amdgpu_vm_bo_update(adev, bo_va, false);
926 if (r)
927 return r;
928
929 f = bo_va->last_pt_update;
930 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
931 if (r)
932 return r;
933 }
934
935 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
936 struct dma_fence *f;
937
938 /* ignore duplicates */
939 bo = ttm_to_amdgpu_bo(e->tv.bo);
940 if (!bo)
941 continue;
942
943 bo_va = e->bo_va;
944 if (bo_va == NULL)
945 continue;
946
947 r = amdgpu_vm_bo_update(adev, bo_va, false);
948 if (r)
949 return r;
950
951 f = bo_va->last_pt_update;
952 r = amdgpu_sync_fence(adev, &p->job->sync, f, false);
953 if (r)
954 return r;
955 }
956
957 r = amdgpu_vm_handle_moved(adev, vm);
958 if (r)
959 return r;
960
961 r = amdgpu_vm_update_directories(adev, vm);
962 if (r)
963 return r;
964
965 r = amdgpu_sync_fence(adev, &p->job->sync, vm->last_update, false);
966 if (r)
967 return r;
968
969 p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
970
971 if (amdgpu_vm_debug) {
972 /* Invalidate all BOs to test for userspace bugs */
973 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
974 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
975
976 /* ignore duplicates */
977 if (!bo)
978 continue;
979
980 amdgpu_vm_bo_invalidate(adev, bo, false);
981 }
982 }
983
984 return amdgpu_cs_sync_rings(p);
985 }
986
987 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
988 struct amdgpu_cs_parser *parser)
989 {
990 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
991 struct amdgpu_vm *vm = &fpriv->vm;
992 int r, ce_preempt = 0, de_preempt = 0;
993 struct amdgpu_ring *ring;
994 int i, j;
995
996 for (i = 0, j = 0; i < parser->nchunks && j < parser->job->num_ibs; i++) {
997 struct amdgpu_cs_chunk *chunk;
998 struct amdgpu_ib *ib;
999 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
1000 struct drm_sched_entity *entity;
1001
1002 chunk = &parser->chunks[i];
1003 ib = &parser->job->ibs[j];
1004 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
1005
1006 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
1007 continue;
1008
1009 if (chunk_ib->ip_type == AMDGPU_HW_IP_GFX && amdgpu_sriov_vf(adev)) {
1010 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREEMPT) {
1011 if (chunk_ib->flags & AMDGPU_IB_FLAG_CE)
1012 ce_preempt++;
1013 else
1014 de_preempt++;
1015 }
1016
1017 /* each GFX command submit allows 0 or 1 IB preemptible for CE & DE */
1018 if (ce_preempt > 1 || de_preempt > 1)
1019 return -EINVAL;
1020 }
1021
1022 r = amdgpu_ctx_get_entity(parser->ctx, chunk_ib->ip_type,
1023 chunk_ib->ip_instance, chunk_ib->ring,
1024 &entity);
1025 if (r)
1026 return r;
1027
1028 if (chunk_ib->flags & AMDGPU_IB_FLAG_PREAMBLE)
1029 parser->job->preamble_status |=
1030 AMDGPU_PREAMBLE_IB_PRESENT;
1031
1032 if (parser->entity && parser->entity != entity)
1033 return -EINVAL;
1034
1035 parser->entity = entity;
1036
1037 ring = to_amdgpu_ring(entity->rq->sched);
1038 r = amdgpu_ib_get(adev, vm, ring->funcs->parse_cs ?
1039 chunk_ib->ib_bytes : 0, ib);
1040 if (r) {
1041 DRM_ERROR("Failed to get ib !\n");
1042 return r;
1043 }
1044
1045 ib->gpu_addr = chunk_ib->va_start;
1046 ib->length_dw = chunk_ib->ib_bytes / 4;
1047 ib->flags = chunk_ib->flags;
1048
1049 j++;
1050 }
1051
1052 /* UVD & VCE fw doesn't support user fences */
1053 ring = to_amdgpu_ring(parser->entity->rq->sched);
1054 if (parser->job->uf_addr && (
1055 ring->funcs->type == AMDGPU_RING_TYPE_UVD ||
1056 ring->funcs->type == AMDGPU_RING_TYPE_VCE))
1057 return -EINVAL;
1058
1059 return amdgpu_ctx_wait_prev_fence(parser->ctx, parser->entity);
1060 }
1061
1062 static int amdgpu_cs_process_fence_dep(struct amdgpu_cs_parser *p,
1063 struct amdgpu_cs_chunk *chunk)
1064 {
1065 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1066 unsigned num_deps;
1067 int i, r;
1068 struct drm_amdgpu_cs_chunk_dep *deps;
1069
1070 deps = (struct drm_amdgpu_cs_chunk_dep *)chunk->kdata;
1071 num_deps = chunk->length_dw * 4 /
1072 sizeof(struct drm_amdgpu_cs_chunk_dep);
1073
1074 for (i = 0; i < num_deps; ++i) {
1075 struct amdgpu_ctx *ctx;
1076 struct drm_sched_entity *entity;
1077 struct dma_fence *fence;
1078
1079 ctx = amdgpu_ctx_get(fpriv, deps[i].ctx_id);
1080 if (ctx == NULL)
1081 return -EINVAL;
1082
1083 r = amdgpu_ctx_get_entity(ctx, deps[i].ip_type,
1084 deps[i].ip_instance,
1085 deps[i].ring, &entity);
1086 if (r) {
1087 amdgpu_ctx_put(ctx);
1088 return r;
1089 }
1090
1091 fence = amdgpu_ctx_get_fence(ctx, entity,
1092 deps[i].handle);
1093 if (IS_ERR(fence)) {
1094 r = PTR_ERR(fence);
1095 amdgpu_ctx_put(ctx);
1096 return r;
1097 } else if (fence) {
1098 r = amdgpu_sync_fence(p->adev, &p->job->sync, fence,
1099 true);
1100 dma_fence_put(fence);
1101 amdgpu_ctx_put(ctx);
1102 if (r)
1103 return r;
1104 }
1105 }
1106 return 0;
1107 }
1108
1109 static int amdgpu_syncobj_lookup_and_add_to_sync(struct amdgpu_cs_parser *p,
1110 uint32_t handle)
1111 {
1112 int r;
1113 struct dma_fence *fence;
1114 r = drm_syncobj_find_fence(p->filp, handle, 0, 0, &fence);
1115 if (r)
1116 return r;
1117
1118 r = amdgpu_sync_fence(p->adev, &p->job->sync, fence, true);
1119 dma_fence_put(fence);
1120
1121 return r;
1122 }
1123
1124 static int amdgpu_cs_process_syncobj_in_dep(struct amdgpu_cs_parser *p,
1125 struct amdgpu_cs_chunk *chunk)
1126 {
1127 unsigned num_deps;
1128 int i, r;
1129 struct drm_amdgpu_cs_chunk_sem *deps;
1130
1131 deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1132 num_deps = chunk->length_dw * 4 /
1133 sizeof(struct drm_amdgpu_cs_chunk_sem);
1134
1135 for (i = 0; i < num_deps; ++i) {
1136 r = amdgpu_syncobj_lookup_and_add_to_sync(p, deps[i].handle);
1137 if (r)
1138 return r;
1139 }
1140 return 0;
1141 }
1142
1143 static int amdgpu_cs_process_syncobj_out_dep(struct amdgpu_cs_parser *p,
1144 struct amdgpu_cs_chunk *chunk)
1145 {
1146 unsigned num_deps;
1147 int i;
1148 struct drm_amdgpu_cs_chunk_sem *deps;
1149 deps = (struct drm_amdgpu_cs_chunk_sem *)chunk->kdata;
1150 num_deps = chunk->length_dw * 4 /
1151 sizeof(struct drm_amdgpu_cs_chunk_sem);
1152
1153 p->post_dep_syncobjs = kmalloc_array(num_deps,
1154 sizeof(struct drm_syncobj *),
1155 GFP_KERNEL);
1156 p->num_post_dep_syncobjs = 0;
1157
1158 if (!p->post_dep_syncobjs)
1159 return -ENOMEM;
1160
1161 for (i = 0; i < num_deps; ++i) {
1162 p->post_dep_syncobjs[i] = drm_syncobj_find(p->filp, deps[i].handle);
1163 if (!p->post_dep_syncobjs[i])
1164 return -EINVAL;
1165 p->num_post_dep_syncobjs++;
1166 }
1167 return 0;
1168 }
1169
1170 static int amdgpu_cs_dependencies(struct amdgpu_device *adev,
1171 struct amdgpu_cs_parser *p)
1172 {
1173 int i, r;
1174
1175 for (i = 0; i < p->nchunks; ++i) {
1176 struct amdgpu_cs_chunk *chunk;
1177
1178 chunk = &p->chunks[i];
1179
1180 if (chunk->chunk_id == AMDGPU_CHUNK_ID_DEPENDENCIES) {
1181 r = amdgpu_cs_process_fence_dep(p, chunk);
1182 if (r)
1183 return r;
1184 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_IN) {
1185 r = amdgpu_cs_process_syncobj_in_dep(p, chunk);
1186 if (r)
1187 return r;
1188 } else if (chunk->chunk_id == AMDGPU_CHUNK_ID_SYNCOBJ_OUT) {
1189 r = amdgpu_cs_process_syncobj_out_dep(p, chunk);
1190 if (r)
1191 return r;
1192 }
1193 }
1194
1195 return 0;
1196 }
1197
1198 static void amdgpu_cs_post_dependencies(struct amdgpu_cs_parser *p)
1199 {
1200 int i;
1201
1202 for (i = 0; i < p->num_post_dep_syncobjs; ++i)
1203 drm_syncobj_replace_fence(p->post_dep_syncobjs[i], p->fence);
1204 }
1205
1206 static int amdgpu_cs_submit(struct amdgpu_cs_parser *p,
1207 union drm_amdgpu_cs *cs)
1208 {
1209 struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
1210 struct drm_sched_entity *entity = p->entity;
1211 enum drm_sched_priority priority;
1212 struct amdgpu_ring *ring;
1213 struct amdgpu_bo_list_entry *e;
1214 struct amdgpu_job *job;
1215 uint64_t seq;
1216
1217 int r;
1218
1219 job = p->job;
1220 p->job = NULL;
1221
1222 r = drm_sched_job_init(&job->base, entity, p->filp);
1223 if (r)
1224 goto error_unlock;
1225
1226 /* No memory allocation is allowed while holding the mn lock */
1227 amdgpu_mn_lock(p->mn);
1228 amdgpu_bo_list_for_each_userptr_entry(e, p->bo_list) {
1229 struct amdgpu_bo *bo = ttm_to_amdgpu_bo(e->tv.bo);
1230
1231 if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm)) {
1232 r = -ERESTARTSYS;
1233 goto error_abort;
1234 }
1235 }
1236
1237 job->owner = p->filp;
1238 p->fence = dma_fence_get(&job->base.s_fence->finished);
1239
1240 amdgpu_ctx_add_fence(p->ctx, entity, p->fence, &seq);
1241 amdgpu_cs_post_dependencies(p);
1242
1243 if ((job->preamble_status & AMDGPU_PREAMBLE_IB_PRESENT) &&
1244 !p->ctx->preamble_presented) {
1245 job->preamble_status |= AMDGPU_PREAMBLE_IB_PRESENT_FIRST;
1246 p->ctx->preamble_presented = true;
1247 }
1248
1249 cs->out.handle = seq;
1250 job->uf_sequence = seq;
1251
1252 amdgpu_job_free_resources(job);
1253
1254 trace_amdgpu_cs_ioctl(job);
1255 amdgpu_vm_bo_trace_cs(&fpriv->vm, &p->ticket);
1256 priority = job->base.s_priority;
1257 drm_sched_entity_push_job(&job->base, entity);
1258
1259 ring = to_amdgpu_ring(entity->rq->sched);
1260 amdgpu_ring_priority_get(ring, priority);
1261
1262 amdgpu_vm_move_to_lru_tail(p->adev, &fpriv->vm);
1263
1264 ttm_eu_fence_buffer_objects(&p->ticket, &p->validated, p->fence);
1265 amdgpu_mn_unlock(p->mn);
1266
1267 return 0;
1268
1269 error_abort:
1270 drm_sched_job_cleanup(&job->base);
1271 amdgpu_mn_unlock(p->mn);
1272
1273 error_unlock:
1274 amdgpu_job_free(job);
1275 return r;
1276 }
1277
1278 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
1279 {
1280 struct amdgpu_device *adev = dev->dev_private;
1281 union drm_amdgpu_cs *cs = data;
1282 struct amdgpu_cs_parser parser = {};
1283 bool reserved_buffers = false;
1284 int i, r;
1285
1286 if (!adev->accel_working)
1287 return -EBUSY;
1288
1289 parser.adev = adev;
1290 parser.filp = filp;
1291
1292 r = amdgpu_cs_parser_init(&parser, data);
1293 if (r) {
1294 DRM_ERROR("Failed to initialize parser %d!\n", r);
1295 goto out;
1296 }
1297
1298 r = amdgpu_cs_ib_fill(adev, &parser);
1299 if (r)
1300 goto out;
1301
1302 r = amdgpu_cs_dependencies(adev, &parser);
1303 if (r) {
1304 DRM_ERROR("Failed in the dependencies handling %d!\n", r);
1305 goto out;
1306 }
1307
1308 r = amdgpu_cs_parser_bos(&parser, data);
1309 if (r) {
1310 if (r == -ENOMEM)
1311 DRM_ERROR("Not enough memory for command submission!\n");
1312 else if (r != -ERESTARTSYS)
1313 DRM_ERROR("Failed to process the buffer list %d!\n", r);
1314 goto out;
1315 }
1316
1317 reserved_buffers = true;
1318
1319 for (i = 0; i < parser.job->num_ibs; i++)
1320 trace_amdgpu_cs(&parser, i);
1321
1322 r = amdgpu_cs_vm_handling(&parser);
1323 if (r)
1324 goto out;
1325
1326 r = amdgpu_cs_submit(&parser, cs);
1327
1328 out:
1329 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
1330 return r;
1331 }
1332
1333 /**
1334 * amdgpu_cs_wait_ioctl - wait for a command submission to finish
1335 *
1336 * @dev: drm device
1337 * @data: data from userspace
1338 * @filp: file private
1339 *
1340 * Wait for the command submission identified by handle to finish.
1341 */
1342 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
1343 struct drm_file *filp)
1344 {
1345 union drm_amdgpu_wait_cs *wait = data;
1346 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
1347 struct drm_sched_entity *entity;
1348 struct amdgpu_ctx *ctx;
1349 struct dma_fence *fence;
1350 long r;
1351
1352 ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
1353 if (ctx == NULL)
1354 return -EINVAL;
1355
1356 r = amdgpu_ctx_get_entity(ctx, wait->in.ip_type, wait->in.ip_instance,
1357 wait->in.ring, &entity);
1358 if (r) {
1359 amdgpu_ctx_put(ctx);
1360 return r;
1361 }
1362
1363 fence = amdgpu_ctx_get_fence(ctx, entity, wait->in.handle);
1364 if (IS_ERR(fence))
1365 r = PTR_ERR(fence);
1366 else if (fence) {
1367 r = dma_fence_wait_timeout(fence, true, timeout);
1368 if (r > 0 && fence->error)
1369 r = fence->error;
1370 dma_fence_put(fence);
1371 } else
1372 r = 1;
1373
1374 amdgpu_ctx_put(ctx);
1375 if (r < 0)
1376 return r;
1377
1378 memset(wait, 0, sizeof(*wait));
1379 wait->out.status = (r == 0);
1380
1381 return 0;
1382 }
1383
1384 /**
1385 * amdgpu_cs_get_fence - helper to get fence from drm_amdgpu_fence
1386 *
1387 * @adev: amdgpu device
1388 * @filp: file private
1389 * @user: drm_amdgpu_fence copied from user space
1390 */
1391 static struct dma_fence *amdgpu_cs_get_fence(struct amdgpu_device *adev,
1392 struct drm_file *filp,
1393 struct drm_amdgpu_fence *user)
1394 {
1395 struct drm_sched_entity *entity;
1396 struct amdgpu_ctx *ctx;
1397 struct dma_fence *fence;
1398 int r;
1399
1400 ctx = amdgpu_ctx_get(filp->driver_priv, user->ctx_id);
1401 if (ctx == NULL)
1402 return ERR_PTR(-EINVAL);
1403
1404 r = amdgpu_ctx_get_entity(ctx, user->ip_type, user->ip_instance,
1405 user->ring, &entity);
1406 if (r) {
1407 amdgpu_ctx_put(ctx);
1408 return ERR_PTR(r);
1409 }
1410
1411 fence = amdgpu_ctx_get_fence(ctx, entity, user->seq_no);
1412 amdgpu_ctx_put(ctx);
1413
1414 return fence;
1415 }
1416
1417 int amdgpu_cs_fence_to_handle_ioctl(struct drm_device *dev, void *data,
1418 struct drm_file *filp)
1419 {
1420 struct amdgpu_device *adev = dev->dev_private;
1421 union drm_amdgpu_fence_to_handle *info = data;
1422 struct dma_fence *fence;
1423 struct drm_syncobj *syncobj;
1424 struct sync_file *sync_file;
1425 int fd, r;
1426
1427 fence = amdgpu_cs_get_fence(adev, filp, &info->in.fence);
1428 if (IS_ERR(fence))
1429 return PTR_ERR(fence);
1430
1431 if (!fence)
1432 fence = dma_fence_get_stub();
1433
1434 switch (info->in.what) {
1435 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ:
1436 r = drm_syncobj_create(&syncobj, 0, fence);
1437 dma_fence_put(fence);
1438 if (r)
1439 return r;
1440 r = drm_syncobj_get_handle(filp, syncobj, &info->out.handle);
1441 drm_syncobj_put(syncobj);
1442 return r;
1443
1444 case AMDGPU_FENCE_TO_HANDLE_GET_SYNCOBJ_FD:
1445 r = drm_syncobj_create(&syncobj, 0, fence);
1446 dma_fence_put(fence);
1447 if (r)
1448 return r;
1449 r = drm_syncobj_get_fd(syncobj, (int*)&info->out.handle);
1450 drm_syncobj_put(syncobj);
1451 return r;
1452
1453 case AMDGPU_FENCE_TO_HANDLE_GET_SYNC_FILE_FD:
1454 fd = get_unused_fd_flags(O_CLOEXEC);
1455 if (fd < 0) {
1456 dma_fence_put(fence);
1457 return fd;
1458 }
1459
1460 sync_file = sync_file_create(fence);
1461 dma_fence_put(fence);
1462 if (!sync_file) {
1463 put_unused_fd(fd);
1464 return -ENOMEM;
1465 }
1466
1467 fd_install(fd, sync_file->file);
1468 info->out.handle = fd;
1469 return 0;
1470
1471 default:
1472 return -EINVAL;
1473 }
1474 }
1475
1476 /**
1477 * amdgpu_cs_wait_all_fence - wait on all fences to signal
1478 *
1479 * @adev: amdgpu device
1480 * @filp: file private
1481 * @wait: wait parameters
1482 * @fences: array of drm_amdgpu_fence
1483 */
1484 static int amdgpu_cs_wait_all_fences(struct amdgpu_device *adev,
1485 struct drm_file *filp,
1486 union drm_amdgpu_wait_fences *wait,
1487 struct drm_amdgpu_fence *fences)
1488 {
1489 uint32_t fence_count = wait->in.fence_count;
1490 unsigned int i;
1491 long r = 1;
1492
1493 for (i = 0; i < fence_count; i++) {
1494 struct dma_fence *fence;
1495 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1496
1497 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1498 if (IS_ERR(fence))
1499 return PTR_ERR(fence);
1500 else if (!fence)
1501 continue;
1502
1503 r = dma_fence_wait_timeout(fence, true, timeout);
1504 dma_fence_put(fence);
1505 if (r < 0)
1506 return r;
1507
1508 if (r == 0)
1509 break;
1510
1511 if (fence->error)
1512 return fence->error;
1513 }
1514
1515 memset(wait, 0, sizeof(*wait));
1516 wait->out.status = (r > 0);
1517
1518 return 0;
1519 }
1520
1521 /**
1522 * amdgpu_cs_wait_any_fence - wait on any fence to signal
1523 *
1524 * @adev: amdgpu device
1525 * @filp: file private
1526 * @wait: wait parameters
1527 * @fences: array of drm_amdgpu_fence
1528 */
1529 static int amdgpu_cs_wait_any_fence(struct amdgpu_device *adev,
1530 struct drm_file *filp,
1531 union drm_amdgpu_wait_fences *wait,
1532 struct drm_amdgpu_fence *fences)
1533 {
1534 unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout_ns);
1535 uint32_t fence_count = wait->in.fence_count;
1536 uint32_t first = ~0;
1537 struct dma_fence **array;
1538 unsigned int i;
1539 long r;
1540
1541 /* Prepare the fence array */
1542 array = kcalloc(fence_count, sizeof(struct dma_fence *), GFP_KERNEL);
1543
1544 if (array == NULL)
1545 return -ENOMEM;
1546
1547 for (i = 0; i < fence_count; i++) {
1548 struct dma_fence *fence;
1549
1550 fence = amdgpu_cs_get_fence(adev, filp, &fences[i]);
1551 if (IS_ERR(fence)) {
1552 r = PTR_ERR(fence);
1553 goto err_free_fence_array;
1554 } else if (fence) {
1555 array[i] = fence;
1556 } else { /* NULL, the fence has been already signaled */
1557 r = 1;
1558 first = i;
1559 goto out;
1560 }
1561 }
1562
1563 r = dma_fence_wait_any_timeout(array, fence_count, true, timeout,
1564 &first);
1565 if (r < 0)
1566 goto err_free_fence_array;
1567
1568 out:
1569 memset(wait, 0, sizeof(*wait));
1570 wait->out.status = (r > 0);
1571 wait->out.first_signaled = first;
1572
1573 if (first < fence_count && array[first])
1574 r = array[first]->error;
1575 else
1576 r = 0;
1577
1578 err_free_fence_array:
1579 for (i = 0; i < fence_count; i++)
1580 dma_fence_put(array[i]);
1581 kfree(array);
1582
1583 return r;
1584 }
1585
1586 /**
1587 * amdgpu_cs_wait_fences_ioctl - wait for multiple command submissions to finish
1588 *
1589 * @dev: drm device
1590 * @data: data from userspace
1591 * @filp: file private
1592 */
1593 int amdgpu_cs_wait_fences_ioctl(struct drm_device *dev, void *data,
1594 struct drm_file *filp)
1595 {
1596 struct amdgpu_device *adev = dev->dev_private;
1597 union drm_amdgpu_wait_fences *wait = data;
1598 uint32_t fence_count = wait->in.fence_count;
1599 struct drm_amdgpu_fence *fences_user;
1600 struct drm_amdgpu_fence *fences;
1601 int r;
1602
1603 /* Get the fences from userspace */
1604 fences = kmalloc_array(fence_count, sizeof(struct drm_amdgpu_fence),
1605 GFP_KERNEL);
1606 if (fences == NULL)
1607 return -ENOMEM;
1608
1609 fences_user = u64_to_user_ptr(wait->in.fences);
1610 if (copy_from_user(fences, fences_user,
1611 sizeof(struct drm_amdgpu_fence) * fence_count)) {
1612 r = -EFAULT;
1613 goto err_free_fences;
1614 }
1615
1616 if (wait->in.wait_all)
1617 r = amdgpu_cs_wait_all_fences(adev, filp, wait, fences);
1618 else
1619 r = amdgpu_cs_wait_any_fence(adev, filp, wait, fences);
1620
1621 err_free_fences:
1622 kfree(fences);
1623
1624 return r;
1625 }
1626
1627 /**
1628 * amdgpu_cs_find_bo_va - find bo_va for VM address
1629 *
1630 * @parser: command submission parser context
1631 * @addr: VM address
1632 * @bo: resulting BO of the mapping found
1633 *
1634 * Search the buffer objects in the command submission context for a certain
1635 * virtual memory address. Returns allocation structure when found, NULL
1636 * otherwise.
1637 */
1638 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
1639 uint64_t addr, struct amdgpu_bo **bo,
1640 struct amdgpu_bo_va_mapping **map)
1641 {
1642 struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
1643 struct ttm_operation_ctx ctx = { false, false };
1644 struct amdgpu_vm *vm = &fpriv->vm;
1645 struct amdgpu_bo_va_mapping *mapping;
1646 int r;
1647
1648 addr /= AMDGPU_GPU_PAGE_SIZE;
1649
1650 mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
1651 if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo)
1652 return -EINVAL;
1653
1654 *bo = mapping->bo_va->base.bo;
1655 *map = mapping;
1656
1657 /* Double check that the BO is reserved by this CS */
1658 if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket)
1659 return -EINVAL;
1660
1661 if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
1662 (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
1663 amdgpu_bo_placement_from_domain(*bo, (*bo)->allowed_domains);
1664 r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
1665 if (r)
1666 return r;
1667 }
1668
1669 return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
1670 }
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