drivers/gpu/drm/cirrus/cirrus_drv.h

   1 /*
   2  * Copyright 2012 Red Hat
   3  *
   4  * This file is subject to the terms and conditions of the GNU General
   5  * Public License version 2. See the file COPYING in the main
   6  * directory of this archive for more details.
   7  *
   8  * Authors: Matthew Garrett
   9  *          Dave Airlie
  10  */
  11 #ifndef __CIRRUS_DRV_H__
  12 #define __CIRRUS_DRV_H__
  13
  14 #include <video/vga.h>
  15
  16 #include <drm/drm_encoder.h>
  17 #include <drm/drm_fb_helper.h>
  18
  19 #include <drm/ttm/ttm_bo_api.h>
  20 #include <drm/ttm/ttm_bo_driver.h>
  21 #include <drm/ttm/ttm_placement.h>
  22 #include <drm/ttm/ttm_memory.h>
  23 #include <drm/ttm/ttm_module.h>
  24
  25 #include <drm/drm_gem.h>
  26
  27 #define DRIVER_AUTHOR           "Matthew Garrett"
  28
  29 #define DRIVER_NAME             "cirrus"
  30 #define DRIVER_DESC             "qemu Cirrus emulation"
  31 #define DRIVER_DATE             "20110418"
  32
  33 #define DRIVER_MAJOR            1
  34 #define DRIVER_MINOR            0
  35 #define DRIVER_PATCHLEVEL       0
  36
  37 #define CIRRUSFB_CONN_LIMIT 1
  38
  39 #define RREG8(reg) ioread8(((void __iomem *)cdev->rmmio) + (reg))
  40 #define WREG8(reg, v) iowrite8(v, ((void __iomem *)cdev->rmmio) + (reg))
  41 #define RREG32(reg) ioread32(((void __iomem *)cdev->rmmio) + (reg))
  42 #define WREG32(reg, v) iowrite32(v, ((void __iomem *)cdev->rmmio) + (reg))
  43
  44 #define SEQ_INDEX 4
  45 #define SEQ_DATA 5
  46
  47 #define WREG_SEQ(reg, v)                                        \
  48         do {                                                    \
  49                 WREG8(SEQ_INDEX, reg);                          \
  50                 WREG8(SEQ_DATA, v);                             \
  51         } while (0)                                             \
  52
  53 #define CRT_INDEX 0x14
  54 #define CRT_DATA 0x15
  55
  56 #define WREG_CRT(reg, v)                                        \
  57         do {                                                    \
  58                 WREG8(CRT_INDEX, reg);                          \
  59                 WREG8(CRT_DATA, v);                             \
  60         } while (0)                                             \
  61
  62 #define GFX_INDEX 0xe
  63 #define GFX_DATA 0xf
  64
  65 #define WREG_GFX(reg, v)                                        \
  66         do {                                                    \
  67                 WREG8(GFX_INDEX, reg);                          \
  68                 WREG8(GFX_DATA, v);                             \
  69         } while (0)                                             \
  70
  71 /*
  72  * Cirrus has a "hidden" DAC register that can be accessed by writing to
  73  * the pixel mask register to reset the state, then reading from the register
  74  * four times. The next write will then pass to the DAC
  75  */
  76 #define VGA_DAC_MASK 0x6
  77
  78 #define WREG_HDR(v)                                             \
  79         do {                                                    \
  80                 RREG8(VGA_DAC_MASK);                                    \
  81                 RREG8(VGA_DAC_MASK);                                    \
  82                 RREG8(VGA_DAC_MASK);                                    \
  83                 RREG8(VGA_DAC_MASK);                                    \
  84                 WREG8(VGA_DAC_MASK, v);                                 \
  85         } while (0)                                             \
  86
  87
  88 #define CIRRUS_MAX_FB_HEIGHT 4096
  89 #define CIRRUS_MAX_FB_WIDTH 4096
  90
  91 #define CIRRUS_DPMS_CLEARED (-1)
  92
  93 #define to_cirrus_crtc(x) container_of(x, struct cirrus_crtc, base)
  94 #define to_cirrus_encoder(x) container_of(x, struct cirrus_encoder, base)
  95 #define to_cirrus_framebuffer(x) container_of(x, struct cirrus_framebuffer, base)
  96
  97 struct cirrus_crtc {
  98         struct drm_crtc                 base;
  99         int                             last_dpms;
 100         bool                            enabled;
 101 };
 102
 103 struct cirrus_fbdev;
 104 struct cirrus_mode_info {
 105         bool                            mode_config_initialized;
 106         struct cirrus_crtc              *crtc;
 107         /* pointer to fbdev info structure */
 108         struct cirrus_fbdev             *gfbdev;
 109 };
 110
 111 struct cirrus_encoder {
 112         struct drm_encoder              base;
 113         int                             last_dpms;
 114 };
 115
 116 struct cirrus_connector {
 117         struct drm_connector            base;
 118 };
 119
 120 struct cirrus_framebuffer {
 121         struct drm_framebuffer          base;
 122         struct drm_gem_object *obj;
 123 };
 124
 125 struct cirrus_mc {
 126         resource_size_t                 vram_size;
 127         resource_size_t                 vram_base;
 128 };
 129
 130 struct cirrus_device {
 131         struct drm_device               *dev;
 132         unsigned long                   flags;
 133
 134         resource_size_t                 rmmio_base;
 135         resource_size_t                 rmmio_size;
 136         void __iomem                    *rmmio;
 137
 138         struct cirrus_mc                        mc;
 139         struct cirrus_mode_info         mode_info;
 140
 141         int                             num_crtc;
 142         int fb_mtrr;
 143
 144         struct {
 145                 struct drm_global_reference mem_global_ref;
 146                 struct ttm_bo_global_ref bo_global_ref;
 147                 struct ttm_bo_device bdev;
 148         } ttm;
 149         bool mm_inited;
 150 };
 151
 152
 153 struct cirrus_fbdev {
 154         struct drm_fb_helper helper;
 155         struct cirrus_framebuffer gfb;
 156         void *sysram;
 157         int size;
 158         int x1, y1, x2, y2; /* dirty rect */
 159         spinlock_t dirty_lock;
 160 };
 161
 162 struct cirrus_bo {
 163         struct ttm_buffer_object bo;
 164         struct ttm_placement placement;
 165         struct ttm_bo_kmap_obj kmap;
 166         struct drm_gem_object gem;
 167         struct ttm_place placements[3];
 168         int pin_count;
 169 };
 170 #define gem_to_cirrus_bo(gobj) container_of((gobj), struct cirrus_bo, gem)
 171
 172 static inline struct cirrus_bo *
 173 cirrus_bo(struct ttm_buffer_object *bo)
 174 {
 175         return container_of(bo, struct cirrus_bo, bo);
 176 }
 177
 178
 179 #define to_cirrus_obj(x) container_of(x, struct cirrus_gem_object, base)
 180 #define DRM_FILE_PAGE_OFFSET (0x100000000ULL >> PAGE_SHIFT)
 181
 182                                 /* cirrus_main.c */
 183 int cirrus_device_init(struct cirrus_device *cdev,
 184                       struct drm_device *ddev,
 185                       struct pci_dev *pdev,
 186                       uint32_t flags);
 187 void cirrus_device_fini(struct cirrus_device *cdev);
 188 void cirrus_gem_free_object(struct drm_gem_object *obj);
 189 int cirrus_dumb_mmap_offset(struct drm_file *file,
 190                             struct drm_device *dev,
 191                             uint32_t handle,
 192                             uint64_t *offset);
 193 int cirrus_gem_create(struct drm_device *dev,
 194                    u32 size, bool iskernel,
 195                       struct drm_gem_object **obj);
 196 int cirrus_dumb_create(struct drm_file *file,
 197                     struct drm_device *dev,
 198                        struct drm_mode_create_dumb *args);
 199
 200 int cirrus_framebuffer_init(struct drm_device *dev,
 201                            struct cirrus_framebuffer *gfb,
 202                             const struct drm_mode_fb_cmd2 *mode_cmd,
 203                             struct drm_gem_object *obj);
 204
 205 bool cirrus_check_framebuffer(struct cirrus_device *cdev, int width, int height,
 206                               int bpp, int pitch);
 207
 208                                 /* cirrus_display.c */
 209 int cirrus_modeset_init(struct cirrus_device *cdev);
 210 void cirrus_modeset_fini(struct cirrus_device *cdev);
 211
 212                                 /* cirrus_fbdev.c */
 213 int cirrus_fbdev_init(struct cirrus_device *cdev);
 214 void cirrus_fbdev_fini(struct cirrus_device *cdev);
 215
 216
 217
 218                                 /* cirrus_irq.c */
 219 void cirrus_driver_irq_preinstall(struct drm_device *dev);
 220 int cirrus_driver_irq_postinstall(struct drm_device *dev);
 221 void cirrus_driver_irq_uninstall(struct drm_device *dev);
 222 irqreturn_t cirrus_driver_irq_handler(int irq, void *arg);
 223
 224                                 /* cirrus_kms.c */
 225 int cirrus_driver_load(struct drm_device *dev, unsigned long flags);
 226 void cirrus_driver_unload(struct drm_device *dev);
 227 extern struct drm_ioctl_desc cirrus_ioctls[];
 228 extern int cirrus_max_ioctl;
 229
 230 int cirrus_mm_init(struct cirrus_device *cirrus);
 231 void cirrus_mm_fini(struct cirrus_device *cirrus);
 232 void cirrus_ttm_placement(struct cirrus_bo *bo, int domain);
 233 int cirrus_bo_create(struct drm_device *dev, int size, int align,
 234                      uint32_t flags, struct cirrus_bo **pcirrusbo);
 235 int cirrus_mmap(struct file *filp, struct vm_area_struct *vma);
 236
 237 static inline int cirrus_bo_reserve(struct cirrus_bo *bo, bool no_wait)
 238 {
 239         int ret;
 240
 241         ret = ttm_bo_reserve(&bo->bo, true, no_wait, NULL);
 242         if (ret) {
 243                 if (ret != -ERESTARTSYS && ret != -EBUSY)
 244                         DRM_ERROR("reserve failed %p\n", bo);
 245                 return ret;
 246         }
 247         return 0;
 248 }
 249
 250 static inline void cirrus_bo_unreserve(struct cirrus_bo *bo)
 251 {
 252         ttm_bo_unreserve(&bo->bo);
 253 }
 254
 255 int cirrus_bo_push_sysram(struct cirrus_bo *bo);
 256 int cirrus_bo_pin(struct cirrus_bo *bo, u32 pl_flag, u64 *gpu_addr);
 257
 258 extern int cirrus_bpp;
 259
 260 #endif                          /* __CIRRUS_DRV_H__ */