4 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
26 * Zhi Wang <zhi.a.wang@intel.com>
27 * Zhenyu Wang <zhenyuw@linux.intel.com>
28 * Xiao Zheng <xiao.zheng@intel.com>
31 * Min He <min.he@intel.com>
32 * Bing Niu <bing.niu@intel.com>
38 #include "i915_pvinfo.h"
41 static bool enable_out_of_sync
= false;
42 static int preallocated_oos_pages
= 8192;
45 * validate a gm address and related range size,
46 * translate it to host gm address
48 bool intel_gvt_ggtt_validate_range(struct intel_vgpu
*vgpu
, u64 addr
, u32 size
)
50 if ((!vgpu_gmadr_is_valid(vgpu
, addr
)) || (size
51 && !vgpu_gmadr_is_valid(vgpu
, addr
+ size
- 1))) {
52 gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
59 /* translate a guest gmadr to host gmadr */
60 int intel_gvt_ggtt_gmadr_g2h(struct intel_vgpu
*vgpu
, u64 g_addr
, u64
*h_addr
)
62 if (WARN(!vgpu_gmadr_is_valid(vgpu
, g_addr
),
63 "invalid guest gmadr %llx\n", g_addr
))
66 if (vgpu_gmadr_is_aperture(vgpu
, g_addr
))
67 *h_addr
= vgpu_aperture_gmadr_base(vgpu
)
68 + (g_addr
- vgpu_aperture_offset(vgpu
));
70 *h_addr
= vgpu_hidden_gmadr_base(vgpu
)
71 + (g_addr
- vgpu_hidden_offset(vgpu
));
75 /* translate a host gmadr to guest gmadr */
76 int intel_gvt_ggtt_gmadr_h2g(struct intel_vgpu
*vgpu
, u64 h_addr
, u64
*g_addr
)
78 if (WARN(!gvt_gmadr_is_valid(vgpu
->gvt
, h_addr
),
79 "invalid host gmadr %llx\n", h_addr
))
82 if (gvt_gmadr_is_aperture(vgpu
->gvt
, h_addr
))
83 *g_addr
= vgpu_aperture_gmadr_base(vgpu
)
84 + (h_addr
- gvt_aperture_gmadr_base(vgpu
->gvt
));
86 *g_addr
= vgpu_hidden_gmadr_base(vgpu
)
87 + (h_addr
- gvt_hidden_gmadr_base(vgpu
->gvt
));
91 int intel_gvt_ggtt_index_g2h(struct intel_vgpu
*vgpu
, unsigned long g_index
,
92 unsigned long *h_index
)
97 ret
= intel_gvt_ggtt_gmadr_g2h(vgpu
, g_index
<< GTT_PAGE_SHIFT
,
102 *h_index
= h_addr
>> GTT_PAGE_SHIFT
;
106 int intel_gvt_ggtt_h2g_index(struct intel_vgpu
*vgpu
, unsigned long h_index
,
107 unsigned long *g_index
)
112 ret
= intel_gvt_ggtt_gmadr_h2g(vgpu
, h_index
<< GTT_PAGE_SHIFT
,
117 *g_index
= g_addr
>> GTT_PAGE_SHIFT
;
121 #define gtt_type_is_entry(type) \
122 (type > GTT_TYPE_INVALID && type < GTT_TYPE_PPGTT_ENTRY \
123 && type != GTT_TYPE_PPGTT_PTE_ENTRY \
124 && type != GTT_TYPE_PPGTT_ROOT_ENTRY)
126 #define gtt_type_is_pt(type) \
127 (type >= GTT_TYPE_PPGTT_PTE_PT && type < GTT_TYPE_MAX)
129 #define gtt_type_is_pte_pt(type) \
130 (type == GTT_TYPE_PPGTT_PTE_PT)
132 #define gtt_type_is_root_pointer(type) \
133 (gtt_type_is_entry(type) && type > GTT_TYPE_PPGTT_ROOT_ENTRY)
135 #define gtt_init_entry(e, t, p, v) do { \
138 memcpy(&(e)->val64, &v, sizeof(v)); \
142 * Mappings between GTT_TYPE* enumerations.
143 * Following information can be found according to the given type:
144 * - type of next level page table
145 * - type of entry inside this level page table
146 * - type of entry with PSE set
148 * If the given type doesn't have such a kind of information,
149 * e.g. give a l4 root entry type, then request to get its PSE type,
150 * give a PTE page table type, then request to get its next level page
151 * table type, as we know l4 root entry doesn't have a PSE bit,
152 * and a PTE page table doesn't have a next level page table type,
153 * GTT_TYPE_INVALID will be returned. This is useful when traversing a
157 struct gtt_type_table_entry
{
163 #define GTT_TYPE_TABLE_ENTRY(type, e_type, npt_type, pse_type) \
165 .entry_type = e_type, \
166 .next_pt_type = npt_type, \
167 .pse_entry_type = pse_type, \
170 static struct gtt_type_table_entry gtt_type_table
[] = {
171 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L4_ENTRY
,
172 GTT_TYPE_PPGTT_ROOT_L4_ENTRY
,
173 GTT_TYPE_PPGTT_PML4_PT
,
175 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_PT
,
176 GTT_TYPE_PPGTT_PML4_ENTRY
,
177 GTT_TYPE_PPGTT_PDP_PT
,
179 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PML4_ENTRY
,
180 GTT_TYPE_PPGTT_PML4_ENTRY
,
181 GTT_TYPE_PPGTT_PDP_PT
,
183 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_PT
,
184 GTT_TYPE_PPGTT_PDP_ENTRY
,
185 GTT_TYPE_PPGTT_PDE_PT
,
186 GTT_TYPE_PPGTT_PTE_1G_ENTRY
),
187 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_ROOT_L3_ENTRY
,
188 GTT_TYPE_PPGTT_ROOT_L3_ENTRY
,
189 GTT_TYPE_PPGTT_PDE_PT
,
190 GTT_TYPE_PPGTT_PTE_1G_ENTRY
),
191 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDP_ENTRY
,
192 GTT_TYPE_PPGTT_PDP_ENTRY
,
193 GTT_TYPE_PPGTT_PDE_PT
,
194 GTT_TYPE_PPGTT_PTE_1G_ENTRY
),
195 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_PT
,
196 GTT_TYPE_PPGTT_PDE_ENTRY
,
197 GTT_TYPE_PPGTT_PTE_PT
,
198 GTT_TYPE_PPGTT_PTE_2M_ENTRY
),
199 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PDE_ENTRY
,
200 GTT_TYPE_PPGTT_PDE_ENTRY
,
201 GTT_TYPE_PPGTT_PTE_PT
,
202 GTT_TYPE_PPGTT_PTE_2M_ENTRY
),
203 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_PT
,
204 GTT_TYPE_PPGTT_PTE_4K_ENTRY
,
207 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_4K_ENTRY
,
208 GTT_TYPE_PPGTT_PTE_4K_ENTRY
,
211 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_2M_ENTRY
,
212 GTT_TYPE_PPGTT_PDE_ENTRY
,
214 GTT_TYPE_PPGTT_PTE_2M_ENTRY
),
215 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_PPGTT_PTE_1G_ENTRY
,
216 GTT_TYPE_PPGTT_PDP_ENTRY
,
218 GTT_TYPE_PPGTT_PTE_1G_ENTRY
),
219 GTT_TYPE_TABLE_ENTRY(GTT_TYPE_GGTT_PTE
,
225 static inline int get_next_pt_type(int type
)
227 return gtt_type_table
[type
].next_pt_type
;
230 static inline int get_entry_type(int type
)
232 return gtt_type_table
[type
].entry_type
;
235 static inline int get_pse_type(int type
)
237 return gtt_type_table
[type
].pse_entry_type
;
240 static u64
read_pte64(struct drm_i915_private
*dev_priv
, unsigned long index
)
242 void __iomem
*addr
= (gen8_pte_t __iomem
*)dev_priv
->ggtt
.gsm
+ index
;
247 static void gtt_invalidate(struct drm_i915_private
*dev_priv
)
249 mmio_hw_access_pre(dev_priv
);
250 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
251 mmio_hw_access_post(dev_priv
);
254 static void write_pte64(struct drm_i915_private
*dev_priv
,
255 unsigned long index
, u64 pte
)
257 void __iomem
*addr
= (gen8_pte_t __iomem
*)dev_priv
->ggtt
.gsm
+ index
;
262 static inline int gtt_get_entry64(void *pt
,
263 struct intel_gvt_gtt_entry
*e
,
264 unsigned long index
, bool hypervisor_access
, unsigned long gpa
,
265 struct intel_vgpu
*vgpu
)
267 const struct intel_gvt_device_info
*info
= &vgpu
->gvt
->device_info
;
270 if (WARN_ON(info
->gtt_entry_size
!= 8))
273 if (hypervisor_access
) {
274 ret
= intel_gvt_hypervisor_read_gpa(vgpu
, gpa
+
275 (index
<< info
->gtt_entry_size_shift
),
280 e
->val64
= read_pte64(vgpu
->gvt
->dev_priv
, index
);
282 e
->val64
= *((u64
*)pt
+ index
);
287 static inline int gtt_set_entry64(void *pt
,
288 struct intel_gvt_gtt_entry
*e
,
289 unsigned long index
, bool hypervisor_access
, unsigned long gpa
,
290 struct intel_vgpu
*vgpu
)
292 const struct intel_gvt_device_info
*info
= &vgpu
->gvt
->device_info
;
295 if (WARN_ON(info
->gtt_entry_size
!= 8))
298 if (hypervisor_access
) {
299 ret
= intel_gvt_hypervisor_write_gpa(vgpu
, gpa
+
300 (index
<< info
->gtt_entry_size_shift
),
305 write_pte64(vgpu
->gvt
->dev_priv
, index
, e
->val64
);
307 *((u64
*)pt
+ index
) = e
->val64
;
314 #define ADDR_1G_MASK (((1UL << (GTT_HAW - 30 + 1)) - 1) << 30)
315 #define ADDR_2M_MASK (((1UL << (GTT_HAW - 21 + 1)) - 1) << 21)
316 #define ADDR_4K_MASK (((1UL << (GTT_HAW - 12 + 1)) - 1) << 12)
318 static unsigned long gen8_gtt_get_pfn(struct intel_gvt_gtt_entry
*e
)
322 if (e
->type
== GTT_TYPE_PPGTT_PTE_1G_ENTRY
)
323 pfn
= (e
->val64
& ADDR_1G_MASK
) >> 12;
324 else if (e
->type
== GTT_TYPE_PPGTT_PTE_2M_ENTRY
)
325 pfn
= (e
->val64
& ADDR_2M_MASK
) >> 12;
327 pfn
= (e
->val64
& ADDR_4K_MASK
) >> 12;
331 static void gen8_gtt_set_pfn(struct intel_gvt_gtt_entry
*e
, unsigned long pfn
)
333 if (e
->type
== GTT_TYPE_PPGTT_PTE_1G_ENTRY
) {
334 e
->val64
&= ~ADDR_1G_MASK
;
335 pfn
&= (ADDR_1G_MASK
>> 12);
336 } else if (e
->type
== GTT_TYPE_PPGTT_PTE_2M_ENTRY
) {
337 e
->val64
&= ~ADDR_2M_MASK
;
338 pfn
&= (ADDR_2M_MASK
>> 12);
340 e
->val64
&= ~ADDR_4K_MASK
;
341 pfn
&= (ADDR_4K_MASK
>> 12);
344 e
->val64
|= (pfn
<< 12);
347 static bool gen8_gtt_test_pse(struct intel_gvt_gtt_entry
*e
)
349 /* Entry doesn't have PSE bit. */
350 if (get_pse_type(e
->type
) == GTT_TYPE_INVALID
)
353 e
->type
= get_entry_type(e
->type
);
354 if (!(e
->val64
& (1 << 7)))
357 e
->type
= get_pse_type(e
->type
);
361 static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry
*e
)
364 * i915 writes PDP root pointer registers without present bit,
365 * it also works, so we need to treat root pointer entry
368 if (e
->type
== GTT_TYPE_PPGTT_ROOT_L3_ENTRY
369 || e
->type
== GTT_TYPE_PPGTT_ROOT_L4_ENTRY
)
370 return (e
->val64
!= 0);
372 return (e
->val64
& (1 << 0));
375 static void gtt_entry_clear_present(struct intel_gvt_gtt_entry
*e
)
377 e
->val64
&= ~(1 << 0);
381 * Per-platform GMA routines.
383 static unsigned long gma_to_ggtt_pte_index(unsigned long gma
)
385 unsigned long x
= (gma
>> GTT_PAGE_SHIFT
);
387 trace_gma_index(__func__
, gma
, x
);
391 #define DEFINE_PPGTT_GMA_TO_INDEX(prefix, ename, exp) \
392 static unsigned long prefix##_gma_to_##ename##_index(unsigned long gma) \
394 unsigned long x = (exp); \
395 trace_gma_index(__func__, gma, x); \
399 DEFINE_PPGTT_GMA_TO_INDEX(gen8
, pte
, (gma
>> 12 & 0x1ff));
400 DEFINE_PPGTT_GMA_TO_INDEX(gen8
, pde
, (gma
>> 21 & 0x1ff));
401 DEFINE_PPGTT_GMA_TO_INDEX(gen8
, l3_pdp
, (gma
>> 30 & 0x3));
402 DEFINE_PPGTT_GMA_TO_INDEX(gen8
, l4_pdp
, (gma
>> 30 & 0x1ff));
403 DEFINE_PPGTT_GMA_TO_INDEX(gen8
, pml4
, (gma
>> 39 & 0x1ff));
405 static struct intel_gvt_gtt_pte_ops gen8_gtt_pte_ops
= {
406 .get_entry
= gtt_get_entry64
,
407 .set_entry
= gtt_set_entry64
,
408 .clear_present
= gtt_entry_clear_present
,
409 .test_present
= gen8_gtt_test_present
,
410 .test_pse
= gen8_gtt_test_pse
,
411 .get_pfn
= gen8_gtt_get_pfn
,
412 .set_pfn
= gen8_gtt_set_pfn
,
415 static struct intel_gvt_gtt_gma_ops gen8_gtt_gma_ops
= {
416 .gma_to_ggtt_pte_index
= gma_to_ggtt_pte_index
,
417 .gma_to_pte_index
= gen8_gma_to_pte_index
,
418 .gma_to_pde_index
= gen8_gma_to_pde_index
,
419 .gma_to_l3_pdp_index
= gen8_gma_to_l3_pdp_index
,
420 .gma_to_l4_pdp_index
= gen8_gma_to_l4_pdp_index
,
421 .gma_to_pml4_index
= gen8_gma_to_pml4_index
,
424 static int gtt_entry_p2m(struct intel_vgpu
*vgpu
, struct intel_gvt_gtt_entry
*p
,
425 struct intel_gvt_gtt_entry
*m
)
427 struct intel_gvt_gtt_pte_ops
*ops
= vgpu
->gvt
->gtt
.pte_ops
;
428 unsigned long gfn
, mfn
;
432 if (!ops
->test_present(p
))
435 gfn
= ops
->get_pfn(p
);
437 mfn
= intel_gvt_hypervisor_gfn_to_mfn(vgpu
, gfn
);
438 if (mfn
== INTEL_GVT_INVALID_ADDR
) {
439 gvt_vgpu_err("fail to translate gfn: 0x%lx\n", gfn
);
443 ops
->set_pfn(m
, mfn
);
450 int intel_vgpu_mm_get_entry(struct intel_vgpu_mm
*mm
,
451 void *page_table
, struct intel_gvt_gtt_entry
*e
,
454 struct intel_gvt
*gvt
= mm
->vgpu
->gvt
;
455 struct intel_gvt_gtt_pte_ops
*ops
= gvt
->gtt
.pte_ops
;
458 e
->type
= mm
->page_table_entry_type
;
460 ret
= ops
->get_entry(page_table
, e
, index
, false, 0, mm
->vgpu
);
468 int intel_vgpu_mm_set_entry(struct intel_vgpu_mm
*mm
,
469 void *page_table
, struct intel_gvt_gtt_entry
*e
,
472 struct intel_gvt
*gvt
= mm
->vgpu
->gvt
;
473 struct intel_gvt_gtt_pte_ops
*ops
= gvt
->gtt
.pte_ops
;
475 return ops
->set_entry(page_table
, e
, index
, false, 0, mm
->vgpu
);
479 * PPGTT shadow page table helpers.
481 static inline int ppgtt_spt_get_entry(
482 struct intel_vgpu_ppgtt_spt
*spt
,
483 void *page_table
, int type
,
484 struct intel_gvt_gtt_entry
*e
, unsigned long index
,
487 struct intel_gvt
*gvt
= spt
->vgpu
->gvt
;
488 struct intel_gvt_gtt_pte_ops
*ops
= gvt
->gtt
.pte_ops
;
491 e
->type
= get_entry_type(type
);
493 if (WARN(!gtt_type_is_entry(e
->type
), "invalid entry type\n"))
496 ret
= ops
->get_entry(page_table
, e
, index
, guest
,
497 spt
->guest_page
.gfn
<< GTT_PAGE_SHIFT
,
506 static inline int ppgtt_spt_set_entry(
507 struct intel_vgpu_ppgtt_spt
*spt
,
508 void *page_table
, int type
,
509 struct intel_gvt_gtt_entry
*e
, unsigned long index
,
512 struct intel_gvt
*gvt
= spt
->vgpu
->gvt
;
513 struct intel_gvt_gtt_pte_ops
*ops
= gvt
->gtt
.pte_ops
;
515 if (WARN(!gtt_type_is_entry(e
->type
), "invalid entry type\n"))
518 return ops
->set_entry(page_table
, e
, index
, guest
,
519 spt
->guest_page
.gfn
<< GTT_PAGE_SHIFT
,
523 #define ppgtt_get_guest_entry(spt, e, index) \
524 ppgtt_spt_get_entry(spt, NULL, \
525 spt->guest_page_type, e, index, true)
527 #define ppgtt_set_guest_entry(spt, e, index) \
528 ppgtt_spt_set_entry(spt, NULL, \
529 spt->guest_page_type, e, index, true)
531 #define ppgtt_get_shadow_entry(spt, e, index) \
532 ppgtt_spt_get_entry(spt, spt->shadow_page.vaddr, \
533 spt->shadow_page.type, e, index, false)
535 #define ppgtt_set_shadow_entry(spt, e, index) \
536 ppgtt_spt_set_entry(spt, spt->shadow_page.vaddr, \
537 spt->shadow_page.type, e, index, false)
540 * intel_vgpu_init_guest_page - init a guest page data structure
542 * @p: a guest page data structure
543 * @gfn: guest memory page frame number
544 * @handler: function will be called when target guest memory page has
547 * This function is called when user wants to track a guest memory page.
550 * Zero on success, negative error code if failed.
552 int intel_vgpu_init_guest_page(struct intel_vgpu
*vgpu
,
553 struct intel_vgpu_guest_page
*p
,
555 int (*handler
)(void *, u64
, void *, int),
558 INIT_HLIST_NODE(&p
->node
);
560 p
->writeprotection
= false;
562 p
->handler
= handler
;
567 hash_add(vgpu
->gtt
.guest_page_hash_table
, &p
->node
, p
->gfn
);
571 static int detach_oos_page(struct intel_vgpu
*vgpu
,
572 struct intel_vgpu_oos_page
*oos_page
);
575 * intel_vgpu_clean_guest_page - release the resource owned by guest page data
578 * @p: a tracked guest page
580 * This function is called when user tries to stop tracking a guest memory
583 void intel_vgpu_clean_guest_page(struct intel_vgpu
*vgpu
,
584 struct intel_vgpu_guest_page
*p
)
586 if (!hlist_unhashed(&p
->node
))
590 detach_oos_page(vgpu
, p
->oos_page
);
592 if (p
->writeprotection
)
593 intel_gvt_hypervisor_unset_wp_page(vgpu
, p
);
597 * intel_vgpu_find_guest_page - find a guest page data structure by GFN.
599 * @gfn: guest memory page frame number
601 * This function is called when emulation logic wants to know if a trapped GFN
602 * is a tracked guest page.
605 * Pointer to guest page data structure, NULL if failed.
607 struct intel_vgpu_guest_page
*intel_vgpu_find_guest_page(
608 struct intel_vgpu
*vgpu
, unsigned long gfn
)
610 struct intel_vgpu_guest_page
*p
;
612 hash_for_each_possible(vgpu
->gtt
.guest_page_hash_table
,
620 static inline int init_shadow_page(struct intel_vgpu
*vgpu
,
621 struct intel_vgpu_shadow_page
*p
, int type
)
623 struct device
*kdev
= &vgpu
->gvt
->dev_priv
->drm
.pdev
->dev
;
626 daddr
= dma_map_page(kdev
, p
->page
, 0, 4096, PCI_DMA_BIDIRECTIONAL
);
627 if (dma_mapping_error(kdev
, daddr
)) {
628 gvt_vgpu_err("fail to map dma addr\n");
632 p
->vaddr
= page_address(p
->page
);
635 INIT_HLIST_NODE(&p
->node
);
637 p
->mfn
= daddr
>> GTT_PAGE_SHIFT
;
638 hash_add(vgpu
->gtt
.shadow_page_hash_table
, &p
->node
, p
->mfn
);
642 static inline void clean_shadow_page(struct intel_vgpu
*vgpu
,
643 struct intel_vgpu_shadow_page
*p
)
645 struct device
*kdev
= &vgpu
->gvt
->dev_priv
->drm
.pdev
->dev
;
647 dma_unmap_page(kdev
, p
->mfn
<< GTT_PAGE_SHIFT
, 4096,
648 PCI_DMA_BIDIRECTIONAL
);
650 if (!hlist_unhashed(&p
->node
))
654 static inline struct intel_vgpu_shadow_page
*find_shadow_page(
655 struct intel_vgpu
*vgpu
, unsigned long mfn
)
657 struct intel_vgpu_shadow_page
*p
;
659 hash_for_each_possible(vgpu
->gtt
.shadow_page_hash_table
,
667 #define guest_page_to_ppgtt_spt(ptr) \
668 container_of(ptr, struct intel_vgpu_ppgtt_spt, guest_page)
670 #define shadow_page_to_ppgtt_spt(ptr) \
671 container_of(ptr, struct intel_vgpu_ppgtt_spt, shadow_page)
673 static void *alloc_spt(gfp_t gfp_mask
)
675 struct intel_vgpu_ppgtt_spt
*spt
;
677 spt
= kzalloc(sizeof(*spt
), gfp_mask
);
681 spt
->shadow_page
.page
= alloc_page(gfp_mask
);
682 if (!spt
->shadow_page
.page
) {
689 static void free_spt(struct intel_vgpu_ppgtt_spt
*spt
)
691 __free_page(spt
->shadow_page
.page
);
695 static void ppgtt_free_shadow_page(struct intel_vgpu_ppgtt_spt
*spt
)
697 trace_spt_free(spt
->vgpu
->id
, spt
, spt
->shadow_page
.type
);
699 clean_shadow_page(spt
->vgpu
, &spt
->shadow_page
);
700 intel_vgpu_clean_guest_page(spt
->vgpu
, &spt
->guest_page
);
701 list_del_init(&spt
->post_shadow_list
);
706 static void ppgtt_free_all_shadow_page(struct intel_vgpu
*vgpu
)
708 struct hlist_node
*n
;
709 struct intel_vgpu_shadow_page
*sp
;
712 hash_for_each_safe(vgpu
->gtt
.shadow_page_hash_table
, i
, n
, sp
, node
)
713 ppgtt_free_shadow_page(shadow_page_to_ppgtt_spt(sp
));
716 static int ppgtt_handle_guest_write_page_table_bytes(void *gp
,
717 u64 pa
, void *p_data
, int bytes
);
719 static int ppgtt_write_protection_handler(void *gp
, u64 pa
,
720 void *p_data
, int bytes
)
722 struct intel_vgpu_guest_page
*gpt
= (struct intel_vgpu_guest_page
*)gp
;
725 if (bytes
!= 4 && bytes
!= 8)
728 if (!gpt
->writeprotection
)
731 ret
= ppgtt_handle_guest_write_page_table_bytes(gp
,
738 static int reclaim_one_mm(struct intel_gvt
*gvt
);
740 static struct intel_vgpu_ppgtt_spt
*ppgtt_alloc_shadow_page(
741 struct intel_vgpu
*vgpu
, int type
, unsigned long gfn
)
743 struct intel_vgpu_ppgtt_spt
*spt
= NULL
;
747 spt
= alloc_spt(GFP_KERNEL
| __GFP_ZERO
);
749 if (reclaim_one_mm(vgpu
->gvt
))
752 gvt_vgpu_err("fail to allocate ppgtt shadow page\n");
753 return ERR_PTR(-ENOMEM
);
757 spt
->guest_page_type
= type
;
758 atomic_set(&spt
->refcount
, 1);
759 INIT_LIST_HEAD(&spt
->post_shadow_list
);
762 * TODO: guest page type may be different with shadow page type,
763 * when we support PSE page in future.
765 ret
= init_shadow_page(vgpu
, &spt
->shadow_page
, type
);
767 gvt_vgpu_err("fail to initialize shadow page for spt\n");
771 ret
= intel_vgpu_init_guest_page(vgpu
, &spt
->guest_page
,
772 gfn
, ppgtt_write_protection_handler
, NULL
);
774 gvt_vgpu_err("fail to initialize guest page for spt\n");
778 trace_spt_alloc(vgpu
->id
, spt
, type
, spt
->shadow_page
.mfn
, gfn
);
781 ppgtt_free_shadow_page(spt
);
785 static struct intel_vgpu_ppgtt_spt
*ppgtt_find_shadow_page(
786 struct intel_vgpu
*vgpu
, unsigned long mfn
)
788 struct intel_vgpu_shadow_page
*p
= find_shadow_page(vgpu
, mfn
);
791 return shadow_page_to_ppgtt_spt(p
);
793 gvt_vgpu_err("fail to find ppgtt shadow page: 0x%lx\n", mfn
);
797 #define pt_entry_size_shift(spt) \
798 ((spt)->vgpu->gvt->device_info.gtt_entry_size_shift)
800 #define pt_entries(spt) \
801 (GTT_PAGE_SIZE >> pt_entry_size_shift(spt))
803 #define for_each_present_guest_entry(spt, e, i) \
804 for (i = 0; i < pt_entries(spt); i++) \
805 if (!ppgtt_get_guest_entry(spt, e, i) && \
806 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
808 #define for_each_present_shadow_entry(spt, e, i) \
809 for (i = 0; i < pt_entries(spt); i++) \
810 if (!ppgtt_get_shadow_entry(spt, e, i) && \
811 spt->vgpu->gvt->gtt.pte_ops->test_present(e))
813 static void ppgtt_get_shadow_page(struct intel_vgpu_ppgtt_spt
*spt
)
815 int v
= atomic_read(&spt
->refcount
);
817 trace_spt_refcount(spt
->vgpu
->id
, "inc", spt
, v
, (v
+ 1));
819 atomic_inc(&spt
->refcount
);
822 static int ppgtt_invalidate_shadow_page(struct intel_vgpu_ppgtt_spt
*spt
);
824 static int ppgtt_invalidate_shadow_page_by_shadow_entry(struct intel_vgpu
*vgpu
,
825 struct intel_gvt_gtt_entry
*e
)
827 struct intel_gvt_gtt_pte_ops
*ops
= vgpu
->gvt
->gtt
.pte_ops
;
828 struct intel_vgpu_ppgtt_spt
*s
;
829 intel_gvt_gtt_type_t cur_pt_type
;
831 if (WARN_ON(!gtt_type_is_pt(get_next_pt_type(e
->type
))))
834 if (e
->type
!= GTT_TYPE_PPGTT_ROOT_L3_ENTRY
835 && e
->type
!= GTT_TYPE_PPGTT_ROOT_L4_ENTRY
) {
836 cur_pt_type
= get_next_pt_type(e
->type
) + 1;
837 if (ops
->get_pfn(e
) ==
838 vgpu
->gtt
.scratch_pt
[cur_pt_type
].page_mfn
)
841 s
= ppgtt_find_shadow_page(vgpu
, ops
->get_pfn(e
));
843 gvt_vgpu_err("fail to find shadow page: mfn: 0x%lx\n",
847 return ppgtt_invalidate_shadow_page(s
);
850 static int ppgtt_invalidate_shadow_page(struct intel_vgpu_ppgtt_spt
*spt
)
852 struct intel_vgpu
*vgpu
= spt
->vgpu
;
853 struct intel_gvt_gtt_entry e
;
856 int v
= atomic_read(&spt
->refcount
);
858 trace_spt_change(spt
->vgpu
->id
, "die", spt
,
859 spt
->guest_page
.gfn
, spt
->shadow_page
.type
);
861 trace_spt_refcount(spt
->vgpu
->id
, "dec", spt
, v
, (v
- 1));
863 if (atomic_dec_return(&spt
->refcount
) > 0)
866 if (gtt_type_is_pte_pt(spt
->shadow_page
.type
))
869 for_each_present_shadow_entry(spt
, &e
, index
) {
870 if (!gtt_type_is_pt(get_next_pt_type(e
.type
))) {
871 gvt_vgpu_err("GVT doesn't support pse bit for now\n");
874 ret
= ppgtt_invalidate_shadow_page_by_shadow_entry(
880 trace_spt_change(spt
->vgpu
->id
, "release", spt
,
881 spt
->guest_page
.gfn
, spt
->shadow_page
.type
);
882 ppgtt_free_shadow_page(spt
);
885 gvt_vgpu_err("fail: shadow page %p shadow entry 0x%llx type %d\n",
886 spt
, e
.val64
, e
.type
);
890 static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt
*spt
);
892 static struct intel_vgpu_ppgtt_spt
*ppgtt_populate_shadow_page_by_guest_entry(
893 struct intel_vgpu
*vgpu
, struct intel_gvt_gtt_entry
*we
)
895 struct intel_gvt_gtt_pte_ops
*ops
= vgpu
->gvt
->gtt
.pte_ops
;
896 struct intel_vgpu_ppgtt_spt
*s
= NULL
;
897 struct intel_vgpu_guest_page
*g
;
900 if (WARN_ON(!gtt_type_is_pt(get_next_pt_type(we
->type
)))) {
905 g
= intel_vgpu_find_guest_page(vgpu
, ops
->get_pfn(we
));
907 s
= guest_page_to_ppgtt_spt(g
);
908 ppgtt_get_shadow_page(s
);
910 int type
= get_next_pt_type(we
->type
);
912 s
= ppgtt_alloc_shadow_page(vgpu
, type
, ops
->get_pfn(we
));
918 ret
= intel_gvt_hypervisor_set_wp_page(vgpu
, &s
->guest_page
);
922 ret
= ppgtt_populate_shadow_page(s
);
926 trace_spt_change(vgpu
->id
, "new", s
, s
->guest_page
.gfn
,
927 s
->shadow_page
.type
);
931 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
932 s
, we
->val64
, we
->type
);
936 static inline void ppgtt_generate_shadow_entry(struct intel_gvt_gtt_entry
*se
,
937 struct intel_vgpu_ppgtt_spt
*s
, struct intel_gvt_gtt_entry
*ge
)
939 struct intel_gvt_gtt_pte_ops
*ops
= s
->vgpu
->gvt
->gtt
.pte_ops
;
942 se
->val64
= ge
->val64
;
944 ops
->set_pfn(se
, s
->shadow_page
.mfn
);
947 static int ppgtt_populate_shadow_page(struct intel_vgpu_ppgtt_spt
*spt
)
949 struct intel_vgpu
*vgpu
= spt
->vgpu
;
950 struct intel_vgpu_ppgtt_spt
*s
;
951 struct intel_gvt_gtt_entry se
, ge
;
955 trace_spt_change(spt
->vgpu
->id
, "born", spt
,
956 spt
->guest_page
.gfn
, spt
->shadow_page
.type
);
958 if (gtt_type_is_pte_pt(spt
->shadow_page
.type
)) {
959 for_each_present_guest_entry(spt
, &ge
, i
) {
960 ret
= gtt_entry_p2m(vgpu
, &ge
, &se
);
963 ppgtt_set_shadow_entry(spt
, &se
, i
);
968 for_each_present_guest_entry(spt
, &ge
, i
) {
969 if (!gtt_type_is_pt(get_next_pt_type(ge
.type
))) {
970 gvt_vgpu_err("GVT doesn't support pse bit now\n");
975 s
= ppgtt_populate_shadow_page_by_guest_entry(vgpu
, &ge
);
980 ppgtt_get_shadow_entry(spt
, &se
, i
);
981 ppgtt_generate_shadow_entry(&se
, s
, &ge
);
982 ppgtt_set_shadow_entry(spt
, &se
, i
);
986 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
987 spt
, ge
.val64
, ge
.type
);
991 static int ppgtt_handle_guest_entry_removal(struct intel_vgpu_guest_page
*gpt
,
992 struct intel_gvt_gtt_entry
*se
, unsigned long index
)
994 struct intel_vgpu_ppgtt_spt
*spt
= guest_page_to_ppgtt_spt(gpt
);
995 struct intel_vgpu_shadow_page
*sp
= &spt
->shadow_page
;
996 struct intel_vgpu
*vgpu
= spt
->vgpu
;
997 struct intel_gvt_gtt_pte_ops
*ops
= vgpu
->gvt
->gtt
.pte_ops
;
1000 trace_gpt_change(spt
->vgpu
->id
, "remove", spt
, sp
->type
, se
->val64
,
1003 if (!ops
->test_present(se
))
1006 if (ops
->get_pfn(se
) == vgpu
->gtt
.scratch_pt
[sp
->type
].page_mfn
)
1009 if (gtt_type_is_pt(get_next_pt_type(se
->type
))) {
1010 struct intel_vgpu_ppgtt_spt
*s
=
1011 ppgtt_find_shadow_page(vgpu
, ops
->get_pfn(se
));
1013 gvt_vgpu_err("fail to find guest page\n");
1017 ret
= ppgtt_invalidate_shadow_page(s
);
1023 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d\n",
1024 spt
, se
->val64
, se
->type
);
1028 static int ppgtt_handle_guest_entry_add(struct intel_vgpu_guest_page
*gpt
,
1029 struct intel_gvt_gtt_entry
*we
, unsigned long index
)
1031 struct intel_vgpu_ppgtt_spt
*spt
= guest_page_to_ppgtt_spt(gpt
);
1032 struct intel_vgpu_shadow_page
*sp
= &spt
->shadow_page
;
1033 struct intel_vgpu
*vgpu
= spt
->vgpu
;
1034 struct intel_gvt_gtt_entry m
;
1035 struct intel_vgpu_ppgtt_spt
*s
;
1038 trace_gpt_change(spt
->vgpu
->id
, "add", spt
, sp
->type
,
1041 if (gtt_type_is_pt(get_next_pt_type(we
->type
))) {
1042 s
= ppgtt_populate_shadow_page_by_guest_entry(vgpu
, we
);
1047 ppgtt_get_shadow_entry(spt
, &m
, index
);
1048 ppgtt_generate_shadow_entry(&m
, s
, we
);
1049 ppgtt_set_shadow_entry(spt
, &m
, index
);
1051 ret
= gtt_entry_p2m(vgpu
, we
, &m
);
1054 ppgtt_set_shadow_entry(spt
, &m
, index
);
1058 gvt_vgpu_err("fail: spt %p guest entry 0x%llx type %d\n",
1059 spt
, we
->val64
, we
->type
);
1063 static int sync_oos_page(struct intel_vgpu
*vgpu
,
1064 struct intel_vgpu_oos_page
*oos_page
)
1066 const struct intel_gvt_device_info
*info
= &vgpu
->gvt
->device_info
;
1067 struct intel_gvt
*gvt
= vgpu
->gvt
;
1068 struct intel_gvt_gtt_pte_ops
*ops
= gvt
->gtt
.pte_ops
;
1069 struct intel_vgpu_ppgtt_spt
*spt
=
1070 guest_page_to_ppgtt_spt(oos_page
->guest_page
);
1071 struct intel_gvt_gtt_entry old
, new, m
;
1075 trace_oos_change(vgpu
->id
, "sync", oos_page
->id
,
1076 oos_page
->guest_page
, spt
->guest_page_type
);
1078 old
.type
= new.type
= get_entry_type(spt
->guest_page_type
);
1079 old
.val64
= new.val64
= 0;
1081 for (index
= 0; index
< (GTT_PAGE_SIZE
>> info
->gtt_entry_size_shift
);
1083 ops
->get_entry(oos_page
->mem
, &old
, index
, false, 0, vgpu
);
1084 ops
->get_entry(NULL
, &new, index
, true,
1085 oos_page
->guest_page
->gfn
<< PAGE_SHIFT
, vgpu
);
1087 if (old
.val64
== new.val64
1088 && !test_and_clear_bit(index
, spt
->post_shadow_bitmap
))
1091 trace_oos_sync(vgpu
->id
, oos_page
->id
,
1092 oos_page
->guest_page
, spt
->guest_page_type
,
1095 ret
= gtt_entry_p2m(vgpu
, &new, &m
);
1099 ops
->set_entry(oos_page
->mem
, &new, index
, false, 0, vgpu
);
1100 ppgtt_set_shadow_entry(spt
, &m
, index
);
1103 oos_page
->guest_page
->write_cnt
= 0;
1104 list_del_init(&spt
->post_shadow_list
);
1108 static int detach_oos_page(struct intel_vgpu
*vgpu
,
1109 struct intel_vgpu_oos_page
*oos_page
)
1111 struct intel_gvt
*gvt
= vgpu
->gvt
;
1112 struct intel_vgpu_ppgtt_spt
*spt
=
1113 guest_page_to_ppgtt_spt(oos_page
->guest_page
);
1115 trace_oos_change(vgpu
->id
, "detach", oos_page
->id
,
1116 oos_page
->guest_page
, spt
->guest_page_type
);
1118 oos_page
->guest_page
->write_cnt
= 0;
1119 oos_page
->guest_page
->oos_page
= NULL
;
1120 oos_page
->guest_page
= NULL
;
1122 list_del_init(&oos_page
->vm_list
);
1123 list_move_tail(&oos_page
->list
, &gvt
->gtt
.oos_page_free_list_head
);
1128 static int attach_oos_page(struct intel_vgpu
*vgpu
,
1129 struct intel_vgpu_oos_page
*oos_page
,
1130 struct intel_vgpu_guest_page
*gpt
)
1132 struct intel_gvt
*gvt
= vgpu
->gvt
;
1135 ret
= intel_gvt_hypervisor_read_gpa(vgpu
, gpt
->gfn
<< GTT_PAGE_SHIFT
,
1136 oos_page
->mem
, GTT_PAGE_SIZE
);
1140 oos_page
->guest_page
= gpt
;
1141 gpt
->oos_page
= oos_page
;
1143 list_move_tail(&oos_page
->list
, &gvt
->gtt
.oos_page_use_list_head
);
1145 trace_oos_change(vgpu
->id
, "attach", gpt
->oos_page
->id
,
1146 gpt
, guest_page_to_ppgtt_spt(gpt
)->guest_page_type
);
1150 static int ppgtt_set_guest_page_sync(struct intel_vgpu
*vgpu
,
1151 struct intel_vgpu_guest_page
*gpt
)
1155 ret
= intel_gvt_hypervisor_set_wp_page(vgpu
, gpt
);
1159 trace_oos_change(vgpu
->id
, "set page sync", gpt
->oos_page
->id
,
1160 gpt
, guest_page_to_ppgtt_spt(gpt
)->guest_page_type
);
1162 list_del_init(&gpt
->oos_page
->vm_list
);
1163 return sync_oos_page(vgpu
, gpt
->oos_page
);
1166 static int ppgtt_allocate_oos_page(struct intel_vgpu
*vgpu
,
1167 struct intel_vgpu_guest_page
*gpt
)
1169 struct intel_gvt
*gvt
= vgpu
->gvt
;
1170 struct intel_gvt_gtt
*gtt
= &gvt
->gtt
;
1171 struct intel_vgpu_oos_page
*oos_page
= gpt
->oos_page
;
1174 WARN(oos_page
, "shadow PPGTT page has already has a oos page\n");
1176 if (list_empty(>t
->oos_page_free_list_head
)) {
1177 oos_page
= container_of(gtt
->oos_page_use_list_head
.next
,
1178 struct intel_vgpu_oos_page
, list
);
1179 ret
= ppgtt_set_guest_page_sync(vgpu
, oos_page
->guest_page
);
1182 ret
= detach_oos_page(vgpu
, oos_page
);
1186 oos_page
= container_of(gtt
->oos_page_free_list_head
.next
,
1187 struct intel_vgpu_oos_page
, list
);
1188 return attach_oos_page(vgpu
, oos_page
, gpt
);
1191 static int ppgtt_set_guest_page_oos(struct intel_vgpu
*vgpu
,
1192 struct intel_vgpu_guest_page
*gpt
)
1194 struct intel_vgpu_oos_page
*oos_page
= gpt
->oos_page
;
1196 if (WARN(!oos_page
, "shadow PPGTT page should have a oos page\n"))
1199 trace_oos_change(vgpu
->id
, "set page out of sync", gpt
->oos_page
->id
,
1200 gpt
, guest_page_to_ppgtt_spt(gpt
)->guest_page_type
);
1202 list_add_tail(&oos_page
->vm_list
, &vgpu
->gtt
.oos_page_list_head
);
1203 return intel_gvt_hypervisor_unset_wp_page(vgpu
, gpt
);
1207 * intel_vgpu_sync_oos_pages - sync all the out-of-synced shadow for vGPU
1210 * This function is called before submitting a guest workload to host,
1211 * to sync all the out-of-synced shadow for vGPU
1214 * Zero on success, negative error code if failed.
1216 int intel_vgpu_sync_oos_pages(struct intel_vgpu
*vgpu
)
1218 struct list_head
*pos
, *n
;
1219 struct intel_vgpu_oos_page
*oos_page
;
1222 if (!enable_out_of_sync
)
1225 list_for_each_safe(pos
, n
, &vgpu
->gtt
.oos_page_list_head
) {
1226 oos_page
= container_of(pos
,
1227 struct intel_vgpu_oos_page
, vm_list
);
1228 ret
= ppgtt_set_guest_page_sync(vgpu
, oos_page
->guest_page
);
1236 * The heart of PPGTT shadow page table.
1238 static int ppgtt_handle_guest_write_page_table(
1239 struct intel_vgpu_guest_page
*gpt
,
1240 struct intel_gvt_gtt_entry
*we
, unsigned long index
)
1242 struct intel_vgpu_ppgtt_spt
*spt
= guest_page_to_ppgtt_spt(gpt
);
1243 struct intel_vgpu
*vgpu
= spt
->vgpu
;
1244 int type
= spt
->shadow_page
.type
;
1245 struct intel_gvt_gtt_pte_ops
*ops
= vgpu
->gvt
->gtt
.pte_ops
;
1246 struct intel_gvt_gtt_entry se
;
1251 new_present
= ops
->test_present(we
);
1254 * Adding the new entry first and then removing the old one, that can
1255 * guarantee the ppgtt table is validated during the window between
1256 * adding and removal.
1258 ppgtt_get_shadow_entry(spt
, &se
, index
);
1261 ret
= ppgtt_handle_guest_entry_add(gpt
, we
, index
);
1266 ret
= ppgtt_handle_guest_entry_removal(gpt
, &se
, index
);
1271 ops
->set_pfn(&se
, vgpu
->gtt
.scratch_pt
[type
].page_mfn
);
1272 ppgtt_set_shadow_entry(spt
, &se
, index
);
1277 gvt_vgpu_err("fail: shadow page %p guest entry 0x%llx type %d.\n",
1278 spt
, we
->val64
, we
->type
);
1282 static inline bool can_do_out_of_sync(struct intel_vgpu_guest_page
*gpt
)
1284 return enable_out_of_sync
1285 && gtt_type_is_pte_pt(
1286 guest_page_to_ppgtt_spt(gpt
)->guest_page_type
)
1287 && gpt
->write_cnt
>= 2;
1290 static void ppgtt_set_post_shadow(struct intel_vgpu_ppgtt_spt
*spt
,
1291 unsigned long index
)
1293 set_bit(index
, spt
->post_shadow_bitmap
);
1294 if (!list_empty(&spt
->post_shadow_list
))
1297 list_add_tail(&spt
->post_shadow_list
,
1298 &spt
->vgpu
->gtt
.post_shadow_list_head
);
1302 * intel_vgpu_flush_post_shadow - flush the post shadow transactions
1305 * This function is called before submitting a guest workload to host,
1306 * to flush all the post shadows for a vGPU.
1309 * Zero on success, negative error code if failed.
1311 int intel_vgpu_flush_post_shadow(struct intel_vgpu
*vgpu
)
1313 struct list_head
*pos
, *n
;
1314 struct intel_vgpu_ppgtt_spt
*spt
;
1315 struct intel_gvt_gtt_entry ge
;
1316 unsigned long index
;
1319 list_for_each_safe(pos
, n
, &vgpu
->gtt
.post_shadow_list_head
) {
1320 spt
= container_of(pos
, struct intel_vgpu_ppgtt_spt
,
1323 for_each_set_bit(index
, spt
->post_shadow_bitmap
,
1324 GTT_ENTRY_NUM_IN_ONE_PAGE
) {
1325 ppgtt_get_guest_entry(spt
, &ge
, index
);
1327 ret
= ppgtt_handle_guest_write_page_table(
1328 &spt
->guest_page
, &ge
, index
);
1331 clear_bit(index
, spt
->post_shadow_bitmap
);
1333 list_del_init(&spt
->post_shadow_list
);
1338 static int ppgtt_handle_guest_write_page_table_bytes(void *gp
,
1339 u64 pa
, void *p_data
, int bytes
)
1341 struct intel_vgpu_guest_page
*gpt
= (struct intel_vgpu_guest_page
*)gp
;
1342 struct intel_vgpu_ppgtt_spt
*spt
= guest_page_to_ppgtt_spt(gpt
);
1343 struct intel_vgpu
*vgpu
= spt
->vgpu
;
1344 struct intel_gvt_gtt_pte_ops
*ops
= vgpu
->gvt
->gtt
.pte_ops
;
1345 const struct intel_gvt_device_info
*info
= &vgpu
->gvt
->device_info
;
1346 struct intel_gvt_gtt_entry we
, se
;
1347 unsigned long index
;
1350 index
= (pa
& (PAGE_SIZE
- 1)) >> info
->gtt_entry_size_shift
;
1352 ppgtt_get_guest_entry(spt
, &we
, index
);
1356 if (bytes
== info
->gtt_entry_size
) {
1357 ret
= ppgtt_handle_guest_write_page_table(gpt
, &we
, index
);
1361 if (!test_bit(index
, spt
->post_shadow_bitmap
)) {
1362 ppgtt_get_shadow_entry(spt
, &se
, index
);
1363 ret
= ppgtt_handle_guest_entry_removal(gpt
, &se
, index
);
1368 ppgtt_set_post_shadow(spt
, index
);
1371 if (!enable_out_of_sync
)
1377 ops
->set_entry(gpt
->oos_page
->mem
, &we
, index
,
1380 if (can_do_out_of_sync(gpt
)) {
1382 ppgtt_allocate_oos_page(vgpu
, gpt
);
1384 ret
= ppgtt_set_guest_page_oos(vgpu
, gpt
);
1392 * mm page table allocation policy for bdw+
1393 * - for ggtt, only virtual page table will be allocated.
1394 * - for ppgtt, dedicated virtual/shadow page table will be allocated.
1396 static int gen8_mm_alloc_page_table(struct intel_vgpu_mm
*mm
)
1398 struct intel_vgpu
*vgpu
= mm
->vgpu
;
1399 struct intel_gvt
*gvt
= vgpu
->gvt
;
1400 const struct intel_gvt_device_info
*info
= &gvt
->device_info
;
1403 if (mm
->type
== INTEL_GVT_MM_PPGTT
) {
1404 mm
->page_table_entry_cnt
= 4;
1405 mm
->page_table_entry_size
= mm
->page_table_entry_cnt
*
1406 info
->gtt_entry_size
;
1407 mem
= kzalloc(mm
->has_shadow_page_table
?
1408 mm
->page_table_entry_size
* 2
1409 : mm
->page_table_entry_size
, GFP_KERNEL
);
1412 mm
->virtual_page_table
= mem
;
1413 if (!mm
->has_shadow_page_table
)
1415 mm
->shadow_page_table
= mem
+ mm
->page_table_entry_size
;
1416 } else if (mm
->type
== INTEL_GVT_MM_GGTT
) {
1417 mm
->page_table_entry_cnt
=
1418 (gvt_ggtt_gm_sz(gvt
) >> GTT_PAGE_SHIFT
);
1419 mm
->page_table_entry_size
= mm
->page_table_entry_cnt
*
1420 info
->gtt_entry_size
;
1421 mem
= vzalloc(mm
->page_table_entry_size
);
1424 mm
->virtual_page_table
= mem
;
1429 static void gen8_mm_free_page_table(struct intel_vgpu_mm
*mm
)
1431 if (mm
->type
== INTEL_GVT_MM_PPGTT
) {
1432 kfree(mm
->virtual_page_table
);
1433 } else if (mm
->type
== INTEL_GVT_MM_GGTT
) {
1434 if (mm
->virtual_page_table
)
1435 vfree(mm
->virtual_page_table
);
1437 mm
->virtual_page_table
= mm
->shadow_page_table
= NULL
;
1440 static void invalidate_mm(struct intel_vgpu_mm
*mm
)
1442 struct intel_vgpu
*vgpu
= mm
->vgpu
;
1443 struct intel_gvt
*gvt
= vgpu
->gvt
;
1444 struct intel_gvt_gtt
*gtt
= &gvt
->gtt
;
1445 struct intel_gvt_gtt_pte_ops
*ops
= gtt
->pte_ops
;
1446 struct intel_gvt_gtt_entry se
;
1449 if (WARN_ON(!mm
->has_shadow_page_table
|| !mm
->shadowed
))
1452 for (i
= 0; i
< mm
->page_table_entry_cnt
; i
++) {
1453 ppgtt_get_shadow_root_entry(mm
, &se
, i
);
1454 if (!ops
->test_present(&se
))
1456 ppgtt_invalidate_shadow_page_by_shadow_entry(
1459 ppgtt_set_shadow_root_entry(mm
, &se
, i
);
1461 trace_gpt_change(vgpu
->id
, "destroy root pointer",
1462 NULL
, se
.type
, se
.val64
, i
);
1464 mm
->shadowed
= false;
1468 * intel_vgpu_destroy_mm - destroy a mm object
1469 * @mm: a kref object
1471 * This function is used to destroy a mm object for vGPU
1474 void intel_vgpu_destroy_mm(struct kref
*mm_ref
)
1476 struct intel_vgpu_mm
*mm
= container_of(mm_ref
, typeof(*mm
), ref
);
1477 struct intel_vgpu
*vgpu
= mm
->vgpu
;
1478 struct intel_gvt
*gvt
= vgpu
->gvt
;
1479 struct intel_gvt_gtt
*gtt
= &gvt
->gtt
;
1481 if (!mm
->initialized
)
1484 list_del(&mm
->list
);
1485 list_del(&mm
->lru_list
);
1487 if (mm
->has_shadow_page_table
)
1490 gtt
->mm_free_page_table(mm
);
1495 static int shadow_mm(struct intel_vgpu_mm
*mm
)
1497 struct intel_vgpu
*vgpu
= mm
->vgpu
;
1498 struct intel_gvt
*gvt
= vgpu
->gvt
;
1499 struct intel_gvt_gtt
*gtt
= &gvt
->gtt
;
1500 struct intel_gvt_gtt_pte_ops
*ops
= gtt
->pte_ops
;
1501 struct intel_vgpu_ppgtt_spt
*spt
;
1502 struct intel_gvt_gtt_entry ge
, se
;
1506 if (WARN_ON(!mm
->has_shadow_page_table
|| mm
->shadowed
))
1509 mm
->shadowed
= true;
1511 for (i
= 0; i
< mm
->page_table_entry_cnt
; i
++) {
1512 ppgtt_get_guest_root_entry(mm
, &ge
, i
);
1513 if (!ops
->test_present(&ge
))
1516 trace_gpt_change(vgpu
->id
, __func__
, NULL
,
1517 ge
.type
, ge
.val64
, i
);
1519 spt
= ppgtt_populate_shadow_page_by_guest_entry(vgpu
, &ge
);
1521 gvt_vgpu_err("fail to populate guest root pointer\n");
1525 ppgtt_generate_shadow_entry(&se
, spt
, &ge
);
1526 ppgtt_set_shadow_root_entry(mm
, &se
, i
);
1528 trace_gpt_change(vgpu
->id
, "populate root pointer",
1529 NULL
, se
.type
, se
.val64
, i
);
1538 * intel_vgpu_create_mm - create a mm object for a vGPU
1540 * @mm_type: mm object type, should be PPGTT or GGTT
1541 * @virtual_page_table: page table root pointers. Could be NULL if user wants
1542 * to populate shadow later.
1543 * @page_table_level: describe the page table level of the mm object
1544 * @pde_base_index: pde root pointer base in GGTT MMIO.
1546 * This function is used to create a mm object for a vGPU.
1549 * Zero on success, negative error code in pointer if failed.
1551 struct intel_vgpu_mm
*intel_vgpu_create_mm(struct intel_vgpu
*vgpu
,
1552 int mm_type
, void *virtual_page_table
, int page_table_level
,
1555 struct intel_gvt
*gvt
= vgpu
->gvt
;
1556 struct intel_gvt_gtt
*gtt
= &gvt
->gtt
;
1557 struct intel_vgpu_mm
*mm
;
1560 mm
= kzalloc(sizeof(*mm
), GFP_KERNEL
);
1568 if (page_table_level
== 1)
1569 mm
->page_table_entry_type
= GTT_TYPE_GGTT_PTE
;
1570 else if (page_table_level
== 3)
1571 mm
->page_table_entry_type
= GTT_TYPE_PPGTT_ROOT_L3_ENTRY
;
1572 else if (page_table_level
== 4)
1573 mm
->page_table_entry_type
= GTT_TYPE_PPGTT_ROOT_L4_ENTRY
;
1580 mm
->page_table_level
= page_table_level
;
1581 mm
->pde_base_index
= pde_base_index
;
1584 mm
->has_shadow_page_table
= !!(mm_type
== INTEL_GVT_MM_PPGTT
);
1586 kref_init(&mm
->ref
);
1587 atomic_set(&mm
->pincount
, 0);
1588 INIT_LIST_HEAD(&mm
->list
);
1589 INIT_LIST_HEAD(&mm
->lru_list
);
1590 list_add_tail(&mm
->list
, &vgpu
->gtt
.mm_list_head
);
1592 ret
= gtt
->mm_alloc_page_table(mm
);
1594 gvt_vgpu_err("fail to allocate page table for mm\n");
1598 mm
->initialized
= true;
1600 if (virtual_page_table
)
1601 memcpy(mm
->virtual_page_table
, virtual_page_table
,
1602 mm
->page_table_entry_size
);
1604 if (mm
->has_shadow_page_table
) {
1605 ret
= shadow_mm(mm
);
1608 list_add_tail(&mm
->lru_list
, &gvt
->gtt
.mm_lru_list_head
);
1612 gvt_vgpu_err("fail to create mm\n");
1614 intel_gvt_mm_unreference(mm
);
1615 return ERR_PTR(ret
);
1619 * intel_vgpu_unpin_mm - decrease the pin count of a vGPU mm object
1620 * @mm: a vGPU mm object
1622 * This function is called when user doesn't want to use a vGPU mm object
1624 void intel_vgpu_unpin_mm(struct intel_vgpu_mm
*mm
)
1626 if (WARN_ON(mm
->type
!= INTEL_GVT_MM_PPGTT
))
1629 atomic_dec(&mm
->pincount
);
1633 * intel_vgpu_pin_mm - increase the pin count of a vGPU mm object
1636 * This function is called when user wants to use a vGPU mm object. If this
1637 * mm object hasn't been shadowed yet, the shadow will be populated at this
1641 * Zero on success, negative error code if failed.
1643 int intel_vgpu_pin_mm(struct intel_vgpu_mm
*mm
)
1647 if (WARN_ON(mm
->type
!= INTEL_GVT_MM_PPGTT
))
1650 if (!mm
->shadowed
) {
1651 ret
= shadow_mm(mm
);
1656 atomic_inc(&mm
->pincount
);
1657 list_del_init(&mm
->lru_list
);
1658 list_add_tail(&mm
->lru_list
, &mm
->vgpu
->gvt
->gtt
.mm_lru_list_head
);
1662 static int reclaim_one_mm(struct intel_gvt
*gvt
)
1664 struct intel_vgpu_mm
*mm
;
1665 struct list_head
*pos
, *n
;
1667 list_for_each_safe(pos
, n
, &gvt
->gtt
.mm_lru_list_head
) {
1668 mm
= container_of(pos
, struct intel_vgpu_mm
, lru_list
);
1670 if (mm
->type
!= INTEL_GVT_MM_PPGTT
)
1672 if (atomic_read(&mm
->pincount
))
1675 list_del_init(&mm
->lru_list
);
1683 * GMA translation APIs.
1685 static inline int ppgtt_get_next_level_entry(struct intel_vgpu_mm
*mm
,
1686 struct intel_gvt_gtt_entry
*e
, unsigned long index
, bool guest
)
1688 struct intel_vgpu
*vgpu
= mm
->vgpu
;
1689 struct intel_gvt_gtt_pte_ops
*ops
= vgpu
->gvt
->gtt
.pte_ops
;
1690 struct intel_vgpu_ppgtt_spt
*s
;
1692 if (WARN_ON(!mm
->has_shadow_page_table
))
1695 s
= ppgtt_find_shadow_page(vgpu
, ops
->get_pfn(e
));
1700 ppgtt_get_shadow_entry(s
, e
, index
);
1702 ppgtt_get_guest_entry(s
, e
, index
);
1707 * intel_vgpu_gma_to_gpa - translate a gma to GPA
1708 * @mm: mm object. could be a PPGTT or GGTT mm object
1709 * @gma: graphics memory address in this mm object
1711 * This function is used to translate a graphics memory address in specific
1712 * graphics memory space to guest physical address.
1715 * Guest physical address on success, INTEL_GVT_INVALID_ADDR if failed.
1717 unsigned long intel_vgpu_gma_to_gpa(struct intel_vgpu_mm
*mm
, unsigned long gma
)
1719 struct intel_vgpu
*vgpu
= mm
->vgpu
;
1720 struct intel_gvt
*gvt
= vgpu
->gvt
;
1721 struct intel_gvt_gtt_pte_ops
*pte_ops
= gvt
->gtt
.pte_ops
;
1722 struct intel_gvt_gtt_gma_ops
*gma_ops
= gvt
->gtt
.gma_ops
;
1723 unsigned long gpa
= INTEL_GVT_INVALID_ADDR
;
1724 unsigned long gma_index
[4];
1725 struct intel_gvt_gtt_entry e
;
1729 if (mm
->type
!= INTEL_GVT_MM_GGTT
&& mm
->type
!= INTEL_GVT_MM_PPGTT
)
1730 return INTEL_GVT_INVALID_ADDR
;
1732 if (mm
->type
== INTEL_GVT_MM_GGTT
) {
1733 if (!vgpu_gmadr_is_valid(vgpu
, gma
))
1736 ret
= ggtt_get_guest_entry(mm
, &e
,
1737 gma_ops
->gma_to_ggtt_pte_index(gma
));
1740 gpa
= (pte_ops
->get_pfn(&e
) << GTT_PAGE_SHIFT
)
1741 + (gma
& ~GTT_PAGE_MASK
);
1743 trace_gma_translate(vgpu
->id
, "ggtt", 0, 0, gma
, gpa
);
1747 switch (mm
->page_table_level
) {
1749 ret
= ppgtt_get_shadow_root_entry(mm
, &e
, 0);
1752 gma_index
[0] = gma_ops
->gma_to_pml4_index(gma
);
1753 gma_index
[1] = gma_ops
->gma_to_l4_pdp_index(gma
);
1754 gma_index
[2] = gma_ops
->gma_to_pde_index(gma
);
1755 gma_index
[3] = gma_ops
->gma_to_pte_index(gma
);
1759 ret
= ppgtt_get_shadow_root_entry(mm
, &e
,
1760 gma_ops
->gma_to_l3_pdp_index(gma
));
1763 gma_index
[0] = gma_ops
->gma_to_pde_index(gma
);
1764 gma_index
[1] = gma_ops
->gma_to_pte_index(gma
);
1768 ret
= ppgtt_get_shadow_root_entry(mm
, &e
,
1769 gma_ops
->gma_to_pde_index(gma
));
1772 gma_index
[0] = gma_ops
->gma_to_pte_index(gma
);
1780 /* walk into the shadow page table and get gpa from guest entry */
1781 for (i
= 0; i
< index
; i
++) {
1782 ret
= ppgtt_get_next_level_entry(mm
, &e
, gma_index
[i
],
1787 if (!pte_ops
->test_present(&e
)) {
1788 gvt_dbg_core("GMA 0x%lx is not present\n", gma
);
1793 gpa
= (pte_ops
->get_pfn(&e
) << GTT_PAGE_SHIFT
)
1794 + (gma
& ~GTT_PAGE_MASK
);
1796 trace_gma_translate(vgpu
->id
, "ppgtt", 0,
1797 mm
->page_table_level
, gma
, gpa
);
1800 gvt_vgpu_err("invalid mm type: %d gma %lx\n", mm
->type
, gma
);
1801 return INTEL_GVT_INVALID_ADDR
;
1804 static int emulate_gtt_mmio_read(struct intel_vgpu
*vgpu
,
1805 unsigned int off
, void *p_data
, unsigned int bytes
)
1807 struct intel_vgpu_mm
*ggtt_mm
= vgpu
->gtt
.ggtt_mm
;
1808 const struct intel_gvt_device_info
*info
= &vgpu
->gvt
->device_info
;
1809 unsigned long index
= off
>> info
->gtt_entry_size_shift
;
1810 struct intel_gvt_gtt_entry e
;
1812 if (bytes
!= 4 && bytes
!= 8)
1815 ggtt_get_guest_entry(ggtt_mm
, &e
, index
);
1816 memcpy(p_data
, (void *)&e
.val64
+ (off
& (info
->gtt_entry_size
- 1)),
1822 * intel_vgpu_emulate_gtt_mmio_read - emulate GTT MMIO register read
1824 * @off: register offset
1825 * @p_data: data will be returned to guest
1826 * @bytes: data length
1828 * This function is used to emulate the GTT MMIO register read
1831 * Zero on success, error code if failed.
1833 int intel_vgpu_emulate_gtt_mmio_read(struct intel_vgpu
*vgpu
, unsigned int off
,
1834 void *p_data
, unsigned int bytes
)
1836 const struct intel_gvt_device_info
*info
= &vgpu
->gvt
->device_info
;
1839 if (bytes
!= 4 && bytes
!= 8)
1842 off
-= info
->gtt_start_offset
;
1843 ret
= emulate_gtt_mmio_read(vgpu
, off
, p_data
, bytes
);
1847 static int emulate_gtt_mmio_write(struct intel_vgpu
*vgpu
, unsigned int off
,
1848 void *p_data
, unsigned int bytes
)
1850 struct intel_gvt
*gvt
= vgpu
->gvt
;
1851 const struct intel_gvt_device_info
*info
= &gvt
->device_info
;
1852 struct intel_vgpu_mm
*ggtt_mm
= vgpu
->gtt
.ggtt_mm
;
1853 struct intel_gvt_gtt_pte_ops
*ops
= gvt
->gtt
.pte_ops
;
1854 unsigned long g_gtt_index
= off
>> info
->gtt_entry_size_shift
;
1856 struct intel_gvt_gtt_entry e
, m
;
1859 if (bytes
!= 4 && bytes
!= 8)
1862 gma
= g_gtt_index
<< GTT_PAGE_SHIFT
;
1864 /* the VM may configure the whole GM space when ballooning is used */
1865 if (!vgpu_gmadr_is_valid(vgpu
, gma
))
1868 ggtt_get_guest_entry(ggtt_mm
, &e
, g_gtt_index
);
1870 memcpy((void *)&e
.val64
+ (off
& (info
->gtt_entry_size
- 1)), p_data
,
1873 if (ops
->test_present(&e
)) {
1874 ret
= gtt_entry_p2m(vgpu
, &e
, &m
);
1876 gvt_vgpu_err("fail to translate guest gtt entry\n");
1877 /* guest driver may read/write the entry when partial
1878 * update the entry in this situation p2m will fail
1879 * settting the shadow entry to point to a scratch page
1881 ops
->set_pfn(&m
, gvt
->gtt
.scratch_ggtt_mfn
);
1885 ops
->set_pfn(&m
, gvt
->gtt
.scratch_ggtt_mfn
);
1888 ggtt_set_shadow_entry(ggtt_mm
, &m
, g_gtt_index
);
1889 gtt_invalidate(gvt
->dev_priv
);
1890 ggtt_set_guest_entry(ggtt_mm
, &e
, g_gtt_index
);
1895 * intel_vgpu_emulate_gtt_mmio_write - emulate GTT MMIO register write
1897 * @off: register offset
1898 * @p_data: data from guest write
1899 * @bytes: data length
1901 * This function is used to emulate the GTT MMIO register write
1904 * Zero on success, error code if failed.
1906 int intel_vgpu_emulate_gtt_mmio_write(struct intel_vgpu
*vgpu
, unsigned int off
,
1907 void *p_data
, unsigned int bytes
)
1909 const struct intel_gvt_device_info
*info
= &vgpu
->gvt
->device_info
;
1912 if (bytes
!= 4 && bytes
!= 8)
1915 off
-= info
->gtt_start_offset
;
1916 ret
= emulate_gtt_mmio_write(vgpu
, off
, p_data
, bytes
);
1920 static int alloc_scratch_pages(struct intel_vgpu
*vgpu
,
1921 intel_gvt_gtt_type_t type
)
1923 struct intel_vgpu_gtt
*gtt
= &vgpu
->gtt
;
1924 struct intel_gvt_gtt_pte_ops
*ops
= vgpu
->gvt
->gtt
.pte_ops
;
1925 int page_entry_num
= GTT_PAGE_SIZE
>>
1926 vgpu
->gvt
->device_info
.gtt_entry_size_shift
;
1929 struct device
*dev
= &vgpu
->gvt
->dev_priv
->drm
.pdev
->dev
;
1932 if (WARN_ON(type
< GTT_TYPE_PPGTT_PTE_PT
|| type
>= GTT_TYPE_MAX
))
1935 scratch_pt
= (void *)get_zeroed_page(GFP_KERNEL
);
1937 gvt_vgpu_err("fail to allocate scratch page\n");
1941 daddr
= dma_map_page(dev
, virt_to_page(scratch_pt
), 0,
1942 4096, PCI_DMA_BIDIRECTIONAL
);
1943 if (dma_mapping_error(dev
, daddr
)) {
1944 gvt_vgpu_err("fail to dmamap scratch_pt\n");
1945 __free_page(virt_to_page(scratch_pt
));
1948 gtt
->scratch_pt
[type
].page_mfn
=
1949 (unsigned long)(daddr
>> GTT_PAGE_SHIFT
);
1950 gtt
->scratch_pt
[type
].page
= virt_to_page(scratch_pt
);
1951 gvt_dbg_mm("vgpu%d create scratch_pt: type %d mfn=0x%lx\n",
1952 vgpu
->id
, type
, gtt
->scratch_pt
[type
].page_mfn
);
1954 /* Build the tree by full filled the scratch pt with the entries which
1955 * point to the next level scratch pt or scratch page. The
1956 * scratch_pt[type] indicate the scratch pt/scratch page used by the
1958 * e.g. scratch_pt[GTT_TYPE_PPGTT_PDE_PT] is used by
1959 * GTT_TYPE_PPGTT_PDE_PT level pt, that means this scratch_pt it self
1960 * is GTT_TYPE_PPGTT_PTE_PT, and full filled by scratch page mfn.
1962 if (type
> GTT_TYPE_PPGTT_PTE_PT
&& type
< GTT_TYPE_MAX
) {
1963 struct intel_gvt_gtt_entry se
;
1965 memset(&se
, 0, sizeof(struct intel_gvt_gtt_entry
));
1966 se
.type
= get_entry_type(type
- 1);
1967 ops
->set_pfn(&se
, gtt
->scratch_pt
[type
- 1].page_mfn
);
1969 /* The entry parameters like present/writeable/cache type
1970 * set to the same as i915's scratch page tree.
1972 se
.val64
|= _PAGE_PRESENT
| _PAGE_RW
;
1973 if (type
== GTT_TYPE_PPGTT_PDE_PT
)
1974 se
.val64
|= PPAT_CACHED
;
1976 for (i
= 0; i
< page_entry_num
; i
++)
1977 ops
->set_entry(scratch_pt
, &se
, i
, false, 0, vgpu
);
1983 static int release_scratch_page_tree(struct intel_vgpu
*vgpu
)
1986 struct device
*dev
= &vgpu
->gvt
->dev_priv
->drm
.pdev
->dev
;
1989 for (i
= GTT_TYPE_PPGTT_PTE_PT
; i
< GTT_TYPE_MAX
; i
++) {
1990 if (vgpu
->gtt
.scratch_pt
[i
].page
!= NULL
) {
1991 daddr
= (dma_addr_t
)(vgpu
->gtt
.scratch_pt
[i
].page_mfn
<<
1993 dma_unmap_page(dev
, daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
1994 __free_page(vgpu
->gtt
.scratch_pt
[i
].page
);
1995 vgpu
->gtt
.scratch_pt
[i
].page
= NULL
;
1996 vgpu
->gtt
.scratch_pt
[i
].page_mfn
= 0;
2003 static int create_scratch_page_tree(struct intel_vgpu
*vgpu
)
2007 for (i
= GTT_TYPE_PPGTT_PTE_PT
; i
< GTT_TYPE_MAX
; i
++) {
2008 ret
= alloc_scratch_pages(vgpu
, i
);
2016 release_scratch_page_tree(vgpu
);
2021 * intel_vgpu_init_gtt - initialize per-vGPU graphics memory virulization
2024 * This function is used to initialize per-vGPU graphics memory virtualization
2028 * Zero on success, error code if failed.
2030 int intel_vgpu_init_gtt(struct intel_vgpu
*vgpu
)
2032 struct intel_vgpu_gtt
*gtt
= &vgpu
->gtt
;
2033 struct intel_vgpu_mm
*ggtt_mm
;
2035 hash_init(gtt
->guest_page_hash_table
);
2036 hash_init(gtt
->shadow_page_hash_table
);
2038 INIT_LIST_HEAD(>t
->mm_list_head
);
2039 INIT_LIST_HEAD(>t
->oos_page_list_head
);
2040 INIT_LIST_HEAD(>t
->post_shadow_list_head
);
2042 intel_vgpu_reset_ggtt(vgpu
);
2044 ggtt_mm
= intel_vgpu_create_mm(vgpu
, INTEL_GVT_MM_GGTT
,
2046 if (IS_ERR(ggtt_mm
)) {
2047 gvt_vgpu_err("fail to create mm for ggtt.\n");
2048 return PTR_ERR(ggtt_mm
);
2051 gtt
->ggtt_mm
= ggtt_mm
;
2053 return create_scratch_page_tree(vgpu
);
2056 static void intel_vgpu_free_mm(struct intel_vgpu
*vgpu
, int type
)
2058 struct list_head
*pos
, *n
;
2059 struct intel_vgpu_mm
*mm
;
2061 list_for_each_safe(pos
, n
, &vgpu
->gtt
.mm_list_head
) {
2062 mm
= container_of(pos
, struct intel_vgpu_mm
, list
);
2063 if (mm
->type
== type
) {
2064 vgpu
->gvt
->gtt
.mm_free_page_table(mm
);
2065 list_del(&mm
->list
);
2066 list_del(&mm
->lru_list
);
2073 * intel_vgpu_clean_gtt - clean up per-vGPU graphics memory virulization
2076 * This function is used to clean up per-vGPU graphics memory virtualization
2080 * Zero on success, error code if failed.
2082 void intel_vgpu_clean_gtt(struct intel_vgpu
*vgpu
)
2084 ppgtt_free_all_shadow_page(vgpu
);
2085 release_scratch_page_tree(vgpu
);
2087 intel_vgpu_free_mm(vgpu
, INTEL_GVT_MM_PPGTT
);
2088 intel_vgpu_free_mm(vgpu
, INTEL_GVT_MM_GGTT
);
2091 static void clean_spt_oos(struct intel_gvt
*gvt
)
2093 struct intel_gvt_gtt
*gtt
= &gvt
->gtt
;
2094 struct list_head
*pos
, *n
;
2095 struct intel_vgpu_oos_page
*oos_page
;
2097 WARN(!list_empty(>t
->oos_page_use_list_head
),
2098 "someone is still using oos page\n");
2100 list_for_each_safe(pos
, n
, >t
->oos_page_free_list_head
) {
2101 oos_page
= container_of(pos
, struct intel_vgpu_oos_page
, list
);
2102 list_del(&oos_page
->list
);
2107 static int setup_spt_oos(struct intel_gvt
*gvt
)
2109 struct intel_gvt_gtt
*gtt
= &gvt
->gtt
;
2110 struct intel_vgpu_oos_page
*oos_page
;
2114 INIT_LIST_HEAD(>t
->oos_page_free_list_head
);
2115 INIT_LIST_HEAD(>t
->oos_page_use_list_head
);
2117 for (i
= 0; i
< preallocated_oos_pages
; i
++) {
2118 oos_page
= kzalloc(sizeof(*oos_page
), GFP_KERNEL
);
2124 INIT_LIST_HEAD(&oos_page
->list
);
2125 INIT_LIST_HEAD(&oos_page
->vm_list
);
2127 list_add_tail(&oos_page
->list
, >t
->oos_page_free_list_head
);
2130 gvt_dbg_mm("%d oos pages preallocated\n", i
);
2139 * intel_vgpu_find_ppgtt_mm - find a PPGTT mm object
2141 * @page_table_level: PPGTT page table level
2142 * @root_entry: PPGTT page table root pointers
2144 * This function is used to find a PPGTT mm object from mm object pool
2147 * pointer to mm object on success, NULL if failed.
2149 struct intel_vgpu_mm
*intel_vgpu_find_ppgtt_mm(struct intel_vgpu
*vgpu
,
2150 int page_table_level
, void *root_entry
)
2152 struct list_head
*pos
;
2153 struct intel_vgpu_mm
*mm
;
2156 list_for_each(pos
, &vgpu
->gtt
.mm_list_head
) {
2157 mm
= container_of(pos
, struct intel_vgpu_mm
, list
);
2158 if (mm
->type
!= INTEL_GVT_MM_PPGTT
)
2161 if (mm
->page_table_level
!= page_table_level
)
2165 dst
= mm
->virtual_page_table
;
2167 if (page_table_level
== 3) {
2168 if (src
[0] == dst
[0]
2171 && src
[3] == dst
[3])
2174 if (src
[0] == dst
[0])
2182 * intel_vgpu_g2v_create_ppgtt_mm - create a PPGTT mm object from
2185 * @page_table_level: PPGTT page table level
2187 * This function is used to create a PPGTT mm object from a guest to GVT-g
2191 * Zero on success, negative error code if failed.
2193 int intel_vgpu_g2v_create_ppgtt_mm(struct intel_vgpu
*vgpu
,
2194 int page_table_level
)
2196 u64
*pdp
= (u64
*)&vgpu_vreg64(vgpu
, vgtif_reg(pdp
[0]));
2197 struct intel_vgpu_mm
*mm
;
2199 if (WARN_ON((page_table_level
!= 4) && (page_table_level
!= 3)))
2202 mm
= intel_vgpu_find_ppgtt_mm(vgpu
, page_table_level
, pdp
);
2204 intel_gvt_mm_reference(mm
);
2206 mm
= intel_vgpu_create_mm(vgpu
, INTEL_GVT_MM_PPGTT
,
2207 pdp
, page_table_level
, 0);
2209 gvt_vgpu_err("fail to create mm\n");
2217 * intel_vgpu_g2v_destroy_ppgtt_mm - destroy a PPGTT mm object from
2220 * @page_table_level: PPGTT page table level
2222 * This function is used to create a PPGTT mm object from a guest to GVT-g
2226 * Zero on success, negative error code if failed.
2228 int intel_vgpu_g2v_destroy_ppgtt_mm(struct intel_vgpu
*vgpu
,
2229 int page_table_level
)
2231 u64
*pdp
= (u64
*)&vgpu_vreg64(vgpu
, vgtif_reg(pdp
[0]));
2232 struct intel_vgpu_mm
*mm
;
2234 if (WARN_ON((page_table_level
!= 4) && (page_table_level
!= 3)))
2237 mm
= intel_vgpu_find_ppgtt_mm(vgpu
, page_table_level
, pdp
);
2239 gvt_vgpu_err("fail to find ppgtt instance.\n");
2242 intel_gvt_mm_unreference(mm
);
2247 * intel_gvt_init_gtt - initialize mm components of a GVT device
2250 * This function is called at the initialization stage, to initialize
2251 * the mm components of a GVT device.
2254 * zero on success, negative error code if failed.
2256 int intel_gvt_init_gtt(struct intel_gvt
*gvt
)
2260 struct device
*dev
= &gvt
->dev_priv
->drm
.pdev
->dev
;
2263 gvt_dbg_core("init gtt\n");
2265 if (IS_BROADWELL(gvt
->dev_priv
) || IS_SKYLAKE(gvt
->dev_priv
)
2266 || IS_KABYLAKE(gvt
->dev_priv
)) {
2267 gvt
->gtt
.pte_ops
= &gen8_gtt_pte_ops
;
2268 gvt
->gtt
.gma_ops
= &gen8_gtt_gma_ops
;
2269 gvt
->gtt
.mm_alloc_page_table
= gen8_mm_alloc_page_table
;
2270 gvt
->gtt
.mm_free_page_table
= gen8_mm_free_page_table
;
2275 page
= (void *)get_zeroed_page(GFP_KERNEL
);
2277 gvt_err("fail to allocate scratch ggtt page\n");
2281 daddr
= dma_map_page(dev
, virt_to_page(page
), 0,
2282 4096, PCI_DMA_BIDIRECTIONAL
);
2283 if (dma_mapping_error(dev
, daddr
)) {
2284 gvt_err("fail to dmamap scratch ggtt page\n");
2285 __free_page(virt_to_page(page
));
2288 gvt
->gtt
.scratch_ggtt_page
= virt_to_page(page
);
2289 gvt
->gtt
.scratch_ggtt_mfn
= (unsigned long)(daddr
>> GTT_PAGE_SHIFT
);
2291 if (enable_out_of_sync
) {
2292 ret
= setup_spt_oos(gvt
);
2294 gvt_err("fail to initialize SPT oos\n");
2295 dma_unmap_page(dev
, daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
2296 __free_page(gvt
->gtt
.scratch_ggtt_page
);
2300 INIT_LIST_HEAD(&gvt
->gtt
.mm_lru_list_head
);
2305 * intel_gvt_clean_gtt - clean up mm components of a GVT device
2308 * This function is called at the driver unloading stage, to clean up the
2309 * the mm components of a GVT device.
2312 void intel_gvt_clean_gtt(struct intel_gvt
*gvt
)
2314 struct device
*dev
= &gvt
->dev_priv
->drm
.pdev
->dev
;
2315 dma_addr_t daddr
= (dma_addr_t
)(gvt
->gtt
.scratch_ggtt_mfn
<<
2318 dma_unmap_page(dev
, daddr
, 4096, PCI_DMA_BIDIRECTIONAL
);
2320 __free_page(gvt
->gtt
.scratch_ggtt_page
);
2322 if (enable_out_of_sync
)
2327 * intel_vgpu_reset_ggtt - reset the GGTT entry
2330 * This function is called at the vGPU create stage
2331 * to reset all the GGTT entries.
2334 void intel_vgpu_reset_ggtt(struct intel_vgpu
*vgpu
)
2336 struct intel_gvt
*gvt
= vgpu
->gvt
;
2337 struct drm_i915_private
*dev_priv
= gvt
->dev_priv
;
2338 struct intel_gvt_gtt_pte_ops
*ops
= vgpu
->gvt
->gtt
.pte_ops
;
2342 struct intel_gvt_gtt_entry e
;
2344 memset(&e
, 0, sizeof(struct intel_gvt_gtt_entry
));
2345 e
.type
= GTT_TYPE_GGTT_PTE
;
2346 ops
->set_pfn(&e
, gvt
->gtt
.scratch_ggtt_mfn
);
2347 e
.val64
|= _PAGE_PRESENT
;
2349 index
= vgpu_aperture_gmadr_base(vgpu
) >> PAGE_SHIFT
;
2350 num_entries
= vgpu_aperture_sz(vgpu
) >> PAGE_SHIFT
;
2351 for (offset
= 0; offset
< num_entries
; offset
++)
2352 ops
->set_entry(NULL
, &e
, index
+ offset
, false, 0, vgpu
);
2354 index
= vgpu_hidden_gmadr_base(vgpu
) >> PAGE_SHIFT
;
2355 num_entries
= vgpu_hidden_sz(vgpu
) >> PAGE_SHIFT
;
2356 for (offset
= 0; offset
< num_entries
; offset
++)
2357 ops
->set_entry(NULL
, &e
, index
+ offset
, false, 0, vgpu
);
2359 gtt_invalidate(dev_priv
);
2363 * intel_vgpu_reset_gtt - reset the all GTT related status
2366 * This function is called from vfio core to reset reset all
2367 * GTT related status, including GGTT, PPGTT, scratch page.
2370 void intel_vgpu_reset_gtt(struct intel_vgpu
*vgpu
)
2374 ppgtt_free_all_shadow_page(vgpu
);
2376 /* Shadow pages are only created when there is no page
2377 * table tracking data, so remove page tracking data after
2378 * removing the shadow pages.
2380 intel_vgpu_free_mm(vgpu
, INTEL_GVT_MM_PPGTT
);
2382 intel_vgpu_reset_ggtt(vgpu
);
2384 /* clear scratch page for security */
2385 for (i
= GTT_TYPE_PPGTT_PTE_PT
; i
< GTT_TYPE_MAX
; i
++) {
2386 if (vgpu
->gtt
.scratch_pt
[i
].page
!= NULL
)
2387 memset(page_address(vgpu
->gtt
.scratch_pt
[i
].page
),