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Merge tag 'drm-intel-next-2016-10-24' of git://anongit.freedesktop.org/drm-intel...
[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / i915 / gvt / handlers.c
1 /*
2 * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Kevin Tian <kevin.tian@intel.com>
25 * Eddie Dong <eddie.dong@intel.com>
26 * Zhiyuan Lv <zhiyuan.lv@intel.com>
27 *
28 * Contributors:
29 * Min He <min.he@intel.com>
30 * Tina Zhang <tina.zhang@intel.com>
31 * Pei Zhang <pei.zhang@intel.com>
32 * Niu Bing <bing.niu@intel.com>
33 * Ping Gao <ping.a.gao@intel.com>
34 * Zhi Wang <zhi.a.wang@intel.com>
35 *
36
37 */
38
39 #include "i915_drv.h"
40 #include "gvt.h"
41 #include "i915_pvinfo.h"
42
43 /* XXX FIXME i915 has changed PP_XXX definition */
44 #define PCH_PP_STATUS _MMIO(0xc7200)
45 #define PCH_PP_CONTROL _MMIO(0xc7204)
46 #define PCH_PP_ON_DELAYS _MMIO(0xc7208)
47 #define PCH_PP_OFF_DELAYS _MMIO(0xc720c)
48 #define PCH_PP_DIVISOR _MMIO(0xc7210)
49
50 /* Register contains RO bits */
51 #define F_RO (1 << 0)
52 /* Register contains graphics address */
53 #define F_GMADR (1 << 1)
54 /* Mode mask registers with high 16 bits as the mask bits */
55 #define F_MODE_MASK (1 << 2)
56 /* This reg can be accessed by GPU commands */
57 #define F_CMD_ACCESS (1 << 3)
58 /* This reg has been accessed by a VM */
59 #define F_ACCESSED (1 << 4)
60 /* This reg has been accessed through GPU commands */
61 #define F_CMD_ACCESSED (1 << 5)
62 /* This reg could be accessed by unaligned address */
63 #define F_UNALIGN (1 << 6)
64
65 unsigned long intel_gvt_get_device_type(struct intel_gvt *gvt)
66 {
67 if (IS_BROADWELL(gvt->dev_priv))
68 return D_BDW;
69 else if (IS_SKYLAKE(gvt->dev_priv))
70 return D_SKL;
71
72 return 0;
73 }
74
75 bool intel_gvt_match_device(struct intel_gvt *gvt,
76 unsigned long device)
77 {
78 return intel_gvt_get_device_type(gvt) & device;
79 }
80
81 static void read_vreg(struct intel_vgpu *vgpu, unsigned int offset,
82 void *p_data, unsigned int bytes)
83 {
84 memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
85 }
86
87 static void write_vreg(struct intel_vgpu *vgpu, unsigned int offset,
88 void *p_data, unsigned int bytes)
89 {
90 memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
91 }
92
93 static int new_mmio_info(struct intel_gvt *gvt,
94 u32 offset, u32 flags, u32 size,
95 u32 addr_mask, u32 ro_mask, u32 device,
96 void *read, void *write)
97 {
98 struct intel_gvt_mmio_info *info, *p;
99 u32 start, end, i;
100
101 if (!intel_gvt_match_device(gvt, device))
102 return 0;
103
104 if (WARN_ON(!IS_ALIGNED(offset, 4)))
105 return -EINVAL;
106
107 start = offset;
108 end = offset + size;
109
110 for (i = start; i < end; i += 4) {
111 info = kzalloc(sizeof(*info), GFP_KERNEL);
112 if (!info)
113 return -ENOMEM;
114
115 info->offset = i;
116 p = intel_gvt_find_mmio_info(gvt, info->offset);
117 if (p)
118 gvt_err("dup mmio definition offset %x\n",
119 info->offset);
120 info->size = size;
121 info->length = (i + 4) < end ? 4 : (end - i);
122 info->addr_mask = addr_mask;
123 info->device = device;
124 info->read = read ? read : intel_vgpu_default_mmio_read;
125 info->write = write ? write : intel_vgpu_default_mmio_write;
126 gvt->mmio.mmio_attribute[info->offset / 4] = flags;
127 INIT_HLIST_NODE(&info->node);
128 hash_add(gvt->mmio.mmio_info_table, &info->node, info->offset);
129 }
130 return 0;
131 }
132
133 static int render_mmio_to_ring_id(struct intel_gvt *gvt, unsigned int reg)
134 {
135 enum intel_engine_id id;
136 struct intel_engine_cs *engine;
137
138 reg &= ~GENMASK(11, 0);
139 for_each_engine(engine, gvt->dev_priv, id) {
140 if (engine->mmio_base == reg)
141 return id;
142 }
143 return -1;
144 }
145
146 #define offset_to_fence_num(offset) \
147 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
148
149 #define fence_num_to_offset(num) \
150 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
151
152 static int sanitize_fence_mmio_access(struct intel_vgpu *vgpu,
153 unsigned int fence_num, void *p_data, unsigned int bytes)
154 {
155 if (fence_num >= vgpu_fence_sz(vgpu)) {
156 gvt_err("vgpu%d: found oob fence register access\n",
157 vgpu->id);
158 gvt_err("vgpu%d: total fence num %d access fence num %d\n",
159 vgpu->id, vgpu_fence_sz(vgpu), fence_num);
160 memset(p_data, 0, bytes);
161 }
162 return 0;
163 }
164
165 static int fence_mmio_read(struct intel_vgpu *vgpu, unsigned int off,
166 void *p_data, unsigned int bytes)
167 {
168 int ret;
169
170 ret = sanitize_fence_mmio_access(vgpu, offset_to_fence_num(off),
171 p_data, bytes);
172 if (ret)
173 return ret;
174 read_vreg(vgpu, off, p_data, bytes);
175 return 0;
176 }
177
178 static int fence_mmio_write(struct intel_vgpu *vgpu, unsigned int off,
179 void *p_data, unsigned int bytes)
180 {
181 unsigned int fence_num = offset_to_fence_num(off);
182 int ret;
183
184 ret = sanitize_fence_mmio_access(vgpu, fence_num, p_data, bytes);
185 if (ret)
186 return ret;
187 write_vreg(vgpu, off, p_data, bytes);
188
189 intel_vgpu_write_fence(vgpu, fence_num,
190 vgpu_vreg64(vgpu, fence_num_to_offset(fence_num)));
191 return 0;
192 }
193
194 #define CALC_MODE_MASK_REG(old, new) \
195 (((new) & GENMASK(31, 16)) \
196 | ((((old) & GENMASK(15, 0)) & ~((new) >> 16)) \
197 | ((new) & ((new) >> 16))))
198
199 static int mul_force_wake_write(struct intel_vgpu *vgpu,
200 unsigned int offset, void *p_data, unsigned int bytes)
201 {
202 u32 old, new;
203 uint32_t ack_reg_offset;
204
205 old = vgpu_vreg(vgpu, offset);
206 new = CALC_MODE_MASK_REG(old, *(u32 *)p_data);
207
208 if (IS_SKYLAKE(vgpu->gvt->dev_priv)) {
209 switch (offset) {
210 case FORCEWAKE_RENDER_GEN9_REG:
211 ack_reg_offset = FORCEWAKE_ACK_RENDER_GEN9_REG;
212 break;
213 case FORCEWAKE_BLITTER_GEN9_REG:
214 ack_reg_offset = FORCEWAKE_ACK_BLITTER_GEN9_REG;
215 break;
216 case FORCEWAKE_MEDIA_GEN9_REG:
217 ack_reg_offset = FORCEWAKE_ACK_MEDIA_GEN9_REG;
218 break;
219 default:
220 /*should not hit here*/
221 gvt_err("invalid forcewake offset 0x%x\n", offset);
222 return 1;
223 }
224 } else {
225 ack_reg_offset = FORCEWAKE_ACK_HSW_REG;
226 }
227
228 vgpu_vreg(vgpu, offset) = new;
229 vgpu_vreg(vgpu, ack_reg_offset) = (new & GENMASK(15, 0));
230 return 0;
231 }
232
233 static int handle_device_reset(struct intel_vgpu *vgpu, unsigned int offset,
234 void *p_data, unsigned int bytes, unsigned long bitmap)
235 {
236 struct intel_gvt_workload_scheduler *scheduler =
237 &vgpu->gvt->scheduler;
238
239 vgpu->resetting = true;
240
241 intel_vgpu_stop_schedule(vgpu);
242 if (scheduler->current_vgpu == vgpu) {
243 mutex_unlock(&vgpu->gvt->lock);
244 intel_gvt_wait_vgpu_idle(vgpu);
245 mutex_lock(&vgpu->gvt->lock);
246 }
247
248 intel_vgpu_reset_execlist(vgpu, bitmap);
249
250 vgpu->resetting = false;
251
252 return 0;
253 }
254
255 static int gdrst_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
256 void *p_data, unsigned int bytes)
257 {
258 u32 data;
259 u64 bitmap = 0;
260
261 data = vgpu_vreg(vgpu, offset);
262
263 if (data & GEN6_GRDOM_FULL) {
264 gvt_dbg_mmio("vgpu%d: request full GPU reset\n", vgpu->id);
265 bitmap = 0xff;
266 }
267 if (data & GEN6_GRDOM_RENDER) {
268 gvt_dbg_mmio("vgpu%d: request RCS reset\n", vgpu->id);
269 bitmap |= (1 << RCS);
270 }
271 if (data & GEN6_GRDOM_MEDIA) {
272 gvt_dbg_mmio("vgpu%d: request VCS reset\n", vgpu->id);
273 bitmap |= (1 << VCS);
274 }
275 if (data & GEN6_GRDOM_BLT) {
276 gvt_dbg_mmio("vgpu%d: request BCS Reset\n", vgpu->id);
277 bitmap |= (1 << BCS);
278 }
279 if (data & GEN6_GRDOM_VECS) {
280 gvt_dbg_mmio("vgpu%d: request VECS Reset\n", vgpu->id);
281 bitmap |= (1 << VECS);
282 }
283 if (data & GEN8_GRDOM_MEDIA2) {
284 gvt_dbg_mmio("vgpu%d: request VCS2 Reset\n", vgpu->id);
285 if (HAS_BSD2(vgpu->gvt->dev_priv))
286 bitmap |= (1 << VCS2);
287 }
288 return handle_device_reset(vgpu, offset, p_data, bytes, bitmap);
289 }
290
291 static int gmbus_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
292 void *p_data, unsigned int bytes)
293 {
294 return intel_gvt_i2c_handle_gmbus_read(vgpu, offset, p_data, bytes);
295 }
296
297 static int gmbus_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
298 void *p_data, unsigned int bytes)
299 {
300 return intel_gvt_i2c_handle_gmbus_write(vgpu, offset, p_data, bytes);
301 }
302
303 static int pch_pp_control_mmio_write(struct intel_vgpu *vgpu,
304 unsigned int offset, void *p_data, unsigned int bytes)
305 {
306 write_vreg(vgpu, offset, p_data, bytes);
307
308 if (vgpu_vreg(vgpu, offset) & PANEL_POWER_ON) {
309 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_ON;
310 vgpu_vreg(vgpu, PCH_PP_STATUS) |= PP_SEQUENCE_STATE_ON_IDLE;
311 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_SEQUENCE_POWER_DOWN;
312 vgpu_vreg(vgpu, PCH_PP_STATUS) &= ~PP_CYCLE_DELAY_ACTIVE;
313
314 } else
315 vgpu_vreg(vgpu, PCH_PP_STATUS) &=
316 ~(PP_ON | PP_SEQUENCE_POWER_DOWN
317 | PP_CYCLE_DELAY_ACTIVE);
318 return 0;
319 }
320
321 static int transconf_mmio_write(struct intel_vgpu *vgpu,
322 unsigned int offset, void *p_data, unsigned int bytes)
323 {
324 write_vreg(vgpu, offset, p_data, bytes);
325
326 if (vgpu_vreg(vgpu, offset) & TRANS_ENABLE)
327 vgpu_vreg(vgpu, offset) |= TRANS_STATE_ENABLE;
328 else
329 vgpu_vreg(vgpu, offset) &= ~TRANS_STATE_ENABLE;
330 return 0;
331 }
332
333 static int lcpll_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
334 void *p_data, unsigned int bytes)
335 {
336 write_vreg(vgpu, offset, p_data, bytes);
337
338 if (vgpu_vreg(vgpu, offset) & LCPLL_PLL_DISABLE)
339 vgpu_vreg(vgpu, offset) &= ~LCPLL_PLL_LOCK;
340 else
341 vgpu_vreg(vgpu, offset) |= LCPLL_PLL_LOCK;
342
343 if (vgpu_vreg(vgpu, offset) & LCPLL_CD_SOURCE_FCLK)
344 vgpu_vreg(vgpu, offset) |= LCPLL_CD_SOURCE_FCLK_DONE;
345 else
346 vgpu_vreg(vgpu, offset) &= ~LCPLL_CD_SOURCE_FCLK_DONE;
347
348 return 0;
349 }
350
351 static int dpy_reg_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
352 void *p_data, unsigned int bytes)
353 {
354 *(u32 *)p_data = (1 << 17);
355 return 0;
356 }
357
358 static int dpy_reg_mmio_read_2(struct intel_vgpu *vgpu, unsigned int offset,
359 void *p_data, unsigned int bytes)
360 {
361 *(u32 *)p_data = 3;
362 return 0;
363 }
364
365 static int dpy_reg_mmio_read_3(struct intel_vgpu *vgpu, unsigned int offset,
366 void *p_data, unsigned int bytes)
367 {
368 *(u32 *)p_data = (0x2f << 16);
369 return 0;
370 }
371
372 static int pipeconf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
373 void *p_data, unsigned int bytes)
374 {
375 u32 data;
376
377 write_vreg(vgpu, offset, p_data, bytes);
378 data = vgpu_vreg(vgpu, offset);
379
380 if (data & PIPECONF_ENABLE)
381 vgpu_vreg(vgpu, offset) |= I965_PIPECONF_ACTIVE;
382 else
383 vgpu_vreg(vgpu, offset) &= ~I965_PIPECONF_ACTIVE;
384 intel_gvt_check_vblank_emulation(vgpu->gvt);
385 return 0;
386 }
387
388 static int ddi_buf_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
389 void *p_data, unsigned int bytes)
390 {
391 write_vreg(vgpu, offset, p_data, bytes);
392
393 if (vgpu_vreg(vgpu, offset) & DDI_BUF_CTL_ENABLE) {
394 vgpu_vreg(vgpu, offset) &= ~DDI_BUF_IS_IDLE;
395 } else {
396 vgpu_vreg(vgpu, offset) |= DDI_BUF_IS_IDLE;
397 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E)))
398 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E))
399 &= ~DP_TP_STATUS_AUTOTRAIN_DONE;
400 }
401 return 0;
402 }
403
404 static int fdi_rx_iir_mmio_write(struct intel_vgpu *vgpu,
405 unsigned int offset, void *p_data, unsigned int bytes)
406 {
407 vgpu_vreg(vgpu, offset) &= ~*(u32 *)p_data;
408 return 0;
409 }
410
411 #define FDI_LINK_TRAIN_PATTERN1 0
412 #define FDI_LINK_TRAIN_PATTERN2 1
413
414 static int fdi_auto_training_started(struct intel_vgpu *vgpu)
415 {
416 u32 ddi_buf_ctl = vgpu_vreg(vgpu, DDI_BUF_CTL(PORT_E));
417 u32 rx_ctl = vgpu_vreg(vgpu, _FDI_RXA_CTL);
418 u32 tx_ctl = vgpu_vreg(vgpu, DP_TP_CTL(PORT_E));
419
420 if ((ddi_buf_ctl & DDI_BUF_CTL_ENABLE) &&
421 (rx_ctl & FDI_RX_ENABLE) &&
422 (rx_ctl & FDI_AUTO_TRAINING) &&
423 (tx_ctl & DP_TP_CTL_ENABLE) &&
424 (tx_ctl & DP_TP_CTL_FDI_AUTOTRAIN))
425 return 1;
426 else
427 return 0;
428 }
429
430 static int check_fdi_rx_train_status(struct intel_vgpu *vgpu,
431 enum pipe pipe, unsigned int train_pattern)
432 {
433 i915_reg_t fdi_rx_imr, fdi_tx_ctl, fdi_rx_ctl;
434 unsigned int fdi_rx_check_bits, fdi_tx_check_bits;
435 unsigned int fdi_rx_train_bits, fdi_tx_train_bits;
436 unsigned int fdi_iir_check_bits;
437
438 fdi_rx_imr = FDI_RX_IMR(pipe);
439 fdi_tx_ctl = FDI_TX_CTL(pipe);
440 fdi_rx_ctl = FDI_RX_CTL(pipe);
441
442 if (train_pattern == FDI_LINK_TRAIN_PATTERN1) {
443 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_1_CPT;
444 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_1;
445 fdi_iir_check_bits = FDI_RX_BIT_LOCK;
446 } else if (train_pattern == FDI_LINK_TRAIN_PATTERN2) {
447 fdi_rx_train_bits = FDI_LINK_TRAIN_PATTERN_2_CPT;
448 fdi_tx_train_bits = FDI_LINK_TRAIN_PATTERN_2;
449 fdi_iir_check_bits = FDI_RX_SYMBOL_LOCK;
450 } else {
451 gvt_err("Invalid train pattern %d\n", train_pattern);
452 return -EINVAL;
453 }
454
455 fdi_rx_check_bits = FDI_RX_ENABLE | fdi_rx_train_bits;
456 fdi_tx_check_bits = FDI_TX_ENABLE | fdi_tx_train_bits;
457
458 /* If imr bit has been masked */
459 if (vgpu_vreg(vgpu, fdi_rx_imr) & fdi_iir_check_bits)
460 return 0;
461
462 if (((vgpu_vreg(vgpu, fdi_tx_ctl) & fdi_tx_check_bits)
463 == fdi_tx_check_bits)
464 && ((vgpu_vreg(vgpu, fdi_rx_ctl) & fdi_rx_check_bits)
465 == fdi_rx_check_bits))
466 return 1;
467 else
468 return 0;
469 }
470
471 #define INVALID_INDEX (~0U)
472
473 static unsigned int calc_index(unsigned int offset, unsigned int start,
474 unsigned int next, unsigned int end, i915_reg_t i915_end)
475 {
476 unsigned int range = next - start;
477
478 if (!end)
479 end = i915_mmio_reg_offset(i915_end);
480 if (offset < start || offset > end)
481 return INVALID_INDEX;
482 offset -= start;
483 return offset / range;
484 }
485
486 #define FDI_RX_CTL_TO_PIPE(offset) \
487 calc_index(offset, _FDI_RXA_CTL, _FDI_RXB_CTL, 0, FDI_RX_CTL(PIPE_C))
488
489 #define FDI_TX_CTL_TO_PIPE(offset) \
490 calc_index(offset, _FDI_TXA_CTL, _FDI_TXB_CTL, 0, FDI_TX_CTL(PIPE_C))
491
492 #define FDI_RX_IMR_TO_PIPE(offset) \
493 calc_index(offset, _FDI_RXA_IMR, _FDI_RXB_IMR, 0, FDI_RX_IMR(PIPE_C))
494
495 static int update_fdi_rx_iir_status(struct intel_vgpu *vgpu,
496 unsigned int offset, void *p_data, unsigned int bytes)
497 {
498 i915_reg_t fdi_rx_iir;
499 unsigned int index;
500 int ret;
501
502 if (FDI_RX_CTL_TO_PIPE(offset) != INVALID_INDEX)
503 index = FDI_RX_CTL_TO_PIPE(offset);
504 else if (FDI_TX_CTL_TO_PIPE(offset) != INVALID_INDEX)
505 index = FDI_TX_CTL_TO_PIPE(offset);
506 else if (FDI_RX_IMR_TO_PIPE(offset) != INVALID_INDEX)
507 index = FDI_RX_IMR_TO_PIPE(offset);
508 else {
509 gvt_err("Unsupport registers %x\n", offset);
510 return -EINVAL;
511 }
512
513 write_vreg(vgpu, offset, p_data, bytes);
514
515 fdi_rx_iir = FDI_RX_IIR(index);
516
517 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN1);
518 if (ret < 0)
519 return ret;
520 if (ret)
521 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_BIT_LOCK;
522
523 ret = check_fdi_rx_train_status(vgpu, index, FDI_LINK_TRAIN_PATTERN2);
524 if (ret < 0)
525 return ret;
526 if (ret)
527 vgpu_vreg(vgpu, fdi_rx_iir) |= FDI_RX_SYMBOL_LOCK;
528
529 if (offset == _FDI_RXA_CTL)
530 if (fdi_auto_training_started(vgpu))
531 vgpu_vreg(vgpu, DP_TP_STATUS(PORT_E)) |=
532 DP_TP_STATUS_AUTOTRAIN_DONE;
533 return 0;
534 }
535
536 #define DP_TP_CTL_TO_PORT(offset) \
537 calc_index(offset, _DP_TP_CTL_A, _DP_TP_CTL_B, 0, DP_TP_CTL(PORT_E))
538
539 static int dp_tp_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
540 void *p_data, unsigned int bytes)
541 {
542 i915_reg_t status_reg;
543 unsigned int index;
544 u32 data;
545
546 write_vreg(vgpu, offset, p_data, bytes);
547
548 index = DP_TP_CTL_TO_PORT(offset);
549 data = (vgpu_vreg(vgpu, offset) & GENMASK(10, 8)) >> 8;
550 if (data == 0x2) {
551 status_reg = DP_TP_STATUS(index);
552 vgpu_vreg(vgpu, status_reg) |= (1 << 25);
553 }
554 return 0;
555 }
556
557 static int dp_tp_status_mmio_write(struct intel_vgpu *vgpu,
558 unsigned int offset, void *p_data, unsigned int bytes)
559 {
560 u32 reg_val;
561 u32 sticky_mask;
562
563 reg_val = *((u32 *)p_data);
564 sticky_mask = GENMASK(27, 26) | (1 << 24);
565
566 vgpu_vreg(vgpu, offset) = (reg_val & ~sticky_mask) |
567 (vgpu_vreg(vgpu, offset) & sticky_mask);
568 vgpu_vreg(vgpu, offset) &= ~(reg_val & sticky_mask);
569 return 0;
570 }
571
572 static int pch_adpa_mmio_write(struct intel_vgpu *vgpu,
573 unsigned int offset, void *p_data, unsigned int bytes)
574 {
575 u32 data;
576
577 write_vreg(vgpu, offset, p_data, bytes);
578 data = vgpu_vreg(vgpu, offset);
579
580 if (data & ADPA_CRT_HOTPLUG_FORCE_TRIGGER)
581 vgpu_vreg(vgpu, offset) &= ~ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
582 return 0;
583 }
584
585 static int south_chicken2_mmio_write(struct intel_vgpu *vgpu,
586 unsigned int offset, void *p_data, unsigned int bytes)
587 {
588 u32 data;
589
590 write_vreg(vgpu, offset, p_data, bytes);
591 data = vgpu_vreg(vgpu, offset);
592
593 if (data & FDI_MPHY_IOSFSB_RESET_CTL)
594 vgpu_vreg(vgpu, offset) |= FDI_MPHY_IOSFSB_RESET_STATUS;
595 else
596 vgpu_vreg(vgpu, offset) &= ~FDI_MPHY_IOSFSB_RESET_STATUS;
597 return 0;
598 }
599
600 #define DSPSURF_TO_PIPE(offset) \
601 calc_index(offset, _DSPASURF, _DSPBSURF, 0, DSPSURF(PIPE_C))
602
603 static int pri_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
604 void *p_data, unsigned int bytes)
605 {
606 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
607 unsigned int index = DSPSURF_TO_PIPE(offset);
608 i915_reg_t surflive_reg = DSPSURFLIVE(index);
609 int flip_event[] = {
610 [PIPE_A] = PRIMARY_A_FLIP_DONE,
611 [PIPE_B] = PRIMARY_B_FLIP_DONE,
612 [PIPE_C] = PRIMARY_C_FLIP_DONE,
613 };
614
615 write_vreg(vgpu, offset, p_data, bytes);
616 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
617
618 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
619 return 0;
620 }
621
622 #define SPRSURF_TO_PIPE(offset) \
623 calc_index(offset, _SPRA_SURF, _SPRB_SURF, 0, SPRSURF(PIPE_C))
624
625 static int spr_surf_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
626 void *p_data, unsigned int bytes)
627 {
628 unsigned int index = SPRSURF_TO_PIPE(offset);
629 i915_reg_t surflive_reg = SPRSURFLIVE(index);
630 int flip_event[] = {
631 [PIPE_A] = SPRITE_A_FLIP_DONE,
632 [PIPE_B] = SPRITE_B_FLIP_DONE,
633 [PIPE_C] = SPRITE_C_FLIP_DONE,
634 };
635
636 write_vreg(vgpu, offset, p_data, bytes);
637 vgpu_vreg(vgpu, surflive_reg) = vgpu_vreg(vgpu, offset);
638
639 set_bit(flip_event[index], vgpu->irq.flip_done_event[index]);
640 return 0;
641 }
642
643 static int trigger_aux_channel_interrupt(struct intel_vgpu *vgpu,
644 unsigned int reg)
645 {
646 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
647 enum intel_gvt_event_type event;
648
649 if (reg == _DPA_AUX_CH_CTL)
650 event = AUX_CHANNEL_A;
651 else if (reg == _PCH_DPB_AUX_CH_CTL || reg == _DPB_AUX_CH_CTL)
652 event = AUX_CHANNEL_B;
653 else if (reg == _PCH_DPC_AUX_CH_CTL || reg == _DPC_AUX_CH_CTL)
654 event = AUX_CHANNEL_C;
655 else if (reg == _PCH_DPD_AUX_CH_CTL || reg == _DPD_AUX_CH_CTL)
656 event = AUX_CHANNEL_D;
657 else {
658 WARN_ON(true);
659 return -EINVAL;
660 }
661
662 intel_vgpu_trigger_virtual_event(vgpu, event);
663 return 0;
664 }
665
666 static int dp_aux_ch_ctl_trans_done(struct intel_vgpu *vgpu, u32 value,
667 unsigned int reg, int len, bool data_valid)
668 {
669 /* mark transaction done */
670 value |= DP_AUX_CH_CTL_DONE;
671 value &= ~DP_AUX_CH_CTL_SEND_BUSY;
672 value &= ~DP_AUX_CH_CTL_RECEIVE_ERROR;
673
674 if (data_valid)
675 value &= ~DP_AUX_CH_CTL_TIME_OUT_ERROR;
676 else
677 value |= DP_AUX_CH_CTL_TIME_OUT_ERROR;
678
679 /* message size */
680 value &= ~(0xf << 20);
681 value |= (len << 20);
682 vgpu_vreg(vgpu, reg) = value;
683
684 if (value & DP_AUX_CH_CTL_INTERRUPT)
685 return trigger_aux_channel_interrupt(vgpu, reg);
686 return 0;
687 }
688
689 static void dp_aux_ch_ctl_link_training(struct intel_vgpu_dpcd_data *dpcd,
690 uint8_t t)
691 {
692 if ((t & DPCD_TRAINING_PATTERN_SET_MASK) == DPCD_TRAINING_PATTERN_1) {
693 /* training pattern 1 for CR */
694 /* set LANE0_CR_DONE, LANE1_CR_DONE */
695 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_CR_DONE;
696 /* set LANE2_CR_DONE, LANE3_CR_DONE */
697 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_CR_DONE;
698 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
699 DPCD_TRAINING_PATTERN_2) {
700 /* training pattern 2 for EQ */
701 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane0_1 */
702 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_LANES_EQ_DONE;
703 dpcd->data[DPCD_LANE0_1_STATUS] |= DPCD_SYMBOL_LOCKED;
704 /* Set CHANNEL_EQ_DONE and SYMBOL_LOCKED for Lane2_3 */
705 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_LANES_EQ_DONE;
706 dpcd->data[DPCD_LANE2_3_STATUS] |= DPCD_SYMBOL_LOCKED;
707 /* set INTERLANE_ALIGN_DONE */
708 dpcd->data[DPCD_LANE_ALIGN_STATUS_UPDATED] |=
709 DPCD_INTERLANE_ALIGN_DONE;
710 } else if ((t & DPCD_TRAINING_PATTERN_SET_MASK) ==
711 DPCD_LINK_TRAINING_DISABLED) {
712 /* finish link training */
713 /* set sink status as synchronized */
714 dpcd->data[DPCD_SINK_STATUS] = DPCD_SINK_IN_SYNC;
715 }
716 }
717
718 #define _REG_HSW_DP_AUX_CH_CTL(dp) \
719 ((dp) ? (_PCH_DPB_AUX_CH_CTL + ((dp)-1)*0x100) : 0x64010)
720
721 #define _REG_SKL_DP_AUX_CH_CTL(dp) (0x64010 + (dp) * 0x100)
722
723 #define OFFSET_TO_DP_AUX_PORT(offset) (((offset) & 0xF00) >> 8)
724
725 #define dpy_is_valid_port(port) \
726 (((port) >= PORT_A) && ((port) < I915_MAX_PORTS))
727
728 static int dp_aux_ch_ctl_mmio_write(struct intel_vgpu *vgpu,
729 unsigned int offset, void *p_data, unsigned int bytes)
730 {
731 struct intel_vgpu_display *display = &vgpu->display;
732 int msg, addr, ctrl, op, len;
733 int port_index = OFFSET_TO_DP_AUX_PORT(offset);
734 struct intel_vgpu_dpcd_data *dpcd = NULL;
735 struct intel_vgpu_port *port = NULL;
736 u32 data;
737
738 if (!dpy_is_valid_port(port_index)) {
739 gvt_err("GVT(%d): Unsupported DP port access!\n", vgpu->id);
740 return 0;
741 }
742
743 write_vreg(vgpu, offset, p_data, bytes);
744 data = vgpu_vreg(vgpu, offset);
745
746 if (IS_SKYLAKE(vgpu->gvt->dev_priv) &&
747 offset != _REG_SKL_DP_AUX_CH_CTL(port_index)) {
748 /* SKL DPB/C/D aux ctl register changed */
749 return 0;
750 } else if (IS_BROADWELL(vgpu->gvt->dev_priv) &&
751 offset != _REG_HSW_DP_AUX_CH_CTL(port_index)) {
752 /* write to the data registers */
753 return 0;
754 }
755
756 if (!(data & DP_AUX_CH_CTL_SEND_BUSY)) {
757 /* just want to clear the sticky bits */
758 vgpu_vreg(vgpu, offset) = 0;
759 return 0;
760 }
761
762 port = &display->ports[port_index];
763 dpcd = port->dpcd;
764
765 /* read out message from DATA1 register */
766 msg = vgpu_vreg(vgpu, offset + 4);
767 addr = (msg >> 8) & 0xffff;
768 ctrl = (msg >> 24) & 0xff;
769 len = msg & 0xff;
770 op = ctrl >> 4;
771
772 if (op == GVT_AUX_NATIVE_WRITE) {
773 int t;
774 uint8_t buf[16];
775
776 if ((addr + len + 1) >= DPCD_SIZE) {
777 /*
778 * Write request exceeds what we supported,
779 * DCPD spec: When a Source Device is writing a DPCD
780 * address not supported by the Sink Device, the Sink
781 * Device shall reply with AUX NACK and “M” equal to
782 * zero.
783 */
784
785 /* NAK the write */
786 vgpu_vreg(vgpu, offset + 4) = AUX_NATIVE_REPLY_NAK;
787 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 2, true);
788 return 0;
789 }
790
791 /*
792 * Write request format: (command + address) occupies
793 * 3 bytes, followed by (len + 1) bytes of data.
794 */
795 if (WARN_ON((len + 4) > AUX_BURST_SIZE))
796 return -EINVAL;
797
798 /* unpack data from vreg to buf */
799 for (t = 0; t < 4; t++) {
800 u32 r = vgpu_vreg(vgpu, offset + 8 + t * 4);
801
802 buf[t * 4] = (r >> 24) & 0xff;
803 buf[t * 4 + 1] = (r >> 16) & 0xff;
804 buf[t * 4 + 2] = (r >> 8) & 0xff;
805 buf[t * 4 + 3] = r & 0xff;
806 }
807
808 /* write to virtual DPCD */
809 if (dpcd && dpcd->data_valid) {
810 for (t = 0; t <= len; t++) {
811 int p = addr + t;
812
813 dpcd->data[p] = buf[t];
814 /* check for link training */
815 if (p == DPCD_TRAINING_PATTERN_SET)
816 dp_aux_ch_ctl_link_training(dpcd,
817 buf[t]);
818 }
819 }
820
821 /* ACK the write */
822 vgpu_vreg(vgpu, offset + 4) = 0;
823 dp_aux_ch_ctl_trans_done(vgpu, data, offset, 1,
824 dpcd && dpcd->data_valid);
825 return 0;
826 }
827
828 if (op == GVT_AUX_NATIVE_READ) {
829 int idx, i, ret = 0;
830
831 if ((addr + len + 1) >= DPCD_SIZE) {
832 /*
833 * read request exceeds what we supported
834 * DPCD spec: A Sink Device receiving a Native AUX CH
835 * read request for an unsupported DPCD address must
836 * reply with an AUX ACK and read data set equal to
837 * zero instead of replying with AUX NACK.
838 */
839
840 /* ACK the READ*/
841 vgpu_vreg(vgpu, offset + 4) = 0;
842 vgpu_vreg(vgpu, offset + 8) = 0;
843 vgpu_vreg(vgpu, offset + 12) = 0;
844 vgpu_vreg(vgpu, offset + 16) = 0;
845 vgpu_vreg(vgpu, offset + 20) = 0;
846
847 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
848 true);
849 return 0;
850 }
851
852 for (idx = 1; idx <= 5; idx++) {
853 /* clear the data registers */
854 vgpu_vreg(vgpu, offset + 4 * idx) = 0;
855 }
856
857 /*
858 * Read reply format: ACK (1 byte) plus (len + 1) bytes of data.
859 */
860 if (WARN_ON((len + 2) > AUX_BURST_SIZE))
861 return -EINVAL;
862
863 /* read from virtual DPCD to vreg */
864 /* first 4 bytes: [ACK][addr][addr+1][addr+2] */
865 if (dpcd && dpcd->data_valid) {
866 for (i = 1; i <= (len + 1); i++) {
867 int t;
868
869 t = dpcd->data[addr + i - 1];
870 t <<= (24 - 8 * (i % 4));
871 ret |= t;
872
873 if ((i % 4 == 3) || (i == (len + 1))) {
874 vgpu_vreg(vgpu, offset +
875 (i / 4 + 1) * 4) = ret;
876 ret = 0;
877 }
878 }
879 }
880 dp_aux_ch_ctl_trans_done(vgpu, data, offset, len + 2,
881 dpcd && dpcd->data_valid);
882 return 0;
883 }
884
885 /* i2c transaction starts */
886 intel_gvt_i2c_handle_aux_ch_write(vgpu, port_index, offset, p_data);
887
888 if (data & DP_AUX_CH_CTL_INTERRUPT)
889 trigger_aux_channel_interrupt(vgpu, offset);
890 return 0;
891 }
892
893 static int vga_control_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
894 void *p_data, unsigned int bytes)
895 {
896 bool vga_disable;
897
898 write_vreg(vgpu, offset, p_data, bytes);
899 vga_disable = vgpu_vreg(vgpu, offset) & VGA_DISP_DISABLE;
900
901 gvt_dbg_core("vgpu%d: %s VGA mode\n", vgpu->id,
902 vga_disable ? "Disable" : "Enable");
903 return 0;
904 }
905
906 static u32 read_virtual_sbi_register(struct intel_vgpu *vgpu,
907 unsigned int sbi_offset)
908 {
909 struct intel_vgpu_display *display = &vgpu->display;
910 int num = display->sbi.number;
911 int i;
912
913 for (i = 0; i < num; ++i)
914 if (display->sbi.registers[i].offset == sbi_offset)
915 break;
916
917 if (i == num)
918 return 0;
919
920 return display->sbi.registers[i].value;
921 }
922
923 static void write_virtual_sbi_register(struct intel_vgpu *vgpu,
924 unsigned int offset, u32 value)
925 {
926 struct intel_vgpu_display *display = &vgpu->display;
927 int num = display->sbi.number;
928 int i;
929
930 for (i = 0; i < num; ++i) {
931 if (display->sbi.registers[i].offset == offset)
932 break;
933 }
934
935 if (i == num) {
936 if (num == SBI_REG_MAX) {
937 gvt_err("vgpu%d: SBI caching meets maximum limits\n",
938 vgpu->id);
939 return;
940 }
941 display->sbi.number++;
942 }
943
944 display->sbi.registers[i].offset = offset;
945 display->sbi.registers[i].value = value;
946 }
947
948 static int sbi_data_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
949 void *p_data, unsigned int bytes)
950 {
951 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
952 SBI_OPCODE_SHIFT) == SBI_CMD_CRRD) {
953 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
954 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
955 vgpu_vreg(vgpu, offset) = read_virtual_sbi_register(vgpu,
956 sbi_offset);
957 }
958 read_vreg(vgpu, offset, p_data, bytes);
959 return 0;
960 }
961
962 static bool sbi_ctl_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
963 void *p_data, unsigned int bytes)
964 {
965 u32 data;
966
967 write_vreg(vgpu, offset, p_data, bytes);
968 data = vgpu_vreg(vgpu, offset);
969
970 data &= ~(SBI_STAT_MASK << SBI_STAT_SHIFT);
971 data |= SBI_READY;
972
973 data &= ~(SBI_RESPONSE_MASK << SBI_RESPONSE_SHIFT);
974 data |= SBI_RESPONSE_SUCCESS;
975
976 vgpu_vreg(vgpu, offset) = data;
977
978 if (((vgpu_vreg(vgpu, SBI_CTL_STAT) & SBI_OPCODE_MASK) >>
979 SBI_OPCODE_SHIFT) == SBI_CMD_CRWR) {
980 unsigned int sbi_offset = (vgpu_vreg(vgpu, SBI_ADDR) &
981 SBI_ADDR_OFFSET_MASK) >> SBI_ADDR_OFFSET_SHIFT;
982
983 write_virtual_sbi_register(vgpu, sbi_offset,
984 vgpu_vreg(vgpu, SBI_DATA));
985 }
986 return 0;
987 }
988
989 #define _vgtif_reg(x) \
990 (VGT_PVINFO_PAGE + offsetof(struct vgt_if, x))
991
992 static int pvinfo_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
993 void *p_data, unsigned int bytes)
994 {
995 bool invalid_read = false;
996
997 read_vreg(vgpu, offset, p_data, bytes);
998
999 switch (offset) {
1000 case _vgtif_reg(magic) ... _vgtif_reg(vgt_id):
1001 if (offset + bytes > _vgtif_reg(vgt_id) + 4)
1002 invalid_read = true;
1003 break;
1004 case _vgtif_reg(avail_rs.mappable_gmadr.base) ...
1005 _vgtif_reg(avail_rs.fence_num):
1006 if (offset + bytes >
1007 _vgtif_reg(avail_rs.fence_num) + 4)
1008 invalid_read = true;
1009 break;
1010 case 0x78010: /* vgt_caps */
1011 case 0x7881c:
1012 break;
1013 default:
1014 invalid_read = true;
1015 break;
1016 }
1017 if (invalid_read)
1018 gvt_err("invalid pvinfo read: [%x:%x] = %x\n",
1019 offset, bytes, *(u32 *)p_data);
1020 return 0;
1021 }
1022
1023 static int handle_g2v_notification(struct intel_vgpu *vgpu, int notification)
1024 {
1025 int ret = 0;
1026
1027 switch (notification) {
1028 case VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE:
1029 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 3);
1030 break;
1031 case VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY:
1032 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 3);
1033 break;
1034 case VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE:
1035 ret = intel_vgpu_g2v_create_ppgtt_mm(vgpu, 4);
1036 break;
1037 case VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY:
1038 ret = intel_vgpu_g2v_destroy_ppgtt_mm(vgpu, 4);
1039 break;
1040 case VGT_G2V_EXECLIST_CONTEXT_CREATE:
1041 case VGT_G2V_EXECLIST_CONTEXT_DESTROY:
1042 case 1: /* Remove this in guest driver. */
1043 break;
1044 default:
1045 gvt_err("Invalid PV notification %d\n", notification);
1046 }
1047 return ret;
1048 }
1049
1050 static int send_display_ready_uevent(struct intel_vgpu *vgpu, int ready)
1051 {
1052 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1053 struct kobject *kobj = &dev_priv->drm.primary->kdev->kobj;
1054 char *env[3] = {NULL, NULL, NULL};
1055 char vmid_str[20];
1056 char display_ready_str[20];
1057
1058 snprintf(display_ready_str, 20, "GVT_DISPLAY_READY=%d\n", ready);
1059 env[0] = display_ready_str;
1060
1061 snprintf(vmid_str, 20, "VMID=%d", vgpu->id);
1062 env[1] = vmid_str;
1063
1064 return kobject_uevent_env(kobj, KOBJ_ADD, env);
1065 }
1066
1067 static int pvinfo_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1068 void *p_data, unsigned int bytes)
1069 {
1070 u32 data;
1071 int ret;
1072
1073 write_vreg(vgpu, offset, p_data, bytes);
1074 data = vgpu_vreg(vgpu, offset);
1075
1076 switch (offset) {
1077 case _vgtif_reg(display_ready):
1078 send_display_ready_uevent(vgpu, data ? 1 : 0);
1079 break;
1080 case _vgtif_reg(g2v_notify):
1081 ret = handle_g2v_notification(vgpu, data);
1082 break;
1083 /* add xhot and yhot to handled list to avoid error log */
1084 case 0x78830:
1085 case 0x78834:
1086 case _vgtif_reg(pdp[0].lo):
1087 case _vgtif_reg(pdp[0].hi):
1088 case _vgtif_reg(pdp[1].lo):
1089 case _vgtif_reg(pdp[1].hi):
1090 case _vgtif_reg(pdp[2].lo):
1091 case _vgtif_reg(pdp[2].hi):
1092 case _vgtif_reg(pdp[3].lo):
1093 case _vgtif_reg(pdp[3].hi):
1094 case _vgtif_reg(execlist_context_descriptor_lo):
1095 case _vgtif_reg(execlist_context_descriptor_hi):
1096 break;
1097 default:
1098 gvt_err("invalid pvinfo write offset %x bytes %x data %x\n",
1099 offset, bytes, data);
1100 break;
1101 }
1102 return 0;
1103 }
1104
1105 static int pf_write(struct intel_vgpu *vgpu,
1106 unsigned int offset, void *p_data, unsigned int bytes)
1107 {
1108 u32 val = *(u32 *)p_data;
1109
1110 if ((offset == _PS_1A_CTRL || offset == _PS_2A_CTRL ||
1111 offset == _PS_1B_CTRL || offset == _PS_2B_CTRL ||
1112 offset == _PS_1C_CTRL) && (val & PS_PLANE_SEL_MASK) != 0) {
1113 WARN_ONCE(true, "VM(%d): guest is trying to scaling a plane\n",
1114 vgpu->id);
1115 return 0;
1116 }
1117
1118 return intel_vgpu_default_mmio_write(vgpu, offset, p_data, bytes);
1119 }
1120
1121 static int power_well_ctl_mmio_write(struct intel_vgpu *vgpu,
1122 unsigned int offset, void *p_data, unsigned int bytes)
1123 {
1124 write_vreg(vgpu, offset, p_data, bytes);
1125
1126 if (vgpu_vreg(vgpu, offset) & HSW_PWR_WELL_ENABLE_REQUEST)
1127 vgpu_vreg(vgpu, offset) |= HSW_PWR_WELL_STATE_ENABLED;
1128 else
1129 vgpu_vreg(vgpu, offset) &= ~HSW_PWR_WELL_STATE_ENABLED;
1130 return 0;
1131 }
1132
1133 static int fpga_dbg_mmio_write(struct intel_vgpu *vgpu,
1134 unsigned int offset, void *p_data, unsigned int bytes)
1135 {
1136 write_vreg(vgpu, offset, p_data, bytes);
1137
1138 if (vgpu_vreg(vgpu, offset) & FPGA_DBG_RM_NOCLAIM)
1139 vgpu_vreg(vgpu, offset) &= ~FPGA_DBG_RM_NOCLAIM;
1140 return 0;
1141 }
1142
1143 static int dma_ctrl_write(struct intel_vgpu *vgpu, unsigned int offset,
1144 void *p_data, unsigned int bytes)
1145 {
1146 u32 mode = *(u32 *)p_data;
1147
1148 if (GFX_MODE_BIT_SET_IN_MASK(mode, START_DMA)) {
1149 WARN_ONCE(1, "VM(%d): iGVT-g doesn't supporte GuC\n",
1150 vgpu->id);
1151 return 0;
1152 }
1153
1154 return 0;
1155 }
1156
1157 static int gen9_trtte_write(struct intel_vgpu *vgpu, unsigned int offset,
1158 void *p_data, unsigned int bytes)
1159 {
1160 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1161 u32 trtte = *(u32 *)p_data;
1162
1163 if ((trtte & 1) && (trtte & (1 << 1)) == 0) {
1164 WARN(1, "VM(%d): Use physical address for TRTT!\n",
1165 vgpu->id);
1166 return -EINVAL;
1167 }
1168 write_vreg(vgpu, offset, p_data, bytes);
1169 /* TRTTE is not per-context */
1170 I915_WRITE(_MMIO(offset), vgpu_vreg(vgpu, offset));
1171
1172 return 0;
1173 }
1174
1175 static int gen9_trtt_chicken_write(struct intel_vgpu *vgpu, unsigned int offset,
1176 void *p_data, unsigned int bytes)
1177 {
1178 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1179 u32 val = *(u32 *)p_data;
1180
1181 if (val & 1) {
1182 /* unblock hw logic */
1183 I915_WRITE(_MMIO(offset), val);
1184 }
1185 write_vreg(vgpu, offset, p_data, bytes);
1186 return 0;
1187 }
1188
1189 static int dpll_status_read(struct intel_vgpu *vgpu, unsigned int offset,
1190 void *p_data, unsigned int bytes)
1191 {
1192 u32 v = 0;
1193
1194 if (vgpu_vreg(vgpu, 0x46010) & (1 << 31))
1195 v |= (1 << 0);
1196
1197 if (vgpu_vreg(vgpu, 0x46014) & (1 << 31))
1198 v |= (1 << 8);
1199
1200 if (vgpu_vreg(vgpu, 0x46040) & (1 << 31))
1201 v |= (1 << 16);
1202
1203 if (vgpu_vreg(vgpu, 0x46060) & (1 << 31))
1204 v |= (1 << 24);
1205
1206 vgpu_vreg(vgpu, offset) = v;
1207
1208 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1209 }
1210
1211 static int mailbox_write(struct intel_vgpu *vgpu, unsigned int offset,
1212 void *p_data, unsigned int bytes)
1213 {
1214 u32 value = *(u32 *)p_data;
1215 u32 cmd = value & 0xff;
1216 u32 *data0 = &vgpu_vreg(vgpu, GEN6_PCODE_DATA);
1217
1218 switch (cmd) {
1219 case 0x6:
1220 /**
1221 * "Read memory latency" command on gen9.
1222 * Below memory latency values are read
1223 * from skylake platform.
1224 */
1225 if (!*data0)
1226 *data0 = 0x1e1a1100;
1227 else
1228 *data0 = 0x61514b3d;
1229 break;
1230 case 0x5:
1231 *data0 |= 0x1;
1232 break;
1233 }
1234
1235 gvt_dbg_core("VM(%d) write %x to mailbox, return data0 %x\n",
1236 vgpu->id, value, *data0);
1237
1238 value &= ~(1 << 31);
1239 return intel_vgpu_default_mmio_write(vgpu, offset, &value, bytes);
1240 }
1241
1242 static int skl_power_well_ctl_write(struct intel_vgpu *vgpu,
1243 unsigned int offset, void *p_data, unsigned int bytes)
1244 {
1245 u32 v = *(u32 *)p_data;
1246
1247 v &= (1 << 31) | (1 << 29) | (1 << 9) |
1248 (1 << 7) | (1 << 5) | (1 << 3) | (1 << 1);
1249 v |= (v >> 1);
1250
1251 return intel_vgpu_default_mmio_write(vgpu, offset, &v, bytes);
1252 }
1253
1254 static int skl_misc_ctl_write(struct intel_vgpu *vgpu, unsigned int offset,
1255 void *p_data, unsigned int bytes)
1256 {
1257 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1258 i915_reg_t reg = {.reg = offset};
1259
1260 switch (offset) {
1261 case 0x4ddc:
1262 vgpu_vreg(vgpu, offset) = 0x8000003c;
1263 break;
1264 case 0x42080:
1265 vgpu_vreg(vgpu, offset) = 0x8000;
1266 break;
1267 default:
1268 return -EINVAL;
1269 }
1270
1271 /**
1272 * TODO: need detect stepping info after gvt contain such information
1273 * 0x4ddc enabled after C0, 0x42080 enabled after E0.
1274 */
1275 I915_WRITE(reg, vgpu_vreg(vgpu, offset));
1276 return 0;
1277 }
1278
1279 static int skl_lcpll_write(struct intel_vgpu *vgpu, unsigned int offset,
1280 void *p_data, unsigned int bytes)
1281 {
1282 u32 v = *(u32 *)p_data;
1283
1284 /* other bits are MBZ. */
1285 v &= (1 << 31) | (1 << 30);
1286 v & (1 << 31) ? (v |= (1 << 30)) : (v &= ~(1 << 30));
1287
1288 vgpu_vreg(vgpu, offset) = v;
1289
1290 return 0;
1291 }
1292
1293 static int ring_timestamp_mmio_read(struct intel_vgpu *vgpu,
1294 unsigned int offset, void *p_data, unsigned int bytes)
1295 {
1296 struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
1297
1298 vgpu_vreg(vgpu, offset) = I915_READ(_MMIO(offset));
1299 return intel_vgpu_default_mmio_read(vgpu, offset, p_data, bytes);
1300 }
1301
1302 static int elsp_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1303 void *p_data, unsigned int bytes)
1304 {
1305 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
1306 struct intel_vgpu_execlist *execlist;
1307 u32 data = *(u32 *)p_data;
1308 int ret;
1309
1310 if (WARN_ON(ring_id < 0 || ring_id > I915_NUM_ENGINES - 1))
1311 return -EINVAL;
1312
1313 execlist = &vgpu->execlist[ring_id];
1314
1315 execlist->elsp_dwords.data[execlist->elsp_dwords.index] = data;
1316 if (execlist->elsp_dwords.index == 3)
1317 ret = intel_vgpu_submit_execlist(vgpu, ring_id);
1318
1319 ++execlist->elsp_dwords.index;
1320 execlist->elsp_dwords.index &= 0x3;
1321 return 0;
1322 }
1323
1324 static int ring_mode_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
1325 void *p_data, unsigned int bytes)
1326 {
1327 u32 data = *(u32 *)p_data;
1328 int ring_id = render_mmio_to_ring_id(vgpu->gvt, offset);
1329 bool enable_execlist;
1330
1331 write_vreg(vgpu, offset, p_data, bytes);
1332 if ((data & _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE))
1333 || (data & _MASKED_BIT_DISABLE(GFX_RUN_LIST_ENABLE))) {
1334 enable_execlist = !!(data & GFX_RUN_LIST_ENABLE);
1335
1336 gvt_dbg_core("EXECLIST %s on ring %d\n",
1337 (enable_execlist ? "enabling" : "disabling"),
1338 ring_id);
1339
1340 if (enable_execlist)
1341 intel_vgpu_start_schedule(vgpu);
1342 }
1343 return 0;
1344 }
1345
1346 static int gvt_reg_tlb_control_handler(struct intel_vgpu *vgpu,
1347 unsigned int offset, void *p_data, unsigned int bytes)
1348 {
1349 int rc = 0;
1350 unsigned int id = 0;
1351
1352 switch (offset) {
1353 case 0x4260:
1354 id = RCS;
1355 break;
1356 case 0x4264:
1357 id = VCS;
1358 break;
1359 case 0x4268:
1360 id = VCS2;
1361 break;
1362 case 0x426c:
1363 id = BCS;
1364 break;
1365 case 0x4270:
1366 id = VECS;
1367 break;
1368 default:
1369 rc = -EINVAL;
1370 break;
1371 }
1372 set_bit(id, (void *)vgpu->tlb_handle_pending);
1373
1374 return rc;
1375 }
1376
1377 #define MMIO_F(reg, s, f, am, rm, d, r, w) do { \
1378 ret = new_mmio_info(gvt, INTEL_GVT_MMIO_OFFSET(reg), \
1379 f, s, am, rm, d, r, w); \
1380 if (ret) \
1381 return ret; \
1382 } while (0)
1383
1384 #define MMIO_D(reg, d) \
1385 MMIO_F(reg, 4, 0, 0, 0, d, NULL, NULL)
1386
1387 #define MMIO_DH(reg, d, r, w) \
1388 MMIO_F(reg, 4, 0, 0, 0, d, r, w)
1389
1390 #define MMIO_DFH(reg, d, f, r, w) \
1391 MMIO_F(reg, 4, f, 0, 0, d, r, w)
1392
1393 #define MMIO_GM(reg, d, r, w) \
1394 MMIO_F(reg, 4, F_GMADR, 0xFFFFF000, 0, d, r, w)
1395
1396 #define MMIO_RO(reg, d, f, rm, r, w) \
1397 MMIO_F(reg, 4, F_RO | f, 0, rm, d, r, w)
1398
1399 #define MMIO_RING_F(prefix, s, f, am, rm, d, r, w) do { \
1400 MMIO_F(prefix(RENDER_RING_BASE), s, f, am, rm, d, r, w); \
1401 MMIO_F(prefix(BLT_RING_BASE), s, f, am, rm, d, r, w); \
1402 MMIO_F(prefix(GEN6_BSD_RING_BASE), s, f, am, rm, d, r, w); \
1403 MMIO_F(prefix(VEBOX_RING_BASE), s, f, am, rm, d, r, w); \
1404 } while (0)
1405
1406 #define MMIO_RING_D(prefix, d) \
1407 MMIO_RING_F(prefix, 4, 0, 0, 0, d, NULL, NULL)
1408
1409 #define MMIO_RING_DFH(prefix, d, f, r, w) \
1410 MMIO_RING_F(prefix, 4, f, 0, 0, d, r, w)
1411
1412 #define MMIO_RING_GM(prefix, d, r, w) \
1413 MMIO_RING_F(prefix, 4, F_GMADR, 0xFFFF0000, 0, d, r, w)
1414
1415 #define MMIO_RING_RO(prefix, d, f, rm, r, w) \
1416 MMIO_RING_F(prefix, 4, F_RO | f, 0, rm, d, r, w)
1417
1418 static int init_generic_mmio_info(struct intel_gvt *gvt)
1419 {
1420 struct drm_i915_private *dev_priv = gvt->dev_priv;
1421 int ret;
1422
1423 MMIO_RING_DFH(RING_IMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1424
1425 MMIO_DFH(SDEIMR, D_ALL, 0, NULL, intel_vgpu_reg_imr_handler);
1426 MMIO_DFH(SDEIER, D_ALL, 0, NULL, intel_vgpu_reg_ier_handler);
1427 MMIO_DFH(SDEIIR, D_ALL, 0, NULL, intel_vgpu_reg_iir_handler);
1428 MMIO_D(SDEISR, D_ALL);
1429
1430 MMIO_RING_D(RING_HWSTAM, D_ALL);
1431
1432 MMIO_GM(RENDER_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1433 MMIO_GM(BSD_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1434 MMIO_GM(BLT_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1435 MMIO_GM(VEBOX_HWS_PGA_GEN7, D_ALL, NULL, NULL);
1436
1437 #define RING_REG(base) (base + 0x28)
1438 MMIO_RING_D(RING_REG, D_ALL);
1439 #undef RING_REG
1440
1441 #define RING_REG(base) (base + 0x134)
1442 MMIO_RING_D(RING_REG, D_ALL);
1443 #undef RING_REG
1444
1445 MMIO_GM(0x2148, D_ALL, NULL, NULL);
1446 MMIO_GM(CCID, D_ALL, NULL, NULL);
1447 MMIO_GM(0x12198, D_ALL, NULL, NULL);
1448 MMIO_D(GEN7_CXT_SIZE, D_ALL);
1449
1450 MMIO_RING_D(RING_TAIL, D_ALL);
1451 MMIO_RING_D(RING_HEAD, D_ALL);
1452 MMIO_RING_D(RING_CTL, D_ALL);
1453 MMIO_RING_D(RING_ACTHD, D_ALL);
1454 MMIO_RING_GM(RING_START, D_ALL, NULL, NULL);
1455
1456 /* RING MODE */
1457 #define RING_REG(base) (base + 0x29c)
1458 MMIO_RING_DFH(RING_REG, D_ALL, F_MODE_MASK, NULL, ring_mode_mmio_write);
1459 #undef RING_REG
1460
1461 MMIO_RING_DFH(RING_MI_MODE, D_ALL, F_MODE_MASK, NULL, NULL);
1462 MMIO_RING_DFH(RING_INSTPM, D_ALL, F_MODE_MASK, NULL, NULL);
1463 MMIO_RING_DFH(RING_TIMESTAMP, D_ALL, F_CMD_ACCESS,
1464 ring_timestamp_mmio_read, NULL);
1465 MMIO_RING_DFH(RING_TIMESTAMP_UDW, D_ALL, F_CMD_ACCESS,
1466 ring_timestamp_mmio_read, NULL);
1467
1468 MMIO_DFH(GEN7_GT_MODE, D_ALL, F_MODE_MASK, NULL, NULL);
1469 MMIO_DFH(CACHE_MODE_0_GEN7, D_ALL, F_MODE_MASK, NULL, NULL);
1470 MMIO_DFH(CACHE_MODE_1, D_ALL, F_MODE_MASK, NULL, NULL);
1471
1472 MMIO_DFH(0x20dc, D_ALL, F_MODE_MASK, NULL, NULL);
1473 MMIO_DFH(_3D_CHICKEN3, D_ALL, F_MODE_MASK, NULL, NULL);
1474 MMIO_DFH(0x2088, D_ALL, F_MODE_MASK, NULL, NULL);
1475 MMIO_DFH(0x20e4, D_ALL, F_MODE_MASK, NULL, NULL);
1476 MMIO_DFH(0x2470, D_ALL, F_MODE_MASK, NULL, NULL);
1477 MMIO_D(GAM_ECOCHK, D_ALL);
1478 MMIO_DFH(GEN7_COMMON_SLICE_CHICKEN1, D_ALL, F_MODE_MASK, NULL, NULL);
1479 MMIO_DFH(COMMON_SLICE_CHICKEN2, D_ALL, F_MODE_MASK, NULL, NULL);
1480 MMIO_D(0x9030, D_ALL);
1481 MMIO_D(0x20a0, D_ALL);
1482 MMIO_D(0x2420, D_ALL);
1483 MMIO_D(0x2430, D_ALL);
1484 MMIO_D(0x2434, D_ALL);
1485 MMIO_D(0x2438, D_ALL);
1486 MMIO_D(0x243c, D_ALL);
1487 MMIO_DFH(0x7018, D_ALL, F_MODE_MASK, NULL, NULL);
1488 MMIO_DFH(0xe184, D_ALL, F_MODE_MASK, NULL, NULL);
1489 MMIO_DFH(0xe100, D_ALL, F_MODE_MASK, NULL, NULL);
1490
1491 /* display */
1492 MMIO_F(0x60220, 0x20, 0, 0, 0, D_ALL, NULL, NULL);
1493 MMIO_D(0x602a0, D_ALL);
1494
1495 MMIO_D(0x65050, D_ALL);
1496 MMIO_D(0x650b4, D_ALL);
1497
1498 MMIO_D(0xc4040, D_ALL);
1499 MMIO_D(DERRMR, D_ALL);
1500
1501 MMIO_D(PIPEDSL(PIPE_A), D_ALL);
1502 MMIO_D(PIPEDSL(PIPE_B), D_ALL);
1503 MMIO_D(PIPEDSL(PIPE_C), D_ALL);
1504 MMIO_D(PIPEDSL(_PIPE_EDP), D_ALL);
1505
1506 MMIO_DH(PIPECONF(PIPE_A), D_ALL, NULL, pipeconf_mmio_write);
1507 MMIO_DH(PIPECONF(PIPE_B), D_ALL, NULL, pipeconf_mmio_write);
1508 MMIO_DH(PIPECONF(PIPE_C), D_ALL, NULL, pipeconf_mmio_write);
1509 MMIO_DH(PIPECONF(_PIPE_EDP), D_ALL, NULL, pipeconf_mmio_write);
1510
1511 MMIO_D(PIPESTAT(PIPE_A), D_ALL);
1512 MMIO_D(PIPESTAT(PIPE_B), D_ALL);
1513 MMIO_D(PIPESTAT(PIPE_C), D_ALL);
1514 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL);
1515
1516 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_A), D_ALL);
1517 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_B), D_ALL);
1518 MMIO_D(PIPE_FLIPCOUNT_G4X(PIPE_C), D_ALL);
1519 MMIO_D(PIPE_FLIPCOUNT_G4X(_PIPE_EDP), D_ALL);
1520
1521 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_A), D_ALL);
1522 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_B), D_ALL);
1523 MMIO_D(PIPE_FRMCOUNT_G4X(PIPE_C), D_ALL);
1524 MMIO_D(PIPE_FRMCOUNT_G4X(_PIPE_EDP), D_ALL);
1525
1526 MMIO_D(CURCNTR(PIPE_A), D_ALL);
1527 MMIO_D(CURCNTR(PIPE_B), D_ALL);
1528 MMIO_D(CURCNTR(PIPE_C), D_ALL);
1529
1530 MMIO_D(CURPOS(PIPE_A), D_ALL);
1531 MMIO_D(CURPOS(PIPE_B), D_ALL);
1532 MMIO_D(CURPOS(PIPE_C), D_ALL);
1533
1534 MMIO_D(CURBASE(PIPE_A), D_ALL);
1535 MMIO_D(CURBASE(PIPE_B), D_ALL);
1536 MMIO_D(CURBASE(PIPE_C), D_ALL);
1537
1538 MMIO_D(0x700ac, D_ALL);
1539 MMIO_D(0x710ac, D_ALL);
1540 MMIO_D(0x720ac, D_ALL);
1541
1542 MMIO_D(0x70090, D_ALL);
1543 MMIO_D(0x70094, D_ALL);
1544 MMIO_D(0x70098, D_ALL);
1545 MMIO_D(0x7009c, D_ALL);
1546
1547 MMIO_D(DSPCNTR(PIPE_A), D_ALL);
1548 MMIO_D(DSPADDR(PIPE_A), D_ALL);
1549 MMIO_D(DSPSTRIDE(PIPE_A), D_ALL);
1550 MMIO_D(DSPPOS(PIPE_A), D_ALL);
1551 MMIO_D(DSPSIZE(PIPE_A), D_ALL);
1552 MMIO_DH(DSPSURF(PIPE_A), D_ALL, NULL, pri_surf_mmio_write);
1553 MMIO_D(DSPOFFSET(PIPE_A), D_ALL);
1554 MMIO_D(DSPSURFLIVE(PIPE_A), D_ALL);
1555
1556 MMIO_D(DSPCNTR(PIPE_B), D_ALL);
1557 MMIO_D(DSPADDR(PIPE_B), D_ALL);
1558 MMIO_D(DSPSTRIDE(PIPE_B), D_ALL);
1559 MMIO_D(DSPPOS(PIPE_B), D_ALL);
1560 MMIO_D(DSPSIZE(PIPE_B), D_ALL);
1561 MMIO_DH(DSPSURF(PIPE_B), D_ALL, NULL, pri_surf_mmio_write);
1562 MMIO_D(DSPOFFSET(PIPE_B), D_ALL);
1563 MMIO_D(DSPSURFLIVE(PIPE_B), D_ALL);
1564
1565 MMIO_D(DSPCNTR(PIPE_C), D_ALL);
1566 MMIO_D(DSPADDR(PIPE_C), D_ALL);
1567 MMIO_D(DSPSTRIDE(PIPE_C), D_ALL);
1568 MMIO_D(DSPPOS(PIPE_C), D_ALL);
1569 MMIO_D(DSPSIZE(PIPE_C), D_ALL);
1570 MMIO_DH(DSPSURF(PIPE_C), D_ALL, NULL, pri_surf_mmio_write);
1571 MMIO_D(DSPOFFSET(PIPE_C), D_ALL);
1572 MMIO_D(DSPSURFLIVE(PIPE_C), D_ALL);
1573
1574 MMIO_D(SPRCTL(PIPE_A), D_ALL);
1575 MMIO_D(SPRLINOFF(PIPE_A), D_ALL);
1576 MMIO_D(SPRSTRIDE(PIPE_A), D_ALL);
1577 MMIO_D(SPRPOS(PIPE_A), D_ALL);
1578 MMIO_D(SPRSIZE(PIPE_A), D_ALL);
1579 MMIO_D(SPRKEYVAL(PIPE_A), D_ALL);
1580 MMIO_D(SPRKEYMSK(PIPE_A), D_ALL);
1581 MMIO_DH(SPRSURF(PIPE_A), D_ALL, NULL, spr_surf_mmio_write);
1582 MMIO_D(SPRKEYMAX(PIPE_A), D_ALL);
1583 MMIO_D(SPROFFSET(PIPE_A), D_ALL);
1584 MMIO_D(SPRSCALE(PIPE_A), D_ALL);
1585 MMIO_D(SPRSURFLIVE(PIPE_A), D_ALL);
1586
1587 MMIO_D(SPRCTL(PIPE_B), D_ALL);
1588 MMIO_D(SPRLINOFF(PIPE_B), D_ALL);
1589 MMIO_D(SPRSTRIDE(PIPE_B), D_ALL);
1590 MMIO_D(SPRPOS(PIPE_B), D_ALL);
1591 MMIO_D(SPRSIZE(PIPE_B), D_ALL);
1592 MMIO_D(SPRKEYVAL(PIPE_B), D_ALL);
1593 MMIO_D(SPRKEYMSK(PIPE_B), D_ALL);
1594 MMIO_DH(SPRSURF(PIPE_B), D_ALL, NULL, spr_surf_mmio_write);
1595 MMIO_D(SPRKEYMAX(PIPE_B), D_ALL);
1596 MMIO_D(SPROFFSET(PIPE_B), D_ALL);
1597 MMIO_D(SPRSCALE(PIPE_B), D_ALL);
1598 MMIO_D(SPRSURFLIVE(PIPE_B), D_ALL);
1599
1600 MMIO_D(SPRCTL(PIPE_C), D_ALL);
1601 MMIO_D(SPRLINOFF(PIPE_C), D_ALL);
1602 MMIO_D(SPRSTRIDE(PIPE_C), D_ALL);
1603 MMIO_D(SPRPOS(PIPE_C), D_ALL);
1604 MMIO_D(SPRSIZE(PIPE_C), D_ALL);
1605 MMIO_D(SPRKEYVAL(PIPE_C), D_ALL);
1606 MMIO_D(SPRKEYMSK(PIPE_C), D_ALL);
1607 MMIO_DH(SPRSURF(PIPE_C), D_ALL, NULL, spr_surf_mmio_write);
1608 MMIO_D(SPRKEYMAX(PIPE_C), D_ALL);
1609 MMIO_D(SPROFFSET(PIPE_C), D_ALL);
1610 MMIO_D(SPRSCALE(PIPE_C), D_ALL);
1611 MMIO_D(SPRSURFLIVE(PIPE_C), D_ALL);
1612
1613 MMIO_F(LGC_PALETTE(PIPE_A, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
1614 MMIO_F(LGC_PALETTE(PIPE_B, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
1615 MMIO_F(LGC_PALETTE(PIPE_C, 0), 4 * 256, 0, 0, 0, D_ALL, NULL, NULL);
1616
1617 MMIO_D(HTOTAL(TRANSCODER_A), D_ALL);
1618 MMIO_D(HBLANK(TRANSCODER_A), D_ALL);
1619 MMIO_D(HSYNC(TRANSCODER_A), D_ALL);
1620 MMIO_D(VTOTAL(TRANSCODER_A), D_ALL);
1621 MMIO_D(VBLANK(TRANSCODER_A), D_ALL);
1622 MMIO_D(VSYNC(TRANSCODER_A), D_ALL);
1623 MMIO_D(BCLRPAT(TRANSCODER_A), D_ALL);
1624 MMIO_D(VSYNCSHIFT(TRANSCODER_A), D_ALL);
1625 MMIO_D(PIPESRC(TRANSCODER_A), D_ALL);
1626
1627 MMIO_D(HTOTAL(TRANSCODER_B), D_ALL);
1628 MMIO_D(HBLANK(TRANSCODER_B), D_ALL);
1629 MMIO_D(HSYNC(TRANSCODER_B), D_ALL);
1630 MMIO_D(VTOTAL(TRANSCODER_B), D_ALL);
1631 MMIO_D(VBLANK(TRANSCODER_B), D_ALL);
1632 MMIO_D(VSYNC(TRANSCODER_B), D_ALL);
1633 MMIO_D(BCLRPAT(TRANSCODER_B), D_ALL);
1634 MMIO_D(VSYNCSHIFT(TRANSCODER_B), D_ALL);
1635 MMIO_D(PIPESRC(TRANSCODER_B), D_ALL);
1636
1637 MMIO_D(HTOTAL(TRANSCODER_C), D_ALL);
1638 MMIO_D(HBLANK(TRANSCODER_C), D_ALL);
1639 MMIO_D(HSYNC(TRANSCODER_C), D_ALL);
1640 MMIO_D(VTOTAL(TRANSCODER_C), D_ALL);
1641 MMIO_D(VBLANK(TRANSCODER_C), D_ALL);
1642 MMIO_D(VSYNC(TRANSCODER_C), D_ALL);
1643 MMIO_D(BCLRPAT(TRANSCODER_C), D_ALL);
1644 MMIO_D(VSYNCSHIFT(TRANSCODER_C), D_ALL);
1645 MMIO_D(PIPESRC(TRANSCODER_C), D_ALL);
1646
1647 MMIO_D(HTOTAL(TRANSCODER_EDP), D_ALL);
1648 MMIO_D(HBLANK(TRANSCODER_EDP), D_ALL);
1649 MMIO_D(HSYNC(TRANSCODER_EDP), D_ALL);
1650 MMIO_D(VTOTAL(TRANSCODER_EDP), D_ALL);
1651 MMIO_D(VBLANK(TRANSCODER_EDP), D_ALL);
1652 MMIO_D(VSYNC(TRANSCODER_EDP), D_ALL);
1653 MMIO_D(BCLRPAT(TRANSCODER_EDP), D_ALL);
1654 MMIO_D(VSYNCSHIFT(TRANSCODER_EDP), D_ALL);
1655
1656 MMIO_D(PIPE_DATA_M1(TRANSCODER_A), D_ALL);
1657 MMIO_D(PIPE_DATA_N1(TRANSCODER_A), D_ALL);
1658 MMIO_D(PIPE_DATA_M2(TRANSCODER_A), D_ALL);
1659 MMIO_D(PIPE_DATA_N2(TRANSCODER_A), D_ALL);
1660 MMIO_D(PIPE_LINK_M1(TRANSCODER_A), D_ALL);
1661 MMIO_D(PIPE_LINK_N1(TRANSCODER_A), D_ALL);
1662 MMIO_D(PIPE_LINK_M2(TRANSCODER_A), D_ALL);
1663 MMIO_D(PIPE_LINK_N2(TRANSCODER_A), D_ALL);
1664
1665 MMIO_D(PIPE_DATA_M1(TRANSCODER_B), D_ALL);
1666 MMIO_D(PIPE_DATA_N1(TRANSCODER_B), D_ALL);
1667 MMIO_D(PIPE_DATA_M2(TRANSCODER_B), D_ALL);
1668 MMIO_D(PIPE_DATA_N2(TRANSCODER_B), D_ALL);
1669 MMIO_D(PIPE_LINK_M1(TRANSCODER_B), D_ALL);
1670 MMIO_D(PIPE_LINK_N1(TRANSCODER_B), D_ALL);
1671 MMIO_D(PIPE_LINK_M2(TRANSCODER_B), D_ALL);
1672 MMIO_D(PIPE_LINK_N2(TRANSCODER_B), D_ALL);
1673
1674 MMIO_D(PIPE_DATA_M1(TRANSCODER_C), D_ALL);
1675 MMIO_D(PIPE_DATA_N1(TRANSCODER_C), D_ALL);
1676 MMIO_D(PIPE_DATA_M2(TRANSCODER_C), D_ALL);
1677 MMIO_D(PIPE_DATA_N2(TRANSCODER_C), D_ALL);
1678 MMIO_D(PIPE_LINK_M1(TRANSCODER_C), D_ALL);
1679 MMIO_D(PIPE_LINK_N1(TRANSCODER_C), D_ALL);
1680 MMIO_D(PIPE_LINK_M2(TRANSCODER_C), D_ALL);
1681 MMIO_D(PIPE_LINK_N2(TRANSCODER_C), D_ALL);
1682
1683 MMIO_D(PIPE_DATA_M1(TRANSCODER_EDP), D_ALL);
1684 MMIO_D(PIPE_DATA_N1(TRANSCODER_EDP), D_ALL);
1685 MMIO_D(PIPE_DATA_M2(TRANSCODER_EDP), D_ALL);
1686 MMIO_D(PIPE_DATA_N2(TRANSCODER_EDP), D_ALL);
1687 MMIO_D(PIPE_LINK_M1(TRANSCODER_EDP), D_ALL);
1688 MMIO_D(PIPE_LINK_N1(TRANSCODER_EDP), D_ALL);
1689 MMIO_D(PIPE_LINK_M2(TRANSCODER_EDP), D_ALL);
1690 MMIO_D(PIPE_LINK_N2(TRANSCODER_EDP), D_ALL);
1691
1692 MMIO_D(PF_CTL(PIPE_A), D_ALL);
1693 MMIO_D(PF_WIN_SZ(PIPE_A), D_ALL);
1694 MMIO_D(PF_WIN_POS(PIPE_A), D_ALL);
1695 MMIO_D(PF_VSCALE(PIPE_A), D_ALL);
1696 MMIO_D(PF_HSCALE(PIPE_A), D_ALL);
1697
1698 MMIO_D(PF_CTL(PIPE_B), D_ALL);
1699 MMIO_D(PF_WIN_SZ(PIPE_B), D_ALL);
1700 MMIO_D(PF_WIN_POS(PIPE_B), D_ALL);
1701 MMIO_D(PF_VSCALE(PIPE_B), D_ALL);
1702 MMIO_D(PF_HSCALE(PIPE_B), D_ALL);
1703
1704 MMIO_D(PF_CTL(PIPE_C), D_ALL);
1705 MMIO_D(PF_WIN_SZ(PIPE_C), D_ALL);
1706 MMIO_D(PF_WIN_POS(PIPE_C), D_ALL);
1707 MMIO_D(PF_VSCALE(PIPE_C), D_ALL);
1708 MMIO_D(PF_HSCALE(PIPE_C), D_ALL);
1709
1710 MMIO_D(WM0_PIPEA_ILK, D_ALL);
1711 MMIO_D(WM0_PIPEB_ILK, D_ALL);
1712 MMIO_D(WM0_PIPEC_IVB, D_ALL);
1713 MMIO_D(WM1_LP_ILK, D_ALL);
1714 MMIO_D(WM2_LP_ILK, D_ALL);
1715 MMIO_D(WM3_LP_ILK, D_ALL);
1716 MMIO_D(WM1S_LP_ILK, D_ALL);
1717 MMIO_D(WM2S_LP_IVB, D_ALL);
1718 MMIO_D(WM3S_LP_IVB, D_ALL);
1719
1720 MMIO_D(BLC_PWM_CPU_CTL2, D_ALL);
1721 MMIO_D(BLC_PWM_CPU_CTL, D_ALL);
1722 MMIO_D(BLC_PWM_PCH_CTL1, D_ALL);
1723 MMIO_D(BLC_PWM_PCH_CTL2, D_ALL);
1724
1725 MMIO_D(0x48268, D_ALL);
1726
1727 MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
1728 gmbus_mmio_write);
1729 MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
1730 MMIO_F(0xe4f00, 0x28, 0, 0, 0, D_ALL, NULL, NULL);
1731
1732 MMIO_F(_PCH_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1733 dp_aux_ch_ctl_mmio_write);
1734 MMIO_F(_PCH_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1735 dp_aux_ch_ctl_mmio_write);
1736 MMIO_F(_PCH_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
1737 dp_aux_ch_ctl_mmio_write);
1738
1739 MMIO_RO(PCH_ADPA, D_ALL, 0, ADPA_CRT_HOTPLUG_MONITOR_MASK, NULL, pch_adpa_mmio_write);
1740
1741 MMIO_DH(_PCH_TRANSACONF, D_ALL, NULL, transconf_mmio_write);
1742 MMIO_DH(_PCH_TRANSBCONF, D_ALL, NULL, transconf_mmio_write);
1743
1744 MMIO_DH(FDI_RX_IIR(PIPE_A), D_ALL, NULL, fdi_rx_iir_mmio_write);
1745 MMIO_DH(FDI_RX_IIR(PIPE_B), D_ALL, NULL, fdi_rx_iir_mmio_write);
1746 MMIO_DH(FDI_RX_IIR(PIPE_C), D_ALL, NULL, fdi_rx_iir_mmio_write);
1747 MMIO_DH(FDI_RX_IMR(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1748 MMIO_DH(FDI_RX_IMR(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1749 MMIO_DH(FDI_RX_IMR(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1750 MMIO_DH(FDI_RX_CTL(PIPE_A), D_ALL, NULL, update_fdi_rx_iir_status);
1751 MMIO_DH(FDI_RX_CTL(PIPE_B), D_ALL, NULL, update_fdi_rx_iir_status);
1752 MMIO_DH(FDI_RX_CTL(PIPE_C), D_ALL, NULL, update_fdi_rx_iir_status);
1753
1754 MMIO_D(_PCH_TRANS_HTOTAL_A, D_ALL);
1755 MMIO_D(_PCH_TRANS_HBLANK_A, D_ALL);
1756 MMIO_D(_PCH_TRANS_HSYNC_A, D_ALL);
1757 MMIO_D(_PCH_TRANS_VTOTAL_A, D_ALL);
1758 MMIO_D(_PCH_TRANS_VBLANK_A, D_ALL);
1759 MMIO_D(_PCH_TRANS_VSYNC_A, D_ALL);
1760 MMIO_D(_PCH_TRANS_VSYNCSHIFT_A, D_ALL);
1761
1762 MMIO_D(_PCH_TRANS_HTOTAL_B, D_ALL);
1763 MMIO_D(_PCH_TRANS_HBLANK_B, D_ALL);
1764 MMIO_D(_PCH_TRANS_HSYNC_B, D_ALL);
1765 MMIO_D(_PCH_TRANS_VTOTAL_B, D_ALL);
1766 MMIO_D(_PCH_TRANS_VBLANK_B, D_ALL);
1767 MMIO_D(_PCH_TRANS_VSYNC_B, D_ALL);
1768 MMIO_D(_PCH_TRANS_VSYNCSHIFT_B, D_ALL);
1769
1770 MMIO_D(_PCH_TRANSA_DATA_M1, D_ALL);
1771 MMIO_D(_PCH_TRANSA_DATA_N1, D_ALL);
1772 MMIO_D(_PCH_TRANSA_DATA_M2, D_ALL);
1773 MMIO_D(_PCH_TRANSA_DATA_N2, D_ALL);
1774 MMIO_D(_PCH_TRANSA_LINK_M1, D_ALL);
1775 MMIO_D(_PCH_TRANSA_LINK_N1, D_ALL);
1776 MMIO_D(_PCH_TRANSA_LINK_M2, D_ALL);
1777 MMIO_D(_PCH_TRANSA_LINK_N2, D_ALL);
1778
1779 MMIO_D(TRANS_DP_CTL(PIPE_A), D_ALL);
1780 MMIO_D(TRANS_DP_CTL(PIPE_B), D_ALL);
1781 MMIO_D(TRANS_DP_CTL(PIPE_C), D_ALL);
1782
1783 MMIO_D(TVIDEO_DIP_CTL(PIPE_A), D_ALL);
1784 MMIO_D(TVIDEO_DIP_DATA(PIPE_A), D_ALL);
1785 MMIO_D(TVIDEO_DIP_GCP(PIPE_A), D_ALL);
1786
1787 MMIO_D(TVIDEO_DIP_CTL(PIPE_B), D_ALL);
1788 MMIO_D(TVIDEO_DIP_DATA(PIPE_B), D_ALL);
1789 MMIO_D(TVIDEO_DIP_GCP(PIPE_B), D_ALL);
1790
1791 MMIO_D(TVIDEO_DIP_CTL(PIPE_C), D_ALL);
1792 MMIO_D(TVIDEO_DIP_DATA(PIPE_C), D_ALL);
1793 MMIO_D(TVIDEO_DIP_GCP(PIPE_C), D_ALL);
1794
1795 MMIO_D(_FDI_RXA_MISC, D_ALL);
1796 MMIO_D(_FDI_RXB_MISC, D_ALL);
1797 MMIO_D(_FDI_RXA_TUSIZE1, D_ALL);
1798 MMIO_D(_FDI_RXA_TUSIZE2, D_ALL);
1799 MMIO_D(_FDI_RXB_TUSIZE1, D_ALL);
1800 MMIO_D(_FDI_RXB_TUSIZE2, D_ALL);
1801
1802 MMIO_DH(PCH_PP_CONTROL, D_ALL, NULL, pch_pp_control_mmio_write);
1803 MMIO_D(PCH_PP_DIVISOR, D_ALL);
1804 MMIO_D(PCH_PP_STATUS, D_ALL);
1805 MMIO_D(PCH_LVDS, D_ALL);
1806 MMIO_D(_PCH_DPLL_A, D_ALL);
1807 MMIO_D(_PCH_DPLL_B, D_ALL);
1808 MMIO_D(_PCH_FPA0, D_ALL);
1809 MMIO_D(_PCH_FPA1, D_ALL);
1810 MMIO_D(_PCH_FPB0, D_ALL);
1811 MMIO_D(_PCH_FPB1, D_ALL);
1812 MMIO_D(PCH_DREF_CONTROL, D_ALL);
1813 MMIO_D(PCH_RAWCLK_FREQ, D_ALL);
1814 MMIO_D(PCH_DPLL_SEL, D_ALL);
1815
1816 MMIO_D(0x61208, D_ALL);
1817 MMIO_D(0x6120c, D_ALL);
1818 MMIO_D(PCH_PP_ON_DELAYS, D_ALL);
1819 MMIO_D(PCH_PP_OFF_DELAYS, D_ALL);
1820
1821 MMIO_DH(0xe651c, D_ALL, dpy_reg_mmio_read, NULL);
1822 MMIO_DH(0xe661c, D_ALL, dpy_reg_mmio_read, NULL);
1823 MMIO_DH(0xe671c, D_ALL, dpy_reg_mmio_read, NULL);
1824 MMIO_DH(0xe681c, D_ALL, dpy_reg_mmio_read, NULL);
1825 MMIO_DH(0xe6c04, D_ALL, dpy_reg_mmio_read_2, NULL);
1826 MMIO_DH(0xe6e1c, D_ALL, dpy_reg_mmio_read_3, NULL);
1827
1828 MMIO_RO(PCH_PORT_HOTPLUG, D_ALL, 0,
1829 PORTA_HOTPLUG_STATUS_MASK
1830 | PORTB_HOTPLUG_STATUS_MASK
1831 | PORTC_HOTPLUG_STATUS_MASK
1832 | PORTD_HOTPLUG_STATUS_MASK,
1833 NULL, NULL);
1834
1835 MMIO_DH(LCPLL_CTL, D_ALL, NULL, lcpll_ctl_mmio_write);
1836 MMIO_D(FUSE_STRAP, D_ALL);
1837 MMIO_D(DIGITAL_PORT_HOTPLUG_CNTRL, D_ALL);
1838
1839 MMIO_D(DISP_ARB_CTL, D_ALL);
1840 MMIO_D(DISP_ARB_CTL2, D_ALL);
1841
1842 MMIO_D(ILK_DISPLAY_CHICKEN1, D_ALL);
1843 MMIO_D(ILK_DISPLAY_CHICKEN2, D_ALL);
1844 MMIO_D(ILK_DSPCLK_GATE_D, D_ALL);
1845
1846 MMIO_D(SOUTH_CHICKEN1, D_ALL);
1847 MMIO_DH(SOUTH_CHICKEN2, D_ALL, NULL, south_chicken2_mmio_write);
1848 MMIO_D(_TRANSA_CHICKEN1, D_ALL);
1849 MMIO_D(_TRANSB_CHICKEN1, D_ALL);
1850 MMIO_D(SOUTH_DSPCLK_GATE_D, D_ALL);
1851 MMIO_D(_TRANSA_CHICKEN2, D_ALL);
1852 MMIO_D(_TRANSB_CHICKEN2, D_ALL);
1853
1854 MMIO_D(ILK_DPFC_CB_BASE, D_ALL);
1855 MMIO_D(ILK_DPFC_CONTROL, D_ALL);
1856 MMIO_D(ILK_DPFC_RECOMP_CTL, D_ALL);
1857 MMIO_D(ILK_DPFC_STATUS, D_ALL);
1858 MMIO_D(ILK_DPFC_FENCE_YOFF, D_ALL);
1859 MMIO_D(ILK_DPFC_CHICKEN, D_ALL);
1860 MMIO_D(ILK_FBC_RT_BASE, D_ALL);
1861
1862 MMIO_D(IPS_CTL, D_ALL);
1863
1864 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_A), D_ALL);
1865 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_A), D_ALL);
1866 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_A), D_ALL);
1867 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_A), D_ALL);
1868 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_A), D_ALL);
1869 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_A), D_ALL);
1870 MMIO_D(PIPE_CSC_MODE(PIPE_A), D_ALL);
1871 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_A), D_ALL);
1872 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_A), D_ALL);
1873 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_A), D_ALL);
1874 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_A), D_ALL);
1875 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_A), D_ALL);
1876 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_A), D_ALL);
1877
1878 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_B), D_ALL);
1879 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_B), D_ALL);
1880 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_B), D_ALL);
1881 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_B), D_ALL);
1882 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_B), D_ALL);
1883 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_B), D_ALL);
1884 MMIO_D(PIPE_CSC_MODE(PIPE_B), D_ALL);
1885 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_B), D_ALL);
1886 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_B), D_ALL);
1887 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_B), D_ALL);
1888 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_B), D_ALL);
1889 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_B), D_ALL);
1890 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_B), D_ALL);
1891
1892 MMIO_D(PIPE_CSC_COEFF_RY_GY(PIPE_C), D_ALL);
1893 MMIO_D(PIPE_CSC_COEFF_BY(PIPE_C), D_ALL);
1894 MMIO_D(PIPE_CSC_COEFF_RU_GU(PIPE_C), D_ALL);
1895 MMIO_D(PIPE_CSC_COEFF_BU(PIPE_C), D_ALL);
1896 MMIO_D(PIPE_CSC_COEFF_RV_GV(PIPE_C), D_ALL);
1897 MMIO_D(PIPE_CSC_COEFF_BV(PIPE_C), D_ALL);
1898 MMIO_D(PIPE_CSC_MODE(PIPE_C), D_ALL);
1899 MMIO_D(PIPE_CSC_PREOFF_HI(PIPE_C), D_ALL);
1900 MMIO_D(PIPE_CSC_PREOFF_ME(PIPE_C), D_ALL);
1901 MMIO_D(PIPE_CSC_PREOFF_LO(PIPE_C), D_ALL);
1902 MMIO_D(PIPE_CSC_POSTOFF_HI(PIPE_C), D_ALL);
1903 MMIO_D(PIPE_CSC_POSTOFF_ME(PIPE_C), D_ALL);
1904 MMIO_D(PIPE_CSC_POSTOFF_LO(PIPE_C), D_ALL);
1905
1906 MMIO_D(PREC_PAL_INDEX(PIPE_A), D_ALL);
1907 MMIO_D(PREC_PAL_DATA(PIPE_A), D_ALL);
1908 MMIO_F(PREC_PAL_GC_MAX(PIPE_A, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
1909
1910 MMIO_D(PREC_PAL_INDEX(PIPE_B), D_ALL);
1911 MMIO_D(PREC_PAL_DATA(PIPE_B), D_ALL);
1912 MMIO_F(PREC_PAL_GC_MAX(PIPE_B, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
1913
1914 MMIO_D(PREC_PAL_INDEX(PIPE_C), D_ALL);
1915 MMIO_D(PREC_PAL_DATA(PIPE_C), D_ALL);
1916 MMIO_F(PREC_PAL_GC_MAX(PIPE_C, 0), 4 * 3, 0, 0, 0, D_ALL, NULL, NULL);
1917
1918 MMIO_D(0x60110, D_ALL);
1919 MMIO_D(0x61110, D_ALL);
1920 MMIO_F(0x70400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
1921 MMIO_F(0x71400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
1922 MMIO_F(0x72400, 0x40, 0, 0, 0, D_ALL, NULL, NULL);
1923 MMIO_F(0x70440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
1924 MMIO_F(0x71440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
1925 MMIO_F(0x72440, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
1926 MMIO_F(0x7044c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
1927 MMIO_F(0x7144c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
1928 MMIO_F(0x7244c, 0xc, 0, 0, 0, D_PRE_SKL, NULL, NULL);
1929
1930 MMIO_D(PIPE_WM_LINETIME(PIPE_A), D_ALL);
1931 MMIO_D(PIPE_WM_LINETIME(PIPE_B), D_ALL);
1932 MMIO_D(PIPE_WM_LINETIME(PIPE_C), D_ALL);
1933 MMIO_D(SPLL_CTL, D_ALL);
1934 MMIO_D(_WRPLL_CTL1, D_ALL);
1935 MMIO_D(_WRPLL_CTL2, D_ALL);
1936 MMIO_D(PORT_CLK_SEL(PORT_A), D_ALL);
1937 MMIO_D(PORT_CLK_SEL(PORT_B), D_ALL);
1938 MMIO_D(PORT_CLK_SEL(PORT_C), D_ALL);
1939 MMIO_D(PORT_CLK_SEL(PORT_D), D_ALL);
1940 MMIO_D(PORT_CLK_SEL(PORT_E), D_ALL);
1941 MMIO_D(TRANS_CLK_SEL(TRANSCODER_A), D_ALL);
1942 MMIO_D(TRANS_CLK_SEL(TRANSCODER_B), D_ALL);
1943 MMIO_D(TRANS_CLK_SEL(TRANSCODER_C), D_ALL);
1944
1945 MMIO_D(HSW_NDE_RSTWRN_OPT, D_ALL);
1946 MMIO_D(0x46508, D_ALL);
1947
1948 MMIO_D(0x49080, D_ALL);
1949 MMIO_D(0x49180, D_ALL);
1950 MMIO_D(0x49280, D_ALL);
1951
1952 MMIO_F(0x49090, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
1953 MMIO_F(0x49190, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
1954 MMIO_F(0x49290, 0x14, 0, 0, 0, D_ALL, NULL, NULL);
1955
1956 MMIO_D(GAMMA_MODE(PIPE_A), D_ALL);
1957 MMIO_D(GAMMA_MODE(PIPE_B), D_ALL);
1958 MMIO_D(GAMMA_MODE(PIPE_C), D_ALL);
1959
1960 MMIO_D(PIPE_MULT(PIPE_A), D_ALL);
1961 MMIO_D(PIPE_MULT(PIPE_B), D_ALL);
1962 MMIO_D(PIPE_MULT(PIPE_C), D_ALL);
1963
1964 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_A), D_ALL);
1965 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_B), D_ALL);
1966 MMIO_D(HSW_TVIDEO_DIP_CTL(TRANSCODER_C), D_ALL);
1967
1968 MMIO_DH(SFUSE_STRAP, D_ALL, NULL, NULL);
1969 MMIO_D(SBI_ADDR, D_ALL);
1970 MMIO_DH(SBI_DATA, D_ALL, sbi_data_mmio_read, NULL);
1971 MMIO_DH(SBI_CTL_STAT, D_ALL, NULL, sbi_ctl_mmio_write);
1972 MMIO_D(PIXCLK_GATE, D_ALL);
1973
1974 MMIO_F(_DPA_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_ALL, NULL,
1975 dp_aux_ch_ctl_mmio_write);
1976
1977 MMIO_DH(DDI_BUF_CTL(PORT_A), D_ALL, NULL, ddi_buf_ctl_mmio_write);
1978 MMIO_DH(DDI_BUF_CTL(PORT_B), D_ALL, NULL, ddi_buf_ctl_mmio_write);
1979 MMIO_DH(DDI_BUF_CTL(PORT_C), D_ALL, NULL, ddi_buf_ctl_mmio_write);
1980 MMIO_DH(DDI_BUF_CTL(PORT_D), D_ALL, NULL, ddi_buf_ctl_mmio_write);
1981 MMIO_DH(DDI_BUF_CTL(PORT_E), D_ALL, NULL, ddi_buf_ctl_mmio_write);
1982
1983 MMIO_DH(DP_TP_CTL(PORT_A), D_ALL, NULL, dp_tp_ctl_mmio_write);
1984 MMIO_DH(DP_TP_CTL(PORT_B), D_ALL, NULL, dp_tp_ctl_mmio_write);
1985 MMIO_DH(DP_TP_CTL(PORT_C), D_ALL, NULL, dp_tp_ctl_mmio_write);
1986 MMIO_DH(DP_TP_CTL(PORT_D), D_ALL, NULL, dp_tp_ctl_mmio_write);
1987 MMIO_DH(DP_TP_CTL(PORT_E), D_ALL, NULL, dp_tp_ctl_mmio_write);
1988
1989 MMIO_DH(DP_TP_STATUS(PORT_A), D_ALL, NULL, dp_tp_status_mmio_write);
1990 MMIO_DH(DP_TP_STATUS(PORT_B), D_ALL, NULL, dp_tp_status_mmio_write);
1991 MMIO_DH(DP_TP_STATUS(PORT_C), D_ALL, NULL, dp_tp_status_mmio_write);
1992 MMIO_DH(DP_TP_STATUS(PORT_D), D_ALL, NULL, dp_tp_status_mmio_write);
1993 MMIO_DH(DP_TP_STATUS(PORT_E), D_ALL, NULL, NULL);
1994
1995 MMIO_F(_DDI_BUF_TRANS_A, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1996 MMIO_F(0x64e60, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1997 MMIO_F(0x64eC0, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1998 MMIO_F(0x64f20, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
1999 MMIO_F(0x64f80, 0x50, 0, 0, 0, D_ALL, NULL, NULL);
2000
2001 MMIO_D(HSW_AUD_CFG(PIPE_A), D_ALL);
2002 MMIO_D(HSW_AUD_PIN_ELD_CP_VLD, D_ALL);
2003
2004 MMIO_DH(_TRANS_DDI_FUNC_CTL_A, D_ALL, NULL, NULL);
2005 MMIO_DH(_TRANS_DDI_FUNC_CTL_B, D_ALL, NULL, NULL);
2006 MMIO_DH(_TRANS_DDI_FUNC_CTL_C, D_ALL, NULL, NULL);
2007 MMIO_DH(_TRANS_DDI_FUNC_CTL_EDP, D_ALL, NULL, NULL);
2008
2009 MMIO_D(_TRANSA_MSA_MISC, D_ALL);
2010 MMIO_D(_TRANSB_MSA_MISC, D_ALL);
2011 MMIO_D(_TRANSC_MSA_MISC, D_ALL);
2012 MMIO_D(_TRANS_EDP_MSA_MISC, D_ALL);
2013
2014 MMIO_DH(FORCEWAKE, D_ALL, NULL, NULL);
2015 MMIO_D(FORCEWAKE_ACK, D_ALL);
2016 MMIO_D(GEN6_GT_CORE_STATUS, D_ALL);
2017 MMIO_D(GEN6_GT_THREAD_STATUS_REG, D_ALL);
2018 MMIO_D(GTFIFODBG, D_ALL);
2019 MMIO_D(GTFIFOCTL, D_ALL);
2020 MMIO_DH(FORCEWAKE_MT, D_PRE_SKL, NULL, mul_force_wake_write);
2021 MMIO_DH(FORCEWAKE_ACK_HSW, D_HSW | D_BDW, NULL, NULL);
2022 MMIO_D(ECOBUS, D_ALL);
2023 MMIO_DH(GEN6_RC_CONTROL, D_ALL, NULL, NULL);
2024 MMIO_DH(GEN6_RC_STATE, D_ALL, NULL, NULL);
2025 MMIO_D(GEN6_RPNSWREQ, D_ALL);
2026 MMIO_D(GEN6_RC_VIDEO_FREQ, D_ALL);
2027 MMIO_D(GEN6_RP_DOWN_TIMEOUT, D_ALL);
2028 MMIO_D(GEN6_RP_INTERRUPT_LIMITS, D_ALL);
2029 MMIO_D(GEN6_RPSTAT1, D_ALL);
2030 MMIO_D(GEN6_RP_CONTROL, D_ALL);
2031 MMIO_D(GEN6_RP_UP_THRESHOLD, D_ALL);
2032 MMIO_D(GEN6_RP_DOWN_THRESHOLD, D_ALL);
2033 MMIO_D(GEN6_RP_CUR_UP_EI, D_ALL);
2034 MMIO_D(GEN6_RP_CUR_UP, D_ALL);
2035 MMIO_D(GEN6_RP_PREV_UP, D_ALL);
2036 MMIO_D(GEN6_RP_CUR_DOWN_EI, D_ALL);
2037 MMIO_D(GEN6_RP_CUR_DOWN, D_ALL);
2038 MMIO_D(GEN6_RP_PREV_DOWN, D_ALL);
2039 MMIO_D(GEN6_RP_UP_EI, D_ALL);
2040 MMIO_D(GEN6_RP_DOWN_EI, D_ALL);
2041 MMIO_D(GEN6_RP_IDLE_HYSTERSIS, D_ALL);
2042 MMIO_D(GEN6_RC1_WAKE_RATE_LIMIT, D_ALL);
2043 MMIO_D(GEN6_RC6_WAKE_RATE_LIMIT, D_ALL);
2044 MMIO_D(GEN6_RC6pp_WAKE_RATE_LIMIT, D_ALL);
2045 MMIO_D(GEN6_RC_EVALUATION_INTERVAL, D_ALL);
2046 MMIO_D(GEN6_RC_IDLE_HYSTERSIS, D_ALL);
2047 MMIO_D(GEN6_RC_SLEEP, D_ALL);
2048 MMIO_D(GEN6_RC1e_THRESHOLD, D_ALL);
2049 MMIO_D(GEN6_RC6_THRESHOLD, D_ALL);
2050 MMIO_D(GEN6_RC6p_THRESHOLD, D_ALL);
2051 MMIO_D(GEN6_RC6pp_THRESHOLD, D_ALL);
2052 MMIO_D(GEN6_PMINTRMSK, D_ALL);
2053 MMIO_DH(HSW_PWR_WELL_BIOS, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2054 MMIO_DH(HSW_PWR_WELL_DRIVER, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2055 MMIO_DH(HSW_PWR_WELL_KVMR, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2056 MMIO_DH(HSW_PWR_WELL_DEBUG, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2057 MMIO_DH(HSW_PWR_WELL_CTL5, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2058 MMIO_DH(HSW_PWR_WELL_CTL6, D_HSW | D_BDW, NULL, power_well_ctl_mmio_write);
2059
2060 MMIO_D(RSTDBYCTL, D_ALL);
2061
2062 MMIO_DH(GEN6_GDRST, D_ALL, NULL, gdrst_mmio_write);
2063 MMIO_F(FENCE_REG_GEN6_LO(0), 0x80, 0, 0, 0, D_ALL, fence_mmio_read, fence_mmio_write);
2064 MMIO_F(VGT_PVINFO_PAGE, VGT_PVINFO_SIZE, F_UNALIGN, 0, 0, D_ALL, pvinfo_mmio_read, pvinfo_mmio_write);
2065 MMIO_DH(CPU_VGACNTRL, D_ALL, NULL, vga_control_mmio_write);
2066
2067 MMIO_F(MCHBAR_MIRROR_BASE_SNB, 0x40000, 0, 0, 0, D_ALL, NULL, NULL);
2068
2069 MMIO_D(TILECTL, D_ALL);
2070
2071 MMIO_D(GEN6_UCGCTL1, D_ALL);
2072 MMIO_D(GEN6_UCGCTL2, D_ALL);
2073
2074 MMIO_F(0x4f000, 0x90, 0, 0, 0, D_ALL, NULL, NULL);
2075
2076 MMIO_D(GEN6_PCODE_MAILBOX, D_PRE_SKL);
2077 MMIO_D(GEN6_PCODE_DATA, D_ALL);
2078 MMIO_D(0x13812c, D_ALL);
2079 MMIO_DH(GEN7_ERR_INT, D_ALL, NULL, NULL);
2080 MMIO_D(HSW_EDRAM_CAP, D_ALL);
2081 MMIO_D(HSW_IDICR, D_ALL);
2082 MMIO_DH(GFX_FLSH_CNTL_GEN6, D_ALL, NULL, NULL);
2083
2084 MMIO_D(0x3c, D_ALL);
2085 MMIO_D(0x860, D_ALL);
2086 MMIO_D(ECOSKPD, D_ALL);
2087 MMIO_D(0x121d0, D_ALL);
2088 MMIO_D(GEN6_BLITTER_ECOSKPD, D_ALL);
2089 MMIO_D(0x41d0, D_ALL);
2090 MMIO_D(GAC_ECO_BITS, D_ALL);
2091 MMIO_D(0x6200, D_ALL);
2092 MMIO_D(0x6204, D_ALL);
2093 MMIO_D(0x6208, D_ALL);
2094 MMIO_D(0x7118, D_ALL);
2095 MMIO_D(0x7180, D_ALL);
2096 MMIO_D(0x7408, D_ALL);
2097 MMIO_D(0x7c00, D_ALL);
2098 MMIO_D(GEN6_MBCTL, D_ALL);
2099 MMIO_D(0x911c, D_ALL);
2100 MMIO_D(0x9120, D_ALL);
2101
2102 MMIO_D(GAB_CTL, D_ALL);
2103 MMIO_D(0x48800, D_ALL);
2104 MMIO_D(0xce044, D_ALL);
2105 MMIO_D(0xe6500, D_ALL);
2106 MMIO_D(0xe6504, D_ALL);
2107 MMIO_D(0xe6600, D_ALL);
2108 MMIO_D(0xe6604, D_ALL);
2109 MMIO_D(0xe6700, D_ALL);
2110 MMIO_D(0xe6704, D_ALL);
2111 MMIO_D(0xe6800, D_ALL);
2112 MMIO_D(0xe6804, D_ALL);
2113 MMIO_D(PCH_GMBUS4, D_ALL);
2114 MMIO_D(PCH_GMBUS5, D_ALL);
2115
2116 MMIO_D(0x902c, D_ALL);
2117 MMIO_D(0xec008, D_ALL);
2118 MMIO_D(0xec00c, D_ALL);
2119 MMIO_D(0xec008 + 0x18, D_ALL);
2120 MMIO_D(0xec00c + 0x18, D_ALL);
2121 MMIO_D(0xec008 + 0x18 * 2, D_ALL);
2122 MMIO_D(0xec00c + 0x18 * 2, D_ALL);
2123 MMIO_D(0xec008 + 0x18 * 3, D_ALL);
2124 MMIO_D(0xec00c + 0x18 * 3, D_ALL);
2125 MMIO_D(0xec408, D_ALL);
2126 MMIO_D(0xec40c, D_ALL);
2127 MMIO_D(0xec408 + 0x18, D_ALL);
2128 MMIO_D(0xec40c + 0x18, D_ALL);
2129 MMIO_D(0xec408 + 0x18 * 2, D_ALL);
2130 MMIO_D(0xec40c + 0x18 * 2, D_ALL);
2131 MMIO_D(0xec408 + 0x18 * 3, D_ALL);
2132 MMIO_D(0xec40c + 0x18 * 3, D_ALL);
2133 MMIO_D(0xfc810, D_ALL);
2134 MMIO_D(0xfc81c, D_ALL);
2135 MMIO_D(0xfc828, D_ALL);
2136 MMIO_D(0xfc834, D_ALL);
2137 MMIO_D(0xfcc00, D_ALL);
2138 MMIO_D(0xfcc0c, D_ALL);
2139 MMIO_D(0xfcc18, D_ALL);
2140 MMIO_D(0xfcc24, D_ALL);
2141 MMIO_D(0xfd000, D_ALL);
2142 MMIO_D(0xfd00c, D_ALL);
2143 MMIO_D(0xfd018, D_ALL);
2144 MMIO_D(0xfd024, D_ALL);
2145 MMIO_D(0xfd034, D_ALL);
2146
2147 MMIO_DH(FPGA_DBG, D_ALL, NULL, fpga_dbg_mmio_write);
2148 MMIO_D(0x2054, D_ALL);
2149 MMIO_D(0x12054, D_ALL);
2150 MMIO_D(0x22054, D_ALL);
2151 MMIO_D(0x1a054, D_ALL);
2152
2153 MMIO_D(0x44070, D_ALL);
2154
2155 MMIO_D(0x215c, D_HSW_PLUS);
2156 MMIO_DFH(0x2178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2157 MMIO_DFH(0x217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2158 MMIO_DFH(0x12178, D_ALL, F_CMD_ACCESS, NULL, NULL);
2159 MMIO_DFH(0x1217c, D_ALL, F_CMD_ACCESS, NULL, NULL);
2160
2161 MMIO_F(0x2290, 8, 0, 0, 0, D_HSW_PLUS, NULL, NULL);
2162 MMIO_D(OACONTROL, D_HSW);
2163 MMIO_D(0x2b00, D_BDW_PLUS);
2164 MMIO_D(0x2360, D_BDW_PLUS);
2165 MMIO_F(0x5200, 32, 0, 0, 0, D_ALL, NULL, NULL);
2166 MMIO_F(0x5240, 32, 0, 0, 0, D_ALL, NULL, NULL);
2167 MMIO_F(0x5280, 16, 0, 0, 0, D_ALL, NULL, NULL);
2168
2169 MMIO_DFH(0x1c17c, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2170 MMIO_DFH(0x1c178, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2171 MMIO_D(BCS_SWCTRL, D_ALL);
2172
2173 MMIO_F(HS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL);
2174 MMIO_F(DS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL);
2175 MMIO_F(IA_VERTICES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL);
2176 MMIO_F(IA_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL);
2177 MMIO_F(VS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL);
2178 MMIO_F(GS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL);
2179 MMIO_F(GS_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL);
2180 MMIO_F(CL_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL);
2181 MMIO_F(CL_PRIMITIVES_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL);
2182 MMIO_F(PS_INVOCATION_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL);
2183 MMIO_F(PS_DEPTH_COUNT, 8, 0, 0, 0, D_ALL, NULL, NULL);
2184 MMIO_DH(0x4260, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2185 MMIO_DH(0x4264, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2186 MMIO_DH(0x4268, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2187 MMIO_DH(0x426c, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2188 MMIO_DH(0x4270, D_BDW_PLUS, NULL, gvt_reg_tlb_control_handler);
2189 MMIO_DFH(0x4094, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2190
2191 return 0;
2192 }
2193
2194 static int init_broadwell_mmio_info(struct intel_gvt *gvt)
2195 {
2196 struct drm_i915_private *dev_priv = gvt->dev_priv;
2197 int ret;
2198
2199 MMIO_DH(RING_IMR(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL,
2200 intel_vgpu_reg_imr_handler);
2201
2202 MMIO_DH(GEN8_GT_IMR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2203 MMIO_DH(GEN8_GT_IER(0), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2204 MMIO_DH(GEN8_GT_IIR(0), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2205 MMIO_D(GEN8_GT_ISR(0), D_BDW_PLUS);
2206
2207 MMIO_DH(GEN8_GT_IMR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2208 MMIO_DH(GEN8_GT_IER(1), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2209 MMIO_DH(GEN8_GT_IIR(1), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2210 MMIO_D(GEN8_GT_ISR(1), D_BDW_PLUS);
2211
2212 MMIO_DH(GEN8_GT_IMR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2213 MMIO_DH(GEN8_GT_IER(2), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2214 MMIO_DH(GEN8_GT_IIR(2), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2215 MMIO_D(GEN8_GT_ISR(2), D_BDW_PLUS);
2216
2217 MMIO_DH(GEN8_GT_IMR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2218 MMIO_DH(GEN8_GT_IER(3), D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2219 MMIO_DH(GEN8_GT_IIR(3), D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2220 MMIO_D(GEN8_GT_ISR(3), D_BDW_PLUS);
2221
2222 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_A), D_BDW_PLUS, NULL,
2223 intel_vgpu_reg_imr_handler);
2224 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_A), D_BDW_PLUS, NULL,
2225 intel_vgpu_reg_ier_handler);
2226 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_A), D_BDW_PLUS, NULL,
2227 intel_vgpu_reg_iir_handler);
2228 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_A), D_BDW_PLUS);
2229
2230 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_B), D_BDW_PLUS, NULL,
2231 intel_vgpu_reg_imr_handler);
2232 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_B), D_BDW_PLUS, NULL,
2233 intel_vgpu_reg_ier_handler);
2234 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_B), D_BDW_PLUS, NULL,
2235 intel_vgpu_reg_iir_handler);
2236 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_B), D_BDW_PLUS);
2237
2238 MMIO_DH(GEN8_DE_PIPE_IMR(PIPE_C), D_BDW_PLUS, NULL,
2239 intel_vgpu_reg_imr_handler);
2240 MMIO_DH(GEN8_DE_PIPE_IER(PIPE_C), D_BDW_PLUS, NULL,
2241 intel_vgpu_reg_ier_handler);
2242 MMIO_DH(GEN8_DE_PIPE_IIR(PIPE_C), D_BDW_PLUS, NULL,
2243 intel_vgpu_reg_iir_handler);
2244 MMIO_D(GEN8_DE_PIPE_ISR(PIPE_C), D_BDW_PLUS);
2245
2246 MMIO_DH(GEN8_DE_PORT_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2247 MMIO_DH(GEN8_DE_PORT_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2248 MMIO_DH(GEN8_DE_PORT_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2249 MMIO_D(GEN8_DE_PORT_ISR, D_BDW_PLUS);
2250
2251 MMIO_DH(GEN8_DE_MISC_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2252 MMIO_DH(GEN8_DE_MISC_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2253 MMIO_DH(GEN8_DE_MISC_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2254 MMIO_D(GEN8_DE_MISC_ISR, D_BDW_PLUS);
2255
2256 MMIO_DH(GEN8_PCU_IMR, D_BDW_PLUS, NULL, intel_vgpu_reg_imr_handler);
2257 MMIO_DH(GEN8_PCU_IER, D_BDW_PLUS, NULL, intel_vgpu_reg_ier_handler);
2258 MMIO_DH(GEN8_PCU_IIR, D_BDW_PLUS, NULL, intel_vgpu_reg_iir_handler);
2259 MMIO_D(GEN8_PCU_ISR, D_BDW_PLUS);
2260
2261 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL,
2262 intel_vgpu_reg_master_irq_handler);
2263
2264 MMIO_D(RING_HWSTAM(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
2265 MMIO_D(0x1c134, D_BDW_PLUS);
2266
2267 MMIO_D(RING_TAIL(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
2268 MMIO_D(RING_HEAD(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
2269 MMIO_GM(RING_START(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, NULL);
2270 MMIO_D(RING_CTL(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
2271 MMIO_D(RING_ACTHD(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
2272 MMIO_D(RING_ACTHD_UDW(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
2273 MMIO_DFH(0x1c29c, D_BDW_PLUS, F_MODE_MASK, NULL, ring_mode_mmio_write);
2274 MMIO_DFH(RING_MI_MODE(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK,
2275 NULL, NULL);
2276 MMIO_DFH(RING_INSTPM(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK,
2277 NULL, NULL);
2278 MMIO_DFH(RING_TIMESTAMP(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_CMD_ACCESS,
2279 ring_timestamp_mmio_read, NULL);
2280
2281 MMIO_RING_D(RING_ACTHD_UDW, D_BDW_PLUS);
2282
2283 #define RING_REG(base) (base + 0x230)
2284 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, 0, NULL, elsp_mmio_write);
2285 MMIO_DH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, NULL, elsp_mmio_write);
2286 #undef RING_REG
2287
2288 #define RING_REG(base) (base + 0x234)
2289 MMIO_RING_F(RING_REG, 8, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2290 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 4, F_RO, 0, ~0LL, D_BDW_PLUS, NULL, NULL);
2291 #undef RING_REG
2292
2293 #define RING_REG(base) (base + 0x244)
2294 MMIO_RING_D(RING_REG, D_BDW_PLUS);
2295 MMIO_D(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS);
2296 #undef RING_REG
2297
2298 #define RING_REG(base) (base + 0x370)
2299 MMIO_RING_F(RING_REG, 48, F_RO, 0, ~0, D_BDW_PLUS, NULL, NULL);
2300 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 48, F_RO, 0, ~0, D_BDW_PLUS,
2301 NULL, NULL);
2302 #undef RING_REG
2303
2304 #define RING_REG(base) (base + 0x3a0)
2305 MMIO_RING_DFH(RING_REG, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2306 MMIO_DFH(RING_REG(GEN8_BSD2_RING_BASE), D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2307 #undef RING_REG
2308
2309 MMIO_D(PIPEMISC(PIPE_A), D_BDW_PLUS);
2310 MMIO_D(PIPEMISC(PIPE_B), D_BDW_PLUS);
2311 MMIO_D(PIPEMISC(PIPE_C), D_BDW_PLUS);
2312 MMIO_D(0x1c1d0, D_BDW_PLUS);
2313 MMIO_D(GEN6_MBCUNIT_SNPCR, D_BDW_PLUS);
2314 MMIO_D(GEN7_MISCCPCTL, D_BDW_PLUS);
2315 MMIO_D(0x1c054, D_BDW_PLUS);
2316
2317 MMIO_D(GEN8_PRIVATE_PAT_LO, D_BDW_PLUS);
2318 MMIO_D(GEN8_PRIVATE_PAT_HI, D_BDW_PLUS);
2319
2320 MMIO_D(GAMTARBMODE, D_BDW_PLUS);
2321
2322 #define RING_REG(base) (base + 0x270)
2323 MMIO_RING_F(RING_REG, 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2324 MMIO_F(RING_REG(GEN8_BSD2_RING_BASE), 32, 0, 0, 0, D_BDW_PLUS, NULL, NULL);
2325 #undef RING_REG
2326
2327 MMIO_RING_GM(RING_HWS_PGA, D_BDW_PLUS, NULL, NULL);
2328 MMIO_GM(0x1c080, D_BDW_PLUS, NULL, NULL);
2329
2330 MMIO_DFH(HDC_CHICKEN0, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2331
2332 MMIO_D(CHICKEN_PIPESL_1(PIPE_A), D_BDW);
2333 MMIO_D(CHICKEN_PIPESL_1(PIPE_B), D_BDW);
2334 MMIO_D(CHICKEN_PIPESL_1(PIPE_C), D_BDW);
2335
2336 MMIO_D(WM_MISC, D_BDW);
2337 MMIO_D(BDW_EDP_PSR_BASE, D_BDW);
2338
2339 MMIO_D(0x66c00, D_BDW_PLUS);
2340 MMIO_D(0x66c04, D_BDW_PLUS);
2341
2342 MMIO_D(HSW_GTT_CACHE_EN, D_BDW_PLUS);
2343
2344 MMIO_D(GEN8_EU_DISABLE0, D_BDW_PLUS);
2345 MMIO_D(GEN8_EU_DISABLE1, D_BDW_PLUS);
2346 MMIO_D(GEN8_EU_DISABLE2, D_BDW_PLUS);
2347
2348 MMIO_D(0xfdc, D_BDW);
2349 MMIO_D(GEN8_ROW_CHICKEN, D_BDW_PLUS);
2350 MMIO_D(GEN7_ROW_CHICKEN2, D_BDW_PLUS);
2351 MMIO_D(GEN8_UCGCTL6, D_BDW_PLUS);
2352
2353 MMIO_D(0xb1f0, D_BDW);
2354 MMIO_D(0xb1c0, D_BDW);
2355 MMIO_DFH(GEN8_L3SQCREG4, D_BDW_PLUS, F_CMD_ACCESS, NULL, NULL);
2356 MMIO_D(0xb100, D_BDW);
2357 MMIO_D(0xb10c, D_BDW);
2358 MMIO_D(0xb110, D_BDW);
2359
2360 MMIO_DH(0x24d0, D_BDW_PLUS, NULL, NULL);
2361 MMIO_DH(0x24d4, D_BDW_PLUS, NULL, NULL);
2362 MMIO_DH(0x24d8, D_BDW_PLUS, NULL, NULL);
2363 MMIO_DH(0x24dc, D_BDW_PLUS, NULL, NULL);
2364
2365 MMIO_D(0x83a4, D_BDW);
2366 MMIO_D(GEN8_L3_LRA_1_GPGPU, D_BDW_PLUS);
2367
2368 MMIO_D(0x8430, D_BDW);
2369
2370 MMIO_D(0x110000, D_BDW_PLUS);
2371
2372 MMIO_D(0x48400, D_BDW_PLUS);
2373
2374 MMIO_D(0x6e570, D_BDW_PLUS);
2375 MMIO_D(0x65f10, D_BDW_PLUS);
2376
2377 MMIO_DFH(0xe194, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2378 MMIO_DFH(0xe188, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2379 MMIO_DFH(0xe180, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2380 MMIO_DFH(0x2580, D_BDW_PLUS, F_MODE_MASK, NULL, NULL);
2381
2382 MMIO_D(0x2248, D_BDW);
2383
2384 return 0;
2385 }
2386
2387 static int init_skl_mmio_info(struct intel_gvt *gvt)
2388 {
2389 struct drm_i915_private *dev_priv = gvt->dev_priv;
2390 int ret;
2391
2392 MMIO_DH(FORCEWAKE_RENDER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2393 MMIO_DH(FORCEWAKE_ACK_RENDER_GEN9, D_SKL_PLUS, NULL, NULL);
2394 MMIO_DH(FORCEWAKE_BLITTER_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2395 MMIO_DH(FORCEWAKE_ACK_BLITTER_GEN9, D_SKL_PLUS, NULL, NULL);
2396 MMIO_DH(FORCEWAKE_MEDIA_GEN9, D_SKL_PLUS, NULL, mul_force_wake_write);
2397 MMIO_DH(FORCEWAKE_ACK_MEDIA_GEN9, D_SKL_PLUS, NULL, NULL);
2398
2399 MMIO_F(_DPB_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
2400 MMIO_F(_DPC_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
2401 MMIO_F(_DPD_AUX_CH_CTL, 6 * 4, 0, 0, 0, D_SKL, NULL, dp_aux_ch_ctl_mmio_write);
2402
2403 MMIO_D(HSW_PWR_WELL_BIOS, D_SKL);
2404 MMIO_DH(HSW_PWR_WELL_DRIVER, D_SKL, NULL, skl_power_well_ctl_write);
2405
2406 MMIO_DH(GEN6_PCODE_MAILBOX, D_SKL, NULL, mailbox_write);
2407 MMIO_D(0xa210, D_SKL_PLUS);
2408 MMIO_D(GEN9_MEDIA_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2409 MMIO_D(GEN9_RENDER_PG_IDLE_HYSTERESIS, D_SKL_PLUS);
2410 MMIO_DH(0x4ddc, D_SKL, NULL, skl_misc_ctl_write);
2411 MMIO_DH(0x42080, D_SKL, NULL, skl_misc_ctl_write);
2412 MMIO_D(0x45504, D_SKL);
2413 MMIO_D(0x45520, D_SKL);
2414 MMIO_D(0x46000, D_SKL);
2415 MMIO_DH(0x46010, D_SKL, NULL, skl_lcpll_write);
2416 MMIO_DH(0x46014, D_SKL, NULL, skl_lcpll_write);
2417 MMIO_D(0x6C040, D_SKL);
2418 MMIO_D(0x6C048, D_SKL);
2419 MMIO_D(0x6C050, D_SKL);
2420 MMIO_D(0x6C044, D_SKL);
2421 MMIO_D(0x6C04C, D_SKL);
2422 MMIO_D(0x6C054, D_SKL);
2423 MMIO_D(0x6c058, D_SKL);
2424 MMIO_D(0x6c05c, D_SKL);
2425 MMIO_DH(0X6c060, D_SKL, dpll_status_read, NULL);
2426
2427 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 0), D_SKL, NULL, pf_write);
2428 MMIO_DH(SKL_PS_WIN_POS(PIPE_A, 1), D_SKL, NULL, pf_write);
2429 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 0), D_SKL, NULL, pf_write);
2430 MMIO_DH(SKL_PS_WIN_POS(PIPE_B, 1), D_SKL, NULL, pf_write);
2431 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 0), D_SKL, NULL, pf_write);
2432 MMIO_DH(SKL_PS_WIN_POS(PIPE_C, 1), D_SKL, NULL, pf_write);
2433
2434 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 0), D_SKL, NULL, pf_write);
2435 MMIO_DH(SKL_PS_WIN_SZ(PIPE_A, 1), D_SKL, NULL, pf_write);
2436 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 0), D_SKL, NULL, pf_write);
2437 MMIO_DH(SKL_PS_WIN_SZ(PIPE_B, 1), D_SKL, NULL, pf_write);
2438 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 0), D_SKL, NULL, pf_write);
2439 MMIO_DH(SKL_PS_WIN_SZ(PIPE_C, 1), D_SKL, NULL, pf_write);
2440
2441 MMIO_DH(SKL_PS_CTRL(PIPE_A, 0), D_SKL, NULL, pf_write);
2442 MMIO_DH(SKL_PS_CTRL(PIPE_A, 1), D_SKL, NULL, pf_write);
2443 MMIO_DH(SKL_PS_CTRL(PIPE_B, 0), D_SKL, NULL, pf_write);
2444 MMIO_DH(SKL_PS_CTRL(PIPE_B, 1), D_SKL, NULL, pf_write);
2445 MMIO_DH(SKL_PS_CTRL(PIPE_C, 0), D_SKL, NULL, pf_write);
2446 MMIO_DH(SKL_PS_CTRL(PIPE_C, 1), D_SKL, NULL, pf_write);
2447
2448 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL);
2449 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL);
2450 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL);
2451 MMIO_DH(PLANE_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL);
2452
2453 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL);
2454 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL);
2455 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL);
2456 MMIO_DH(PLANE_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL);
2457
2458 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL);
2459 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL);
2460 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL);
2461 MMIO_DH(PLANE_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL);
2462
2463 MMIO_DH(CUR_BUF_CFG(PIPE_A), D_SKL, NULL, NULL);
2464 MMIO_DH(CUR_BUF_CFG(PIPE_B), D_SKL, NULL, NULL);
2465 MMIO_DH(CUR_BUF_CFG(PIPE_C), D_SKL, NULL, NULL);
2466
2467 MMIO_F(PLANE_WM(PIPE_A, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2468 MMIO_F(PLANE_WM(PIPE_A, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2469 MMIO_F(PLANE_WM(PIPE_A, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2470
2471 MMIO_F(PLANE_WM(PIPE_B, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2472 MMIO_F(PLANE_WM(PIPE_B, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2473 MMIO_F(PLANE_WM(PIPE_B, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2474
2475 MMIO_F(PLANE_WM(PIPE_C, 0, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2476 MMIO_F(PLANE_WM(PIPE_C, 1, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2477 MMIO_F(PLANE_WM(PIPE_C, 2, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2478
2479 MMIO_F(CUR_WM(PIPE_A, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2480 MMIO_F(CUR_WM(PIPE_B, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2481 MMIO_F(CUR_WM(PIPE_C, 0), 4 * 8, 0, 0, 0, D_SKL, NULL, NULL);
2482
2483 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 0), D_SKL, NULL, NULL);
2484 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 1), D_SKL, NULL, NULL);
2485 MMIO_DH(PLANE_WM_TRANS(PIPE_A, 2), D_SKL, NULL, NULL);
2486
2487 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 0), D_SKL, NULL, NULL);
2488 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 1), D_SKL, NULL, NULL);
2489 MMIO_DH(PLANE_WM_TRANS(PIPE_B, 2), D_SKL, NULL, NULL);
2490
2491 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 0), D_SKL, NULL, NULL);
2492 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 1), D_SKL, NULL, NULL);
2493 MMIO_DH(PLANE_WM_TRANS(PIPE_C, 2), D_SKL, NULL, NULL);
2494
2495 MMIO_DH(CUR_WM_TRANS(PIPE_A), D_SKL, NULL, NULL);
2496 MMIO_DH(CUR_WM_TRANS(PIPE_B), D_SKL, NULL, NULL);
2497 MMIO_DH(CUR_WM_TRANS(PIPE_C), D_SKL, NULL, NULL);
2498
2499 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 0), D_SKL, NULL, NULL);
2500 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 1), D_SKL, NULL, NULL);
2501 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 2), D_SKL, NULL, NULL);
2502 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_A, 3), D_SKL, NULL, NULL);
2503
2504 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 0), D_SKL, NULL, NULL);
2505 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 1), D_SKL, NULL, NULL);
2506 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 2), D_SKL, NULL, NULL);
2507 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_B, 3), D_SKL, NULL, NULL);
2508
2509 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 0), D_SKL, NULL, NULL);
2510 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 1), D_SKL, NULL, NULL);
2511 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 2), D_SKL, NULL, NULL);
2512 MMIO_DH(PLANE_NV12_BUF_CFG(PIPE_C, 3), D_SKL, NULL, NULL);
2513
2514 MMIO_DH(_REG_701C0(PIPE_A, 1), D_SKL, NULL, NULL);
2515 MMIO_DH(_REG_701C0(PIPE_A, 2), D_SKL, NULL, NULL);
2516 MMIO_DH(_REG_701C0(PIPE_A, 3), D_SKL, NULL, NULL);
2517 MMIO_DH(_REG_701C0(PIPE_A, 4), D_SKL, NULL, NULL);
2518
2519 MMIO_DH(_REG_701C0(PIPE_B, 1), D_SKL, NULL, NULL);
2520 MMIO_DH(_REG_701C0(PIPE_B, 2), D_SKL, NULL, NULL);
2521 MMIO_DH(_REG_701C0(PIPE_B, 3), D_SKL, NULL, NULL);
2522 MMIO_DH(_REG_701C0(PIPE_B, 4), D_SKL, NULL, NULL);
2523
2524 MMIO_DH(_REG_701C0(PIPE_C, 1), D_SKL, NULL, NULL);
2525 MMIO_DH(_REG_701C0(PIPE_C, 2), D_SKL, NULL, NULL);
2526 MMIO_DH(_REG_701C0(PIPE_C, 3), D_SKL, NULL, NULL);
2527 MMIO_DH(_REG_701C0(PIPE_C, 4), D_SKL, NULL, NULL);
2528
2529 MMIO_DH(_REG_701C4(PIPE_A, 1), D_SKL, NULL, NULL);
2530 MMIO_DH(_REG_701C4(PIPE_A, 2), D_SKL, NULL, NULL);
2531 MMIO_DH(_REG_701C4(PIPE_A, 3), D_SKL, NULL, NULL);
2532 MMIO_DH(_REG_701C4(PIPE_A, 4), D_SKL, NULL, NULL);
2533
2534 MMIO_DH(_REG_701C4(PIPE_B, 1), D_SKL, NULL, NULL);
2535 MMIO_DH(_REG_701C4(PIPE_B, 2), D_SKL, NULL, NULL);
2536 MMIO_DH(_REG_701C4(PIPE_B, 3), D_SKL, NULL, NULL);
2537 MMIO_DH(_REG_701C4(PIPE_B, 4), D_SKL, NULL, NULL);
2538
2539 MMIO_DH(_REG_701C4(PIPE_C, 1), D_SKL, NULL, NULL);
2540 MMIO_DH(_REG_701C4(PIPE_C, 2), D_SKL, NULL, NULL);
2541 MMIO_DH(_REG_701C4(PIPE_C, 3), D_SKL, NULL, NULL);
2542 MMIO_DH(_REG_701C4(PIPE_C, 4), D_SKL, NULL, NULL);
2543
2544 MMIO_D(0x70380, D_SKL);
2545 MMIO_D(0x71380, D_SKL);
2546 MMIO_D(0x72380, D_SKL);
2547 MMIO_D(0x7039c, D_SKL);
2548
2549 MMIO_F(0x80000, 0x3000, 0, 0, 0, D_SKL, NULL, NULL);
2550 MMIO_D(0x8f074, D_SKL);
2551 MMIO_D(0x8f004, D_SKL);
2552 MMIO_D(0x8f034, D_SKL);
2553
2554 MMIO_D(0xb11c, D_SKL);
2555
2556 MMIO_D(0x51000, D_SKL);
2557 MMIO_D(0x6c00c, D_SKL);
2558
2559 MMIO_F(0xc800, 0x7f8, 0, 0, 0, D_SKL, NULL, NULL);
2560 MMIO_F(0xb020, 0x80, 0, 0, 0, D_SKL, NULL, NULL);
2561
2562 MMIO_D(0xd08, D_SKL);
2563 MMIO_D(0x20e0, D_SKL);
2564 MMIO_D(0x20ec, D_SKL);
2565
2566 /* TRTT */
2567 MMIO_D(0x4de0, D_SKL);
2568 MMIO_D(0x4de4, D_SKL);
2569 MMIO_D(0x4de8, D_SKL);
2570 MMIO_D(0x4dec, D_SKL);
2571 MMIO_D(0x4df0, D_SKL);
2572 MMIO_DH(0x4df4, D_SKL, NULL, gen9_trtte_write);
2573 MMIO_DH(0x4dfc, D_SKL, NULL, gen9_trtt_chicken_write);
2574
2575 MMIO_D(0x45008, D_SKL);
2576
2577 MMIO_D(0x46430, D_SKL);
2578
2579 MMIO_D(0x46520, D_SKL);
2580
2581 MMIO_D(0xc403c, D_SKL);
2582 MMIO_D(0xb004, D_SKL);
2583 MMIO_DH(DMA_CTRL, D_SKL_PLUS, NULL, dma_ctrl_write);
2584
2585 MMIO_D(0x65900, D_SKL);
2586 MMIO_D(0x1082c0, D_SKL);
2587 MMIO_D(0x4068, D_SKL);
2588 MMIO_D(0x67054, D_SKL);
2589 MMIO_D(0x6e560, D_SKL);
2590 MMIO_D(0x6e554, D_SKL);
2591 MMIO_D(0x2b20, D_SKL);
2592 MMIO_D(0x65f00, D_SKL);
2593 MMIO_D(0x65f08, D_SKL);
2594 MMIO_D(0x320f0, D_SKL);
2595
2596 MMIO_D(_REG_VCS2_EXCC, D_SKL);
2597 MMIO_D(0x70034, D_SKL);
2598 MMIO_D(0x71034, D_SKL);
2599 MMIO_D(0x72034, D_SKL);
2600
2601 MMIO_D(_PLANE_KEYVAL_1(PIPE_A), D_SKL);
2602 MMIO_D(_PLANE_KEYVAL_1(PIPE_B), D_SKL);
2603 MMIO_D(_PLANE_KEYVAL_1(PIPE_C), D_SKL);
2604 MMIO_D(_PLANE_KEYMSK_1(PIPE_A), D_SKL);
2605 MMIO_D(_PLANE_KEYMSK_1(PIPE_B), D_SKL);
2606 MMIO_D(_PLANE_KEYMSK_1(PIPE_C), D_SKL);
2607
2608 MMIO_D(0x44500, D_SKL);
2609 return 0;
2610 }
2611
2612 /**
2613 * intel_gvt_find_mmio_info - find MMIO information entry by aligned offset
2614 * @gvt: GVT device
2615 * @offset: register offset
2616 *
2617 * This function is used to find the MMIO information entry from hash table
2618 *
2619 * Returns:
2620 * pointer to MMIO information entry, NULL if not exists
2621 */
2622 struct intel_gvt_mmio_info *intel_gvt_find_mmio_info(struct intel_gvt *gvt,
2623 unsigned int offset)
2624 {
2625 struct intel_gvt_mmio_info *e;
2626
2627 WARN_ON(!IS_ALIGNED(offset, 4));
2628
2629 hash_for_each_possible(gvt->mmio.mmio_info_table, e, node, offset) {
2630 if (e->offset == offset)
2631 return e;
2632 }
2633 return NULL;
2634 }
2635
2636 /**
2637 * intel_gvt_clean_mmio_info - clean up MMIO information table for GVT device
2638 * @gvt: GVT device
2639 *
2640 * This function is called at the driver unloading stage, to clean up the MMIO
2641 * information table of GVT device
2642 *
2643 */
2644 void intel_gvt_clean_mmio_info(struct intel_gvt *gvt)
2645 {
2646 struct hlist_node *tmp;
2647 struct intel_gvt_mmio_info *e;
2648 int i;
2649
2650 hash_for_each_safe(gvt->mmio.mmio_info_table, i, tmp, e, node)
2651 kfree(e);
2652
2653 vfree(gvt->mmio.mmio_attribute);
2654 gvt->mmio.mmio_attribute = NULL;
2655 }
2656
2657 /**
2658 * intel_gvt_setup_mmio_info - setup MMIO information table for GVT device
2659 * @gvt: GVT device
2660 *
2661 * This function is called at the initialization stage, to setup the MMIO
2662 * information table for GVT device
2663 *
2664 * Returns:
2665 * zero on success, negative if failed.
2666 */
2667 int intel_gvt_setup_mmio_info(struct intel_gvt *gvt)
2668 {
2669 struct intel_gvt_device_info *info = &gvt->device_info;
2670 struct drm_i915_private *dev_priv = gvt->dev_priv;
2671 int ret;
2672
2673 gvt->mmio.mmio_attribute = vzalloc(info->mmio_size);
2674 if (!gvt->mmio.mmio_attribute)
2675 return -ENOMEM;
2676
2677 ret = init_generic_mmio_info(gvt);
2678 if (ret)
2679 goto err;
2680
2681 if (IS_BROADWELL(dev_priv)) {
2682 ret = init_broadwell_mmio_info(gvt);
2683 if (ret)
2684 goto err;
2685 } else if (IS_SKYLAKE(dev_priv)) {
2686 ret = init_broadwell_mmio_info(gvt);
2687 if (ret)
2688 goto err;
2689 ret = init_skl_mmio_info(gvt);
2690 if (ret)
2691 goto err;
2692 }
2693 return 0;
2694 err:
2695 intel_gvt_clean_mmio_info(gvt);
2696 return ret;
2697 }
2698
2699 /**
2700 * intel_gvt_mmio_set_accessed - mark a MMIO has been accessed
2701 * @gvt: a GVT device
2702 * @offset: register offset
2703 *
2704 */
2705 void intel_gvt_mmio_set_accessed(struct intel_gvt *gvt, unsigned int offset)
2706 {
2707 gvt->mmio.mmio_attribute[offset >> 2] |=
2708 F_ACCESSED;
2709 }
2710
2711 /**
2712 * intel_gvt_mmio_is_cmd_accessed - mark a MMIO could be accessed by command
2713 * @gvt: a GVT device
2714 * @offset: register offset
2715 *
2716 */
2717 bool intel_gvt_mmio_is_cmd_access(struct intel_gvt *gvt,
2718 unsigned int offset)
2719 {
2720 return gvt->mmio.mmio_attribute[offset >> 2] &
2721 F_CMD_ACCESS;
2722 }
2723
2724 /**
2725 * intel_gvt_mmio_is_unalign - mark a MMIO could be accessed unaligned
2726 * @gvt: a GVT device
2727 * @offset: register offset
2728 *
2729 */
2730 bool intel_gvt_mmio_is_unalign(struct intel_gvt *gvt,
2731 unsigned int offset)
2732 {
2733 return gvt->mmio.mmio_attribute[offset >> 2] &
2734 F_UNALIGN;
2735 }
2736
2737 /**
2738 * intel_gvt_mmio_set_cmd_accessed - mark a MMIO has been accessed by command
2739 * @gvt: a GVT device
2740 * @offset: register offset
2741 *
2742 */
2743 void intel_gvt_mmio_set_cmd_accessed(struct intel_gvt *gvt,
2744 unsigned int offset)
2745 {
2746 gvt->mmio.mmio_attribute[offset >> 2] |=
2747 F_CMD_ACCESSED;
2748 }
2749
2750 /**
2751 * intel_gvt_mmio_has_mode_mask - if a MMIO has a mode mask
2752 * @gvt: a GVT device
2753 * @offset: register offset
2754 *
2755 * Returns:
2756 * True if a MMIO has a mode mask in its higher 16 bits, false if it isn't.
2757 *
2758 */
2759 bool intel_gvt_mmio_has_mode_mask(struct intel_gvt *gvt, unsigned int offset)
2760 {
2761 return gvt->mmio.mmio_attribute[offset >> 2] &
2762 F_MODE_MASK;
2763 }
2764
2765 /**
2766 * intel_vgpu_default_mmio_read - default MMIO read handler
2767 * @vgpu: a vGPU
2768 * @offset: access offset
2769 * @p_data: data return buffer
2770 * @bytes: access data length
2771 *
2772 * Returns:
2773 * Zero on success, negative error code if failed.
2774 */
2775 int intel_vgpu_default_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
2776 void *p_data, unsigned int bytes)
2777 {
2778 read_vreg(vgpu, offset, p_data, bytes);
2779 return 0;
2780 }
2781
2782 /**
2783 * intel_t_default_mmio_write - default MMIO write handler
2784 * @vgpu: a vGPU
2785 * @offset: access offset
2786 * @p_data: write data buffer
2787 * @bytes: access data length
2788 *
2789 * Returns:
2790 * Zero on success, negative error code if failed.
2791 */
2792 int intel_vgpu_default_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
2793 void *p_data, unsigned int bytes)
2794 {
2795 write_vreg(vgpu, offset, p_data, bytes);
2796 return 0;
2797 }
Ubuntu Disco kernel mirror for Proxmox VE and PMG