2 * Copyright © 2010 Daniel Vetter
3 * Copyright © 2011-2014 Intel Corporation
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include <linux/slab.h> /* fault-inject.h is not standalone! */
28 #include <linux/fault-inject.h>
29 #include <linux/log2.h>
30 #include <linux/random.h>
31 #include <linux/seq_file.h>
32 #include <linux/stop_machine.h>
34 #include <asm/set_memory.h>
37 #include <drm/i915_drm.h>
40 #include "i915_vgpu.h"
41 #include "i915_trace.h"
42 #include "intel_drv.h"
43 #include "intel_frontbuffer.h"
45 #define I915_GFP_ALLOW_FAIL (GFP_KERNEL | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
48 * DOC: Global GTT views
50 * Background and previous state
52 * Historically objects could exists (be bound) in global GTT space only as
53 * singular instances with a view representing all of the object's backing pages
54 * in a linear fashion. This view will be called a normal view.
56 * To support multiple views of the same object, where the number of mapped
57 * pages is not equal to the backing store, or where the layout of the pages
58 * is not linear, concept of a GGTT view was added.
60 * One example of an alternative view is a stereo display driven by a single
61 * image. In this case we would have a framebuffer looking like this
67 * Above would represent a normal GGTT view as normally mapped for GPU or CPU
68 * rendering. In contrast, fed to the display engine would be an alternative
69 * view which could look something like this:
74 * In this example both the size and layout of pages in the alternative view is
75 * different from the normal view.
77 * Implementation and usage
79 * GGTT views are implemented using VMAs and are distinguished via enum
80 * i915_ggtt_view_type and struct i915_ggtt_view.
82 * A new flavour of core GEM functions which work with GGTT bound objects were
83 * added with the _ggtt_ infix, and sometimes with _view postfix to avoid
84 * renaming in large amounts of code. They take the struct i915_ggtt_view
85 * parameter encapsulating all metadata required to implement a view.
87 * As a helper for callers which are only interested in the normal view,
88 * globally const i915_ggtt_view_normal singleton instance exists. All old core
89 * GEM API functions, the ones not taking the view parameter, are operating on,
90 * or with the normal GGTT view.
92 * Code wanting to add or use a new GGTT view needs to:
94 * 1. Add a new enum with a suitable name.
95 * 2. Extend the metadata in the i915_ggtt_view structure if required.
96 * 3. Add support to i915_get_vma_pages().
98 * New views are required to build a scatter-gather table from within the
99 * i915_get_vma_pages function. This table is stored in the vma.ggtt_view and
100 * exists for the lifetime of an VMA.
102 * Core API is designed to have copy semantics which means that passed in
103 * struct i915_ggtt_view does not need to be persistent (left around after
104 * calling the core API functions).
109 i915_get_ggtt_vma_pages(struct i915_vma
*vma
);
111 static void gen6_ggtt_invalidate(struct drm_i915_private
*dev_priv
)
114 * Note that as an uncached mmio write, this will flush the
115 * WCB of the writes into the GGTT before it triggers the invalidate.
117 I915_WRITE(GFX_FLSH_CNTL_GEN6
, GFX_FLSH_CNTL_EN
);
120 static void guc_ggtt_invalidate(struct drm_i915_private
*dev_priv
)
122 gen6_ggtt_invalidate(dev_priv
);
123 I915_WRITE(GEN8_GTCR
, GEN8_GTCR_INVALIDATE
);
126 static void gmch_ggtt_invalidate(struct drm_i915_private
*dev_priv
)
128 intel_gtt_chipset_flush();
131 static inline void i915_ggtt_invalidate(struct drm_i915_private
*i915
)
133 i915
->ggtt
.invalidate(i915
);
136 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
140 bool has_full_48bit_ppgtt
;
142 if (!dev_priv
->info
.has_aliasing_ppgtt
)
145 has_full_ppgtt
= dev_priv
->info
.has_full_ppgtt
;
146 has_full_48bit_ppgtt
= dev_priv
->info
.has_full_48bit_ppgtt
;
148 if (intel_vgpu_active(dev_priv
)) {
149 /* GVT-g has no support for 32bit ppgtt */
150 has_full_ppgtt
= false;
151 has_full_48bit_ppgtt
= intel_vgpu_has_full_48bit_ppgtt(dev_priv
);
155 * We don't allow disabling PPGTT for gen9+ as it's a requirement for
156 * execlists, the sole mechanism available to submit work.
158 if (enable_ppgtt
== 0 && INTEL_GEN(dev_priv
) < 9)
161 if (enable_ppgtt
== 1)
164 if (enable_ppgtt
== 2 && has_full_ppgtt
)
167 if (enable_ppgtt
== 3 && has_full_48bit_ppgtt
)
170 /* Disable ppgtt on SNB if VT-d is on. */
171 if (IS_GEN6(dev_priv
) && intel_vtd_active()) {
172 DRM_INFO("Disabling PPGTT because VT-d is on\n");
176 /* Early VLV doesn't have this */
177 if (IS_VALLEYVIEW(dev_priv
) && dev_priv
->drm
.pdev
->revision
< 0xb) {
178 DRM_DEBUG_DRIVER("disabling PPGTT on pre-B3 step VLV\n");
182 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
)) {
183 if (has_full_48bit_ppgtt
)
193 static int gen6_ppgtt_bind_vma(struct i915_vma
*vma
,
194 enum i915_cache_level cache_level
,
199 /* Currently applicable only to VLV */
202 pte_flags
|= PTE_READ_ONLY
;
204 vma
->vm
->insert_entries(vma
->vm
, vma
, cache_level
, pte_flags
);
209 static int gen8_ppgtt_bind_vma(struct i915_vma
*vma
,
210 enum i915_cache_level cache_level
,
215 if (!(vma
->flags
& I915_VMA_LOCAL_BIND
)) {
216 ret
= vma
->vm
->allocate_va_range(vma
->vm
,
217 vma
->node
.start
, vma
->size
);
222 return gen6_ppgtt_bind_vma(vma
, cache_level
, unused
);
225 static void ppgtt_unbind_vma(struct i915_vma
*vma
)
227 vma
->vm
->clear_range(vma
->vm
, vma
->node
.start
, vma
->size
);
230 static int ppgtt_set_pages(struct i915_vma
*vma
)
232 GEM_BUG_ON(vma
->pages
);
234 vma
->pages
= vma
->obj
->mm
.pages
;
236 vma
->page_sizes
= vma
->obj
->mm
.page_sizes
;
241 static void clear_pages(struct i915_vma
*vma
)
243 GEM_BUG_ON(!vma
->pages
);
245 if (vma
->pages
!= vma
->obj
->mm
.pages
) {
246 sg_free_table(vma
->pages
);
251 memset(&vma
->page_sizes
, 0, sizeof(vma
->page_sizes
));
254 static gen8_pte_t
gen8_pte_encode(dma_addr_t addr
,
255 enum i915_cache_level level
)
257 gen8_pte_t pte
= _PAGE_PRESENT
| _PAGE_RW
;
261 case I915_CACHE_NONE
:
262 pte
|= PPAT_UNCACHED
;
265 pte
|= PPAT_DISPLAY_ELLC
;
275 static gen8_pde_t
gen8_pde_encode(const dma_addr_t addr
,
276 const enum i915_cache_level level
)
278 gen8_pde_t pde
= _PAGE_PRESENT
| _PAGE_RW
;
280 if (level
!= I915_CACHE_NONE
)
281 pde
|= PPAT_CACHED_PDE
;
283 pde
|= PPAT_UNCACHED
;
287 #define gen8_pdpe_encode gen8_pde_encode
288 #define gen8_pml4e_encode gen8_pde_encode
290 static gen6_pte_t
snb_pte_encode(dma_addr_t addr
,
291 enum i915_cache_level level
,
294 gen6_pte_t pte
= GEN6_PTE_VALID
;
295 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
298 case I915_CACHE_L3_LLC
:
300 pte
|= GEN6_PTE_CACHE_LLC
;
302 case I915_CACHE_NONE
:
303 pte
|= GEN6_PTE_UNCACHED
;
312 static gen6_pte_t
ivb_pte_encode(dma_addr_t addr
,
313 enum i915_cache_level level
,
316 gen6_pte_t pte
= GEN6_PTE_VALID
;
317 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
320 case I915_CACHE_L3_LLC
:
321 pte
|= GEN7_PTE_CACHE_L3_LLC
;
324 pte
|= GEN6_PTE_CACHE_LLC
;
326 case I915_CACHE_NONE
:
327 pte
|= GEN6_PTE_UNCACHED
;
336 static gen6_pte_t
byt_pte_encode(dma_addr_t addr
,
337 enum i915_cache_level level
,
340 gen6_pte_t pte
= GEN6_PTE_VALID
;
341 pte
|= GEN6_PTE_ADDR_ENCODE(addr
);
343 if (!(flags
& PTE_READ_ONLY
))
344 pte
|= BYT_PTE_WRITEABLE
;
346 if (level
!= I915_CACHE_NONE
)
347 pte
|= BYT_PTE_SNOOPED_BY_CPU_CACHES
;
352 static gen6_pte_t
hsw_pte_encode(dma_addr_t addr
,
353 enum i915_cache_level level
,
356 gen6_pte_t pte
= GEN6_PTE_VALID
;
357 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
359 if (level
!= I915_CACHE_NONE
)
360 pte
|= HSW_WB_LLC_AGE3
;
365 static gen6_pte_t
iris_pte_encode(dma_addr_t addr
,
366 enum i915_cache_level level
,
369 gen6_pte_t pte
= GEN6_PTE_VALID
;
370 pte
|= HSW_PTE_ADDR_ENCODE(addr
);
373 case I915_CACHE_NONE
:
376 pte
|= HSW_WT_ELLC_LLC_AGE3
;
379 pte
|= HSW_WB_ELLC_LLC_AGE3
;
386 static struct page
*vm_alloc_page(struct i915_address_space
*vm
, gfp_t gfp
)
388 struct pagevec
*pvec
= &vm
->free_pages
;
389 struct pagevec stash
;
391 if (I915_SELFTEST_ONLY(should_fail(&vm
->fault_attr
, 1)))
392 i915_gem_shrink_all(vm
->i915
);
394 if (likely(pvec
->nr
))
395 return pvec
->pages
[--pvec
->nr
];
398 return alloc_page(gfp
);
400 /* A placeholder for a specific mutex to guard the WC stash */
401 lockdep_assert_held(&vm
->i915
->drm
.struct_mutex
);
403 /* Look in our global stash of WC pages... */
404 pvec
= &vm
->i915
->mm
.wc_stash
;
405 if (likely(pvec
->nr
))
406 return pvec
->pages
[--pvec
->nr
];
409 * Otherwise batch allocate pages to amoritize cost of set_pages_wc.
411 * We have to be careful as page allocation may trigger the shrinker
412 * (via direct reclaim) which will fill up the WC stash underneath us.
413 * So we add our WB pages into a temporary pvec on the stack and merge
414 * them into the WC stash after all the allocations are complete.
416 pagevec_init(&stash
);
420 page
= alloc_page(gfp
);
424 stash
.pages
[stash
.nr
++] = page
;
425 } while (stash
.nr
< pagevec_space(pvec
));
428 int nr
= min_t(int, stash
.nr
, pagevec_space(pvec
));
429 struct page
**pages
= stash
.pages
+ stash
.nr
- nr
;
431 if (nr
&& !set_pages_array_wc(pages
, nr
)) {
432 memcpy(pvec
->pages
+ pvec
->nr
,
433 pages
, sizeof(pages
[0]) * nr
);
438 pagevec_release(&stash
);
441 return likely(pvec
->nr
) ? pvec
->pages
[--pvec
->nr
] : NULL
;
444 static void vm_free_pages_release(struct i915_address_space
*vm
,
447 struct pagevec
*pvec
= &vm
->free_pages
;
449 GEM_BUG_ON(!pagevec_count(pvec
));
451 if (vm
->pt_kmap_wc
) {
452 struct pagevec
*stash
= &vm
->i915
->mm
.wc_stash
;
454 /* When we use WC, first fill up the global stash and then
455 * only if full immediately free the overflow.
458 lockdep_assert_held(&vm
->i915
->drm
.struct_mutex
);
459 if (pagevec_space(stash
)) {
461 stash
->pages
[stash
->nr
++] =
462 pvec
->pages
[--pvec
->nr
];
465 } while (pagevec_space(stash
));
467 /* As we have made some room in the VM's free_pages,
468 * we can wait for it to fill again. Unless we are
469 * inside i915_address_space_fini() and must
470 * immediately release the pages!
476 set_pages_array_wb(pvec
->pages
, pvec
->nr
);
479 __pagevec_release(pvec
);
482 static void vm_free_page(struct i915_address_space
*vm
, struct page
*page
)
485 * On !llc, we need to change the pages back to WB. We only do so
486 * in bulk, so we rarely need to change the page attributes here,
487 * but doing so requires a stop_machine() from deep inside arch/x86/mm.
488 * To make detection of the possible sleep more likely, use an
489 * unconditional might_sleep() for everybody.
492 if (!pagevec_add(&vm
->free_pages
, page
))
493 vm_free_pages_release(vm
, false);
496 static int __setup_page_dma(struct i915_address_space
*vm
,
497 struct i915_page_dma
*p
,
500 p
->page
= vm_alloc_page(vm
, gfp
| I915_GFP_ALLOW_FAIL
);
501 if (unlikely(!p
->page
))
504 p
->daddr
= dma_map_page(vm
->dma
, p
->page
, 0, PAGE_SIZE
,
505 PCI_DMA_BIDIRECTIONAL
);
506 if (unlikely(dma_mapping_error(vm
->dma
, p
->daddr
))) {
507 vm_free_page(vm
, p
->page
);
514 static int setup_page_dma(struct i915_address_space
*vm
,
515 struct i915_page_dma
*p
)
517 return __setup_page_dma(vm
, p
, __GFP_HIGHMEM
);
520 static void cleanup_page_dma(struct i915_address_space
*vm
,
521 struct i915_page_dma
*p
)
523 dma_unmap_page(vm
->dma
, p
->daddr
, PAGE_SIZE
, PCI_DMA_BIDIRECTIONAL
);
524 vm_free_page(vm
, p
->page
);
527 #define kmap_atomic_px(px) kmap_atomic(px_base(px)->page)
529 #define setup_px(vm, px) setup_page_dma((vm), px_base(px))
530 #define cleanup_px(vm, px) cleanup_page_dma((vm), px_base(px))
531 #define fill_px(vm, px, v) fill_page_dma((vm), px_base(px), (v))
532 #define fill32_px(vm, px, v) fill_page_dma_32((vm), px_base(px), (v))
534 static void fill_page_dma(struct i915_address_space
*vm
,
535 struct i915_page_dma
*p
,
538 u64
* const vaddr
= kmap_atomic(p
->page
);
540 memset64(vaddr
, val
, PAGE_SIZE
/ sizeof(val
));
542 kunmap_atomic(vaddr
);
545 static void fill_page_dma_32(struct i915_address_space
*vm
,
546 struct i915_page_dma
*p
,
549 fill_page_dma(vm
, p
, (u64
)v
<< 32 | v
);
553 setup_scratch_page(struct i915_address_space
*vm
, gfp_t gfp
)
558 * In order to utilize 64K pages for an object with a size < 2M, we will
559 * need to support a 64K scratch page, given that every 16th entry for a
560 * page-table operating in 64K mode must point to a properly aligned 64K
561 * region, including any PTEs which happen to point to scratch.
563 * This is only relevant for the 48b PPGTT where we support
564 * huge-gtt-pages, see also i915_vma_insert().
566 * TODO: we should really consider write-protecting the scratch-page and
567 * sharing between ppgtt
569 size
= I915_GTT_PAGE_SIZE_4K
;
570 if (i915_vm_is_48bit(vm
) &&
571 HAS_PAGE_SIZES(vm
->i915
, I915_GTT_PAGE_SIZE_64K
)) {
572 size
= I915_GTT_PAGE_SIZE_64K
;
575 gfp
|= __GFP_ZERO
| __GFP_RETRY_MAYFAIL
;
578 int order
= get_order(size
);
582 page
= alloc_pages(gfp
, order
);
586 addr
= dma_map_page(vm
->dma
, page
, 0, size
,
587 PCI_DMA_BIDIRECTIONAL
);
588 if (unlikely(dma_mapping_error(vm
->dma
, addr
)))
591 if (unlikely(!IS_ALIGNED(addr
, size
)))
594 vm
->scratch_page
.page
= page
;
595 vm
->scratch_page
.daddr
= addr
;
596 vm
->scratch_page
.order
= order
;
600 dma_unmap_page(vm
->dma
, addr
, size
, PCI_DMA_BIDIRECTIONAL
);
602 __free_pages(page
, order
);
604 if (size
== I915_GTT_PAGE_SIZE_4K
)
607 size
= I915_GTT_PAGE_SIZE_4K
;
608 gfp
&= ~__GFP_NOWARN
;
612 static void cleanup_scratch_page(struct i915_address_space
*vm
)
614 struct i915_page_dma
*p
= &vm
->scratch_page
;
616 dma_unmap_page(vm
->dma
, p
->daddr
, BIT(p
->order
) << PAGE_SHIFT
,
617 PCI_DMA_BIDIRECTIONAL
);
618 __free_pages(p
->page
, p
->order
);
621 static struct i915_page_table
*alloc_pt(struct i915_address_space
*vm
)
623 struct i915_page_table
*pt
;
625 pt
= kmalloc(sizeof(*pt
), I915_GFP_ALLOW_FAIL
);
627 return ERR_PTR(-ENOMEM
);
629 if (unlikely(setup_px(vm
, pt
))) {
631 return ERR_PTR(-ENOMEM
);
638 static void free_pt(struct i915_address_space
*vm
, struct i915_page_table
*pt
)
644 static void gen8_initialize_pt(struct i915_address_space
*vm
,
645 struct i915_page_table
*pt
)
648 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
));
651 static void gen6_initialize_pt(struct i915_address_space
*vm
,
652 struct i915_page_table
*pt
)
655 vm
->pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
, 0));
658 static struct i915_page_directory
*alloc_pd(struct i915_address_space
*vm
)
660 struct i915_page_directory
*pd
;
662 pd
= kzalloc(sizeof(*pd
), I915_GFP_ALLOW_FAIL
);
664 return ERR_PTR(-ENOMEM
);
666 if (unlikely(setup_px(vm
, pd
))) {
668 return ERR_PTR(-ENOMEM
);
675 static void free_pd(struct i915_address_space
*vm
,
676 struct i915_page_directory
*pd
)
682 static void gen8_initialize_pd(struct i915_address_space
*vm
,
683 struct i915_page_directory
*pd
)
686 gen8_pde_encode(px_dma(vm
->scratch_pt
), I915_CACHE_LLC
));
687 memset_p((void **)pd
->page_table
, vm
->scratch_pt
, I915_PDES
);
690 static int __pdp_init(struct i915_address_space
*vm
,
691 struct i915_page_directory_pointer
*pdp
)
693 const unsigned int pdpes
= i915_pdpes_per_pdp(vm
);
695 pdp
->page_directory
= kmalloc_array(pdpes
, sizeof(*pdp
->page_directory
),
696 I915_GFP_ALLOW_FAIL
);
697 if (unlikely(!pdp
->page_directory
))
700 memset_p((void **)pdp
->page_directory
, vm
->scratch_pd
, pdpes
);
705 static void __pdp_fini(struct i915_page_directory_pointer
*pdp
)
707 kfree(pdp
->page_directory
);
708 pdp
->page_directory
= NULL
;
711 static inline bool use_4lvl(const struct i915_address_space
*vm
)
713 return i915_vm_is_48bit(vm
);
716 static struct i915_page_directory_pointer
*
717 alloc_pdp(struct i915_address_space
*vm
)
719 struct i915_page_directory_pointer
*pdp
;
722 GEM_BUG_ON(!use_4lvl(vm
));
724 pdp
= kzalloc(sizeof(*pdp
), GFP_KERNEL
);
726 return ERR_PTR(-ENOMEM
);
728 ret
= __pdp_init(vm
, pdp
);
732 ret
= setup_px(vm
, pdp
);
746 static void free_pdp(struct i915_address_space
*vm
,
747 struct i915_page_directory_pointer
*pdp
)
758 static void gen8_initialize_pdp(struct i915_address_space
*vm
,
759 struct i915_page_directory_pointer
*pdp
)
761 gen8_ppgtt_pdpe_t scratch_pdpe
;
763 scratch_pdpe
= gen8_pdpe_encode(px_dma(vm
->scratch_pd
), I915_CACHE_LLC
);
765 fill_px(vm
, pdp
, scratch_pdpe
);
768 static void gen8_initialize_pml4(struct i915_address_space
*vm
,
769 struct i915_pml4
*pml4
)
772 gen8_pml4e_encode(px_dma(vm
->scratch_pdp
), I915_CACHE_LLC
));
773 memset_p((void **)pml4
->pdps
, vm
->scratch_pdp
, GEN8_PML4ES_PER_PML4
);
776 /* PDE TLBs are a pain to invalidate on GEN8+. When we modify
777 * the page table structures, we mark them dirty so that
778 * context switching/execlist queuing code takes extra steps
779 * to ensure that tlbs are flushed.
781 static void mark_tlbs_dirty(struct i915_hw_ppgtt
*ppgtt
)
783 ppgtt
->pd_dirty_rings
= INTEL_INFO(ppgtt
->vm
.i915
)->ring_mask
;
786 /* Removes entries from a single page table, releasing it if it's empty.
787 * Caller can use the return value to update higher-level entries.
789 static bool gen8_ppgtt_clear_pt(struct i915_address_space
*vm
,
790 struct i915_page_table
*pt
,
791 u64 start
, u64 length
)
793 unsigned int num_entries
= gen8_pte_count(start
, length
);
794 unsigned int pte
= gen8_pte_index(start
);
795 unsigned int pte_end
= pte
+ num_entries
;
796 const gen8_pte_t scratch_pte
=
797 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
);
800 GEM_BUG_ON(num_entries
> pt
->used_ptes
);
802 pt
->used_ptes
-= num_entries
;
806 vaddr
= kmap_atomic_px(pt
);
807 while (pte
< pte_end
)
808 vaddr
[pte
++] = scratch_pte
;
809 kunmap_atomic(vaddr
);
814 static void gen8_ppgtt_set_pde(struct i915_address_space
*vm
,
815 struct i915_page_directory
*pd
,
816 struct i915_page_table
*pt
,
821 pd
->page_table
[pde
] = pt
;
823 vaddr
= kmap_atomic_px(pd
);
824 vaddr
[pde
] = gen8_pde_encode(px_dma(pt
), I915_CACHE_LLC
);
825 kunmap_atomic(vaddr
);
828 static bool gen8_ppgtt_clear_pd(struct i915_address_space
*vm
,
829 struct i915_page_directory
*pd
,
830 u64 start
, u64 length
)
832 struct i915_page_table
*pt
;
835 gen8_for_each_pde(pt
, pd
, start
, length
, pde
) {
836 GEM_BUG_ON(pt
== vm
->scratch_pt
);
838 if (!gen8_ppgtt_clear_pt(vm
, pt
, start
, length
))
841 gen8_ppgtt_set_pde(vm
, pd
, vm
->scratch_pt
, pde
);
842 GEM_BUG_ON(!pd
->used_pdes
);
848 return !pd
->used_pdes
;
851 static void gen8_ppgtt_set_pdpe(struct i915_address_space
*vm
,
852 struct i915_page_directory_pointer
*pdp
,
853 struct i915_page_directory
*pd
,
856 gen8_ppgtt_pdpe_t
*vaddr
;
858 pdp
->page_directory
[pdpe
] = pd
;
862 vaddr
= kmap_atomic_px(pdp
);
863 vaddr
[pdpe
] = gen8_pdpe_encode(px_dma(pd
), I915_CACHE_LLC
);
864 kunmap_atomic(vaddr
);
867 /* Removes entries from a single page dir pointer, releasing it if it's empty.
868 * Caller can use the return value to update higher-level entries
870 static bool gen8_ppgtt_clear_pdp(struct i915_address_space
*vm
,
871 struct i915_page_directory_pointer
*pdp
,
872 u64 start
, u64 length
)
874 struct i915_page_directory
*pd
;
877 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
878 GEM_BUG_ON(pd
== vm
->scratch_pd
);
880 if (!gen8_ppgtt_clear_pd(vm
, pd
, start
, length
))
883 gen8_ppgtt_set_pdpe(vm
, pdp
, vm
->scratch_pd
, pdpe
);
884 GEM_BUG_ON(!pdp
->used_pdpes
);
890 return !pdp
->used_pdpes
;
893 static void gen8_ppgtt_clear_3lvl(struct i915_address_space
*vm
,
894 u64 start
, u64 length
)
896 gen8_ppgtt_clear_pdp(vm
, &i915_vm_to_ppgtt(vm
)->pdp
, start
, length
);
899 static void gen8_ppgtt_set_pml4e(struct i915_pml4
*pml4
,
900 struct i915_page_directory_pointer
*pdp
,
903 gen8_ppgtt_pml4e_t
*vaddr
;
905 pml4
->pdps
[pml4e
] = pdp
;
907 vaddr
= kmap_atomic_px(pml4
);
908 vaddr
[pml4e
] = gen8_pml4e_encode(px_dma(pdp
), I915_CACHE_LLC
);
909 kunmap_atomic(vaddr
);
912 /* Removes entries from a single pml4.
913 * This is the top-level structure in 4-level page tables used on gen8+.
914 * Empty entries are always scratch pml4e.
916 static void gen8_ppgtt_clear_4lvl(struct i915_address_space
*vm
,
917 u64 start
, u64 length
)
919 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
920 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
921 struct i915_page_directory_pointer
*pdp
;
924 GEM_BUG_ON(!use_4lvl(vm
));
926 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
927 GEM_BUG_ON(pdp
== vm
->scratch_pdp
);
929 if (!gen8_ppgtt_clear_pdp(vm
, pdp
, start
, length
))
932 gen8_ppgtt_set_pml4e(pml4
, vm
->scratch_pdp
, pml4e
);
938 static inline struct sgt_dma
{
939 struct scatterlist
*sg
;
941 } sgt_dma(struct i915_vma
*vma
) {
942 struct scatterlist
*sg
= vma
->pages
->sgl
;
943 dma_addr_t addr
= sg_dma_address(sg
);
944 return (struct sgt_dma
) { sg
, addr
, addr
+ sg
->length
};
947 struct gen8_insert_pte
{
954 static __always_inline
struct gen8_insert_pte
gen8_insert_pte(u64 start
)
956 return (struct gen8_insert_pte
) {
957 gen8_pml4e_index(start
),
958 gen8_pdpe_index(start
),
959 gen8_pde_index(start
),
960 gen8_pte_index(start
),
964 static __always_inline
bool
965 gen8_ppgtt_insert_pte_entries(struct i915_hw_ppgtt
*ppgtt
,
966 struct i915_page_directory_pointer
*pdp
,
967 struct sgt_dma
*iter
,
968 struct gen8_insert_pte
*idx
,
969 enum i915_cache_level cache_level
)
971 struct i915_page_directory
*pd
;
972 const gen8_pte_t pte_encode
= gen8_pte_encode(0, cache_level
);
976 GEM_BUG_ON(idx
->pdpe
>= i915_pdpes_per_pdp(&ppgtt
->vm
));
977 pd
= pdp
->page_directory
[idx
->pdpe
];
978 vaddr
= kmap_atomic_px(pd
->page_table
[idx
->pde
]);
980 vaddr
[idx
->pte
] = pte_encode
| iter
->dma
;
982 iter
->dma
+= PAGE_SIZE
;
983 if (iter
->dma
>= iter
->max
) {
984 iter
->sg
= __sg_next(iter
->sg
);
990 iter
->dma
= sg_dma_address(iter
->sg
);
991 iter
->max
= iter
->dma
+ iter
->sg
->length
;
994 if (++idx
->pte
== GEN8_PTES
) {
997 if (++idx
->pde
== I915_PDES
) {
1000 /* Limited by sg length for 3lvl */
1001 if (++idx
->pdpe
== GEN8_PML4ES_PER_PML4
) {
1007 GEM_BUG_ON(idx
->pdpe
>= i915_pdpes_per_pdp(&ppgtt
->vm
));
1008 pd
= pdp
->page_directory
[idx
->pdpe
];
1011 kunmap_atomic(vaddr
);
1012 vaddr
= kmap_atomic_px(pd
->page_table
[idx
->pde
]);
1015 kunmap_atomic(vaddr
);
1020 static void gen8_ppgtt_insert_3lvl(struct i915_address_space
*vm
,
1021 struct i915_vma
*vma
,
1022 enum i915_cache_level cache_level
,
1025 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1026 struct sgt_dma iter
= sgt_dma(vma
);
1027 struct gen8_insert_pte idx
= gen8_insert_pte(vma
->node
.start
);
1029 gen8_ppgtt_insert_pte_entries(ppgtt
, &ppgtt
->pdp
, &iter
, &idx
,
1032 vma
->page_sizes
.gtt
= I915_GTT_PAGE_SIZE
;
1035 static void gen8_ppgtt_insert_huge_entries(struct i915_vma
*vma
,
1036 struct i915_page_directory_pointer
**pdps
,
1037 struct sgt_dma
*iter
,
1038 enum i915_cache_level cache_level
)
1040 const gen8_pte_t pte_encode
= gen8_pte_encode(0, cache_level
);
1041 u64 start
= vma
->node
.start
;
1042 dma_addr_t rem
= iter
->sg
->length
;
1045 struct gen8_insert_pte idx
= gen8_insert_pte(start
);
1046 struct i915_page_directory_pointer
*pdp
= pdps
[idx
.pml4e
];
1047 struct i915_page_directory
*pd
= pdp
->page_directory
[idx
.pdpe
];
1048 unsigned int page_size
;
1049 bool maybe_64K
= false;
1050 gen8_pte_t encode
= pte_encode
;
1054 if (vma
->page_sizes
.sg
& I915_GTT_PAGE_SIZE_2M
&&
1055 IS_ALIGNED(iter
->dma
, I915_GTT_PAGE_SIZE_2M
) &&
1056 rem
>= I915_GTT_PAGE_SIZE_2M
&& !idx
.pte
) {
1059 page_size
= I915_GTT_PAGE_SIZE_2M
;
1061 encode
|= GEN8_PDE_PS_2M
;
1063 vaddr
= kmap_atomic_px(pd
);
1065 struct i915_page_table
*pt
= pd
->page_table
[idx
.pde
];
1069 page_size
= I915_GTT_PAGE_SIZE
;
1072 vma
->page_sizes
.sg
& I915_GTT_PAGE_SIZE_64K
&&
1073 IS_ALIGNED(iter
->dma
, I915_GTT_PAGE_SIZE_64K
) &&
1074 (IS_ALIGNED(rem
, I915_GTT_PAGE_SIZE_64K
) ||
1075 rem
>= (max
- index
) << PAGE_SHIFT
))
1078 vaddr
= kmap_atomic_px(pt
);
1082 GEM_BUG_ON(iter
->sg
->length
< page_size
);
1083 vaddr
[index
++] = encode
| iter
->dma
;
1086 iter
->dma
+= page_size
;
1088 if (iter
->dma
>= iter
->max
) {
1089 iter
->sg
= __sg_next(iter
->sg
);
1093 rem
= iter
->sg
->length
;
1094 iter
->dma
= sg_dma_address(iter
->sg
);
1095 iter
->max
= iter
->dma
+ rem
;
1097 if (maybe_64K
&& index
< max
&&
1098 !(IS_ALIGNED(iter
->dma
, I915_GTT_PAGE_SIZE_64K
) &&
1099 (IS_ALIGNED(rem
, I915_GTT_PAGE_SIZE_64K
) ||
1100 rem
>= (max
- index
) << PAGE_SHIFT
)))
1103 if (unlikely(!IS_ALIGNED(iter
->dma
, page_size
)))
1106 } while (rem
>= page_size
&& index
< max
);
1108 kunmap_atomic(vaddr
);
1111 * Is it safe to mark the 2M block as 64K? -- Either we have
1112 * filled whole page-table with 64K entries, or filled part of
1113 * it and have reached the end of the sg table and we have
1118 (i915_vm_has_scratch_64K(vma
->vm
) &&
1119 !iter
->sg
&& IS_ALIGNED(vma
->node
.start
+
1121 I915_GTT_PAGE_SIZE_2M
)))) {
1122 vaddr
= kmap_atomic_px(pd
);
1123 vaddr
[idx
.pde
] |= GEN8_PDE_IPS_64K
;
1124 kunmap_atomic(vaddr
);
1125 page_size
= I915_GTT_PAGE_SIZE_64K
;
1128 * We write all 4K page entries, even when using 64K
1129 * pages. In order to verify that the HW isn't cheating
1130 * by using the 4K PTE instead of the 64K PTE, we want
1131 * to remove all the surplus entries. If the HW skipped
1132 * the 64K PTE, it will read/write into the scratch page
1133 * instead - which we detect as missing results during
1136 if (I915_SELFTEST_ONLY(vma
->vm
->scrub_64K
)) {
1139 encode
= pte_encode
| vma
->vm
->scratch_page
.daddr
;
1140 vaddr
= kmap_atomic_px(pd
->page_table
[idx
.pde
]);
1142 for (i
= 1; i
< index
; i
+= 16)
1143 memset64(vaddr
+ i
, encode
, 15);
1145 kunmap_atomic(vaddr
);
1149 vma
->page_sizes
.gtt
|= page_size
;
1153 static void gen8_ppgtt_insert_4lvl(struct i915_address_space
*vm
,
1154 struct i915_vma
*vma
,
1155 enum i915_cache_level cache_level
,
1158 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1159 struct sgt_dma iter
= sgt_dma(vma
);
1160 struct i915_page_directory_pointer
**pdps
= ppgtt
->pml4
.pdps
;
1162 if (vma
->page_sizes
.sg
> I915_GTT_PAGE_SIZE
) {
1163 gen8_ppgtt_insert_huge_entries(vma
, pdps
, &iter
, cache_level
);
1165 struct gen8_insert_pte idx
= gen8_insert_pte(vma
->node
.start
);
1167 while (gen8_ppgtt_insert_pte_entries(ppgtt
, pdps
[idx
.pml4e
++],
1168 &iter
, &idx
, cache_level
))
1169 GEM_BUG_ON(idx
.pml4e
>= GEN8_PML4ES_PER_PML4
);
1171 vma
->page_sizes
.gtt
= I915_GTT_PAGE_SIZE
;
1175 static void gen8_free_page_tables(struct i915_address_space
*vm
,
1176 struct i915_page_directory
*pd
)
1183 for (i
= 0; i
< I915_PDES
; i
++) {
1184 if (pd
->page_table
[i
] != vm
->scratch_pt
)
1185 free_pt(vm
, pd
->page_table
[i
]);
1189 static int gen8_init_scratch(struct i915_address_space
*vm
)
1193 ret
= setup_scratch_page(vm
, __GFP_HIGHMEM
);
1197 vm
->scratch_pt
= alloc_pt(vm
);
1198 if (IS_ERR(vm
->scratch_pt
)) {
1199 ret
= PTR_ERR(vm
->scratch_pt
);
1200 goto free_scratch_page
;
1203 vm
->scratch_pd
= alloc_pd(vm
);
1204 if (IS_ERR(vm
->scratch_pd
)) {
1205 ret
= PTR_ERR(vm
->scratch_pd
);
1210 vm
->scratch_pdp
= alloc_pdp(vm
);
1211 if (IS_ERR(vm
->scratch_pdp
)) {
1212 ret
= PTR_ERR(vm
->scratch_pdp
);
1217 gen8_initialize_pt(vm
, vm
->scratch_pt
);
1218 gen8_initialize_pd(vm
, vm
->scratch_pd
);
1220 gen8_initialize_pdp(vm
, vm
->scratch_pdp
);
1225 free_pd(vm
, vm
->scratch_pd
);
1227 free_pt(vm
, vm
->scratch_pt
);
1229 cleanup_scratch_page(vm
);
1234 static int gen8_ppgtt_notify_vgt(struct i915_hw_ppgtt
*ppgtt
, bool create
)
1236 struct i915_address_space
*vm
= &ppgtt
->vm
;
1237 struct drm_i915_private
*dev_priv
= vm
->i915
;
1238 enum vgt_g2v_type msg
;
1242 const u64 daddr
= px_dma(&ppgtt
->pml4
);
1244 I915_WRITE(vgtif_reg(pdp
[0].lo
), lower_32_bits(daddr
));
1245 I915_WRITE(vgtif_reg(pdp
[0].hi
), upper_32_bits(daddr
));
1247 msg
= (create
? VGT_G2V_PPGTT_L4_PAGE_TABLE_CREATE
:
1248 VGT_G2V_PPGTT_L4_PAGE_TABLE_DESTROY
);
1250 for (i
= 0; i
< GEN8_3LVL_PDPES
; i
++) {
1251 const u64 daddr
= i915_page_dir_dma_addr(ppgtt
, i
);
1253 I915_WRITE(vgtif_reg(pdp
[i
].lo
), lower_32_bits(daddr
));
1254 I915_WRITE(vgtif_reg(pdp
[i
].hi
), upper_32_bits(daddr
));
1257 msg
= (create
? VGT_G2V_PPGTT_L3_PAGE_TABLE_CREATE
:
1258 VGT_G2V_PPGTT_L3_PAGE_TABLE_DESTROY
);
1261 I915_WRITE(vgtif_reg(g2v_notify
), msg
);
1266 static void gen8_free_scratch(struct i915_address_space
*vm
)
1269 free_pdp(vm
, vm
->scratch_pdp
);
1270 free_pd(vm
, vm
->scratch_pd
);
1271 free_pt(vm
, vm
->scratch_pt
);
1272 cleanup_scratch_page(vm
);
1275 static void gen8_ppgtt_cleanup_3lvl(struct i915_address_space
*vm
,
1276 struct i915_page_directory_pointer
*pdp
)
1278 const unsigned int pdpes
= i915_pdpes_per_pdp(vm
);
1281 for (i
= 0; i
< pdpes
; i
++) {
1282 if (pdp
->page_directory
[i
] == vm
->scratch_pd
)
1285 gen8_free_page_tables(vm
, pdp
->page_directory
[i
]);
1286 free_pd(vm
, pdp
->page_directory
[i
]);
1292 static void gen8_ppgtt_cleanup_4lvl(struct i915_hw_ppgtt
*ppgtt
)
1296 for (i
= 0; i
< GEN8_PML4ES_PER_PML4
; i
++) {
1297 if (ppgtt
->pml4
.pdps
[i
] == ppgtt
->vm
.scratch_pdp
)
1300 gen8_ppgtt_cleanup_3lvl(&ppgtt
->vm
, ppgtt
->pml4
.pdps
[i
]);
1303 cleanup_px(&ppgtt
->vm
, &ppgtt
->pml4
);
1306 static void gen8_ppgtt_cleanup(struct i915_address_space
*vm
)
1308 struct drm_i915_private
*dev_priv
= vm
->i915
;
1309 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1311 if (intel_vgpu_active(dev_priv
))
1312 gen8_ppgtt_notify_vgt(ppgtt
, false);
1315 gen8_ppgtt_cleanup_4lvl(ppgtt
);
1317 gen8_ppgtt_cleanup_3lvl(&ppgtt
->vm
, &ppgtt
->pdp
);
1319 gen8_free_scratch(vm
);
1322 static int gen8_ppgtt_alloc_pd(struct i915_address_space
*vm
,
1323 struct i915_page_directory
*pd
,
1324 u64 start
, u64 length
)
1326 struct i915_page_table
*pt
;
1330 gen8_for_each_pde(pt
, pd
, start
, length
, pde
) {
1331 int count
= gen8_pte_count(start
, length
);
1333 if (pt
== vm
->scratch_pt
) {
1342 if (count
< GEN8_PTES
|| intel_vgpu_active(vm
->i915
))
1343 gen8_initialize_pt(vm
, pt
);
1345 gen8_ppgtt_set_pde(vm
, pd
, pt
, pde
);
1346 GEM_BUG_ON(pd
->used_pdes
> I915_PDES
);
1349 pt
->used_ptes
+= count
;
1354 gen8_ppgtt_clear_pd(vm
, pd
, from
, start
- from
);
1358 static int gen8_ppgtt_alloc_pdp(struct i915_address_space
*vm
,
1359 struct i915_page_directory_pointer
*pdp
,
1360 u64 start
, u64 length
)
1362 struct i915_page_directory
*pd
;
1367 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1368 if (pd
== vm
->scratch_pd
) {
1377 gen8_initialize_pd(vm
, pd
);
1378 gen8_ppgtt_set_pdpe(vm
, pdp
, pd
, pdpe
);
1379 GEM_BUG_ON(pdp
->used_pdpes
> i915_pdpes_per_pdp(vm
));
1381 mark_tlbs_dirty(i915_vm_to_ppgtt(vm
));
1384 ret
= gen8_ppgtt_alloc_pd(vm
, pd
, start
, length
);
1392 if (!pd
->used_pdes
) {
1393 gen8_ppgtt_set_pdpe(vm
, pdp
, vm
->scratch_pd
, pdpe
);
1394 GEM_BUG_ON(!pdp
->used_pdpes
);
1399 gen8_ppgtt_clear_pdp(vm
, pdp
, from
, start
- from
);
1403 static int gen8_ppgtt_alloc_3lvl(struct i915_address_space
*vm
,
1404 u64 start
, u64 length
)
1406 return gen8_ppgtt_alloc_pdp(vm
,
1407 &i915_vm_to_ppgtt(vm
)->pdp
, start
, length
);
1410 static int gen8_ppgtt_alloc_4lvl(struct i915_address_space
*vm
,
1411 u64 start
, u64 length
)
1413 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1414 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1415 struct i915_page_directory_pointer
*pdp
;
1420 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1421 if (pml4
->pdps
[pml4e
] == vm
->scratch_pdp
) {
1422 pdp
= alloc_pdp(vm
);
1426 gen8_initialize_pdp(vm
, pdp
);
1427 gen8_ppgtt_set_pml4e(pml4
, pdp
, pml4e
);
1430 ret
= gen8_ppgtt_alloc_pdp(vm
, pdp
, start
, length
);
1438 if (!pdp
->used_pdpes
) {
1439 gen8_ppgtt_set_pml4e(pml4
, vm
->scratch_pdp
, pml4e
);
1443 gen8_ppgtt_clear_4lvl(vm
, from
, start
- from
);
1447 static void gen8_dump_pdp(struct i915_hw_ppgtt
*ppgtt
,
1448 struct i915_page_directory_pointer
*pdp
,
1449 u64 start
, u64 length
,
1450 gen8_pte_t scratch_pte
,
1453 struct i915_address_space
*vm
= &ppgtt
->vm
;
1454 struct i915_page_directory
*pd
;
1457 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1458 struct i915_page_table
*pt
;
1459 u64 pd_len
= length
;
1460 u64 pd_start
= start
;
1463 if (pdp
->page_directory
[pdpe
] == ppgtt
->vm
.scratch_pd
)
1466 seq_printf(m
, "\tPDPE #%d\n", pdpe
);
1467 gen8_for_each_pde(pt
, pd
, pd_start
, pd_len
, pde
) {
1469 gen8_pte_t
*pt_vaddr
;
1471 if (pd
->page_table
[pde
] == ppgtt
->vm
.scratch_pt
)
1474 pt_vaddr
= kmap_atomic_px(pt
);
1475 for (pte
= 0; pte
< GEN8_PTES
; pte
+= 4) {
1476 u64 va
= (pdpe
<< GEN8_PDPE_SHIFT
|
1477 pde
<< GEN8_PDE_SHIFT
|
1478 pte
<< GEN8_PTE_SHIFT
);
1482 for (i
= 0; i
< 4; i
++)
1483 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1488 seq_printf(m
, "\t\t0x%llx [%03d,%03d,%04d]: =", va
, pdpe
, pde
, pte
);
1489 for (i
= 0; i
< 4; i
++) {
1490 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1491 seq_printf(m
, " %llx", pt_vaddr
[pte
+ i
]);
1493 seq_puts(m
, " SCRATCH ");
1497 kunmap_atomic(pt_vaddr
);
1502 static void gen8_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1504 struct i915_address_space
*vm
= &ppgtt
->vm
;
1505 const gen8_pte_t scratch_pte
=
1506 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
);
1507 u64 start
= 0, length
= ppgtt
->vm
.total
;
1511 struct i915_pml4
*pml4
= &ppgtt
->pml4
;
1512 struct i915_page_directory_pointer
*pdp
;
1514 gen8_for_each_pml4e(pdp
, pml4
, start
, length
, pml4e
) {
1515 if (pml4
->pdps
[pml4e
] == ppgtt
->vm
.scratch_pdp
)
1518 seq_printf(m
, " PML4E #%llu\n", pml4e
);
1519 gen8_dump_pdp(ppgtt
, pdp
, start
, length
, scratch_pte
, m
);
1522 gen8_dump_pdp(ppgtt
, &ppgtt
->pdp
, start
, length
, scratch_pte
, m
);
1526 static int gen8_preallocate_top_level_pdp(struct i915_hw_ppgtt
*ppgtt
)
1528 struct i915_address_space
*vm
= &ppgtt
->vm
;
1529 struct i915_page_directory_pointer
*pdp
= &ppgtt
->pdp
;
1530 struct i915_page_directory
*pd
;
1531 u64 start
= 0, length
= ppgtt
->vm
.total
;
1535 gen8_for_each_pdpe(pd
, pdp
, start
, length
, pdpe
) {
1540 gen8_initialize_pd(vm
, pd
);
1541 gen8_ppgtt_set_pdpe(vm
, pdp
, pd
, pdpe
);
1545 pdp
->used_pdpes
++; /* never remove */
1550 gen8_for_each_pdpe(pd
, pdp
, from
, start
, pdpe
) {
1551 gen8_ppgtt_set_pdpe(vm
, pdp
, vm
->scratch_pd
, pdpe
);
1554 pdp
->used_pdpes
= 0;
1559 * GEN8 legacy ppgtt programming is accomplished through a max 4 PDP registers
1560 * with a net effect resembling a 2-level page table in normal x86 terms. Each
1561 * PDP represents 1GB of memory 4 * 512 * 512 * 4096 = 4GB legacy 32b address
1565 static int gen8_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
1567 struct i915_address_space
*vm
= &ppgtt
->vm
;
1568 struct drm_i915_private
*dev_priv
= vm
->i915
;
1571 ppgtt
->vm
.total
= USES_FULL_48BIT_PPGTT(dev_priv
) ?
1575 /* There are only few exceptions for gen >=6. chv and bxt.
1576 * And we are not sure about the latter so play safe for now.
1578 if (IS_CHERRYVIEW(dev_priv
) || IS_BROXTON(dev_priv
))
1579 ppgtt
->vm
.pt_kmap_wc
= true;
1581 ret
= gen8_init_scratch(&ppgtt
->vm
);
1583 ppgtt
->vm
.total
= 0;
1588 ret
= setup_px(&ppgtt
->vm
, &ppgtt
->pml4
);
1592 gen8_initialize_pml4(&ppgtt
->vm
, &ppgtt
->pml4
);
1594 ppgtt
->vm
.allocate_va_range
= gen8_ppgtt_alloc_4lvl
;
1595 ppgtt
->vm
.insert_entries
= gen8_ppgtt_insert_4lvl
;
1596 ppgtt
->vm
.clear_range
= gen8_ppgtt_clear_4lvl
;
1598 ret
= __pdp_init(&ppgtt
->vm
, &ppgtt
->pdp
);
1602 if (intel_vgpu_active(dev_priv
)) {
1603 ret
= gen8_preallocate_top_level_pdp(ppgtt
);
1605 __pdp_fini(&ppgtt
->pdp
);
1610 ppgtt
->vm
.allocate_va_range
= gen8_ppgtt_alloc_3lvl
;
1611 ppgtt
->vm
.insert_entries
= gen8_ppgtt_insert_3lvl
;
1612 ppgtt
->vm
.clear_range
= gen8_ppgtt_clear_3lvl
;
1615 if (intel_vgpu_active(dev_priv
))
1616 gen8_ppgtt_notify_vgt(ppgtt
, true);
1618 ppgtt
->vm
.cleanup
= gen8_ppgtt_cleanup
;
1619 ppgtt
->vm
.bind_vma
= gen8_ppgtt_bind_vma
;
1620 ppgtt
->vm
.unbind_vma
= ppgtt_unbind_vma
;
1621 ppgtt
->vm
.set_pages
= ppgtt_set_pages
;
1622 ppgtt
->vm
.clear_pages
= clear_pages
;
1623 ppgtt
->debug_dump
= gen8_dump_ppgtt
;
1628 gen8_free_scratch(&ppgtt
->vm
);
1632 static void gen6_dump_ppgtt(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
)
1634 struct i915_address_space
*vm
= &ppgtt
->vm
;
1635 struct i915_page_table
*unused
;
1636 gen6_pte_t scratch_pte
;
1637 u32 pd_entry
, pte
, pde
;
1638 u32 start
= 0, length
= ppgtt
->vm
.total
;
1640 scratch_pte
= vm
->pte_encode(vm
->scratch_page
.daddr
,
1643 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
) {
1645 gen6_pte_t
*pt_vaddr
;
1646 const dma_addr_t pt_addr
= px_dma(ppgtt
->pd
.page_table
[pde
]);
1647 pd_entry
= readl(ppgtt
->pd_addr
+ pde
);
1648 expected
= (GEN6_PDE_ADDR_ENCODE(pt_addr
) | GEN6_PDE_VALID
);
1650 if (pd_entry
!= expected
)
1651 seq_printf(m
, "\tPDE #%d mismatch: Actual PDE: %x Expected PDE: %x\n",
1655 seq_printf(m
, "\tPDE: %x\n", pd_entry
);
1657 pt_vaddr
= kmap_atomic_px(ppgtt
->pd
.page_table
[pde
]);
1659 for (pte
= 0; pte
< GEN6_PTES
; pte
+=4) {
1661 (pde
* PAGE_SIZE
* GEN6_PTES
) +
1665 for (i
= 0; i
< 4; i
++)
1666 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1671 seq_printf(m
, "\t\t0x%lx [%03d,%04d]: =", va
, pde
, pte
);
1672 for (i
= 0; i
< 4; i
++) {
1673 if (pt_vaddr
[pte
+ i
] != scratch_pte
)
1674 seq_printf(m
, " %08x", pt_vaddr
[pte
+ i
]);
1676 seq_puts(m
, " SCRATCH ");
1680 kunmap_atomic(pt_vaddr
);
1684 /* Write pde (index) from the page directory @pd to the page table @pt */
1685 static inline void gen6_write_pde(const struct i915_hw_ppgtt
*ppgtt
,
1686 const unsigned int pde
,
1687 const struct i915_page_table
*pt
)
1689 /* Caller needs to make sure the write completes if necessary */
1690 writel_relaxed(GEN6_PDE_ADDR_ENCODE(px_dma(pt
)) | GEN6_PDE_VALID
,
1691 ppgtt
->pd_addr
+ pde
);
1694 /* Write all the page tables found in the ppgtt structure to incrementing page
1696 static void gen6_write_page_range(struct i915_hw_ppgtt
*ppgtt
,
1697 u32 start
, u32 length
)
1699 struct i915_page_table
*pt
;
1702 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
)
1703 gen6_write_pde(ppgtt
, pde
, pt
);
1705 mark_tlbs_dirty(ppgtt
);
1709 static inline u32
get_pd_offset(struct i915_hw_ppgtt
*ppgtt
)
1711 GEM_BUG_ON(ppgtt
->pd
.base
.ggtt_offset
& 0x3f);
1712 return ppgtt
->pd
.base
.ggtt_offset
<< 10;
1715 static int hsw_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1716 struct i915_request
*rq
)
1718 struct intel_engine_cs
*engine
= rq
->engine
;
1721 /* NB: TLBs must be flushed and invalidated before a switch */
1722 cs
= intel_ring_begin(rq
, 6);
1726 *cs
++ = MI_LOAD_REGISTER_IMM(2);
1727 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine
));
1728 *cs
++ = PP_DIR_DCLV_2G
;
1729 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine
));
1730 *cs
++ = get_pd_offset(ppgtt
);
1732 intel_ring_advance(rq
, cs
);
1737 static int gen7_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1738 struct i915_request
*rq
)
1740 struct intel_engine_cs
*engine
= rq
->engine
;
1743 /* NB: TLBs must be flushed and invalidated before a switch */
1744 cs
= intel_ring_begin(rq
, 6);
1748 *cs
++ = MI_LOAD_REGISTER_IMM(2);
1749 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine
));
1750 *cs
++ = PP_DIR_DCLV_2G
;
1751 *cs
++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine
));
1752 *cs
++ = get_pd_offset(ppgtt
);
1754 intel_ring_advance(rq
, cs
);
1759 static int gen6_mm_switch(struct i915_hw_ppgtt
*ppgtt
,
1760 struct i915_request
*rq
)
1762 struct intel_engine_cs
*engine
= rq
->engine
;
1763 struct drm_i915_private
*dev_priv
= rq
->i915
;
1765 I915_WRITE(RING_PP_DIR_DCLV(engine
), PP_DIR_DCLV_2G
);
1766 I915_WRITE(RING_PP_DIR_BASE(engine
), get_pd_offset(ppgtt
));
1770 static void gen8_ppgtt_enable(struct drm_i915_private
*dev_priv
)
1772 struct intel_engine_cs
*engine
;
1773 enum intel_engine_id id
;
1775 for_each_engine(engine
, dev_priv
, id
) {
1776 u32 four_level
= USES_FULL_48BIT_PPGTT(dev_priv
) ?
1777 GEN8_GFX_PPGTT_48B
: 0;
1778 I915_WRITE(RING_MODE_GEN7(engine
),
1779 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
| four_level
));
1783 static void gen7_ppgtt_enable(struct drm_i915_private
*dev_priv
)
1785 struct intel_engine_cs
*engine
;
1786 u32 ecochk
, ecobits
;
1787 enum intel_engine_id id
;
1789 ecobits
= I915_READ(GAC_ECO_BITS
);
1790 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_PPGTT_CACHE64B
);
1792 ecochk
= I915_READ(GAM_ECOCHK
);
1793 if (IS_HASWELL(dev_priv
)) {
1794 ecochk
|= ECOCHK_PPGTT_WB_HSW
;
1796 ecochk
|= ECOCHK_PPGTT_LLC_IVB
;
1797 ecochk
&= ~ECOCHK_PPGTT_GFDT_IVB
;
1799 I915_WRITE(GAM_ECOCHK
, ecochk
);
1801 for_each_engine(engine
, dev_priv
, id
) {
1802 /* GFX_MODE is per-ring on gen7+ */
1803 I915_WRITE(RING_MODE_GEN7(engine
),
1804 _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1808 static void gen6_ppgtt_enable(struct drm_i915_private
*dev_priv
)
1810 u32 ecochk
, gab_ctl
, ecobits
;
1812 ecobits
= I915_READ(GAC_ECO_BITS
);
1813 I915_WRITE(GAC_ECO_BITS
, ecobits
| ECOBITS_SNB_BIT
|
1814 ECOBITS_PPGTT_CACHE64B
);
1816 gab_ctl
= I915_READ(GAB_CTL
);
1817 I915_WRITE(GAB_CTL
, gab_ctl
| GAB_CTL_CONT_AFTER_PAGEFAULT
);
1819 ecochk
= I915_READ(GAM_ECOCHK
);
1820 I915_WRITE(GAM_ECOCHK
, ecochk
| ECOCHK_SNB_BIT
| ECOCHK_PPGTT_CACHE64B
);
1822 I915_WRITE(GFX_MODE
, _MASKED_BIT_ENABLE(GFX_PPGTT_ENABLE
));
1825 /* PPGTT support for Sandybdrige/Gen6 and later */
1826 static void gen6_ppgtt_clear_range(struct i915_address_space
*vm
,
1827 u64 start
, u64 length
)
1829 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1830 unsigned int first_entry
= start
>> PAGE_SHIFT
;
1831 unsigned int pde
= first_entry
/ GEN6_PTES
;
1832 unsigned int pte
= first_entry
% GEN6_PTES
;
1833 unsigned int num_entries
= length
>> PAGE_SHIFT
;
1834 gen6_pte_t scratch_pte
=
1835 vm
->pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
, 0);
1837 while (num_entries
) {
1838 struct i915_page_table
*pt
= ppgtt
->pd
.page_table
[pde
++];
1839 unsigned int end
= min(pte
+ num_entries
, GEN6_PTES
);
1842 num_entries
-= end
- pte
;
1844 /* Note that the hw doesn't support removing PDE on the fly
1845 * (they are cached inside the context with no means to
1846 * invalidate the cache), so we can only reset the PTE
1847 * entries back to scratch.
1850 vaddr
= kmap_atomic_px(pt
);
1852 vaddr
[pte
++] = scratch_pte
;
1853 } while (pte
< end
);
1854 kunmap_atomic(vaddr
);
1860 static void gen6_ppgtt_insert_entries(struct i915_address_space
*vm
,
1861 struct i915_vma
*vma
,
1862 enum i915_cache_level cache_level
,
1865 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1866 unsigned first_entry
= vma
->node
.start
>> PAGE_SHIFT
;
1867 unsigned act_pt
= first_entry
/ GEN6_PTES
;
1868 unsigned act_pte
= first_entry
% GEN6_PTES
;
1869 const u32 pte_encode
= vm
->pte_encode(0, cache_level
, flags
);
1870 struct sgt_dma iter
= sgt_dma(vma
);
1873 vaddr
= kmap_atomic_px(ppgtt
->pd
.page_table
[act_pt
]);
1875 vaddr
[act_pte
] = pte_encode
| GEN6_PTE_ADDR_ENCODE(iter
.dma
);
1877 iter
.dma
+= PAGE_SIZE
;
1878 if (iter
.dma
== iter
.max
) {
1879 iter
.sg
= __sg_next(iter
.sg
);
1883 iter
.dma
= sg_dma_address(iter
.sg
);
1884 iter
.max
= iter
.dma
+ iter
.sg
->length
;
1887 if (++act_pte
== GEN6_PTES
) {
1888 kunmap_atomic(vaddr
);
1889 vaddr
= kmap_atomic_px(ppgtt
->pd
.page_table
[++act_pt
]);
1893 kunmap_atomic(vaddr
);
1895 vma
->page_sizes
.gtt
= I915_GTT_PAGE_SIZE
;
1898 static int gen6_alloc_va_range(struct i915_address_space
*vm
,
1899 u64 start
, u64 length
)
1901 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1902 struct i915_page_table
*pt
;
1907 gen6_for_each_pde(pt
, &ppgtt
->pd
, start
, length
, pde
) {
1908 if (pt
== vm
->scratch_pt
) {
1913 gen6_initialize_pt(vm
, pt
);
1914 ppgtt
->pd
.page_table
[pde
] = pt
;
1915 gen6_write_pde(ppgtt
, pde
, pt
);
1921 mark_tlbs_dirty(ppgtt
);
1928 gen6_ppgtt_clear_range(vm
, from
, start
);
1932 static int gen6_init_scratch(struct i915_address_space
*vm
)
1936 ret
= setup_scratch_page(vm
, __GFP_HIGHMEM
);
1940 vm
->scratch_pt
= alloc_pt(vm
);
1941 if (IS_ERR(vm
->scratch_pt
)) {
1942 cleanup_scratch_page(vm
);
1943 return PTR_ERR(vm
->scratch_pt
);
1946 gen6_initialize_pt(vm
, vm
->scratch_pt
);
1951 static void gen6_free_scratch(struct i915_address_space
*vm
)
1953 free_pt(vm
, vm
->scratch_pt
);
1954 cleanup_scratch_page(vm
);
1957 static void gen6_ppgtt_cleanup(struct i915_address_space
*vm
)
1959 struct i915_hw_ppgtt
*ppgtt
= i915_vm_to_ppgtt(vm
);
1960 struct i915_page_directory
*pd
= &ppgtt
->pd
;
1961 struct i915_page_table
*pt
;
1964 drm_mm_remove_node(&ppgtt
->node
);
1966 gen6_for_all_pdes(pt
, pd
, pde
)
1967 if (pt
!= vm
->scratch_pt
)
1970 gen6_free_scratch(vm
);
1973 static int gen6_ppgtt_allocate_page_directories(struct i915_hw_ppgtt
*ppgtt
)
1975 struct i915_address_space
*vm
= &ppgtt
->vm
;
1976 struct drm_i915_private
*dev_priv
= ppgtt
->vm
.i915
;
1977 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
1980 /* PPGTT PDEs reside in the GGTT and consists of 512 entries. The
1981 * allocator works in address space sizes, so it's multiplied by page
1982 * size. We allocate at the top of the GTT to avoid fragmentation.
1984 BUG_ON(!drm_mm_initialized(&ggtt
->vm
.mm
));
1986 ret
= gen6_init_scratch(vm
);
1990 ret
= i915_gem_gtt_insert(&ggtt
->vm
, &ppgtt
->node
,
1991 GEN6_PD_SIZE
, GEN6_PD_ALIGN
,
1992 I915_COLOR_UNEVICTABLE
,
1998 if (ppgtt
->node
.start
< ggtt
->mappable_end
)
1999 DRM_DEBUG("Forced to use aperture for PDEs\n");
2001 ppgtt
->pd
.base
.ggtt_offset
=
2002 ppgtt
->node
.start
/ PAGE_SIZE
* sizeof(gen6_pte_t
);
2004 ppgtt
->pd_addr
= (gen6_pte_t __iomem
*)ggtt
->gsm
+
2005 ppgtt
->pd
.base
.ggtt_offset
/ sizeof(gen6_pte_t
);
2010 gen6_free_scratch(vm
);
2014 static int gen6_ppgtt_alloc(struct i915_hw_ppgtt
*ppgtt
)
2016 return gen6_ppgtt_allocate_page_directories(ppgtt
);
2019 static void gen6_scratch_va_range(struct i915_hw_ppgtt
*ppgtt
,
2020 u64 start
, u64 length
)
2022 struct i915_page_table
*unused
;
2025 gen6_for_each_pde(unused
, &ppgtt
->pd
, start
, length
, pde
)
2026 ppgtt
->pd
.page_table
[pde
] = ppgtt
->vm
.scratch_pt
;
2029 static int gen6_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
)
2031 struct drm_i915_private
*dev_priv
= ppgtt
->vm
.i915
;
2032 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2035 ppgtt
->vm
.pte_encode
= ggtt
->vm
.pte_encode
;
2036 if (intel_vgpu_active(dev_priv
) || IS_GEN6(dev_priv
))
2037 ppgtt
->switch_mm
= gen6_mm_switch
;
2038 else if (IS_HASWELL(dev_priv
))
2039 ppgtt
->switch_mm
= hsw_mm_switch
;
2040 else if (IS_GEN7(dev_priv
))
2041 ppgtt
->switch_mm
= gen7_mm_switch
;
2045 ret
= gen6_ppgtt_alloc(ppgtt
);
2049 ppgtt
->vm
.total
= I915_PDES
* GEN6_PTES
* PAGE_SIZE
;
2051 gen6_scratch_va_range(ppgtt
, 0, ppgtt
->vm
.total
);
2052 gen6_write_page_range(ppgtt
, 0, ppgtt
->vm
.total
);
2054 ret
= gen6_alloc_va_range(&ppgtt
->vm
, 0, ppgtt
->vm
.total
);
2056 gen6_ppgtt_cleanup(&ppgtt
->vm
);
2060 ppgtt
->vm
.clear_range
= gen6_ppgtt_clear_range
;
2061 ppgtt
->vm
.insert_entries
= gen6_ppgtt_insert_entries
;
2062 ppgtt
->vm
.bind_vma
= gen6_ppgtt_bind_vma
;
2063 ppgtt
->vm
.unbind_vma
= ppgtt_unbind_vma
;
2064 ppgtt
->vm
.set_pages
= ppgtt_set_pages
;
2065 ppgtt
->vm
.clear_pages
= clear_pages
;
2066 ppgtt
->vm
.cleanup
= gen6_ppgtt_cleanup
;
2067 ppgtt
->debug_dump
= gen6_dump_ppgtt
;
2069 DRM_DEBUG_DRIVER("Allocated pde space (%lldM) at GTT entry: %llx\n",
2070 ppgtt
->node
.size
>> 20,
2071 ppgtt
->node
.start
/ PAGE_SIZE
);
2073 DRM_DEBUG_DRIVER("Adding PPGTT at offset %x\n",
2074 ppgtt
->pd
.base
.ggtt_offset
<< 10);
2079 static int __hw_ppgtt_init(struct i915_hw_ppgtt
*ppgtt
,
2080 struct drm_i915_private
*dev_priv
)
2082 ppgtt
->vm
.i915
= dev_priv
;
2083 ppgtt
->vm
.dma
= &dev_priv
->drm
.pdev
->dev
;
2085 if (INTEL_GEN(dev_priv
) < 8)
2086 return gen6_ppgtt_init(ppgtt
);
2088 return gen8_ppgtt_init(ppgtt
);
2091 static void i915_address_space_init(struct i915_address_space
*vm
,
2092 struct drm_i915_private
*dev_priv
,
2095 drm_mm_init(&vm
->mm
, 0, vm
->total
);
2096 vm
->mm
.head_node
.color
= I915_COLOR_UNEVICTABLE
;
2098 INIT_LIST_HEAD(&vm
->active_list
);
2099 INIT_LIST_HEAD(&vm
->inactive_list
);
2100 INIT_LIST_HEAD(&vm
->unbound_list
);
2102 list_add_tail(&vm
->global_link
, &dev_priv
->vm_list
);
2103 pagevec_init(&vm
->free_pages
);
2106 static void i915_address_space_fini(struct i915_address_space
*vm
)
2108 if (pagevec_count(&vm
->free_pages
))
2109 vm_free_pages_release(vm
, true);
2111 drm_mm_takedown(&vm
->mm
);
2112 list_del(&vm
->global_link
);
2115 static void gtt_write_workarounds(struct drm_i915_private
*dev_priv
)
2117 /* This function is for gtt related workarounds. This function is
2118 * called on driver load and after a GPU reset, so you can place
2119 * workarounds here even if they get overwritten by GPU reset.
2121 /* WaIncreaseDefaultTLBEntries:chv,bdw,skl,bxt,kbl,glk,cfl,cnl,icl */
2122 if (IS_BROADWELL(dev_priv
))
2123 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW
);
2124 else if (IS_CHERRYVIEW(dev_priv
))
2125 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV
);
2126 else if (IS_GEN9_LP(dev_priv
))
2127 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT
);
2128 else if (INTEL_GEN(dev_priv
) >= 9)
2129 I915_WRITE(GEN8_L3_LRA_1_GPGPU
, GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL
);
2132 * To support 64K PTEs we need to first enable the use of the
2133 * Intermediate-Page-Size(IPS) bit of the PDE field via some magical
2134 * mmio, otherwise the page-walker will simply ignore the IPS bit. This
2135 * shouldn't be needed after GEN10.
2137 * 64K pages were first introduced from BDW+, although technically they
2138 * only *work* from gen9+. For pre-BDW we instead have the option for
2139 * 32K pages, but we don't currently have any support for it in our
2142 if (HAS_PAGE_SIZES(dev_priv
, I915_GTT_PAGE_SIZE_64K
) &&
2143 INTEL_GEN(dev_priv
) <= 10)
2144 I915_WRITE(GEN8_GAMW_ECO_DEV_RW_IA
,
2145 I915_READ(GEN8_GAMW_ECO_DEV_RW_IA
) |
2146 GAMW_ECO_ENABLE_64K_IPS_FIELD
);
2149 int i915_ppgtt_init_hw(struct drm_i915_private
*dev_priv
)
2151 gtt_write_workarounds(dev_priv
);
2153 /* In the case of execlists, PPGTT is enabled by the context descriptor
2154 * and the PDPs are contained within the context itself. We don't
2155 * need to do anything here. */
2156 if (HAS_LOGICAL_RING_CONTEXTS(dev_priv
))
2159 if (!USES_PPGTT(dev_priv
))
2162 if (IS_GEN6(dev_priv
))
2163 gen6_ppgtt_enable(dev_priv
);
2164 else if (IS_GEN7(dev_priv
))
2165 gen7_ppgtt_enable(dev_priv
);
2166 else if (INTEL_GEN(dev_priv
) >= 8)
2167 gen8_ppgtt_enable(dev_priv
);
2169 MISSING_CASE(INTEL_GEN(dev_priv
));
2174 struct i915_hw_ppgtt
*
2175 i915_ppgtt_create(struct drm_i915_private
*dev_priv
,
2176 struct drm_i915_file_private
*fpriv
,
2179 struct i915_hw_ppgtt
*ppgtt
;
2182 ppgtt
= kzalloc(sizeof(*ppgtt
), GFP_KERNEL
);
2184 return ERR_PTR(-ENOMEM
);
2186 ret
= __hw_ppgtt_init(ppgtt
, dev_priv
);
2189 return ERR_PTR(ret
);
2192 kref_init(&ppgtt
->ref
);
2193 i915_address_space_init(&ppgtt
->vm
, dev_priv
, name
);
2194 ppgtt
->vm
.file
= fpriv
;
2196 trace_i915_ppgtt_create(&ppgtt
->vm
);
2201 void i915_ppgtt_close(struct i915_address_space
*vm
)
2203 GEM_BUG_ON(vm
->closed
);
2207 static void ppgtt_destroy_vma(struct i915_address_space
*vm
)
2209 struct list_head
*phases
[] = {
2217 for (phase
= phases
; *phase
; phase
++) {
2218 struct i915_vma
*vma
, *vn
;
2220 list_for_each_entry_safe(vma
, vn
, *phase
, vm_link
)
2221 i915_vma_destroy(vma
);
2225 void i915_ppgtt_release(struct kref
*kref
)
2227 struct i915_hw_ppgtt
*ppgtt
=
2228 container_of(kref
, struct i915_hw_ppgtt
, ref
);
2230 trace_i915_ppgtt_release(&ppgtt
->vm
);
2232 ppgtt_destroy_vma(&ppgtt
->vm
);
2234 GEM_BUG_ON(!list_empty(&ppgtt
->vm
.active_list
));
2235 GEM_BUG_ON(!list_empty(&ppgtt
->vm
.inactive_list
));
2236 GEM_BUG_ON(!list_empty(&ppgtt
->vm
.unbound_list
));
2238 ppgtt
->vm
.cleanup(&ppgtt
->vm
);
2239 i915_address_space_fini(&ppgtt
->vm
);
2243 /* Certain Gen5 chipsets require require idling the GPU before
2244 * unmapping anything from the GTT when VT-d is enabled.
2246 static bool needs_idle_maps(struct drm_i915_private
*dev_priv
)
2248 /* Query intel_iommu to see if we need the workaround. Presumably that
2251 return IS_GEN5(dev_priv
) && IS_MOBILE(dev_priv
) && intel_vtd_active();
2254 static void gen6_check_and_clear_faults(struct drm_i915_private
*dev_priv
)
2256 struct intel_engine_cs
*engine
;
2257 enum intel_engine_id id
;
2260 for_each_engine(engine
, dev_priv
, id
) {
2261 fault
= I915_READ(RING_FAULT_REG(engine
));
2262 if (fault
& RING_FAULT_VALID
) {
2263 DRM_DEBUG_DRIVER("Unexpected fault\n"
2265 "\tAddress space: %s\n"
2269 fault
& RING_FAULT_GTTSEL_MASK
? "GGTT" : "PPGTT",
2270 RING_FAULT_SRCID(fault
),
2271 RING_FAULT_FAULT_TYPE(fault
));
2272 I915_WRITE(RING_FAULT_REG(engine
),
2273 fault
& ~RING_FAULT_VALID
);
2277 POSTING_READ(RING_FAULT_REG(dev_priv
->engine
[RCS
]));
2280 static void gen8_check_and_clear_faults(struct drm_i915_private
*dev_priv
)
2282 u32 fault
= I915_READ(GEN8_RING_FAULT_REG
);
2284 if (fault
& RING_FAULT_VALID
) {
2285 u32 fault_data0
, fault_data1
;
2288 fault_data0
= I915_READ(GEN8_FAULT_TLB_DATA0
);
2289 fault_data1
= I915_READ(GEN8_FAULT_TLB_DATA1
);
2290 fault_addr
= ((u64
)(fault_data1
& FAULT_VA_HIGH_BITS
) << 44) |
2291 ((u64
)fault_data0
<< 12);
2293 DRM_DEBUG_DRIVER("Unexpected fault\n"
2294 "\tAddr: 0x%08x_%08x\n"
2295 "\tAddress space: %s\n"
2299 upper_32_bits(fault_addr
),
2300 lower_32_bits(fault_addr
),
2301 fault_data1
& FAULT_GTT_SEL
? "GGTT" : "PPGTT",
2302 GEN8_RING_FAULT_ENGINE_ID(fault
),
2303 RING_FAULT_SRCID(fault
),
2304 RING_FAULT_FAULT_TYPE(fault
));
2305 I915_WRITE(GEN8_RING_FAULT_REG
,
2306 fault
& ~RING_FAULT_VALID
);
2309 POSTING_READ(GEN8_RING_FAULT_REG
);
2312 void i915_check_and_clear_faults(struct drm_i915_private
*dev_priv
)
2314 /* From GEN8 onwards we only have one 'All Engine Fault Register' */
2315 if (INTEL_GEN(dev_priv
) >= 8)
2316 gen8_check_and_clear_faults(dev_priv
);
2317 else if (INTEL_GEN(dev_priv
) >= 6)
2318 gen6_check_and_clear_faults(dev_priv
);
2323 void i915_gem_suspend_gtt_mappings(struct drm_i915_private
*dev_priv
)
2325 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2327 /* Don't bother messing with faults pre GEN6 as we have little
2328 * documentation supporting that it's a good idea.
2330 if (INTEL_GEN(dev_priv
) < 6)
2333 i915_check_and_clear_faults(dev_priv
);
2335 ggtt
->vm
.clear_range(&ggtt
->vm
, 0, ggtt
->vm
.total
);
2337 i915_ggtt_invalidate(dev_priv
);
2340 int i915_gem_gtt_prepare_pages(struct drm_i915_gem_object
*obj
,
2341 struct sg_table
*pages
)
2344 if (dma_map_sg_attrs(&obj
->base
.dev
->pdev
->dev
,
2345 pages
->sgl
, pages
->nents
,
2346 PCI_DMA_BIDIRECTIONAL
,
2350 /* If the DMA remap fails, one cause can be that we have
2351 * too many objects pinned in a small remapping table,
2352 * such as swiotlb. Incrementally purge all other objects and
2353 * try again - if there are no more pages to remove from
2354 * the DMA remapper, i915_gem_shrink will return 0.
2356 GEM_BUG_ON(obj
->mm
.pages
== pages
);
2357 } while (i915_gem_shrink(to_i915(obj
->base
.dev
),
2358 obj
->base
.size
>> PAGE_SHIFT
, NULL
,
2360 I915_SHRINK_UNBOUND
|
2361 I915_SHRINK_ACTIVE
));
2366 static void gen8_set_pte(void __iomem
*addr
, gen8_pte_t pte
)
2371 static void gen8_ggtt_insert_page(struct i915_address_space
*vm
,
2374 enum i915_cache_level level
,
2377 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2378 gen8_pte_t __iomem
*pte
=
2379 (gen8_pte_t __iomem
*)ggtt
->gsm
+ (offset
>> PAGE_SHIFT
);
2381 gen8_set_pte(pte
, gen8_pte_encode(addr
, level
));
2383 ggtt
->invalidate(vm
->i915
);
2386 static void gen8_ggtt_insert_entries(struct i915_address_space
*vm
,
2387 struct i915_vma
*vma
,
2388 enum i915_cache_level level
,
2391 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2392 struct sgt_iter sgt_iter
;
2393 gen8_pte_t __iomem
*gtt_entries
;
2394 const gen8_pte_t pte_encode
= gen8_pte_encode(0, level
);
2397 gtt_entries
= (gen8_pte_t __iomem
*)ggtt
->gsm
;
2398 gtt_entries
+= vma
->node
.start
>> PAGE_SHIFT
;
2399 for_each_sgt_dma(addr
, sgt_iter
, vma
->pages
)
2400 gen8_set_pte(gtt_entries
++, pte_encode
| addr
);
2403 * We want to flush the TLBs only after we're certain all the PTE
2404 * updates have finished.
2406 ggtt
->invalidate(vm
->i915
);
2409 static void gen6_ggtt_insert_page(struct i915_address_space
*vm
,
2412 enum i915_cache_level level
,
2415 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2416 gen6_pte_t __iomem
*pte
=
2417 (gen6_pte_t __iomem
*)ggtt
->gsm
+ (offset
>> PAGE_SHIFT
);
2419 iowrite32(vm
->pte_encode(addr
, level
, flags
), pte
);
2421 ggtt
->invalidate(vm
->i915
);
2425 * Binds an object into the global gtt with the specified cache level. The object
2426 * will be accessible to the GPU via commands whose operands reference offsets
2427 * within the global GTT as well as accessible by the GPU through the GMADR
2428 * mapped BAR (dev_priv->mm.gtt->gtt).
2430 static void gen6_ggtt_insert_entries(struct i915_address_space
*vm
,
2431 struct i915_vma
*vma
,
2432 enum i915_cache_level level
,
2435 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2436 gen6_pte_t __iomem
*entries
= (gen6_pte_t __iomem
*)ggtt
->gsm
;
2437 unsigned int i
= vma
->node
.start
>> PAGE_SHIFT
;
2438 struct sgt_iter iter
;
2440 for_each_sgt_dma(addr
, iter
, vma
->pages
)
2441 iowrite32(vm
->pte_encode(addr
, level
, flags
), &entries
[i
++]);
2444 * We want to flush the TLBs only after we're certain all the PTE
2445 * updates have finished.
2447 ggtt
->invalidate(vm
->i915
);
2450 static void nop_clear_range(struct i915_address_space
*vm
,
2451 u64 start
, u64 length
)
2455 static void gen8_ggtt_clear_range(struct i915_address_space
*vm
,
2456 u64 start
, u64 length
)
2458 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2459 unsigned first_entry
= start
>> PAGE_SHIFT
;
2460 unsigned num_entries
= length
>> PAGE_SHIFT
;
2461 const gen8_pte_t scratch_pte
=
2462 gen8_pte_encode(vm
->scratch_page
.daddr
, I915_CACHE_LLC
);
2463 gen8_pte_t __iomem
*gtt_base
=
2464 (gen8_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2465 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2468 if (WARN(num_entries
> max_entries
,
2469 "First entry = %d; Num entries = %d (max=%d)\n",
2470 first_entry
, num_entries
, max_entries
))
2471 num_entries
= max_entries
;
2473 for (i
= 0; i
< num_entries
; i
++)
2474 gen8_set_pte(>t_base
[i
], scratch_pte
);
2477 static void bxt_vtd_ggtt_wa(struct i915_address_space
*vm
)
2479 struct drm_i915_private
*dev_priv
= vm
->i915
;
2482 * Make sure the internal GAM fifo has been cleared of all GTT
2483 * writes before exiting stop_machine(). This guarantees that
2484 * any aperture accesses waiting to start in another process
2485 * cannot back up behind the GTT writes causing a hang.
2486 * The register can be any arbitrary GAM register.
2488 POSTING_READ(GFX_FLSH_CNTL_GEN6
);
2491 struct insert_page
{
2492 struct i915_address_space
*vm
;
2495 enum i915_cache_level level
;
2498 static int bxt_vtd_ggtt_insert_page__cb(void *_arg
)
2500 struct insert_page
*arg
= _arg
;
2502 gen8_ggtt_insert_page(arg
->vm
, arg
->addr
, arg
->offset
, arg
->level
, 0);
2503 bxt_vtd_ggtt_wa(arg
->vm
);
2508 static void bxt_vtd_ggtt_insert_page__BKL(struct i915_address_space
*vm
,
2511 enum i915_cache_level level
,
2514 struct insert_page arg
= { vm
, addr
, offset
, level
};
2516 stop_machine(bxt_vtd_ggtt_insert_page__cb
, &arg
, NULL
);
2519 struct insert_entries
{
2520 struct i915_address_space
*vm
;
2521 struct i915_vma
*vma
;
2522 enum i915_cache_level level
;
2525 static int bxt_vtd_ggtt_insert_entries__cb(void *_arg
)
2527 struct insert_entries
*arg
= _arg
;
2529 gen8_ggtt_insert_entries(arg
->vm
, arg
->vma
, arg
->level
, 0);
2530 bxt_vtd_ggtt_wa(arg
->vm
);
2535 static void bxt_vtd_ggtt_insert_entries__BKL(struct i915_address_space
*vm
,
2536 struct i915_vma
*vma
,
2537 enum i915_cache_level level
,
2540 struct insert_entries arg
= { vm
, vma
, level
};
2542 stop_machine(bxt_vtd_ggtt_insert_entries__cb
, &arg
, NULL
);
2545 struct clear_range
{
2546 struct i915_address_space
*vm
;
2551 static int bxt_vtd_ggtt_clear_range__cb(void *_arg
)
2553 struct clear_range
*arg
= _arg
;
2555 gen8_ggtt_clear_range(arg
->vm
, arg
->start
, arg
->length
);
2556 bxt_vtd_ggtt_wa(arg
->vm
);
2561 static void bxt_vtd_ggtt_clear_range__BKL(struct i915_address_space
*vm
,
2565 struct clear_range arg
= { vm
, start
, length
};
2567 stop_machine(bxt_vtd_ggtt_clear_range__cb
, &arg
, NULL
);
2570 static void gen6_ggtt_clear_range(struct i915_address_space
*vm
,
2571 u64 start
, u64 length
)
2573 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
2574 unsigned first_entry
= start
>> PAGE_SHIFT
;
2575 unsigned num_entries
= length
>> PAGE_SHIFT
;
2576 gen6_pte_t scratch_pte
, __iomem
*gtt_base
=
2577 (gen6_pte_t __iomem
*)ggtt
->gsm
+ first_entry
;
2578 const int max_entries
= ggtt_total_entries(ggtt
) - first_entry
;
2581 if (WARN(num_entries
> max_entries
,
2582 "First entry = %d; Num entries = %d (max=%d)\n",
2583 first_entry
, num_entries
, max_entries
))
2584 num_entries
= max_entries
;
2586 scratch_pte
= vm
->pte_encode(vm
->scratch_page
.daddr
,
2589 for (i
= 0; i
< num_entries
; i
++)
2590 iowrite32(scratch_pte
, >t_base
[i
]);
2593 static void i915_ggtt_insert_page(struct i915_address_space
*vm
,
2596 enum i915_cache_level cache_level
,
2599 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2600 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2602 intel_gtt_insert_page(addr
, offset
>> PAGE_SHIFT
, flags
);
2605 static void i915_ggtt_insert_entries(struct i915_address_space
*vm
,
2606 struct i915_vma
*vma
,
2607 enum i915_cache_level cache_level
,
2610 unsigned int flags
= (cache_level
== I915_CACHE_NONE
) ?
2611 AGP_USER_MEMORY
: AGP_USER_CACHED_MEMORY
;
2613 intel_gtt_insert_sg_entries(vma
->pages
, vma
->node
.start
>> PAGE_SHIFT
,
2617 static void i915_ggtt_clear_range(struct i915_address_space
*vm
,
2618 u64 start
, u64 length
)
2620 intel_gtt_clear_range(start
>> PAGE_SHIFT
, length
>> PAGE_SHIFT
);
2623 static int ggtt_bind_vma(struct i915_vma
*vma
,
2624 enum i915_cache_level cache_level
,
2627 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2628 struct drm_i915_gem_object
*obj
= vma
->obj
;
2631 /* Currently applicable only to VLV */
2634 pte_flags
|= PTE_READ_ONLY
;
2636 intel_runtime_pm_get(i915
);
2637 vma
->vm
->insert_entries(vma
->vm
, vma
, cache_level
, pte_flags
);
2638 intel_runtime_pm_put(i915
);
2640 vma
->page_sizes
.gtt
= I915_GTT_PAGE_SIZE
;
2643 * Without aliasing PPGTT there's no difference between
2644 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
2645 * upgrade to both bound if we bind either to avoid double-binding.
2647 vma
->flags
|= I915_VMA_GLOBAL_BIND
| I915_VMA_LOCAL_BIND
;
2652 static void ggtt_unbind_vma(struct i915_vma
*vma
)
2654 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2656 intel_runtime_pm_get(i915
);
2657 vma
->vm
->clear_range(vma
->vm
, vma
->node
.start
, vma
->size
);
2658 intel_runtime_pm_put(i915
);
2661 static int aliasing_gtt_bind_vma(struct i915_vma
*vma
,
2662 enum i915_cache_level cache_level
,
2665 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2669 /* Currently applicable only to VLV */
2671 if (vma
->obj
->gt_ro
)
2672 pte_flags
|= PTE_READ_ONLY
;
2674 if (flags
& I915_VMA_LOCAL_BIND
) {
2675 struct i915_hw_ppgtt
*appgtt
= i915
->mm
.aliasing_ppgtt
;
2677 if (!(vma
->flags
& I915_VMA_LOCAL_BIND
) &&
2678 appgtt
->vm
.allocate_va_range
) {
2679 ret
= appgtt
->vm
.allocate_va_range(&appgtt
->vm
,
2686 appgtt
->vm
.insert_entries(&appgtt
->vm
, vma
, cache_level
,
2690 if (flags
& I915_VMA_GLOBAL_BIND
) {
2691 intel_runtime_pm_get(i915
);
2692 vma
->vm
->insert_entries(vma
->vm
, vma
, cache_level
, pte_flags
);
2693 intel_runtime_pm_put(i915
);
2699 static void aliasing_gtt_unbind_vma(struct i915_vma
*vma
)
2701 struct drm_i915_private
*i915
= vma
->vm
->i915
;
2703 if (vma
->flags
& I915_VMA_GLOBAL_BIND
) {
2704 intel_runtime_pm_get(i915
);
2705 vma
->vm
->clear_range(vma
->vm
, vma
->node
.start
, vma
->size
);
2706 intel_runtime_pm_put(i915
);
2709 if (vma
->flags
& I915_VMA_LOCAL_BIND
) {
2710 struct i915_address_space
*vm
= &i915
->mm
.aliasing_ppgtt
->vm
;
2712 vm
->clear_range(vm
, vma
->node
.start
, vma
->size
);
2716 void i915_gem_gtt_finish_pages(struct drm_i915_gem_object
*obj
,
2717 struct sg_table
*pages
)
2719 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
2720 struct device
*kdev
= &dev_priv
->drm
.pdev
->dev
;
2721 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2723 if (unlikely(ggtt
->do_idle_maps
)) {
2724 if (i915_gem_wait_for_idle(dev_priv
, 0)) {
2725 DRM_ERROR("Failed to wait for idle; VT'd may hang.\n");
2726 /* Wait a bit, in hopes it avoids the hang */
2731 dma_unmap_sg(kdev
, pages
->sgl
, pages
->nents
, PCI_DMA_BIDIRECTIONAL
);
2734 static int ggtt_set_pages(struct i915_vma
*vma
)
2738 GEM_BUG_ON(vma
->pages
);
2740 ret
= i915_get_ggtt_vma_pages(vma
);
2744 vma
->page_sizes
= vma
->obj
->mm
.page_sizes
;
2749 static void i915_gtt_color_adjust(const struct drm_mm_node
*node
,
2750 unsigned long color
,
2754 if (node
->allocated
&& node
->color
!= color
)
2755 *start
+= I915_GTT_PAGE_SIZE
;
2757 /* Also leave a space between the unallocated reserved node after the
2758 * GTT and any objects within the GTT, i.e. we use the color adjustment
2759 * to insert a guard page to prevent prefetches crossing over the
2762 node
= list_next_entry(node
, node_list
);
2763 if (node
->color
!= color
)
2764 *end
-= I915_GTT_PAGE_SIZE
;
2767 int i915_gem_init_aliasing_ppgtt(struct drm_i915_private
*i915
)
2769 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
2770 struct i915_hw_ppgtt
*ppgtt
;
2773 ppgtt
= i915_ppgtt_create(i915
, ERR_PTR(-EPERM
), "[alias]");
2775 return PTR_ERR(ppgtt
);
2777 if (WARN_ON(ppgtt
->vm
.total
< ggtt
->vm
.total
)) {
2782 if (ppgtt
->vm
.allocate_va_range
) {
2783 /* Note we only pre-allocate as far as the end of the global
2784 * GTT. On 48b / 4-level page-tables, the difference is very,
2785 * very significant! We have to preallocate as GVT/vgpu does
2786 * not like the page directory disappearing.
2788 err
= ppgtt
->vm
.allocate_va_range(&ppgtt
->vm
,
2794 i915
->mm
.aliasing_ppgtt
= ppgtt
;
2796 GEM_BUG_ON(ggtt
->vm
.bind_vma
!= ggtt_bind_vma
);
2797 ggtt
->vm
.bind_vma
= aliasing_gtt_bind_vma
;
2799 GEM_BUG_ON(ggtt
->vm
.unbind_vma
!= ggtt_unbind_vma
);
2800 ggtt
->vm
.unbind_vma
= aliasing_gtt_unbind_vma
;
2805 i915_ppgtt_put(ppgtt
);
2809 void i915_gem_fini_aliasing_ppgtt(struct drm_i915_private
*i915
)
2811 struct i915_ggtt
*ggtt
= &i915
->ggtt
;
2812 struct i915_hw_ppgtt
*ppgtt
;
2814 ppgtt
= fetch_and_zero(&i915
->mm
.aliasing_ppgtt
);
2818 i915_ppgtt_put(ppgtt
);
2820 ggtt
->vm
.bind_vma
= ggtt_bind_vma
;
2821 ggtt
->vm
.unbind_vma
= ggtt_unbind_vma
;
2824 int i915_gem_init_ggtt(struct drm_i915_private
*dev_priv
)
2826 /* Let GEM Manage all of the aperture.
2828 * However, leave one page at the end still bound to the scratch page.
2829 * There are a number of places where the hardware apparently prefetches
2830 * past the end of the object, and we've seen multiple hangs with the
2831 * GPU head pointer stuck in a batchbuffer bound at the last page of the
2832 * aperture. One page should be enough to keep any prefetching inside
2835 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2836 unsigned long hole_start
, hole_end
;
2837 struct drm_mm_node
*entry
;
2840 ret
= intel_vgt_balloon(dev_priv
);
2844 /* Reserve a mappable slot for our lockless error capture */
2845 ret
= drm_mm_insert_node_in_range(&ggtt
->vm
.mm
, &ggtt
->error_capture
,
2846 PAGE_SIZE
, 0, I915_COLOR_UNEVICTABLE
,
2847 0, ggtt
->mappable_end
,
2852 /* Clear any non-preallocated blocks */
2853 drm_mm_for_each_hole(entry
, &ggtt
->vm
.mm
, hole_start
, hole_end
) {
2854 DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
2855 hole_start
, hole_end
);
2856 ggtt
->vm
.clear_range(&ggtt
->vm
, hole_start
,
2857 hole_end
- hole_start
);
2860 /* And finally clear the reserved guard page */
2861 ggtt
->vm
.clear_range(&ggtt
->vm
, ggtt
->vm
.total
- PAGE_SIZE
, PAGE_SIZE
);
2863 if (USES_PPGTT(dev_priv
) && !USES_FULL_PPGTT(dev_priv
)) {
2864 ret
= i915_gem_init_aliasing_ppgtt(dev_priv
);
2872 drm_mm_remove_node(&ggtt
->error_capture
);
2877 * i915_ggtt_cleanup_hw - Clean up GGTT hardware initialization
2878 * @dev_priv: i915 device
2880 void i915_ggtt_cleanup_hw(struct drm_i915_private
*dev_priv
)
2882 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
2883 struct i915_vma
*vma
, *vn
;
2884 struct pagevec
*pvec
;
2886 ggtt
->vm
.closed
= true;
2888 mutex_lock(&dev_priv
->drm
.struct_mutex
);
2889 GEM_BUG_ON(!list_empty(&ggtt
->vm
.active_list
));
2890 list_for_each_entry_safe(vma
, vn
, &ggtt
->vm
.inactive_list
, vm_link
)
2891 WARN_ON(i915_vma_unbind(vma
));
2892 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
2894 i915_gem_cleanup_stolen(&dev_priv
->drm
);
2896 mutex_lock(&dev_priv
->drm
.struct_mutex
);
2897 i915_gem_fini_aliasing_ppgtt(dev_priv
);
2899 if (drm_mm_node_allocated(&ggtt
->error_capture
))
2900 drm_mm_remove_node(&ggtt
->error_capture
);
2902 if (drm_mm_initialized(&ggtt
->vm
.mm
)) {
2903 intel_vgt_deballoon(dev_priv
);
2904 i915_address_space_fini(&ggtt
->vm
);
2907 ggtt
->vm
.cleanup(&ggtt
->vm
);
2909 pvec
= &dev_priv
->mm
.wc_stash
;
2911 set_pages_array_wb(pvec
->pages
, pvec
->nr
);
2912 __pagevec_release(pvec
);
2915 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
2917 arch_phys_wc_del(ggtt
->mtrr
);
2918 io_mapping_fini(&ggtt
->iomap
);
2921 static unsigned int gen6_get_total_gtt_size(u16 snb_gmch_ctl
)
2923 snb_gmch_ctl
>>= SNB_GMCH_GGMS_SHIFT
;
2924 snb_gmch_ctl
&= SNB_GMCH_GGMS_MASK
;
2925 return snb_gmch_ctl
<< 20;
2928 static unsigned int gen8_get_total_gtt_size(u16 bdw_gmch_ctl
)
2930 bdw_gmch_ctl
>>= BDW_GMCH_GGMS_SHIFT
;
2931 bdw_gmch_ctl
&= BDW_GMCH_GGMS_MASK
;
2933 bdw_gmch_ctl
= 1 << bdw_gmch_ctl
;
2935 #ifdef CONFIG_X86_32
2936 /* Limit 32b platforms to a 2GB GGTT: 4 << 20 / pte size * PAGE_SIZE */
2937 if (bdw_gmch_ctl
> 4)
2941 return bdw_gmch_ctl
<< 20;
2944 static unsigned int chv_get_total_gtt_size(u16 gmch_ctrl
)
2946 gmch_ctrl
>>= SNB_GMCH_GGMS_SHIFT
;
2947 gmch_ctrl
&= SNB_GMCH_GGMS_MASK
;
2950 return 1 << (20 + gmch_ctrl
);
2955 static int ggtt_probe_common(struct i915_ggtt
*ggtt
, u64 size
)
2957 struct drm_i915_private
*dev_priv
= ggtt
->vm
.i915
;
2958 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
2959 phys_addr_t phys_addr
;
2962 /* For Modern GENs the PTEs and register space are split in the BAR */
2963 phys_addr
= pci_resource_start(pdev
, 0) + pci_resource_len(pdev
, 0) / 2;
2966 * On BXT+/CNL+ writes larger than 64 bit to the GTT pagetable range
2967 * will be dropped. For WC mappings in general we have 64 byte burst
2968 * writes when the WC buffer is flushed, so we can't use it, but have to
2969 * resort to an uncached mapping. The WC issue is easily caught by the
2970 * readback check when writing GTT PTE entries.
2972 if (IS_GEN9_LP(dev_priv
) || INTEL_GEN(dev_priv
) >= 10)
2973 ggtt
->gsm
= ioremap_nocache(phys_addr
, size
);
2975 ggtt
->gsm
= ioremap_wc(phys_addr
, size
);
2977 DRM_ERROR("Failed to map the ggtt page table\n");
2981 ret
= setup_scratch_page(&ggtt
->vm
, GFP_DMA32
);
2983 DRM_ERROR("Scratch setup failed\n");
2984 /* iounmap will also get called at remove, but meh */
2992 static struct intel_ppat_entry
*
2993 __alloc_ppat_entry(struct intel_ppat
*ppat
, unsigned int index
, u8 value
)
2995 struct intel_ppat_entry
*entry
= &ppat
->entries
[index
];
2997 GEM_BUG_ON(index
>= ppat
->max_entries
);
2998 GEM_BUG_ON(test_bit(index
, ppat
->used
));
3001 entry
->value
= value
;
3002 kref_init(&entry
->ref
);
3003 set_bit(index
, ppat
->used
);
3004 set_bit(index
, ppat
->dirty
);
3009 static void __free_ppat_entry(struct intel_ppat_entry
*entry
)
3011 struct intel_ppat
*ppat
= entry
->ppat
;
3012 unsigned int index
= entry
- ppat
->entries
;
3014 GEM_BUG_ON(index
>= ppat
->max_entries
);
3015 GEM_BUG_ON(!test_bit(index
, ppat
->used
));
3017 entry
->value
= ppat
->clear_value
;
3018 clear_bit(index
, ppat
->used
);
3019 set_bit(index
, ppat
->dirty
);
3023 * intel_ppat_get - get a usable PPAT entry
3024 * @i915: i915 device instance
3025 * @value: the PPAT value required by the caller
3027 * The function tries to search if there is an existing PPAT entry which
3028 * matches with the required value. If perfectly matched, the existing PPAT
3029 * entry will be used. If only partially matched, it will try to check if
3030 * there is any available PPAT index. If yes, it will allocate a new PPAT
3031 * index for the required entry and update the HW. If not, the partially
3032 * matched entry will be used.
3034 const struct intel_ppat_entry
*
3035 intel_ppat_get(struct drm_i915_private
*i915
, u8 value
)
3037 struct intel_ppat
*ppat
= &i915
->ppat
;
3038 struct intel_ppat_entry
*entry
= NULL
;
3039 unsigned int scanned
, best_score
;
3042 GEM_BUG_ON(!ppat
->max_entries
);
3044 scanned
= best_score
= 0;
3045 for_each_set_bit(i
, ppat
->used
, ppat
->max_entries
) {
3048 score
= ppat
->match(ppat
->entries
[i
].value
, value
);
3049 if (score
> best_score
) {
3050 entry
= &ppat
->entries
[i
];
3051 if (score
== INTEL_PPAT_PERFECT_MATCH
) {
3052 kref_get(&entry
->ref
);
3060 if (scanned
== ppat
->max_entries
) {
3062 return ERR_PTR(-ENOSPC
);
3064 kref_get(&entry
->ref
);
3068 i
= find_first_zero_bit(ppat
->used
, ppat
->max_entries
);
3069 entry
= __alloc_ppat_entry(ppat
, i
, value
);
3070 ppat
->update_hw(i915
);
3074 static void release_ppat(struct kref
*kref
)
3076 struct intel_ppat_entry
*entry
=
3077 container_of(kref
, struct intel_ppat_entry
, ref
);
3078 struct drm_i915_private
*i915
= entry
->ppat
->i915
;
3080 __free_ppat_entry(entry
);
3081 entry
->ppat
->update_hw(i915
);
3085 * intel_ppat_put - put back the PPAT entry got from intel_ppat_get()
3086 * @entry: an intel PPAT entry
3088 * Put back the PPAT entry got from intel_ppat_get(). If the PPAT index of the
3089 * entry is dynamically allocated, its reference count will be decreased. Once
3090 * the reference count becomes into zero, the PPAT index becomes free again.
3092 void intel_ppat_put(const struct intel_ppat_entry
*entry
)
3094 struct intel_ppat
*ppat
= entry
->ppat
;
3095 unsigned int index
= entry
- ppat
->entries
;
3097 GEM_BUG_ON(!ppat
->max_entries
);
3099 kref_put(&ppat
->entries
[index
].ref
, release_ppat
);
3102 static void cnl_private_pat_update_hw(struct drm_i915_private
*dev_priv
)
3104 struct intel_ppat
*ppat
= &dev_priv
->ppat
;
3107 for_each_set_bit(i
, ppat
->dirty
, ppat
->max_entries
) {
3108 I915_WRITE(GEN10_PAT_INDEX(i
), ppat
->entries
[i
].value
);
3109 clear_bit(i
, ppat
->dirty
);
3113 static void bdw_private_pat_update_hw(struct drm_i915_private
*dev_priv
)
3115 struct intel_ppat
*ppat
= &dev_priv
->ppat
;
3119 for (i
= 0; i
< ppat
->max_entries
; i
++)
3120 pat
|= GEN8_PPAT(i
, ppat
->entries
[i
].value
);
3122 bitmap_clear(ppat
->dirty
, 0, ppat
->max_entries
);
3124 I915_WRITE(GEN8_PRIVATE_PAT_LO
, lower_32_bits(pat
));
3125 I915_WRITE(GEN8_PRIVATE_PAT_HI
, upper_32_bits(pat
));
3128 static unsigned int bdw_private_pat_match(u8 src
, u8 dst
)
3130 unsigned int score
= 0;
3137 /* Cache attribute has to be matched. */
3138 if (GEN8_PPAT_GET_CA(src
) != GEN8_PPAT_GET_CA(dst
))
3143 if (GEN8_PPAT_GET_TC(src
) == GEN8_PPAT_GET_TC(dst
))
3146 if (GEN8_PPAT_GET_AGE(src
) == GEN8_PPAT_GET_AGE(dst
))
3149 if (score
== (AGE_MATCH
| TC_MATCH
| CA_MATCH
))
3150 return INTEL_PPAT_PERFECT_MATCH
;
3155 static unsigned int chv_private_pat_match(u8 src
, u8 dst
)
3157 return (CHV_PPAT_GET_SNOOP(src
) == CHV_PPAT_GET_SNOOP(dst
)) ?
3158 INTEL_PPAT_PERFECT_MATCH
: 0;
3161 static void cnl_setup_private_ppat(struct intel_ppat
*ppat
)
3163 ppat
->max_entries
= 8;
3164 ppat
->update_hw
= cnl_private_pat_update_hw
;
3165 ppat
->match
= bdw_private_pat_match
;
3166 ppat
->clear_value
= GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3);
3168 __alloc_ppat_entry(ppat
, 0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
);
3169 __alloc_ppat_entry(ppat
, 1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
);
3170 __alloc_ppat_entry(ppat
, 2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
);
3171 __alloc_ppat_entry(ppat
, 3, GEN8_PPAT_UC
);
3172 __alloc_ppat_entry(ppat
, 4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0));
3173 __alloc_ppat_entry(ppat
, 5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1));
3174 __alloc_ppat_entry(ppat
, 6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2));
3175 __alloc_ppat_entry(ppat
, 7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
3178 /* The GGTT and PPGTT need a private PPAT setup in order to handle cacheability
3179 * bits. When using advanced contexts each context stores its own PAT, but
3180 * writing this data shouldn't be harmful even in those cases. */
3181 static void bdw_setup_private_ppat(struct intel_ppat
*ppat
)
3183 ppat
->max_entries
= 8;
3184 ppat
->update_hw
= bdw_private_pat_update_hw
;
3185 ppat
->match
= bdw_private_pat_match
;
3186 ppat
->clear_value
= GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3);
3188 if (!USES_PPGTT(ppat
->i915
)) {
3189 /* Spec: "For GGTT, there is NO pat_sel[2:0] from the entry,
3190 * so RTL will always use the value corresponding to
3192 * So let's disable cache for GGTT to avoid screen corruptions.
3193 * MOCS still can be used though.
3194 * - System agent ggtt writes (i.e. cpu gtt mmaps) already work
3195 * before this patch, i.e. the same uncached + snooping access
3196 * like on gen6/7 seems to be in effect.
3197 * - So this just fixes blitter/render access. Again it looks
3198 * like it's not just uncached access, but uncached + snooping.
3199 * So we can still hold onto all our assumptions wrt cpu
3200 * clflushing on LLC machines.
3202 __alloc_ppat_entry(ppat
, 0, GEN8_PPAT_UC
);
3206 __alloc_ppat_entry(ppat
, 0, GEN8_PPAT_WB
| GEN8_PPAT_LLC
); /* for normal objects, no eLLC */
3207 __alloc_ppat_entry(ppat
, 1, GEN8_PPAT_WC
| GEN8_PPAT_LLCELLC
); /* for something pointing to ptes? */
3208 __alloc_ppat_entry(ppat
, 2, GEN8_PPAT_WT
| GEN8_PPAT_LLCELLC
); /* for scanout with eLLC */
3209 __alloc_ppat_entry(ppat
, 3, GEN8_PPAT_UC
); /* Uncached objects, mostly for scanout */
3210 __alloc_ppat_entry(ppat
, 4, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(0));
3211 __alloc_ppat_entry(ppat
, 5, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(1));
3212 __alloc_ppat_entry(ppat
, 6, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(2));
3213 __alloc_ppat_entry(ppat
, 7, GEN8_PPAT_WB
| GEN8_PPAT_LLCELLC
| GEN8_PPAT_AGE(3));
3216 static void chv_setup_private_ppat(struct intel_ppat
*ppat
)
3218 ppat
->max_entries
= 8;
3219 ppat
->update_hw
= bdw_private_pat_update_hw
;
3220 ppat
->match
= chv_private_pat_match
;
3221 ppat
->clear_value
= CHV_PPAT_SNOOP
;
3224 * Map WB on BDW to snooped on CHV.
3226 * Only the snoop bit has meaning for CHV, the rest is
3229 * The hardware will never snoop for certain types of accesses:
3230 * - CPU GTT (GMADR->GGTT->no snoop->memory)
3231 * - PPGTT page tables
3232 * - some other special cycles
3234 * As with BDW, we also need to consider the following for GT accesses:
3235 * "For GGTT, there is NO pat_sel[2:0] from the entry,
3236 * so RTL will always use the value corresponding to
3238 * Which means we must set the snoop bit in PAT entry 0
3239 * in order to keep the global status page working.
3242 __alloc_ppat_entry(ppat
, 0, CHV_PPAT_SNOOP
);
3243 __alloc_ppat_entry(ppat
, 1, 0);
3244 __alloc_ppat_entry(ppat
, 2, 0);
3245 __alloc_ppat_entry(ppat
, 3, 0);
3246 __alloc_ppat_entry(ppat
, 4, CHV_PPAT_SNOOP
);
3247 __alloc_ppat_entry(ppat
, 5, CHV_PPAT_SNOOP
);
3248 __alloc_ppat_entry(ppat
, 6, CHV_PPAT_SNOOP
);
3249 __alloc_ppat_entry(ppat
, 7, CHV_PPAT_SNOOP
);
3252 static void gen6_gmch_remove(struct i915_address_space
*vm
)
3254 struct i915_ggtt
*ggtt
= i915_vm_to_ggtt(vm
);
3257 cleanup_scratch_page(vm
);
3260 static void setup_private_pat(struct drm_i915_private
*dev_priv
)
3262 struct intel_ppat
*ppat
= &dev_priv
->ppat
;
3265 ppat
->i915
= dev_priv
;
3267 if (INTEL_GEN(dev_priv
) >= 10)
3268 cnl_setup_private_ppat(ppat
);
3269 else if (IS_CHERRYVIEW(dev_priv
) || IS_GEN9_LP(dev_priv
))
3270 chv_setup_private_ppat(ppat
);
3272 bdw_setup_private_ppat(ppat
);
3274 GEM_BUG_ON(ppat
->max_entries
> INTEL_MAX_PPAT_ENTRIES
);
3276 for_each_clear_bit(i
, ppat
->used
, ppat
->max_entries
) {
3277 ppat
->entries
[i
].value
= ppat
->clear_value
;
3278 ppat
->entries
[i
].ppat
= ppat
;
3279 set_bit(i
, ppat
->dirty
);
3282 ppat
->update_hw(dev_priv
);
3285 static int gen8_gmch_probe(struct i915_ggtt
*ggtt
)
3287 struct drm_i915_private
*dev_priv
= ggtt
->vm
.i915
;
3288 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
3293 /* TODO: We're not aware of mappable constraints on gen8 yet */
3295 (struct resource
) DEFINE_RES_MEM(pci_resource_start(pdev
, 2),
3296 pci_resource_len(pdev
, 2));
3297 ggtt
->mappable_end
= resource_size(&ggtt
->gmadr
);
3299 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(39));
3301 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(39));
3303 DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err
);
3305 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3306 if (IS_CHERRYVIEW(dev_priv
))
3307 size
= chv_get_total_gtt_size(snb_gmch_ctl
);
3309 size
= gen8_get_total_gtt_size(snb_gmch_ctl
);
3311 ggtt
->vm
.total
= (size
/ sizeof(gen8_pte_t
)) << PAGE_SHIFT
;
3312 ggtt
->vm
.cleanup
= gen6_gmch_remove
;
3313 ggtt
->vm
.bind_vma
= ggtt_bind_vma
;
3314 ggtt
->vm
.unbind_vma
= ggtt_unbind_vma
;
3315 ggtt
->vm
.set_pages
= ggtt_set_pages
;
3316 ggtt
->vm
.clear_pages
= clear_pages
;
3317 ggtt
->vm
.insert_page
= gen8_ggtt_insert_page
;
3318 ggtt
->vm
.clear_range
= nop_clear_range
;
3319 if (!USES_FULL_PPGTT(dev_priv
) || intel_scanout_needs_vtd_wa(dev_priv
))
3320 ggtt
->vm
.clear_range
= gen8_ggtt_clear_range
;
3322 ggtt
->vm
.insert_entries
= gen8_ggtt_insert_entries
;
3324 /* Serialize GTT updates with aperture access on BXT if VT-d is on. */
3325 if (intel_ggtt_update_needs_vtd_wa(dev_priv
)) {
3326 ggtt
->vm
.insert_entries
= bxt_vtd_ggtt_insert_entries__BKL
;
3327 ggtt
->vm
.insert_page
= bxt_vtd_ggtt_insert_page__BKL
;
3328 if (ggtt
->vm
.clear_range
!= nop_clear_range
)
3329 ggtt
->vm
.clear_range
= bxt_vtd_ggtt_clear_range__BKL
;
3332 ggtt
->invalidate
= gen6_ggtt_invalidate
;
3334 setup_private_pat(dev_priv
);
3336 return ggtt_probe_common(ggtt
, size
);
3339 static int gen6_gmch_probe(struct i915_ggtt
*ggtt
)
3341 struct drm_i915_private
*dev_priv
= ggtt
->vm
.i915
;
3342 struct pci_dev
*pdev
= dev_priv
->drm
.pdev
;
3348 (struct resource
) DEFINE_RES_MEM(pci_resource_start(pdev
, 2),
3349 pci_resource_len(pdev
, 2));
3350 ggtt
->mappable_end
= resource_size(&ggtt
->gmadr
);
3352 /* 64/512MB is the current min/max we actually know of, but this is just
3353 * a coarse sanity check.
3355 if (ggtt
->mappable_end
< (64<<20) || ggtt
->mappable_end
> (512<<20)) {
3356 DRM_ERROR("Unknown GMADR size (%pa)\n", &ggtt
->mappable_end
);
3360 err
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(40));
3362 err
= pci_set_consistent_dma_mask(pdev
, DMA_BIT_MASK(40));
3364 DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err
);
3365 pci_read_config_word(pdev
, SNB_GMCH_CTRL
, &snb_gmch_ctl
);
3367 size
= gen6_get_total_gtt_size(snb_gmch_ctl
);
3368 ggtt
->vm
.total
= (size
/ sizeof(gen6_pte_t
)) << PAGE_SHIFT
;
3370 ggtt
->vm
.clear_range
= gen6_ggtt_clear_range
;
3371 ggtt
->vm
.insert_page
= gen6_ggtt_insert_page
;
3372 ggtt
->vm
.insert_entries
= gen6_ggtt_insert_entries
;
3373 ggtt
->vm
.bind_vma
= ggtt_bind_vma
;
3374 ggtt
->vm
.unbind_vma
= ggtt_unbind_vma
;
3375 ggtt
->vm
.set_pages
= ggtt_set_pages
;
3376 ggtt
->vm
.clear_pages
= clear_pages
;
3377 ggtt
->vm
.cleanup
= gen6_gmch_remove
;
3379 ggtt
->invalidate
= gen6_ggtt_invalidate
;
3381 if (HAS_EDRAM(dev_priv
))
3382 ggtt
->vm
.pte_encode
= iris_pte_encode
;
3383 else if (IS_HASWELL(dev_priv
))
3384 ggtt
->vm
.pte_encode
= hsw_pte_encode
;
3385 else if (IS_VALLEYVIEW(dev_priv
))
3386 ggtt
->vm
.pte_encode
= byt_pte_encode
;
3387 else if (INTEL_GEN(dev_priv
) >= 7)
3388 ggtt
->vm
.pte_encode
= ivb_pte_encode
;
3390 ggtt
->vm
.pte_encode
= snb_pte_encode
;
3392 return ggtt_probe_common(ggtt
, size
);
3395 static void i915_gmch_remove(struct i915_address_space
*vm
)
3397 intel_gmch_remove();
3400 static int i915_gmch_probe(struct i915_ggtt
*ggtt
)
3402 struct drm_i915_private
*dev_priv
= ggtt
->vm
.i915
;
3403 phys_addr_t gmadr_base
;
3406 ret
= intel_gmch_probe(dev_priv
->bridge_dev
, dev_priv
->drm
.pdev
, NULL
);
3408 DRM_ERROR("failed to set up gmch\n");
3412 intel_gtt_get(&ggtt
->vm
.total
, &gmadr_base
, &ggtt
->mappable_end
);
3415 (struct resource
) DEFINE_RES_MEM(gmadr_base
,
3416 ggtt
->mappable_end
);
3418 ggtt
->do_idle_maps
= needs_idle_maps(dev_priv
);
3419 ggtt
->vm
.insert_page
= i915_ggtt_insert_page
;
3420 ggtt
->vm
.insert_entries
= i915_ggtt_insert_entries
;
3421 ggtt
->vm
.clear_range
= i915_ggtt_clear_range
;
3422 ggtt
->vm
.bind_vma
= ggtt_bind_vma
;
3423 ggtt
->vm
.unbind_vma
= ggtt_unbind_vma
;
3424 ggtt
->vm
.set_pages
= ggtt_set_pages
;
3425 ggtt
->vm
.clear_pages
= clear_pages
;
3426 ggtt
->vm
.cleanup
= i915_gmch_remove
;
3428 ggtt
->invalidate
= gmch_ggtt_invalidate
;
3430 if (unlikely(ggtt
->do_idle_maps
))
3431 DRM_INFO("applying Ironlake quirks for intel_iommu\n");
3437 * i915_ggtt_probe_hw - Probe GGTT hardware location
3438 * @dev_priv: i915 device
3440 int i915_ggtt_probe_hw(struct drm_i915_private
*dev_priv
)
3442 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3445 ggtt
->vm
.i915
= dev_priv
;
3446 ggtt
->vm
.dma
= &dev_priv
->drm
.pdev
->dev
;
3448 if (INTEL_GEN(dev_priv
) <= 5)
3449 ret
= i915_gmch_probe(ggtt
);
3450 else if (INTEL_GEN(dev_priv
) < 8)
3451 ret
= gen6_gmch_probe(ggtt
);
3453 ret
= gen8_gmch_probe(ggtt
);
3457 /* Trim the GGTT to fit the GuC mappable upper range (when enabled).
3458 * This is easier than doing range restriction on the fly, as we
3459 * currently don't have any bits spare to pass in this upper
3462 if (USES_GUC(dev_priv
)) {
3463 ggtt
->vm
.total
= min_t(u64
, ggtt
->vm
.total
, GUC_GGTT_TOP
);
3464 ggtt
->mappable_end
=
3465 min_t(u64
, ggtt
->mappable_end
, ggtt
->vm
.total
);
3468 if ((ggtt
->vm
.total
- 1) >> 32) {
3469 DRM_ERROR("We never expected a Global GTT with more than 32bits"
3470 " of address space! Found %lldM!\n",
3471 ggtt
->vm
.total
>> 20);
3472 ggtt
->vm
.total
= 1ULL << 32;
3473 ggtt
->mappable_end
=
3474 min_t(u64
, ggtt
->mappable_end
, ggtt
->vm
.total
);
3477 if (ggtt
->mappable_end
> ggtt
->vm
.total
) {
3478 DRM_ERROR("mappable aperture extends past end of GGTT,"
3479 " aperture=%pa, total=%llx\n",
3480 &ggtt
->mappable_end
, ggtt
->vm
.total
);
3481 ggtt
->mappable_end
= ggtt
->vm
.total
;
3484 /* GMADR is the PCI mmio aperture into the global GTT. */
3485 DRM_DEBUG_DRIVER("GGTT size = %lluM\n", ggtt
->vm
.total
>> 20);
3486 DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64
)ggtt
->mappable_end
>> 20);
3487 DRM_DEBUG_DRIVER("DSM size = %lluM\n",
3488 (u64
)resource_size(&intel_graphics_stolen_res
) >> 20);
3489 if (intel_vtd_active())
3490 DRM_INFO("VT-d active for gfx access\n");
3496 * i915_ggtt_init_hw - Initialize GGTT hardware
3497 * @dev_priv: i915 device
3499 int i915_ggtt_init_hw(struct drm_i915_private
*dev_priv
)
3501 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3504 INIT_LIST_HEAD(&dev_priv
->vm_list
);
3506 /* Note that we use page colouring to enforce a guard page at the
3507 * end of the address space. This is required as the CS may prefetch
3508 * beyond the end of the batch buffer, across the page boundary,
3509 * and beyond the end of the GTT if we do not provide a guard.
3511 mutex_lock(&dev_priv
->drm
.struct_mutex
);
3512 i915_address_space_init(&ggtt
->vm
, dev_priv
, "[global]");
3513 if (!HAS_LLC(dev_priv
) && !USES_PPGTT(dev_priv
))
3514 ggtt
->vm
.mm
.color_adjust
= i915_gtt_color_adjust
;
3515 mutex_unlock(&dev_priv
->drm
.struct_mutex
);
3517 if (!io_mapping_init_wc(&dev_priv
->ggtt
.iomap
,
3518 dev_priv
->ggtt
.gmadr
.start
,
3519 dev_priv
->ggtt
.mappable_end
)) {
3521 goto out_gtt_cleanup
;
3524 ggtt
->mtrr
= arch_phys_wc_add(ggtt
->gmadr
.start
, ggtt
->mappable_end
);
3527 * Initialise stolen early so that we may reserve preallocated
3528 * objects for the BIOS to KMS transition.
3530 ret
= i915_gem_init_stolen(dev_priv
);
3532 goto out_gtt_cleanup
;
3537 ggtt
->vm
.cleanup(&ggtt
->vm
);
3541 int i915_ggtt_enable_hw(struct drm_i915_private
*dev_priv
)
3543 if (INTEL_GEN(dev_priv
) < 6 && !intel_enable_gtt())
3549 void i915_ggtt_enable_guc(struct drm_i915_private
*i915
)
3551 GEM_BUG_ON(i915
->ggtt
.invalidate
!= gen6_ggtt_invalidate
);
3553 i915
->ggtt
.invalidate
= guc_ggtt_invalidate
;
3555 i915_ggtt_invalidate(i915
);
3558 void i915_ggtt_disable_guc(struct drm_i915_private
*i915
)
3560 /* We should only be called after i915_ggtt_enable_guc() */
3561 GEM_BUG_ON(i915
->ggtt
.invalidate
!= guc_ggtt_invalidate
);
3563 i915
->ggtt
.invalidate
= gen6_ggtt_invalidate
;
3565 i915_ggtt_invalidate(i915
);
3568 void i915_gem_restore_gtt_mappings(struct drm_i915_private
*dev_priv
)
3570 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3571 struct i915_vma
*vma
, *vn
;
3573 i915_check_and_clear_faults(dev_priv
);
3575 /* First fill our portion of the GTT with scratch pages */
3576 ggtt
->vm
.clear_range(&ggtt
->vm
, 0, ggtt
->vm
.total
);
3578 ggtt
->vm
.closed
= true; /* skip rewriting PTE on VMA unbind */
3580 /* clflush objects bound into the GGTT and rebind them. */
3581 GEM_BUG_ON(!list_empty(&ggtt
->vm
.active_list
));
3582 list_for_each_entry_safe(vma
, vn
, &ggtt
->vm
.inactive_list
, vm_link
) {
3583 struct drm_i915_gem_object
*obj
= vma
->obj
;
3585 if (!(vma
->flags
& I915_VMA_GLOBAL_BIND
))
3588 if (!i915_vma_unbind(vma
))
3591 WARN_ON(i915_vma_bind(vma
, obj
->cache_level
, PIN_UPDATE
));
3592 WARN_ON(i915_gem_object_set_to_gtt_domain(obj
, false));
3595 ggtt
->vm
.closed
= false;
3597 if (INTEL_GEN(dev_priv
) >= 8) {
3598 struct intel_ppat
*ppat
= &dev_priv
->ppat
;
3600 bitmap_set(ppat
->dirty
, 0, ppat
->max_entries
);
3601 dev_priv
->ppat
.update_hw(dev_priv
);
3605 if (USES_PPGTT(dev_priv
)) {
3606 struct i915_address_space
*vm
;
3608 list_for_each_entry(vm
, &dev_priv
->vm_list
, global_link
) {
3609 struct i915_hw_ppgtt
*ppgtt
;
3611 if (i915_is_ggtt(vm
))
3612 ppgtt
= dev_priv
->mm
.aliasing_ppgtt
;
3614 ppgtt
= i915_vm_to_ppgtt(vm
);
3618 gen6_write_page_range(ppgtt
, 0, ppgtt
->vm
.total
);
3622 i915_ggtt_invalidate(dev_priv
);
3625 static struct scatterlist
*
3626 rotate_pages(const dma_addr_t
*in
, unsigned int offset
,
3627 unsigned int width
, unsigned int height
,
3628 unsigned int stride
,
3629 struct sg_table
*st
, struct scatterlist
*sg
)
3631 unsigned int column
, row
;
3632 unsigned int src_idx
;
3634 for (column
= 0; column
< width
; column
++) {
3635 src_idx
= stride
* (height
- 1) + column
;
3636 for (row
= 0; row
< height
; row
++) {
3638 /* We don't need the pages, but need to initialize
3639 * the entries so the sg list can be happily traversed.
3640 * The only thing we need are DMA addresses.
3642 sg_set_page(sg
, NULL
, PAGE_SIZE
, 0);
3643 sg_dma_address(sg
) = in
[offset
+ src_idx
];
3644 sg_dma_len(sg
) = PAGE_SIZE
;
3653 static noinline
struct sg_table
*
3654 intel_rotate_pages(struct intel_rotation_info
*rot_info
,
3655 struct drm_i915_gem_object
*obj
)
3657 const unsigned long n_pages
= obj
->base
.size
/ PAGE_SIZE
;
3658 unsigned int size
= intel_rotation_info_size(rot_info
);
3659 struct sgt_iter sgt_iter
;
3660 dma_addr_t dma_addr
;
3662 dma_addr_t
*page_addr_list
;
3663 struct sg_table
*st
;
3664 struct scatterlist
*sg
;
3667 /* Allocate a temporary list of source pages for random access. */
3668 page_addr_list
= kvmalloc_array(n_pages
,
3671 if (!page_addr_list
)
3672 return ERR_PTR(ret
);
3674 /* Allocate target SG list. */
3675 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3679 ret
= sg_alloc_table(st
, size
, GFP_KERNEL
);
3683 /* Populate source page list from the object. */
3685 for_each_sgt_dma(dma_addr
, sgt_iter
, obj
->mm
.pages
)
3686 page_addr_list
[i
++] = dma_addr
;
3688 GEM_BUG_ON(i
!= n_pages
);
3692 for (i
= 0 ; i
< ARRAY_SIZE(rot_info
->plane
); i
++) {
3693 sg
= rotate_pages(page_addr_list
, rot_info
->plane
[i
].offset
,
3694 rot_info
->plane
[i
].width
, rot_info
->plane
[i
].height
,
3695 rot_info
->plane
[i
].stride
, st
, sg
);
3698 kvfree(page_addr_list
);
3705 kvfree(page_addr_list
);
3707 DRM_DEBUG_DRIVER("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
3708 obj
->base
.size
, rot_info
->plane
[0].width
, rot_info
->plane
[0].height
, size
);
3710 return ERR_PTR(ret
);
3713 static noinline
struct sg_table
*
3714 intel_partial_pages(const struct i915_ggtt_view
*view
,
3715 struct drm_i915_gem_object
*obj
)
3717 struct sg_table
*st
;
3718 struct scatterlist
*sg
, *iter
;
3719 unsigned int count
= view
->partial
.size
;
3720 unsigned int offset
;
3723 st
= kmalloc(sizeof(*st
), GFP_KERNEL
);
3727 ret
= sg_alloc_table(st
, count
, GFP_KERNEL
);
3731 iter
= i915_gem_object_get_sg(obj
, view
->partial
.offset
, &offset
);
3739 len
= min(iter
->length
- (offset
<< PAGE_SHIFT
),
3740 count
<< PAGE_SHIFT
);
3741 sg_set_page(sg
, NULL
, len
, 0);
3742 sg_dma_address(sg
) =
3743 sg_dma_address(iter
) + (offset
<< PAGE_SHIFT
);
3744 sg_dma_len(sg
) = len
;
3747 count
-= len
>> PAGE_SHIFT
;
3754 iter
= __sg_next(iter
);
3761 return ERR_PTR(ret
);
3765 i915_get_ggtt_vma_pages(struct i915_vma
*vma
)
3769 /* The vma->pages are only valid within the lifespan of the borrowed
3770 * obj->mm.pages. When the obj->mm.pages sg_table is regenerated, so
3771 * must be the vma->pages. A simple rule is that vma->pages must only
3772 * be accessed when the obj->mm.pages are pinned.
3774 GEM_BUG_ON(!i915_gem_object_has_pinned_pages(vma
->obj
));
3776 switch (vma
->ggtt_view
.type
) {
3778 GEM_BUG_ON(vma
->ggtt_view
.type
);
3780 case I915_GGTT_VIEW_NORMAL
:
3781 vma
->pages
= vma
->obj
->mm
.pages
;
3784 case I915_GGTT_VIEW_ROTATED
:
3786 intel_rotate_pages(&vma
->ggtt_view
.rotated
, vma
->obj
);
3789 case I915_GGTT_VIEW_PARTIAL
:
3790 vma
->pages
= intel_partial_pages(&vma
->ggtt_view
, vma
->obj
);
3795 if (unlikely(IS_ERR(vma
->pages
))) {
3796 ret
= PTR_ERR(vma
->pages
);
3798 DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
3799 vma
->ggtt_view
.type
, ret
);
3805 * i915_gem_gtt_reserve - reserve a node in an address_space (GTT)
3806 * @vm: the &struct i915_address_space
3807 * @node: the &struct drm_mm_node (typically i915_vma.mode)
3808 * @size: how much space to allocate inside the GTT,
3809 * must be #I915_GTT_PAGE_SIZE aligned
3810 * @offset: where to insert inside the GTT,
3811 * must be #I915_GTT_MIN_ALIGNMENT aligned, and the node
3812 * (@offset + @size) must fit within the address space
3813 * @color: color to apply to node, if this node is not from a VMA,
3814 * color must be #I915_COLOR_UNEVICTABLE
3815 * @flags: control search and eviction behaviour
3817 * i915_gem_gtt_reserve() tries to insert the @node at the exact @offset inside
3818 * the address space (using @size and @color). If the @node does not fit, it
3819 * tries to evict any overlapping nodes from the GTT, including any
3820 * neighbouring nodes if the colors do not match (to ensure guard pages between
3821 * differing domains). See i915_gem_evict_for_node() for the gory details
3822 * on the eviction algorithm. #PIN_NONBLOCK may used to prevent waiting on
3823 * evicting active overlapping objects, and any overlapping node that is pinned
3824 * or marked as unevictable will also result in failure.
3826 * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3827 * asked to wait for eviction and interrupted.
3829 int i915_gem_gtt_reserve(struct i915_address_space
*vm
,
3830 struct drm_mm_node
*node
,
3831 u64 size
, u64 offset
, unsigned long color
,
3837 GEM_BUG_ON(!IS_ALIGNED(size
, I915_GTT_PAGE_SIZE
));
3838 GEM_BUG_ON(!IS_ALIGNED(offset
, I915_GTT_MIN_ALIGNMENT
));
3839 GEM_BUG_ON(range_overflows(offset
, size
, vm
->total
));
3840 GEM_BUG_ON(vm
== &vm
->i915
->mm
.aliasing_ppgtt
->vm
);
3841 GEM_BUG_ON(drm_mm_node_allocated(node
));
3844 node
->start
= offset
;
3845 node
->color
= color
;
3847 err
= drm_mm_reserve_node(&vm
->mm
, node
);
3851 if (flags
& PIN_NOEVICT
)
3854 err
= i915_gem_evict_for_node(vm
, node
, flags
);
3856 err
= drm_mm_reserve_node(&vm
->mm
, node
);
3861 static u64
random_offset(u64 start
, u64 end
, u64 len
, u64 align
)
3865 GEM_BUG_ON(range_overflows(start
, len
, end
));
3866 GEM_BUG_ON(round_up(start
, align
) > round_down(end
- len
, align
));
3868 range
= round_down(end
- len
, align
) - round_up(start
, align
);
3870 if (sizeof(unsigned long) == sizeof(u64
)) {
3871 addr
= get_random_long();
3873 addr
= get_random_int();
3874 if (range
> U32_MAX
) {
3876 addr
|= get_random_int();
3879 div64_u64_rem(addr
, range
, &addr
);
3883 return round_up(start
, align
);
3887 * i915_gem_gtt_insert - insert a node into an address_space (GTT)
3888 * @vm: the &struct i915_address_space
3889 * @node: the &struct drm_mm_node (typically i915_vma.node)
3890 * @size: how much space to allocate inside the GTT,
3891 * must be #I915_GTT_PAGE_SIZE aligned
3892 * @alignment: required alignment of starting offset, may be 0 but
3893 * if specified, this must be a power-of-two and at least
3894 * #I915_GTT_MIN_ALIGNMENT
3895 * @color: color to apply to node
3896 * @start: start of any range restriction inside GTT (0 for all),
3897 * must be #I915_GTT_PAGE_SIZE aligned
3898 * @end: end of any range restriction inside GTT (U64_MAX for all),
3899 * must be #I915_GTT_PAGE_SIZE aligned if not U64_MAX
3900 * @flags: control search and eviction behaviour
3902 * i915_gem_gtt_insert() first searches for an available hole into which
3903 * is can insert the node. The hole address is aligned to @alignment and
3904 * its @size must then fit entirely within the [@start, @end] bounds. The
3905 * nodes on either side of the hole must match @color, or else a guard page
3906 * will be inserted between the two nodes (or the node evicted). If no
3907 * suitable hole is found, first a victim is randomly selected and tested
3908 * for eviction, otherwise then the LRU list of objects within the GTT
3909 * is scanned to find the first set of replacement nodes to create the hole.
3910 * Those old overlapping nodes are evicted from the GTT (and so must be
3911 * rebound before any future use). Any node that is currently pinned cannot
3912 * be evicted (see i915_vma_pin()). Similar if the node's VMA is currently
3913 * active and #PIN_NONBLOCK is specified, that node is also skipped when
3914 * searching for an eviction candidate. See i915_gem_evict_something() for
3915 * the gory details on the eviction algorithm.
3917 * Returns: 0 on success, -ENOSPC if no suitable hole is found, -EINTR if
3918 * asked to wait for eviction and interrupted.
3920 int i915_gem_gtt_insert(struct i915_address_space
*vm
,
3921 struct drm_mm_node
*node
,
3922 u64 size
, u64 alignment
, unsigned long color
,
3923 u64 start
, u64 end
, unsigned int flags
)
3925 enum drm_mm_insert_mode mode
;
3929 lockdep_assert_held(&vm
->i915
->drm
.struct_mutex
);
3931 GEM_BUG_ON(!IS_ALIGNED(size
, I915_GTT_PAGE_SIZE
));
3932 GEM_BUG_ON(alignment
&& !is_power_of_2(alignment
));
3933 GEM_BUG_ON(alignment
&& !IS_ALIGNED(alignment
, I915_GTT_MIN_ALIGNMENT
));
3934 GEM_BUG_ON(start
>= end
);
3935 GEM_BUG_ON(start
> 0 && !IS_ALIGNED(start
, I915_GTT_PAGE_SIZE
));
3936 GEM_BUG_ON(end
< U64_MAX
&& !IS_ALIGNED(end
, I915_GTT_PAGE_SIZE
));
3937 GEM_BUG_ON(vm
== &vm
->i915
->mm
.aliasing_ppgtt
->vm
);
3938 GEM_BUG_ON(drm_mm_node_allocated(node
));
3940 if (unlikely(range_overflows(start
, size
, end
)))
3943 if (unlikely(round_up(start
, alignment
) > round_down(end
- size
, alignment
)))
3946 mode
= DRM_MM_INSERT_BEST
;
3947 if (flags
& PIN_HIGH
)
3948 mode
= DRM_MM_INSERT_HIGHEST
;
3949 if (flags
& PIN_MAPPABLE
)
3950 mode
= DRM_MM_INSERT_LOW
;
3952 /* We only allocate in PAGE_SIZE/GTT_PAGE_SIZE (4096) chunks,
3953 * so we know that we always have a minimum alignment of 4096.
3954 * The drm_mm range manager is optimised to return results
3955 * with zero alignment, so where possible use the optimal
3958 BUILD_BUG_ON(I915_GTT_MIN_ALIGNMENT
> I915_GTT_PAGE_SIZE
);
3959 if (alignment
<= I915_GTT_MIN_ALIGNMENT
)
3962 err
= drm_mm_insert_node_in_range(&vm
->mm
, node
,
3963 size
, alignment
, color
,
3968 if (mode
& DRM_MM_INSERT_ONCE
) {
3969 err
= drm_mm_insert_node_in_range(&vm
->mm
, node
,
3970 size
, alignment
, color
,
3972 DRM_MM_INSERT_BEST
);
3977 if (flags
& PIN_NOEVICT
)
3980 /* No free space, pick a slot at random.
3982 * There is a pathological case here using a GTT shared between
3983 * mmap and GPU (i.e. ggtt/aliasing_ppgtt but not full-ppgtt):
3985 * |<-- 256 MiB aperture -->||<-- 1792 MiB unmappable -->|
3986 * (64k objects) (448k objects)
3988 * Now imagine that the eviction LRU is ordered top-down (just because
3989 * pathology meets real life), and that we need to evict an object to
3990 * make room inside the aperture. The eviction scan then has to walk
3991 * the 448k list before it finds one within range. And now imagine that
3992 * it has to search for a new hole between every byte inside the memcpy,
3993 * for several simultaneous clients.
3995 * On a full-ppgtt system, if we have run out of available space, there
3996 * will be lots and lots of objects in the eviction list! Again,
3997 * searching that LRU list may be slow if we are also applying any
3998 * range restrictions (e.g. restriction to low 4GiB) and so, for
3999 * simplicity and similarilty between different GTT, try the single
4000 * random replacement first.
4002 offset
= random_offset(start
, end
,
4003 size
, alignment
?: I915_GTT_MIN_ALIGNMENT
);
4004 err
= i915_gem_gtt_reserve(vm
, node
, size
, offset
, color
, flags
);
4008 /* Randomly selected placement is pinned, do a search */
4009 err
= i915_gem_evict_something(vm
, size
, alignment
, color
,
4014 return drm_mm_insert_node_in_range(&vm
->mm
, node
,
4015 size
, alignment
, color
,
4016 start
, end
, DRM_MM_INSERT_EVICT
);
4019 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
4020 #include "selftests/mock_gtt.c"
4021 #include "selftests/i915_gem_gtt.c"