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drm/i915: Prevent machine hang from Broxton's vtd w/a and error capture
[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / i915 / i915_gpu_error.c
1 /*
2 * Copyright (c) 2008 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eric Anholt <eric@anholt.net>
25 * Keith Packard <keithp@keithp.com>
26 * Mika Kuoppala <mika.kuoppala@intel.com>
27 *
28 */
29
30 #include <generated/utsrelease.h>
31 #include <linux/stop_machine.h>
32 #include <linux/zlib.h>
33 #include <drm/drm_print.h>
34 #include <linux/ascii85.h>
35
36 #include "i915_gpu_error.h"
37 #include "i915_drv.h"
38
39 static inline const struct intel_engine_cs *
40 engine_lookup(const struct drm_i915_private *i915, unsigned int id)
41 {
42 if (id >= I915_NUM_ENGINES)
43 return NULL;
44
45 return i915->engine[id];
46 }
47
48 static inline const char *
49 __engine_name(const struct intel_engine_cs *engine)
50 {
51 return engine ? engine->name : "";
52 }
53
54 static const char *
55 engine_name(const struct drm_i915_private *i915, unsigned int id)
56 {
57 return __engine_name(engine_lookup(i915, id));
58 }
59
60 static const char *tiling_flag(int tiling)
61 {
62 switch (tiling) {
63 default:
64 case I915_TILING_NONE: return "";
65 case I915_TILING_X: return " X";
66 case I915_TILING_Y: return " Y";
67 }
68 }
69
70 static const char *dirty_flag(int dirty)
71 {
72 return dirty ? " dirty" : "";
73 }
74
75 static const char *purgeable_flag(int purgeable)
76 {
77 return purgeable ? " purgeable" : "";
78 }
79
80 static bool __i915_error_ok(struct drm_i915_error_state_buf *e)
81 {
82
83 if (!e->err && WARN(e->bytes > (e->size - 1), "overflow")) {
84 e->err = -ENOSPC;
85 return false;
86 }
87
88 if (e->bytes == e->size - 1 || e->err)
89 return false;
90
91 return true;
92 }
93
94 static bool __i915_error_seek(struct drm_i915_error_state_buf *e,
95 unsigned len)
96 {
97 if (e->pos + len <= e->start) {
98 e->pos += len;
99 return false;
100 }
101
102 /* First vsnprintf needs to fit in its entirety for memmove */
103 if (len >= e->size) {
104 e->err = -EIO;
105 return false;
106 }
107
108 return true;
109 }
110
111 static void __i915_error_advance(struct drm_i915_error_state_buf *e,
112 unsigned len)
113 {
114 /* If this is first printf in this window, adjust it so that
115 * start position matches start of the buffer
116 */
117
118 if (e->pos < e->start) {
119 const size_t off = e->start - e->pos;
120
121 /* Should not happen but be paranoid */
122 if (off > len || e->bytes) {
123 e->err = -EIO;
124 return;
125 }
126
127 memmove(e->buf, e->buf + off, len - off);
128 e->bytes = len - off;
129 e->pos = e->start;
130 return;
131 }
132
133 e->bytes += len;
134 e->pos += len;
135 }
136
137 __printf(2, 0)
138 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
139 const char *f, va_list args)
140 {
141 unsigned len;
142
143 if (!__i915_error_ok(e))
144 return;
145
146 /* Seek the first printf which is hits start position */
147 if (e->pos < e->start) {
148 va_list tmp;
149
150 va_copy(tmp, args);
151 len = vsnprintf(NULL, 0, f, tmp);
152 va_end(tmp);
153
154 if (!__i915_error_seek(e, len))
155 return;
156 }
157
158 len = vsnprintf(e->buf + e->bytes, e->size - e->bytes, f, args);
159 if (len >= e->size - e->bytes)
160 len = e->size - e->bytes - 1;
161
162 __i915_error_advance(e, len);
163 }
164
165 static void i915_error_puts(struct drm_i915_error_state_buf *e,
166 const char *str)
167 {
168 unsigned len;
169
170 if (!__i915_error_ok(e))
171 return;
172
173 len = strlen(str);
174
175 /* Seek the first printf which is hits start position */
176 if (e->pos < e->start) {
177 if (!__i915_error_seek(e, len))
178 return;
179 }
180
181 if (len >= e->size - e->bytes)
182 len = e->size - e->bytes - 1;
183 memcpy(e->buf + e->bytes, str, len);
184
185 __i915_error_advance(e, len);
186 }
187
188 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
189 #define err_puts(e, s) i915_error_puts(e, s)
190
191 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
192 {
193 i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
194 }
195
196 static inline struct drm_printer
197 i915_error_printer(struct drm_i915_error_state_buf *e)
198 {
199 struct drm_printer p = {
200 .printfn = __i915_printfn_error,
201 .arg = e,
202 };
203 return p;
204 }
205
206 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
207
208 struct compress {
209 struct z_stream_s zstream;
210 void *tmp;
211 };
212
213 static bool compress_init(struct compress *c)
214 {
215 struct z_stream_s *zstream = memset(&c->zstream, 0, sizeof(c->zstream));
216
217 zstream->workspace =
218 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
219 GFP_ATOMIC | __GFP_NOWARN);
220 if (!zstream->workspace)
221 return false;
222
223 if (zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) != Z_OK) {
224 kfree(zstream->workspace);
225 return false;
226 }
227
228 c->tmp = NULL;
229 if (i915_has_memcpy_from_wc())
230 c->tmp = (void *)__get_free_page(GFP_ATOMIC | __GFP_NOWARN);
231
232 return true;
233 }
234
235 static void *compress_next_page(struct drm_i915_error_object *dst)
236 {
237 unsigned long page;
238
239 if (dst->page_count >= dst->num_pages)
240 return ERR_PTR(-ENOSPC);
241
242 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
243 if (!page)
244 return ERR_PTR(-ENOMEM);
245
246 return dst->pages[dst->page_count++] = (void *)page;
247 }
248
249 static int compress_page(struct compress *c,
250 void *src,
251 struct drm_i915_error_object *dst)
252 {
253 struct z_stream_s *zstream = &c->zstream;
254
255 zstream->next_in = src;
256 if (c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
257 zstream->next_in = c->tmp;
258 zstream->avail_in = PAGE_SIZE;
259
260 do {
261 if (zstream->avail_out == 0) {
262 zstream->next_out = compress_next_page(dst);
263 if (IS_ERR(zstream->next_out))
264 return PTR_ERR(zstream->next_out);
265
266 zstream->avail_out = PAGE_SIZE;
267 }
268
269 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
270 return -EIO;
271 } while (zstream->avail_in);
272
273 /* Fallback to uncompressed if we increase size? */
274 if (0 && zstream->total_out > zstream->total_in)
275 return -E2BIG;
276
277 return 0;
278 }
279
280 static int compress_flush(struct compress *c,
281 struct drm_i915_error_object *dst)
282 {
283 struct z_stream_s *zstream = &c->zstream;
284
285 do {
286 switch (zlib_deflate(zstream, Z_FINISH)) {
287 case Z_OK: /* more space requested */
288 zstream->next_out = compress_next_page(dst);
289 if (IS_ERR(zstream->next_out))
290 return PTR_ERR(zstream->next_out);
291
292 zstream->avail_out = PAGE_SIZE;
293 break;
294
295 case Z_STREAM_END:
296 goto end;
297
298 default: /* any error */
299 return -EIO;
300 }
301 } while (1);
302
303 end:
304 memset(zstream->next_out, 0, zstream->avail_out);
305 dst->unused = zstream->avail_out;
306 return 0;
307 }
308
309 static void compress_fini(struct compress *c,
310 struct drm_i915_error_object *dst)
311 {
312 struct z_stream_s *zstream = &c->zstream;
313
314 zlib_deflateEnd(zstream);
315 kfree(zstream->workspace);
316 if (c->tmp)
317 free_page((unsigned long)c->tmp);
318 }
319
320 static void err_compression_marker(struct drm_i915_error_state_buf *m)
321 {
322 err_puts(m, ":");
323 }
324
325 #else
326
327 struct compress {
328 };
329
330 static bool compress_init(struct compress *c)
331 {
332 return true;
333 }
334
335 static int compress_page(struct compress *c,
336 void *src,
337 struct drm_i915_error_object *dst)
338 {
339 unsigned long page;
340 void *ptr;
341
342 page = __get_free_page(GFP_ATOMIC | __GFP_NOWARN);
343 if (!page)
344 return -ENOMEM;
345
346 ptr = (void *)page;
347 if (!i915_memcpy_from_wc(ptr, src, PAGE_SIZE))
348 memcpy(ptr, src, PAGE_SIZE);
349 dst->pages[dst->page_count++] = ptr;
350
351 return 0;
352 }
353
354 static int compress_flush(struct compress *c,
355 struct drm_i915_error_object *dst)
356 {
357 return 0;
358 }
359
360 static void compress_fini(struct compress *c,
361 struct drm_i915_error_object *dst)
362 {
363 }
364
365 static void err_compression_marker(struct drm_i915_error_state_buf *m)
366 {
367 err_puts(m, "~");
368 }
369
370 #endif
371
372 static void print_error_buffers(struct drm_i915_error_state_buf *m,
373 const char *name,
374 struct drm_i915_error_buffer *err,
375 int count)
376 {
377 err_printf(m, "%s [%d]:\n", name, count);
378
379 while (count--) {
380 err_printf(m, " %08x_%08x %8u %02x %02x %02x",
381 upper_32_bits(err->gtt_offset),
382 lower_32_bits(err->gtt_offset),
383 err->size,
384 err->read_domains,
385 err->write_domain,
386 err->wseqno);
387 err_puts(m, tiling_flag(err->tiling));
388 err_puts(m, dirty_flag(err->dirty));
389 err_puts(m, purgeable_flag(err->purgeable));
390 err_puts(m, err->userptr ? " userptr" : "");
391 err_puts(m, err->engine != -1 ? " " : "");
392 err_puts(m, engine_name(m->i915, err->engine));
393 err_puts(m, i915_cache_level_str(m->i915, err->cache_level));
394
395 if (err->name)
396 err_printf(m, " (name: %d)", err->name);
397 if (err->fence_reg != I915_FENCE_REG_NONE)
398 err_printf(m, " (fence: %d)", err->fence_reg);
399
400 err_puts(m, "\n");
401 err++;
402 }
403 }
404
405 static void error_print_instdone(struct drm_i915_error_state_buf *m,
406 const struct drm_i915_error_engine *ee)
407 {
408 int slice;
409 int subslice;
410
411 err_printf(m, " INSTDONE: 0x%08x\n",
412 ee->instdone.instdone);
413
414 if (ee->engine_id != RCS || INTEL_GEN(m->i915) <= 3)
415 return;
416
417 err_printf(m, " SC_INSTDONE: 0x%08x\n",
418 ee->instdone.slice_common);
419
420 if (INTEL_GEN(m->i915) <= 6)
421 return;
422
423 for_each_instdone_slice_subslice(m->i915, slice, subslice)
424 err_printf(m, " SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
425 slice, subslice,
426 ee->instdone.sampler[slice][subslice]);
427
428 for_each_instdone_slice_subslice(m->i915, slice, subslice)
429 err_printf(m, " ROW_INSTDONE[%d][%d]: 0x%08x\n",
430 slice, subslice,
431 ee->instdone.row[slice][subslice]);
432 }
433
434 static const char *bannable(const struct drm_i915_error_context *ctx)
435 {
436 return ctx->bannable ? "" : " (unbannable)";
437 }
438
439 static void error_print_request(struct drm_i915_error_state_buf *m,
440 const char *prefix,
441 const struct drm_i915_error_request *erq,
442 const unsigned long epoch)
443 {
444 if (!erq->seqno)
445 return;
446
447 err_printf(m, "%s pid %d, ban score %d, seqno %8x:%08x, prio %d, emitted %dms, start %08x, head %08x, tail %08x\n",
448 prefix, erq->pid, erq->ban_score,
449 erq->context, erq->seqno, erq->sched_attr.priority,
450 jiffies_to_msecs(erq->jiffies - epoch),
451 erq->start, erq->head, erq->tail);
452 }
453
454 static void error_print_context(struct drm_i915_error_state_buf *m,
455 const char *header,
456 const struct drm_i915_error_context *ctx)
457 {
458 err_printf(m, "%s%s[%d] user_handle %d hw_id %d, prio %d, ban score %d%s guilty %d active %d\n",
459 header, ctx->comm, ctx->pid, ctx->handle, ctx->hw_id,
460 ctx->sched_attr.priority, ctx->ban_score, bannable(ctx),
461 ctx->guilty, ctx->active);
462 }
463
464 static void error_print_engine(struct drm_i915_error_state_buf *m,
465 const struct drm_i915_error_engine *ee,
466 const unsigned long epoch)
467 {
468 int n;
469
470 err_printf(m, "%s command stream:\n",
471 engine_name(m->i915, ee->engine_id));
472 err_printf(m, " IDLE?: %s\n", yesno(ee->idle));
473 err_printf(m, " START: 0x%08x\n", ee->start);
474 err_printf(m, " HEAD: 0x%08x [0x%08x]\n", ee->head, ee->rq_head);
475 err_printf(m, " TAIL: 0x%08x [0x%08x, 0x%08x]\n",
476 ee->tail, ee->rq_post, ee->rq_tail);
477 err_printf(m, " CTL: 0x%08x\n", ee->ctl);
478 err_printf(m, " MODE: 0x%08x\n", ee->mode);
479 err_printf(m, " HWS: 0x%08x\n", ee->hws);
480 err_printf(m, " ACTHD: 0x%08x %08x\n",
481 (u32)(ee->acthd>>32), (u32)ee->acthd);
482 err_printf(m, " IPEIR: 0x%08x\n", ee->ipeir);
483 err_printf(m, " IPEHR: 0x%08x\n", ee->ipehr);
484
485 error_print_instdone(m, ee);
486
487 if (ee->batchbuffer) {
488 u64 start = ee->batchbuffer->gtt_offset;
489 u64 end = start + ee->batchbuffer->gtt_size;
490
491 err_printf(m, " batch: [0x%08x_%08x, 0x%08x_%08x]\n",
492 upper_32_bits(start), lower_32_bits(start),
493 upper_32_bits(end), lower_32_bits(end));
494 }
495 if (INTEL_GEN(m->i915) >= 4) {
496 err_printf(m, " BBADDR: 0x%08x_%08x\n",
497 (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
498 err_printf(m, " BB_STATE: 0x%08x\n", ee->bbstate);
499 err_printf(m, " INSTPS: 0x%08x\n", ee->instps);
500 }
501 err_printf(m, " INSTPM: 0x%08x\n", ee->instpm);
502 err_printf(m, " FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
503 lower_32_bits(ee->faddr));
504 if (INTEL_GEN(m->i915) >= 6) {
505 err_printf(m, " RC PSMI: 0x%08x\n", ee->rc_psmi);
506 err_printf(m, " FAULT_REG: 0x%08x\n", ee->fault_reg);
507 err_printf(m, " SYNC_0: 0x%08x\n",
508 ee->semaphore_mboxes[0]);
509 err_printf(m, " SYNC_1: 0x%08x\n",
510 ee->semaphore_mboxes[1]);
511 if (HAS_VEBOX(m->i915))
512 err_printf(m, " SYNC_2: 0x%08x\n",
513 ee->semaphore_mboxes[2]);
514 }
515 if (HAS_PPGTT(m->i915)) {
516 err_printf(m, " GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
517
518 if (INTEL_GEN(m->i915) >= 8) {
519 int i;
520 for (i = 0; i < 4; i++)
521 err_printf(m, " PDP%d: 0x%016llx\n",
522 i, ee->vm_info.pdp[i]);
523 } else {
524 err_printf(m, " PP_DIR_BASE: 0x%08x\n",
525 ee->vm_info.pp_dir_base);
526 }
527 }
528 err_printf(m, " seqno: 0x%08x\n", ee->seqno);
529 err_printf(m, " last_seqno: 0x%08x\n", ee->last_seqno);
530 err_printf(m, " waiting: %s\n", yesno(ee->waiting));
531 err_printf(m, " ring->head: 0x%08x\n", ee->cpu_ring_head);
532 err_printf(m, " ring->tail: 0x%08x\n", ee->cpu_ring_tail);
533 err_printf(m, " hangcheck stall: %s\n", yesno(ee->hangcheck_stalled));
534 err_printf(m, " hangcheck action: %s\n",
535 hangcheck_action_to_str(ee->hangcheck_action));
536 err_printf(m, " hangcheck action timestamp: %dms (%lu%s)\n",
537 jiffies_to_msecs(ee->hangcheck_timestamp - epoch),
538 ee->hangcheck_timestamp,
539 ee->hangcheck_timestamp == epoch ? "; epoch" : "");
540 err_printf(m, " engine reset count: %u\n", ee->reset_count);
541
542 for (n = 0; n < ee->num_ports; n++) {
543 err_printf(m, " ELSP[%d]:", n);
544 error_print_request(m, " ", &ee->execlist[n], epoch);
545 }
546
547 error_print_context(m, " Active context: ", &ee->context);
548 }
549
550 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
551 {
552 va_list args;
553
554 va_start(args, f);
555 i915_error_vprintf(e, f, args);
556 va_end(args);
557 }
558
559 static void print_error_obj(struct drm_i915_error_state_buf *m,
560 struct intel_engine_cs *engine,
561 const char *name,
562 struct drm_i915_error_object *obj)
563 {
564 char out[ASCII85_BUFSZ];
565 int page;
566
567 if (!obj)
568 return;
569
570 if (name) {
571 err_printf(m, "%s --- %s = 0x%08x %08x\n",
572 engine ? engine->name : "global", name,
573 upper_32_bits(obj->gtt_offset),
574 lower_32_bits(obj->gtt_offset));
575 }
576
577 err_compression_marker(m);
578 for (page = 0; page < obj->page_count; page++) {
579 int i, len;
580
581 len = PAGE_SIZE;
582 if (page == obj->page_count - 1)
583 len -= obj->unused;
584 len = ascii85_encode_len(len);
585
586 for (i = 0; i < len; i++)
587 err_puts(m, ascii85_encode(obj->pages[page][i], out));
588 }
589 err_puts(m, "\n");
590 }
591
592 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
593 const struct intel_device_info *info,
594 const struct intel_driver_caps *caps)
595 {
596 struct drm_printer p = i915_error_printer(m);
597
598 intel_device_info_dump_flags(info, &p);
599 intel_driver_caps_print(caps, &p);
600 intel_device_info_dump_topology(&info->sseu, &p);
601 }
602
603 static void err_print_params(struct drm_i915_error_state_buf *m,
604 const struct i915_params *params)
605 {
606 struct drm_printer p = i915_error_printer(m);
607
608 i915_params_dump(params, &p);
609 }
610
611 static void err_print_pciid(struct drm_i915_error_state_buf *m,
612 struct drm_i915_private *i915)
613 {
614 struct pci_dev *pdev = i915->drm.pdev;
615
616 err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
617 err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
618 err_printf(m, "PCI Subsystem: %04x:%04x\n",
619 pdev->subsystem_vendor,
620 pdev->subsystem_device);
621 }
622
623 static void err_print_uc(struct drm_i915_error_state_buf *m,
624 const struct i915_error_uc *error_uc)
625 {
626 struct drm_printer p = i915_error_printer(m);
627 const struct i915_gpu_state *error =
628 container_of(error_uc, typeof(*error), uc);
629
630 if (!error->device_info.has_guc)
631 return;
632
633 intel_uc_fw_dump(&error_uc->guc_fw, &p);
634 intel_uc_fw_dump(&error_uc->huc_fw, &p);
635 print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log);
636 }
637
638 int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
639 const struct i915_gpu_state *error)
640 {
641 struct drm_i915_private *dev_priv = m->i915;
642 struct drm_i915_error_object *obj;
643 struct timespec64 ts;
644 int i, j;
645
646 if (!error) {
647 err_printf(m, "No error state collected\n");
648 return 0;
649 }
650
651 if (IS_ERR(error))
652 return PTR_ERR(error);
653
654 if (*error->error_msg)
655 err_printf(m, "%s\n", error->error_msg);
656 err_printf(m, "Kernel: " UTS_RELEASE "\n");
657 ts = ktime_to_timespec64(error->time);
658 err_printf(m, "Time: %lld s %ld us\n",
659 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
660 ts = ktime_to_timespec64(error->boottime);
661 err_printf(m, "Boottime: %lld s %ld us\n",
662 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
663 ts = ktime_to_timespec64(error->uptime);
664 err_printf(m, "Uptime: %lld s %ld us\n",
665 (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
666 err_printf(m, "Epoch: %lu jiffies (%u HZ)\n", error->epoch, HZ);
667 err_printf(m, "Capture: %lu jiffies; %d ms ago, %d ms after epoch\n",
668 error->capture,
669 jiffies_to_msecs(jiffies - error->capture),
670 jiffies_to_msecs(error->capture - error->epoch));
671
672 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
673 if (error->engine[i].hangcheck_stalled &&
674 error->engine[i].context.pid) {
675 err_printf(m, "Active process (on ring %s): %s [%d], score %d%s\n",
676 engine_name(m->i915, i),
677 error->engine[i].context.comm,
678 error->engine[i].context.pid,
679 error->engine[i].context.ban_score,
680 bannable(&error->engine[i].context));
681 }
682 }
683 err_printf(m, "Reset count: %u\n", error->reset_count);
684 err_printf(m, "Suspend count: %u\n", error->suspend_count);
685 err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
686 err_print_pciid(m, error->i915);
687
688 err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
689
690 if (HAS_CSR(dev_priv)) {
691 struct intel_csr *csr = &dev_priv->csr;
692
693 err_printf(m, "DMC loaded: %s\n",
694 yesno(csr->dmc_payload != NULL));
695 err_printf(m, "DMC fw version: %d.%d\n",
696 CSR_VERSION_MAJOR(csr->version),
697 CSR_VERSION_MINOR(csr->version));
698 }
699
700 err_printf(m, "GT awake: %s\n", yesno(error->awake));
701 err_printf(m, "RPM wakelock: %s\n", yesno(error->wakelock));
702 err_printf(m, "PM suspended: %s\n", yesno(error->suspended));
703 err_printf(m, "EIR: 0x%08x\n", error->eir);
704 err_printf(m, "IER: 0x%08x\n", error->ier);
705 for (i = 0; i < error->ngtier; i++)
706 err_printf(m, "GTIER[%d]: 0x%08x\n", i, error->gtier[i]);
707 err_printf(m, "PGTBL_ER: 0x%08x\n", error->pgtbl_er);
708 err_printf(m, "FORCEWAKE: 0x%08x\n", error->forcewake);
709 err_printf(m, "DERRMR: 0x%08x\n", error->derrmr);
710 err_printf(m, "CCID: 0x%08x\n", error->ccid);
711 err_printf(m, "Missed interrupts: 0x%08lx\n", dev_priv->gpu_error.missed_irq_rings);
712
713 for (i = 0; i < error->nfence; i++)
714 err_printf(m, " fence[%d] = %08llx\n", i, error->fence[i]);
715
716 if (INTEL_GEN(dev_priv) >= 6) {
717 err_printf(m, "ERROR: 0x%08x\n", error->error);
718
719 if (INTEL_GEN(dev_priv) >= 8)
720 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
721 error->fault_data1, error->fault_data0);
722
723 err_printf(m, "DONE_REG: 0x%08x\n", error->done_reg);
724 }
725
726 if (IS_GEN7(dev_priv))
727 err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
728
729 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
730 if (error->engine[i].engine_id != -1)
731 error_print_engine(m, &error->engine[i], error->epoch);
732 }
733
734 for (i = 0; i < ARRAY_SIZE(error->active_vm); i++) {
735 char buf[128];
736 int len, first = 1;
737
738 if (!error->active_vm[i])
739 break;
740
741 len = scnprintf(buf, sizeof(buf), "Active (");
742 for (j = 0; j < ARRAY_SIZE(error->engine); j++) {
743 if (error->engine[j].vm != error->active_vm[i])
744 continue;
745
746 len += scnprintf(buf + len, sizeof(buf), "%s%s",
747 first ? "" : ", ",
748 dev_priv->engine[j]->name);
749 first = 0;
750 }
751 scnprintf(buf + len, sizeof(buf), ")");
752 print_error_buffers(m, buf,
753 error->active_bo[i],
754 error->active_bo_count[i]);
755 }
756
757 print_error_buffers(m, "Pinned (global)",
758 error->pinned_bo,
759 error->pinned_bo_count);
760
761 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
762 const struct drm_i915_error_engine *ee = &error->engine[i];
763
764 obj = ee->batchbuffer;
765 if (obj) {
766 err_puts(m, dev_priv->engine[i]->name);
767 if (ee->context.pid)
768 err_printf(m, " (submitted by %s [%d], ctx %d [%d], score %d%s)",
769 ee->context.comm,
770 ee->context.pid,
771 ee->context.handle,
772 ee->context.hw_id,
773 ee->context.ban_score,
774 bannable(&ee->context));
775 err_printf(m, " --- gtt_offset = 0x%08x %08x\n",
776 upper_32_bits(obj->gtt_offset),
777 lower_32_bits(obj->gtt_offset));
778 print_error_obj(m, dev_priv->engine[i], NULL, obj);
779 }
780
781 for (j = 0; j < ee->user_bo_count; j++)
782 print_error_obj(m, dev_priv->engine[i],
783 "user", ee->user_bo[j]);
784
785 if (ee->num_requests) {
786 err_printf(m, "%s --- %d requests\n",
787 dev_priv->engine[i]->name,
788 ee->num_requests);
789 for (j = 0; j < ee->num_requests; j++)
790 error_print_request(m, " ",
791 &ee->requests[j],
792 error->epoch);
793 }
794
795 if (IS_ERR(ee->waiters)) {
796 err_printf(m, "%s --- ? waiters [unable to acquire spinlock]\n",
797 dev_priv->engine[i]->name);
798 } else if (ee->num_waiters) {
799 err_printf(m, "%s --- %d waiters\n",
800 dev_priv->engine[i]->name,
801 ee->num_waiters);
802 for (j = 0; j < ee->num_waiters; j++) {
803 err_printf(m, " seqno 0x%08x for %s [%d]\n",
804 ee->waiters[j].seqno,
805 ee->waiters[j].comm,
806 ee->waiters[j].pid);
807 }
808 }
809
810 print_error_obj(m, dev_priv->engine[i],
811 "ringbuffer", ee->ringbuffer);
812
813 print_error_obj(m, dev_priv->engine[i],
814 "HW Status", ee->hws_page);
815
816 print_error_obj(m, dev_priv->engine[i],
817 "HW context", ee->ctx);
818
819 print_error_obj(m, dev_priv->engine[i],
820 "WA context", ee->wa_ctx);
821
822 print_error_obj(m, dev_priv->engine[i],
823 "WA batchbuffer", ee->wa_batchbuffer);
824
825 print_error_obj(m, dev_priv->engine[i],
826 "NULL context", ee->default_state);
827 }
828
829 if (error->overlay)
830 intel_overlay_print_error_state(m, error->overlay);
831
832 if (error->display)
833 intel_display_print_error_state(m, error->display);
834
835 err_print_capabilities(m, &error->device_info, &error->driver_caps);
836 err_print_params(m, &error->params);
837 err_print_uc(m, &error->uc);
838
839 if (m->bytes == 0 && m->err)
840 return m->err;
841
842 return 0;
843 }
844
845 int i915_error_state_buf_init(struct drm_i915_error_state_buf *ebuf,
846 struct drm_i915_private *i915,
847 size_t count, loff_t pos)
848 {
849 memset(ebuf, 0, sizeof(*ebuf));
850 ebuf->i915 = i915;
851
852 /* We need to have enough room to store any i915_error_state printf
853 * so that we can move it to start position.
854 */
855 ebuf->size = count + 1 > PAGE_SIZE ? count + 1 : PAGE_SIZE;
856 ebuf->buf = kmalloc(ebuf->size,
857 GFP_KERNEL | __GFP_NORETRY | __GFP_NOWARN);
858
859 if (ebuf->buf == NULL) {
860 ebuf->size = PAGE_SIZE;
861 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
862 }
863
864 if (ebuf->buf == NULL) {
865 ebuf->size = 128;
866 ebuf->buf = kmalloc(ebuf->size, GFP_KERNEL);
867 }
868
869 if (ebuf->buf == NULL)
870 return -ENOMEM;
871
872 ebuf->start = pos;
873
874 return 0;
875 }
876
877 static void i915_error_object_free(struct drm_i915_error_object *obj)
878 {
879 int page;
880
881 if (obj == NULL)
882 return;
883
884 for (page = 0; page < obj->page_count; page++)
885 free_page((unsigned long)obj->pages[page]);
886
887 kfree(obj);
888 }
889
890 static __always_inline void free_param(const char *type, void *x)
891 {
892 if (!__builtin_strcmp(type, "char *"))
893 kfree(*(void **)x);
894 }
895
896 static void cleanup_params(struct i915_gpu_state *error)
897 {
898 #define FREE(T, x, ...) free_param(#T, &error->params.x);
899 I915_PARAMS_FOR_EACH(FREE);
900 #undef FREE
901 }
902
903 static void cleanup_uc_state(struct i915_gpu_state *error)
904 {
905 struct i915_error_uc *error_uc = &error->uc;
906
907 kfree(error_uc->guc_fw.path);
908 kfree(error_uc->huc_fw.path);
909 i915_error_object_free(error_uc->guc_log);
910 }
911
912 void __i915_gpu_state_free(struct kref *error_ref)
913 {
914 struct i915_gpu_state *error =
915 container_of(error_ref, typeof(*error), ref);
916 long i, j;
917
918 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
919 struct drm_i915_error_engine *ee = &error->engine[i];
920
921 for (j = 0; j < ee->user_bo_count; j++)
922 i915_error_object_free(ee->user_bo[j]);
923 kfree(ee->user_bo);
924
925 i915_error_object_free(ee->batchbuffer);
926 i915_error_object_free(ee->wa_batchbuffer);
927 i915_error_object_free(ee->ringbuffer);
928 i915_error_object_free(ee->hws_page);
929 i915_error_object_free(ee->ctx);
930 i915_error_object_free(ee->wa_ctx);
931
932 kfree(ee->requests);
933 if (!IS_ERR_OR_NULL(ee->waiters))
934 kfree(ee->waiters);
935 }
936
937 for (i = 0; i < ARRAY_SIZE(error->active_bo); i++)
938 kfree(error->active_bo[i]);
939 kfree(error->pinned_bo);
940
941 kfree(error->overlay);
942 kfree(error->display);
943
944 cleanup_params(error);
945 cleanup_uc_state(error);
946
947 kfree(error);
948 }
949
950 static struct drm_i915_error_object *
951 i915_error_object_create(struct drm_i915_private *i915,
952 struct i915_vma *vma)
953 {
954 struct i915_ggtt *ggtt = &i915->ggtt;
955 const u64 slot = ggtt->error_capture.start;
956 struct drm_i915_error_object *dst;
957 struct compress compress;
958 unsigned long num_pages;
959 struct sgt_iter iter;
960 dma_addr_t dma;
961 int ret;
962
963 if (!vma)
964 return NULL;
965
966 num_pages = min_t(u64, vma->size, vma->obj->base.size) >> PAGE_SHIFT;
967 num_pages = DIV_ROUND_UP(10 * num_pages, 8); /* worstcase zlib growth */
968 dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *),
969 GFP_ATOMIC | __GFP_NOWARN);
970 if (!dst)
971 return NULL;
972
973 dst->gtt_offset = vma->node.start;
974 dst->gtt_size = vma->node.size;
975 dst->num_pages = num_pages;
976 dst->page_count = 0;
977 dst->unused = 0;
978
979 if (!compress_init(&compress)) {
980 kfree(dst);
981 return NULL;
982 }
983
984 ret = -EINVAL;
985 for_each_sgt_dma(dma, iter, vma->pages) {
986 void __iomem *s;
987
988 ggtt->vm.insert_page(&ggtt->vm, dma, slot, I915_CACHE_NONE, 0);
989
990 s = io_mapping_map_atomic_wc(&ggtt->iomap, slot);
991 ret = compress_page(&compress, (void __force *)s, dst);
992 io_mapping_unmap_atomic(s);
993 if (ret)
994 break;
995 }
996
997 if (ret || compress_flush(&compress, dst)) {
998 while (dst->page_count--)
999 free_page((unsigned long)dst->pages[dst->page_count]);
1000 kfree(dst);
1001 dst = NULL;
1002 }
1003
1004 compress_fini(&compress, dst);
1005 return dst;
1006 }
1007
1008 /* The error capture is special as tries to run underneath the normal
1009 * locking rules - so we use the raw version of the i915_gem_active lookup.
1010 */
1011 static inline uint32_t
1012 __active_get_seqno(struct i915_gem_active *active)
1013 {
1014 struct i915_request *request;
1015
1016 request = __i915_gem_active_peek(active);
1017 return request ? request->global_seqno : 0;
1018 }
1019
1020 static inline int
1021 __active_get_engine_id(struct i915_gem_active *active)
1022 {
1023 struct i915_request *request;
1024
1025 request = __i915_gem_active_peek(active);
1026 return request ? request->engine->id : -1;
1027 }
1028
1029 static void capture_bo(struct drm_i915_error_buffer *err,
1030 struct i915_vma *vma)
1031 {
1032 struct drm_i915_gem_object *obj = vma->obj;
1033
1034 err->size = obj->base.size;
1035 err->name = obj->base.name;
1036
1037 err->wseqno = __active_get_seqno(&obj->frontbuffer_write);
1038 err->engine = __active_get_engine_id(&obj->frontbuffer_write);
1039
1040 err->gtt_offset = vma->node.start;
1041 err->read_domains = obj->read_domains;
1042 err->write_domain = obj->write_domain;
1043 err->fence_reg = vma->fence ? vma->fence->id : -1;
1044 err->tiling = i915_gem_object_get_tiling(obj);
1045 err->dirty = obj->mm.dirty;
1046 err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
1047 err->userptr = obj->userptr.mm != NULL;
1048 err->cache_level = obj->cache_level;
1049 }
1050
1051 static u32 capture_error_bo(struct drm_i915_error_buffer *err,
1052 int count, struct list_head *head,
1053 bool pinned_only)
1054 {
1055 struct i915_vma *vma;
1056 int i = 0;
1057
1058 list_for_each_entry(vma, head, vm_link) {
1059 if (!vma->obj)
1060 continue;
1061
1062 if (pinned_only && !i915_vma_is_pinned(vma))
1063 continue;
1064
1065 capture_bo(err++, vma);
1066 if (++i == count)
1067 break;
1068 }
1069
1070 return i;
1071 }
1072
1073 /* Generate a semi-unique error code. The code is not meant to have meaning, The
1074 * code's only purpose is to try to prevent false duplicated bug reports by
1075 * grossly estimating a GPU error state.
1076 *
1077 * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1078 * the hang if we could strip the GTT offset information from it.
1079 *
1080 * It's only a small step better than a random number in its current form.
1081 */
1082 static uint32_t i915_error_generate_code(struct drm_i915_private *dev_priv,
1083 struct i915_gpu_state *error,
1084 int *engine_id)
1085 {
1086 uint32_t error_code = 0;
1087 int i;
1088
1089 /* IPEHR would be an ideal way to detect errors, as it's the gross
1090 * measure of "the command that hung." However, has some very common
1091 * synchronization commands which almost always appear in the case
1092 * strictly a client bug. Use instdone to differentiate those some.
1093 */
1094 for (i = 0; i < I915_NUM_ENGINES; i++) {
1095 if (error->engine[i].hangcheck_stalled) {
1096 if (engine_id)
1097 *engine_id = i;
1098
1099 return error->engine[i].ipehr ^
1100 error->engine[i].instdone.instdone;
1101 }
1102 }
1103
1104 return error_code;
1105 }
1106
1107 static void gem_record_fences(struct i915_gpu_state *error)
1108 {
1109 struct drm_i915_private *dev_priv = error->i915;
1110 int i;
1111
1112 if (INTEL_GEN(dev_priv) >= 6) {
1113 for (i = 0; i < dev_priv->num_fence_regs; i++)
1114 error->fence[i] = I915_READ64(FENCE_REG_GEN6_LO(i));
1115 } else if (INTEL_GEN(dev_priv) >= 4) {
1116 for (i = 0; i < dev_priv->num_fence_regs; i++)
1117 error->fence[i] = I915_READ64(FENCE_REG_965_LO(i));
1118 } else {
1119 for (i = 0; i < dev_priv->num_fence_regs; i++)
1120 error->fence[i] = I915_READ(FENCE_REG(i));
1121 }
1122 error->nfence = i;
1123 }
1124
1125 static void gen6_record_semaphore_state(struct intel_engine_cs *engine,
1126 struct drm_i915_error_engine *ee)
1127 {
1128 struct drm_i915_private *dev_priv = engine->i915;
1129
1130 ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base));
1131 ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base));
1132 if (HAS_VEBOX(dev_priv))
1133 ee->semaphore_mboxes[2] =
1134 I915_READ(RING_SYNC_2(engine->mmio_base));
1135 }
1136
1137 static void error_record_engine_waiters(struct intel_engine_cs *engine,
1138 struct drm_i915_error_engine *ee)
1139 {
1140 struct intel_breadcrumbs *b = &engine->breadcrumbs;
1141 struct drm_i915_error_waiter *waiter;
1142 struct rb_node *rb;
1143 int count;
1144
1145 ee->num_waiters = 0;
1146 ee->waiters = NULL;
1147
1148 if (RB_EMPTY_ROOT(&b->waiters))
1149 return;
1150
1151 if (!spin_trylock_irq(&b->rb_lock)) {
1152 ee->waiters = ERR_PTR(-EDEADLK);
1153 return;
1154 }
1155
1156 count = 0;
1157 for (rb = rb_first(&b->waiters); rb != NULL; rb = rb_next(rb))
1158 count++;
1159 spin_unlock_irq(&b->rb_lock);
1160
1161 waiter = NULL;
1162 if (count)
1163 waiter = kmalloc_array(count,
1164 sizeof(struct drm_i915_error_waiter),
1165 GFP_ATOMIC);
1166 if (!waiter)
1167 return;
1168
1169 if (!spin_trylock_irq(&b->rb_lock)) {
1170 kfree(waiter);
1171 ee->waiters = ERR_PTR(-EDEADLK);
1172 return;
1173 }
1174
1175 ee->waiters = waiter;
1176 for (rb = rb_first(&b->waiters); rb; rb = rb_next(rb)) {
1177 struct intel_wait *w = rb_entry(rb, typeof(*w), node);
1178
1179 strcpy(waiter->comm, w->tsk->comm);
1180 waiter->pid = w->tsk->pid;
1181 waiter->seqno = w->seqno;
1182 waiter++;
1183
1184 if (++ee->num_waiters == count)
1185 break;
1186 }
1187 spin_unlock_irq(&b->rb_lock);
1188 }
1189
1190 static void error_record_engine_registers(struct i915_gpu_state *error,
1191 struct intel_engine_cs *engine,
1192 struct drm_i915_error_engine *ee)
1193 {
1194 struct drm_i915_private *dev_priv = engine->i915;
1195
1196 if (INTEL_GEN(dev_priv) >= 6) {
1197 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base));
1198 if (INTEL_GEN(dev_priv) >= 8) {
1199 ee->fault_reg = I915_READ(GEN8_RING_FAULT_REG);
1200 } else {
1201 gen6_record_semaphore_state(engine, ee);
1202 ee->fault_reg = I915_READ(RING_FAULT_REG(engine));
1203 }
1204 }
1205
1206 if (INTEL_GEN(dev_priv) >= 4) {
1207 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base));
1208 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base));
1209 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base));
1210 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base));
1211 ee->bbaddr = I915_READ(RING_BBADDR(engine->mmio_base));
1212 if (INTEL_GEN(dev_priv) >= 8) {
1213 ee->faddr |= (u64) I915_READ(RING_DMA_FADD_UDW(engine->mmio_base)) << 32;
1214 ee->bbaddr |= (u64) I915_READ(RING_BBADDR_UDW(engine->mmio_base)) << 32;
1215 }
1216 ee->bbstate = I915_READ(RING_BBSTATE(engine->mmio_base));
1217 } else {
1218 ee->faddr = I915_READ(DMA_FADD_I8XX);
1219 ee->ipeir = I915_READ(IPEIR);
1220 ee->ipehr = I915_READ(IPEHR);
1221 }
1222
1223 intel_engine_get_instdone(engine, &ee->instdone);
1224
1225 ee->waiting = intel_engine_has_waiter(engine);
1226 ee->instpm = I915_READ(RING_INSTPM(engine->mmio_base));
1227 ee->acthd = intel_engine_get_active_head(engine);
1228 ee->seqno = intel_engine_get_seqno(engine);
1229 ee->last_seqno = intel_engine_last_submit(engine);
1230 ee->start = I915_READ_START(engine);
1231 ee->head = I915_READ_HEAD(engine);
1232 ee->tail = I915_READ_TAIL(engine);
1233 ee->ctl = I915_READ_CTL(engine);
1234 if (INTEL_GEN(dev_priv) > 2)
1235 ee->mode = I915_READ_MODE(engine);
1236
1237 if (!HWS_NEEDS_PHYSICAL(dev_priv)) {
1238 i915_reg_t mmio;
1239
1240 if (IS_GEN7(dev_priv)) {
1241 switch (engine->id) {
1242 default:
1243 case RCS:
1244 mmio = RENDER_HWS_PGA_GEN7;
1245 break;
1246 case BCS:
1247 mmio = BLT_HWS_PGA_GEN7;
1248 break;
1249 case VCS:
1250 mmio = BSD_HWS_PGA_GEN7;
1251 break;
1252 case VECS:
1253 mmio = VEBOX_HWS_PGA_GEN7;
1254 break;
1255 }
1256 } else if (IS_GEN6(engine->i915)) {
1257 mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1258 } else {
1259 /* XXX: gen8 returns to sanity */
1260 mmio = RING_HWS_PGA(engine->mmio_base);
1261 }
1262
1263 ee->hws = I915_READ(mmio);
1264 }
1265
1266 ee->idle = intel_engine_is_idle(engine);
1267 ee->hangcheck_timestamp = engine->hangcheck.action_timestamp;
1268 ee->hangcheck_action = engine->hangcheck.action;
1269 ee->hangcheck_stalled = engine->hangcheck.stalled;
1270 ee->reset_count = i915_reset_engine_count(&dev_priv->gpu_error,
1271 engine);
1272
1273 if (HAS_PPGTT(dev_priv)) {
1274 int i;
1275
1276 ee->vm_info.gfx_mode = I915_READ(RING_MODE_GEN7(engine));
1277
1278 if (IS_GEN6(dev_priv))
1279 ee->vm_info.pp_dir_base =
1280 I915_READ(RING_PP_DIR_BASE_READ(engine));
1281 else if (IS_GEN7(dev_priv))
1282 ee->vm_info.pp_dir_base =
1283 I915_READ(RING_PP_DIR_BASE(engine));
1284 else if (INTEL_GEN(dev_priv) >= 8)
1285 for (i = 0; i < 4; i++) {
1286 ee->vm_info.pdp[i] =
1287 I915_READ(GEN8_RING_PDP_UDW(engine, i));
1288 ee->vm_info.pdp[i] <<= 32;
1289 ee->vm_info.pdp[i] |=
1290 I915_READ(GEN8_RING_PDP_LDW(engine, i));
1291 }
1292 }
1293 }
1294
1295 static void record_request(struct i915_request *request,
1296 struct drm_i915_error_request *erq)
1297 {
1298 struct i915_gem_context *ctx = request->gem_context;
1299
1300 erq->context = ctx->hw_id;
1301 erq->sched_attr = request->sched.attr;
1302 erq->ban_score = atomic_read(&ctx->ban_score);
1303 erq->seqno = request->global_seqno;
1304 erq->jiffies = request->emitted_jiffies;
1305 erq->start = i915_ggtt_offset(request->ring->vma);
1306 erq->head = request->head;
1307 erq->tail = request->tail;
1308
1309 rcu_read_lock();
1310 erq->pid = ctx->pid ? pid_nr(ctx->pid) : 0;
1311 rcu_read_unlock();
1312 }
1313
1314 static void engine_record_requests(struct intel_engine_cs *engine,
1315 struct i915_request *first,
1316 struct drm_i915_error_engine *ee)
1317 {
1318 struct i915_request *request;
1319 int count;
1320
1321 count = 0;
1322 request = first;
1323 list_for_each_entry_from(request, &engine->timeline.requests, link)
1324 count++;
1325 if (!count)
1326 return;
1327
1328 ee->requests = kcalloc(count, sizeof(*ee->requests), GFP_ATOMIC);
1329 if (!ee->requests)
1330 return;
1331
1332 ee->num_requests = count;
1333
1334 count = 0;
1335 request = first;
1336 list_for_each_entry_from(request, &engine->timeline.requests, link) {
1337 if (count >= ee->num_requests) {
1338 /*
1339 * If the ring request list was changed in
1340 * between the point where the error request
1341 * list was created and dimensioned and this
1342 * point then just exit early to avoid crashes.
1343 *
1344 * We don't need to communicate that the
1345 * request list changed state during error
1346 * state capture and that the error state is
1347 * slightly incorrect as a consequence since we
1348 * are typically only interested in the request
1349 * list state at the point of error state
1350 * capture, not in any changes happening during
1351 * the capture.
1352 */
1353 break;
1354 }
1355
1356 record_request(request, &ee->requests[count++]);
1357 }
1358 ee->num_requests = count;
1359 }
1360
1361 static void error_record_engine_execlists(struct intel_engine_cs *engine,
1362 struct drm_i915_error_engine *ee)
1363 {
1364 const struct intel_engine_execlists * const execlists = &engine->execlists;
1365 unsigned int n;
1366
1367 for (n = 0; n < execlists_num_ports(execlists); n++) {
1368 struct i915_request *rq = port_request(&execlists->port[n]);
1369
1370 if (!rq)
1371 break;
1372
1373 record_request(rq, &ee->execlist[n]);
1374 }
1375
1376 ee->num_ports = n;
1377 }
1378
1379 static void record_context(struct drm_i915_error_context *e,
1380 struct i915_gem_context *ctx)
1381 {
1382 if (ctx->pid) {
1383 struct task_struct *task;
1384
1385 rcu_read_lock();
1386 task = pid_task(ctx->pid, PIDTYPE_PID);
1387 if (task) {
1388 strcpy(e->comm, task->comm);
1389 e->pid = task->pid;
1390 }
1391 rcu_read_unlock();
1392 }
1393
1394 e->handle = ctx->user_handle;
1395 e->hw_id = ctx->hw_id;
1396 e->sched_attr = ctx->sched;
1397 e->ban_score = atomic_read(&ctx->ban_score);
1398 e->bannable = i915_gem_context_is_bannable(ctx);
1399 e->guilty = atomic_read(&ctx->guilty_count);
1400 e->active = atomic_read(&ctx->active_count);
1401 }
1402
1403 static void request_record_user_bo(struct i915_request *request,
1404 struct drm_i915_error_engine *ee)
1405 {
1406 struct i915_capture_list *c;
1407 struct drm_i915_error_object **bo;
1408 long count, max;
1409
1410 max = 0;
1411 for (c = request->capture_list; c; c = c->next)
1412 max++;
1413 if (!max)
1414 return;
1415
1416 bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
1417 if (!bo) {
1418 /* If we can't capture everything, try to capture something. */
1419 max = min_t(long, max, PAGE_SIZE / sizeof(*bo));
1420 bo = kmalloc_array(max, sizeof(*bo), GFP_ATOMIC);
1421 }
1422 if (!bo)
1423 return;
1424
1425 count = 0;
1426 for (c = request->capture_list; c; c = c->next) {
1427 bo[count] = i915_error_object_create(request->i915, c->vma);
1428 if (!bo[count])
1429 break;
1430 if (++count == max)
1431 break;
1432 }
1433
1434 ee->user_bo = bo;
1435 ee->user_bo_count = count;
1436 }
1437
1438 static struct drm_i915_error_object *
1439 capture_object(struct drm_i915_private *dev_priv,
1440 struct drm_i915_gem_object *obj)
1441 {
1442 if (obj && i915_gem_object_has_pages(obj)) {
1443 struct i915_vma fake = {
1444 .node = { .start = U64_MAX, .size = obj->base.size },
1445 .size = obj->base.size,
1446 .pages = obj->mm.pages,
1447 .obj = obj,
1448 };
1449
1450 return i915_error_object_create(dev_priv, &fake);
1451 } else {
1452 return NULL;
1453 }
1454 }
1455
1456 static void gem_record_rings(struct i915_gpu_state *error)
1457 {
1458 struct drm_i915_private *i915 = error->i915;
1459 struct i915_ggtt *ggtt = &i915->ggtt;
1460 int i;
1461
1462 for (i = 0; i < I915_NUM_ENGINES; i++) {
1463 struct intel_engine_cs *engine = i915->engine[i];
1464 struct drm_i915_error_engine *ee = &error->engine[i];
1465 struct i915_request *request;
1466
1467 ee->engine_id = -1;
1468
1469 if (!engine)
1470 continue;
1471
1472 ee->engine_id = i;
1473
1474 error_record_engine_registers(error, engine, ee);
1475 error_record_engine_waiters(engine, ee);
1476 error_record_engine_execlists(engine, ee);
1477
1478 request = i915_gem_find_active_request(engine);
1479 if (request) {
1480 struct i915_gem_context *ctx = request->gem_context;
1481 struct intel_ring *ring;
1482
1483 ee->vm = ctx->ppgtt ? &ctx->ppgtt->vm : &ggtt->vm;
1484
1485 record_context(&ee->context, ctx);
1486
1487 /* We need to copy these to an anonymous buffer
1488 * as the simplest method to avoid being overwritten
1489 * by userspace.
1490 */
1491 ee->batchbuffer =
1492 i915_error_object_create(i915, request->batch);
1493
1494 if (HAS_BROKEN_CS_TLB(i915))
1495 ee->wa_batchbuffer =
1496 i915_error_object_create(i915,
1497 engine->scratch);
1498 request_record_user_bo(request, ee);
1499
1500 ee->ctx =
1501 i915_error_object_create(i915,
1502 request->hw_context->state);
1503
1504 error->simulated |=
1505 i915_gem_context_no_error_capture(ctx);
1506
1507 ee->rq_head = request->head;
1508 ee->rq_post = request->postfix;
1509 ee->rq_tail = request->tail;
1510
1511 ring = request->ring;
1512 ee->cpu_ring_head = ring->head;
1513 ee->cpu_ring_tail = ring->tail;
1514 ee->ringbuffer =
1515 i915_error_object_create(i915, ring->vma);
1516
1517 engine_record_requests(engine, request, ee);
1518 }
1519
1520 ee->hws_page =
1521 i915_error_object_create(i915,
1522 engine->status_page.vma);
1523
1524 ee->wa_ctx = i915_error_object_create(i915, engine->wa_ctx.vma);
1525
1526 ee->default_state = capture_object(i915, engine->default_state);
1527 }
1528 }
1529
1530 static void gem_capture_vm(struct i915_gpu_state *error,
1531 struct i915_address_space *vm,
1532 int idx)
1533 {
1534 struct drm_i915_error_buffer *active_bo;
1535 struct i915_vma *vma;
1536 int count;
1537
1538 count = 0;
1539 list_for_each_entry(vma, &vm->active_list, vm_link)
1540 count++;
1541
1542 active_bo = NULL;
1543 if (count)
1544 active_bo = kcalloc(count, sizeof(*active_bo), GFP_ATOMIC);
1545 if (active_bo)
1546 count = capture_error_bo(active_bo, count, &vm->active_list, false);
1547 else
1548 count = 0;
1549
1550 error->active_vm[idx] = vm;
1551 error->active_bo[idx] = active_bo;
1552 error->active_bo_count[idx] = count;
1553 }
1554
1555 static void capture_active_buffers(struct i915_gpu_state *error)
1556 {
1557 int cnt = 0, i, j;
1558
1559 BUILD_BUG_ON(ARRAY_SIZE(error->engine) > ARRAY_SIZE(error->active_bo));
1560 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_vm));
1561 BUILD_BUG_ON(ARRAY_SIZE(error->active_bo) != ARRAY_SIZE(error->active_bo_count));
1562
1563 /* Scan each engine looking for unique active contexts/vm */
1564 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1565 struct drm_i915_error_engine *ee = &error->engine[i];
1566 bool found;
1567
1568 if (!ee->vm)
1569 continue;
1570
1571 found = false;
1572 for (j = 0; j < i && !found; j++)
1573 found = error->engine[j].vm == ee->vm;
1574 if (!found)
1575 gem_capture_vm(error, ee->vm, cnt++);
1576 }
1577 }
1578
1579 static void capture_pinned_buffers(struct i915_gpu_state *error)
1580 {
1581 struct i915_address_space *vm = &error->i915->ggtt.vm;
1582 struct drm_i915_error_buffer *bo;
1583 struct i915_vma *vma;
1584 int count_inactive, count_active;
1585
1586 count_inactive = 0;
1587 list_for_each_entry(vma, &vm->inactive_list, vm_link)
1588 count_inactive++;
1589
1590 count_active = 0;
1591 list_for_each_entry(vma, &vm->active_list, vm_link)
1592 count_active++;
1593
1594 bo = NULL;
1595 if (count_inactive + count_active)
1596 bo = kcalloc(count_inactive + count_active,
1597 sizeof(*bo), GFP_ATOMIC);
1598 if (!bo)
1599 return;
1600
1601 count_inactive = capture_error_bo(bo, count_inactive,
1602 &vm->active_list, true);
1603 count_active = capture_error_bo(bo + count_inactive, count_active,
1604 &vm->inactive_list, true);
1605 error->pinned_bo_count = count_inactive + count_active;
1606 error->pinned_bo = bo;
1607 }
1608
1609 static void capture_uc_state(struct i915_gpu_state *error)
1610 {
1611 struct drm_i915_private *i915 = error->i915;
1612 struct i915_error_uc *error_uc = &error->uc;
1613
1614 /* Capturing uC state won't be useful if there is no GuC */
1615 if (!error->device_info.has_guc)
1616 return;
1617
1618 error_uc->guc_fw = i915->guc.fw;
1619 error_uc->huc_fw = i915->huc.fw;
1620
1621 /* Non-default firmware paths will be specified by the modparam.
1622 * As modparams are generally accesible from the userspace make
1623 * explicit copies of the firmware paths.
1624 */
1625 error_uc->guc_fw.path = kstrdup(i915->guc.fw.path, GFP_ATOMIC);
1626 error_uc->huc_fw.path = kstrdup(i915->huc.fw.path, GFP_ATOMIC);
1627 error_uc->guc_log = i915_error_object_create(i915, i915->guc.log.vma);
1628 }
1629
1630 /* Capture all registers which don't fit into another category. */
1631 static void capture_reg_state(struct i915_gpu_state *error)
1632 {
1633 struct drm_i915_private *dev_priv = error->i915;
1634 int i;
1635
1636 /* General organization
1637 * 1. Registers specific to a single generation
1638 * 2. Registers which belong to multiple generations
1639 * 3. Feature specific registers.
1640 * 4. Everything else
1641 * Please try to follow the order.
1642 */
1643
1644 /* 1: Registers specific to a single generation */
1645 if (IS_VALLEYVIEW(dev_priv)) {
1646 error->gtier[0] = I915_READ(GTIER);
1647 error->ier = I915_READ(VLV_IER);
1648 error->forcewake = I915_READ_FW(FORCEWAKE_VLV);
1649 }
1650
1651 if (IS_GEN7(dev_priv))
1652 error->err_int = I915_READ(GEN7_ERR_INT);
1653
1654 if (INTEL_GEN(dev_priv) >= 8) {
1655 error->fault_data0 = I915_READ(GEN8_FAULT_TLB_DATA0);
1656 error->fault_data1 = I915_READ(GEN8_FAULT_TLB_DATA1);
1657 }
1658
1659 if (IS_GEN6(dev_priv)) {
1660 error->forcewake = I915_READ_FW(FORCEWAKE);
1661 error->gab_ctl = I915_READ(GAB_CTL);
1662 error->gfx_mode = I915_READ(GFX_MODE);
1663 }
1664
1665 /* 2: Registers which belong to multiple generations */
1666 if (INTEL_GEN(dev_priv) >= 7)
1667 error->forcewake = I915_READ_FW(FORCEWAKE_MT);
1668
1669 if (INTEL_GEN(dev_priv) >= 6) {
1670 error->derrmr = I915_READ(DERRMR);
1671 error->error = I915_READ(ERROR_GEN6);
1672 error->done_reg = I915_READ(DONE_REG);
1673 }
1674
1675 if (INTEL_GEN(dev_priv) >= 5)
1676 error->ccid = I915_READ(CCID);
1677
1678 /* 3: Feature specific registers */
1679 if (IS_GEN6(dev_priv) || IS_GEN7(dev_priv)) {
1680 error->gam_ecochk = I915_READ(GAM_ECOCHK);
1681 error->gac_eco = I915_READ(GAC_ECO_BITS);
1682 }
1683
1684 /* 4: Everything else */
1685 if (INTEL_GEN(dev_priv) >= 11) {
1686 error->ier = I915_READ(GEN8_DE_MISC_IER);
1687 error->gtier[0] = I915_READ(GEN11_RENDER_COPY_INTR_ENABLE);
1688 error->gtier[1] = I915_READ(GEN11_VCS_VECS_INTR_ENABLE);
1689 error->gtier[2] = I915_READ(GEN11_GUC_SG_INTR_ENABLE);
1690 error->gtier[3] = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1691 error->gtier[4] = I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE);
1692 error->gtier[5] = I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE);
1693 error->ngtier = 6;
1694 } else if (INTEL_GEN(dev_priv) >= 8) {
1695 error->ier = I915_READ(GEN8_DE_MISC_IER);
1696 for (i = 0; i < 4; i++)
1697 error->gtier[i] = I915_READ(GEN8_GT_IER(i));
1698 error->ngtier = 4;
1699 } else if (HAS_PCH_SPLIT(dev_priv)) {
1700 error->ier = I915_READ(DEIER);
1701 error->gtier[0] = I915_READ(GTIER);
1702 error->ngtier = 1;
1703 } else if (IS_GEN2(dev_priv)) {
1704 error->ier = I915_READ16(IER);
1705 } else if (!IS_VALLEYVIEW(dev_priv)) {
1706 error->ier = I915_READ(IER);
1707 }
1708 error->eir = I915_READ(EIR);
1709 error->pgtbl_er = I915_READ(PGTBL_ER);
1710 }
1711
1712 static void i915_error_capture_msg(struct drm_i915_private *dev_priv,
1713 struct i915_gpu_state *error,
1714 u32 engine_mask,
1715 const char *error_msg)
1716 {
1717 u32 ecode;
1718 int engine_id = -1, len;
1719
1720 ecode = i915_error_generate_code(dev_priv, error, &engine_id);
1721
1722 len = scnprintf(error->error_msg, sizeof(error->error_msg),
1723 "GPU HANG: ecode %d:%d:0x%08x",
1724 INTEL_GEN(dev_priv), engine_id, ecode);
1725
1726 if (engine_id != -1 && error->engine[engine_id].context.pid)
1727 len += scnprintf(error->error_msg + len,
1728 sizeof(error->error_msg) - len,
1729 ", in %s [%d]",
1730 error->engine[engine_id].context.comm,
1731 error->engine[engine_id].context.pid);
1732
1733 scnprintf(error->error_msg + len, sizeof(error->error_msg) - len,
1734 ", reason: %s, action: %s",
1735 error_msg,
1736 engine_mask ? "reset" : "continue");
1737 }
1738
1739 static void capture_gen_state(struct i915_gpu_state *error)
1740 {
1741 struct drm_i915_private *i915 = error->i915;
1742
1743 error->awake = i915->gt.awake;
1744 error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1745 error->suspended = i915->runtime_pm.suspended;
1746
1747 error->iommu = -1;
1748 #ifdef CONFIG_INTEL_IOMMU
1749 error->iommu = intel_iommu_gfx_mapped;
1750 #endif
1751 error->reset_count = i915_reset_count(&i915->gpu_error);
1752 error->suspend_count = i915->suspend_count;
1753
1754 memcpy(&error->device_info,
1755 INTEL_INFO(i915),
1756 sizeof(error->device_info));
1757 error->driver_caps = i915->caps;
1758 }
1759
1760 static __always_inline void dup_param(const char *type, void *x)
1761 {
1762 if (!__builtin_strcmp(type, "char *"))
1763 *(void **)x = kstrdup(*(void **)x, GFP_ATOMIC);
1764 }
1765
1766 static void capture_params(struct i915_gpu_state *error)
1767 {
1768 error->params = i915_modparams;
1769 #define DUP(T, x, ...) dup_param(#T, &error->params.x);
1770 I915_PARAMS_FOR_EACH(DUP);
1771 #undef DUP
1772 }
1773
1774 static unsigned long capture_find_epoch(const struct i915_gpu_state *error)
1775 {
1776 unsigned long epoch = error->capture;
1777 int i;
1778
1779 for (i = 0; i < ARRAY_SIZE(error->engine); i++) {
1780 const struct drm_i915_error_engine *ee = &error->engine[i];
1781
1782 if (ee->hangcheck_stalled &&
1783 time_before(ee->hangcheck_timestamp, epoch))
1784 epoch = ee->hangcheck_timestamp;
1785 }
1786
1787 return epoch;
1788 }
1789
1790 static void capture_finish(struct i915_gpu_state *error)
1791 {
1792 struct i915_ggtt *ggtt = &error->i915->ggtt;
1793 const u64 slot = ggtt->error_capture.start;
1794
1795 ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
1796 }
1797
1798 static int capture(void *data)
1799 {
1800 struct i915_gpu_state *error = data;
1801
1802 error->time = ktime_get_real();
1803 error->boottime = ktime_get_boottime();
1804 error->uptime = ktime_sub(ktime_get(),
1805 error->i915->gt.last_init_time);
1806 error->capture = jiffies;
1807
1808 capture_params(error);
1809 capture_gen_state(error);
1810 capture_uc_state(error);
1811 capture_reg_state(error);
1812 gem_record_fences(error);
1813 gem_record_rings(error);
1814 capture_active_buffers(error);
1815 capture_pinned_buffers(error);
1816
1817 error->overlay = intel_overlay_capture_error_state(error->i915);
1818 error->display = intel_display_capture_error_state(error->i915);
1819
1820 error->epoch = capture_find_epoch(error);
1821
1822 capture_finish(error);
1823 return 0;
1824 }
1825
1826 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
1827
1828 struct i915_gpu_state *
1829 i915_capture_gpu_state(struct drm_i915_private *i915)
1830 {
1831 struct i915_gpu_state *error;
1832
1833 error = kzalloc(sizeof(*error), GFP_ATOMIC);
1834 if (!error)
1835 return NULL;
1836
1837 kref_init(&error->ref);
1838 error->i915 = i915;
1839
1840 stop_machine(capture, error, NULL);
1841
1842 return error;
1843 }
1844
1845 /**
1846 * i915_capture_error_state - capture an error record for later analysis
1847 * @i915: i915 device
1848 * @engine_mask: the mask of engines triggering the hang
1849 * @error_msg: a message to insert into the error capture header
1850 *
1851 * Should be called when an error is detected (either a hang or an error
1852 * interrupt) to capture error state from the time of the error. Fills
1853 * out a structure which becomes available in debugfs for user level tools
1854 * to pick up.
1855 */
1856 void i915_capture_error_state(struct drm_i915_private *i915,
1857 u32 engine_mask,
1858 const char *error_msg)
1859 {
1860 static bool warned;
1861 struct i915_gpu_state *error;
1862 unsigned long flags;
1863
1864 if (!i915_modparams.error_capture)
1865 return;
1866
1867 if (READ_ONCE(i915->gpu_error.first_error))
1868 return;
1869
1870 error = i915_capture_gpu_state(i915);
1871 if (!error) {
1872 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1873 i915_disable_error_state(i915, -ENOMEM);
1874 return;
1875 }
1876
1877 i915_error_capture_msg(i915, error, engine_mask, error_msg);
1878 DRM_INFO("%s\n", error->error_msg);
1879
1880 if (!error->simulated) {
1881 spin_lock_irqsave(&i915->gpu_error.lock, flags);
1882 if (!i915->gpu_error.first_error) {
1883 i915->gpu_error.first_error = error;
1884 error = NULL;
1885 }
1886 spin_unlock_irqrestore(&i915->gpu_error.lock, flags);
1887 }
1888
1889 if (error) {
1890 __i915_gpu_state_free(&error->ref);
1891 return;
1892 }
1893
1894 if (!warned &&
1895 ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
1896 DRM_INFO("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
1897 DRM_INFO("Please file a _new_ bug report on bugs.freedesktop.org against DRI -> DRM/Intel\n");
1898 DRM_INFO("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
1899 DRM_INFO("The gpu crash dump is required to analyze gpu hangs, so please always attach it.\n");
1900 DRM_INFO("GPU crash dump saved to /sys/class/drm/card%d/error\n",
1901 i915->drm.primary->index);
1902 warned = true;
1903 }
1904 }
1905
1906 struct i915_gpu_state *
1907 i915_first_error_state(struct drm_i915_private *i915)
1908 {
1909 struct i915_gpu_state *error;
1910
1911 spin_lock_irq(&i915->gpu_error.lock);
1912 error = i915->gpu_error.first_error;
1913 if (error)
1914 i915_gpu_state_get(error);
1915 spin_unlock_irq(&i915->gpu_error.lock);
1916
1917 return error;
1918 }
1919
1920 void i915_reset_error_state(struct drm_i915_private *i915)
1921 {
1922 struct i915_gpu_state *error;
1923
1924 spin_lock_irq(&i915->gpu_error.lock);
1925 error = i915->gpu_error.first_error;
1926 i915->gpu_error.first_error = NULL;
1927 spin_unlock_irq(&i915->gpu_error.lock);
1928
1929 if (!IS_ERR(error))
1930 i915_gpu_state_put(error);
1931 }
1932
1933 void i915_disable_error_state(struct drm_i915_private *i915, int err)
1934 {
1935 spin_lock_irq(&i915->gpu_error.lock);
1936 if (!i915->gpu_error.first_error)
1937 i915->gpu_error.first_error = ERR_PTR(err);
1938 spin_unlock_irq(&i915->gpu_error.lock);
1939 }
Ubuntu Disco kernel mirror for Proxmox VE and PMG