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ASoC: ep93xx-ac97: Fix platform_get_irq's error checking
[mirror_ubuntu-disco-kernel.git] / drivers / gpu / drm / i915 / intel_hdmi.c
1 /*
2 * Copyright 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2009 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Jesse Barnes <jesse.barnes@intel.com>
27 */
28
29 #include <linux/i2c.h>
30 #include <linux/slab.h>
31 #include <linux/delay.h>
32 #include <linux/hdmi.h>
33 #include <drm/drmP.h>
34 #include <drm/drm_atomic_helper.h>
35 #include <drm/drm_crtc.h>
36 #include <drm/drm_edid.h>
37 #include <drm/drm_scdc_helper.h>
38 #include "intel_drv.h"
39 #include <drm/i915_drm.h>
40 #include <drm/intel_lpe_audio.h>
41 #include "i915_drv.h"
42
43 static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
44 {
45 return hdmi_to_dig_port(intel_hdmi)->base.base.dev;
46 }
47
48 static void
49 assert_hdmi_port_disabled(struct intel_hdmi *intel_hdmi)
50 {
51 struct drm_device *dev = intel_hdmi_to_dev(intel_hdmi);
52 struct drm_i915_private *dev_priv = to_i915(dev);
53 uint32_t enabled_bits;
54
55 enabled_bits = HAS_DDI(dev_priv) ? DDI_BUF_CTL_ENABLE : SDVO_ENABLE;
56
57 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits,
58 "HDMI port enabled, expecting disabled\n");
59 }
60
61 struct intel_hdmi *enc_to_intel_hdmi(struct drm_encoder *encoder)
62 {
63 struct intel_digital_port *intel_dig_port =
64 container_of(encoder, struct intel_digital_port, base.base);
65 return &intel_dig_port->hdmi;
66 }
67
68 static struct intel_hdmi *intel_attached_hdmi(struct drm_connector *connector)
69 {
70 return enc_to_intel_hdmi(&intel_attached_encoder(connector)->base);
71 }
72
73 static u32 g4x_infoframe_index(unsigned int type)
74 {
75 switch (type) {
76 case HDMI_INFOFRAME_TYPE_AVI:
77 return VIDEO_DIP_SELECT_AVI;
78 case HDMI_INFOFRAME_TYPE_SPD:
79 return VIDEO_DIP_SELECT_SPD;
80 case HDMI_INFOFRAME_TYPE_VENDOR:
81 return VIDEO_DIP_SELECT_VENDOR;
82 default:
83 MISSING_CASE(type);
84 return 0;
85 }
86 }
87
88 static u32 g4x_infoframe_enable(unsigned int type)
89 {
90 switch (type) {
91 case HDMI_INFOFRAME_TYPE_AVI:
92 return VIDEO_DIP_ENABLE_AVI;
93 case HDMI_INFOFRAME_TYPE_SPD:
94 return VIDEO_DIP_ENABLE_SPD;
95 case HDMI_INFOFRAME_TYPE_VENDOR:
96 return VIDEO_DIP_ENABLE_VENDOR;
97 default:
98 MISSING_CASE(type);
99 return 0;
100 }
101 }
102
103 static u32 hsw_infoframe_enable(unsigned int type)
104 {
105 switch (type) {
106 case DP_SDP_VSC:
107 return VIDEO_DIP_ENABLE_VSC_HSW;
108 case HDMI_INFOFRAME_TYPE_AVI:
109 return VIDEO_DIP_ENABLE_AVI_HSW;
110 case HDMI_INFOFRAME_TYPE_SPD:
111 return VIDEO_DIP_ENABLE_SPD_HSW;
112 case HDMI_INFOFRAME_TYPE_VENDOR:
113 return VIDEO_DIP_ENABLE_VS_HSW;
114 default:
115 MISSING_CASE(type);
116 return 0;
117 }
118 }
119
120 static i915_reg_t
121 hsw_dip_data_reg(struct drm_i915_private *dev_priv,
122 enum transcoder cpu_transcoder,
123 unsigned int type,
124 int i)
125 {
126 switch (type) {
127 case DP_SDP_VSC:
128 return HSW_TVIDEO_DIP_VSC_DATA(cpu_transcoder, i);
129 case HDMI_INFOFRAME_TYPE_AVI:
130 return HSW_TVIDEO_DIP_AVI_DATA(cpu_transcoder, i);
131 case HDMI_INFOFRAME_TYPE_SPD:
132 return HSW_TVIDEO_DIP_SPD_DATA(cpu_transcoder, i);
133 case HDMI_INFOFRAME_TYPE_VENDOR:
134 return HSW_TVIDEO_DIP_VS_DATA(cpu_transcoder, i);
135 default:
136 MISSING_CASE(type);
137 return INVALID_MMIO_REG;
138 }
139 }
140
141 static void g4x_write_infoframe(struct drm_encoder *encoder,
142 const struct intel_crtc_state *crtc_state,
143 unsigned int type,
144 const void *frame, ssize_t len)
145 {
146 const uint32_t *data = frame;
147 struct drm_device *dev = encoder->dev;
148 struct drm_i915_private *dev_priv = to_i915(dev);
149 u32 val = I915_READ(VIDEO_DIP_CTL);
150 int i;
151
152 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
153
154 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
155 val |= g4x_infoframe_index(type);
156
157 val &= ~g4x_infoframe_enable(type);
158
159 I915_WRITE(VIDEO_DIP_CTL, val);
160
161 mmiowb();
162 for (i = 0; i < len; i += 4) {
163 I915_WRITE(VIDEO_DIP_DATA, *data);
164 data++;
165 }
166 /* Write every possible data byte to force correct ECC calculation. */
167 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
168 I915_WRITE(VIDEO_DIP_DATA, 0);
169 mmiowb();
170
171 val |= g4x_infoframe_enable(type);
172 val &= ~VIDEO_DIP_FREQ_MASK;
173 val |= VIDEO_DIP_FREQ_VSYNC;
174
175 I915_WRITE(VIDEO_DIP_CTL, val);
176 POSTING_READ(VIDEO_DIP_CTL);
177 }
178
179 static bool g4x_infoframe_enabled(struct drm_encoder *encoder,
180 const struct intel_crtc_state *pipe_config)
181 {
182 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
183 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
184 u32 val = I915_READ(VIDEO_DIP_CTL);
185
186 if ((val & VIDEO_DIP_ENABLE) == 0)
187 return false;
188
189 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
190 return false;
191
192 return val & (VIDEO_DIP_ENABLE_AVI |
193 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
194 }
195
196 static void ibx_write_infoframe(struct drm_encoder *encoder,
197 const struct intel_crtc_state *crtc_state,
198 unsigned int type,
199 const void *frame, ssize_t len)
200 {
201 const uint32_t *data = frame;
202 struct drm_device *dev = encoder->dev;
203 struct drm_i915_private *dev_priv = to_i915(dev);
204 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
205 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
206 u32 val = I915_READ(reg);
207 int i;
208
209 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
210
211 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
212 val |= g4x_infoframe_index(type);
213
214 val &= ~g4x_infoframe_enable(type);
215
216 I915_WRITE(reg, val);
217
218 mmiowb();
219 for (i = 0; i < len; i += 4) {
220 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
221 data++;
222 }
223 /* Write every possible data byte to force correct ECC calculation. */
224 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
225 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
226 mmiowb();
227
228 val |= g4x_infoframe_enable(type);
229 val &= ~VIDEO_DIP_FREQ_MASK;
230 val |= VIDEO_DIP_FREQ_VSYNC;
231
232 I915_WRITE(reg, val);
233 POSTING_READ(reg);
234 }
235
236 static bool ibx_infoframe_enabled(struct drm_encoder *encoder,
237 const struct intel_crtc_state *pipe_config)
238 {
239 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
240 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
241 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
242 i915_reg_t reg = TVIDEO_DIP_CTL(pipe);
243 u32 val = I915_READ(reg);
244
245 if ((val & VIDEO_DIP_ENABLE) == 0)
246 return false;
247
248 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
249 return false;
250
251 return val & (VIDEO_DIP_ENABLE_AVI |
252 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
253 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
254 }
255
256 static void cpt_write_infoframe(struct drm_encoder *encoder,
257 const struct intel_crtc_state *crtc_state,
258 unsigned int type,
259 const void *frame, ssize_t len)
260 {
261 const uint32_t *data = frame;
262 struct drm_device *dev = encoder->dev;
263 struct drm_i915_private *dev_priv = to_i915(dev);
264 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
265 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
266 u32 val = I915_READ(reg);
267 int i;
268
269 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
270
271 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
272 val |= g4x_infoframe_index(type);
273
274 /* The DIP control register spec says that we need to update the AVI
275 * infoframe without clearing its enable bit */
276 if (type != HDMI_INFOFRAME_TYPE_AVI)
277 val &= ~g4x_infoframe_enable(type);
278
279 I915_WRITE(reg, val);
280
281 mmiowb();
282 for (i = 0; i < len; i += 4) {
283 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
284 data++;
285 }
286 /* Write every possible data byte to force correct ECC calculation. */
287 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
288 I915_WRITE(TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
289 mmiowb();
290
291 val |= g4x_infoframe_enable(type);
292 val &= ~VIDEO_DIP_FREQ_MASK;
293 val |= VIDEO_DIP_FREQ_VSYNC;
294
295 I915_WRITE(reg, val);
296 POSTING_READ(reg);
297 }
298
299 static bool cpt_infoframe_enabled(struct drm_encoder *encoder,
300 const struct intel_crtc_state *pipe_config)
301 {
302 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
303 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
304 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe));
305
306 if ((val & VIDEO_DIP_ENABLE) == 0)
307 return false;
308
309 return val & (VIDEO_DIP_ENABLE_AVI |
310 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
311 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
312 }
313
314 static void vlv_write_infoframe(struct drm_encoder *encoder,
315 const struct intel_crtc_state *crtc_state,
316 unsigned int type,
317 const void *frame, ssize_t len)
318 {
319 const uint32_t *data = frame;
320 struct drm_device *dev = encoder->dev;
321 struct drm_i915_private *dev_priv = to_i915(dev);
322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
323 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
324 u32 val = I915_READ(reg);
325 int i;
326
327 WARN(!(val & VIDEO_DIP_ENABLE), "Writing DIP with CTL reg disabled\n");
328
329 val &= ~(VIDEO_DIP_SELECT_MASK | 0xf); /* clear DIP data offset */
330 val |= g4x_infoframe_index(type);
331
332 val &= ~g4x_infoframe_enable(type);
333
334 I915_WRITE(reg, val);
335
336 mmiowb();
337 for (i = 0; i < len; i += 4) {
338 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), *data);
339 data++;
340 }
341 /* Write every possible data byte to force correct ECC calculation. */
342 for (; i < VIDEO_DIP_DATA_SIZE; i += 4)
343 I915_WRITE(VLV_TVIDEO_DIP_DATA(intel_crtc->pipe), 0);
344 mmiowb();
345
346 val |= g4x_infoframe_enable(type);
347 val &= ~VIDEO_DIP_FREQ_MASK;
348 val |= VIDEO_DIP_FREQ_VSYNC;
349
350 I915_WRITE(reg, val);
351 POSTING_READ(reg);
352 }
353
354 static bool vlv_infoframe_enabled(struct drm_encoder *encoder,
355 const struct intel_crtc_state *pipe_config)
356 {
357 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
358 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
359 enum pipe pipe = to_intel_crtc(pipe_config->base.crtc)->pipe;
360 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe));
361
362 if ((val & VIDEO_DIP_ENABLE) == 0)
363 return false;
364
365 if ((val & VIDEO_DIP_PORT_MASK) != VIDEO_DIP_PORT(intel_dig_port->port))
366 return false;
367
368 return val & (VIDEO_DIP_ENABLE_AVI |
369 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
370 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
371 }
372
373 static void hsw_write_infoframe(struct drm_encoder *encoder,
374 const struct intel_crtc_state *crtc_state,
375 unsigned int type,
376 const void *frame, ssize_t len)
377 {
378 const uint32_t *data = frame;
379 struct drm_device *dev = encoder->dev;
380 struct drm_i915_private *dev_priv = to_i915(dev);
381 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
382 i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(cpu_transcoder);
383 i915_reg_t data_reg;
384 int data_size = type == DP_SDP_VSC ?
385 VIDEO_DIP_VSC_DATA_SIZE : VIDEO_DIP_DATA_SIZE;
386 int i;
387 u32 val = I915_READ(ctl_reg);
388
389 data_reg = hsw_dip_data_reg(dev_priv, cpu_transcoder, type, 0);
390
391 val &= ~hsw_infoframe_enable(type);
392 I915_WRITE(ctl_reg, val);
393
394 mmiowb();
395 for (i = 0; i < len; i += 4) {
396 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
397 type, i >> 2), *data);
398 data++;
399 }
400 /* Write every possible data byte to force correct ECC calculation. */
401 for (; i < data_size; i += 4)
402 I915_WRITE(hsw_dip_data_reg(dev_priv, cpu_transcoder,
403 type, i >> 2), 0);
404 mmiowb();
405
406 val |= hsw_infoframe_enable(type);
407 I915_WRITE(ctl_reg, val);
408 POSTING_READ(ctl_reg);
409 }
410
411 static bool hsw_infoframe_enabled(struct drm_encoder *encoder,
412 const struct intel_crtc_state *pipe_config)
413 {
414 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
415 u32 val = I915_READ(HSW_TVIDEO_DIP_CTL(pipe_config->cpu_transcoder));
416
417 return val & (VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
418 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
419 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
420 }
421
422 /*
423 * The data we write to the DIP data buffer registers is 1 byte bigger than the
424 * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
425 * at 0). It's also a byte used by DisplayPort so the same DIP registers can be
426 * used for both technologies.
427 *
428 * DW0: Reserved/ECC/DP | HB2 | HB1 | HB0
429 * DW1: DB3 | DB2 | DB1 | DB0
430 * DW2: DB7 | DB6 | DB5 | DB4
431 * DW3: ...
432 *
433 * (HB is Header Byte, DB is Data Byte)
434 *
435 * The hdmi pack() functions don't know about that hardware specific hole so we
436 * trick them by giving an offset into the buffer and moving back the header
437 * bytes by one.
438 */
439 static void intel_write_infoframe(struct drm_encoder *encoder,
440 const struct intel_crtc_state *crtc_state,
441 union hdmi_infoframe *frame)
442 {
443 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
444 uint8_t buffer[VIDEO_DIP_DATA_SIZE];
445 ssize_t len;
446
447 /* see comment above for the reason for this offset */
448 len = hdmi_infoframe_pack(frame, buffer + 1, sizeof(buffer) - 1);
449 if (len < 0)
450 return;
451
452 /* Insert the 'hole' (see big comment above) at position 3 */
453 buffer[0] = buffer[1];
454 buffer[1] = buffer[2];
455 buffer[2] = buffer[3];
456 buffer[3] = 0;
457 len++;
458
459 intel_dig_port->write_infoframe(encoder, crtc_state, frame->any.type, buffer, len);
460 }
461
462 static void intel_hdmi_set_avi_infoframe(struct drm_encoder *encoder,
463 const struct intel_crtc_state *crtc_state)
464 {
465 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
466 const struct drm_display_mode *adjusted_mode =
467 &crtc_state->base.adjusted_mode;
468 struct drm_connector *connector = &intel_hdmi->attached_connector->base;
469 bool is_hdmi2_sink = connector->display_info.hdmi.scdc.supported;
470 union hdmi_infoframe frame;
471 int ret;
472
473 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
474 adjusted_mode,
475 is_hdmi2_sink);
476 if (ret < 0) {
477 DRM_ERROR("couldn't fill AVI infoframe\n");
478 return;
479 }
480
481 if (crtc_state->ycbcr420)
482 frame.avi.colorspace = HDMI_COLORSPACE_YUV420;
483 else
484 frame.avi.colorspace = HDMI_COLORSPACE_RGB;
485
486 drm_hdmi_avi_infoframe_quant_range(&frame.avi, adjusted_mode,
487 crtc_state->limited_color_range ?
488 HDMI_QUANTIZATION_RANGE_LIMITED :
489 HDMI_QUANTIZATION_RANGE_FULL,
490 intel_hdmi->rgb_quant_range_selectable);
491
492 /* TODO: handle pixel repetition for YCBCR420 outputs */
493 intel_write_infoframe(encoder, crtc_state, &frame);
494 }
495
496 static void intel_hdmi_set_spd_infoframe(struct drm_encoder *encoder,
497 const struct intel_crtc_state *crtc_state)
498 {
499 union hdmi_infoframe frame;
500 int ret;
501
502 ret = hdmi_spd_infoframe_init(&frame.spd, "Intel", "Integrated gfx");
503 if (ret < 0) {
504 DRM_ERROR("couldn't fill SPD infoframe\n");
505 return;
506 }
507
508 frame.spd.sdi = HDMI_SPD_SDI_PC;
509
510 intel_write_infoframe(encoder, crtc_state, &frame);
511 }
512
513 static void
514 intel_hdmi_set_hdmi_infoframe(struct drm_encoder *encoder,
515 const struct intel_crtc_state *crtc_state)
516 {
517 union hdmi_infoframe frame;
518 int ret;
519
520 ret = drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi,
521 &crtc_state->base.adjusted_mode);
522 if (ret < 0)
523 return;
524
525 intel_write_infoframe(encoder, crtc_state, &frame);
526 }
527
528 static void g4x_set_infoframes(struct drm_encoder *encoder,
529 bool enable,
530 const struct intel_crtc_state *crtc_state,
531 const struct drm_connector_state *conn_state)
532 {
533 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
534 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
535 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
536 i915_reg_t reg = VIDEO_DIP_CTL;
537 u32 val = I915_READ(reg);
538 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
539
540 assert_hdmi_port_disabled(intel_hdmi);
541
542 /* If the registers were not initialized yet, they might be zeroes,
543 * which means we're selecting the AVI DIP and we're setting its
544 * frequency to once. This seems to really confuse the HW and make
545 * things stop working (the register spec says the AVI always needs to
546 * be sent every VSync). So here we avoid writing to the register more
547 * than we need and also explicitly select the AVI DIP and explicitly
548 * set its frequency to every VSync. Avoiding to write it twice seems to
549 * be enough to solve the problem, but being defensive shouldn't hurt us
550 * either. */
551 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
552
553 if (!enable) {
554 if (!(val & VIDEO_DIP_ENABLE))
555 return;
556 if (port != (val & VIDEO_DIP_PORT_MASK)) {
557 DRM_DEBUG_KMS("video DIP still enabled on port %c\n",
558 (val & VIDEO_DIP_PORT_MASK) >> 29);
559 return;
560 }
561 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
562 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
563 I915_WRITE(reg, val);
564 POSTING_READ(reg);
565 return;
566 }
567
568 if (port != (val & VIDEO_DIP_PORT_MASK)) {
569 if (val & VIDEO_DIP_ENABLE) {
570 DRM_DEBUG_KMS("video DIP already enabled on port %c\n",
571 (val & VIDEO_DIP_PORT_MASK) >> 29);
572 return;
573 }
574 val &= ~VIDEO_DIP_PORT_MASK;
575 val |= port;
576 }
577
578 val |= VIDEO_DIP_ENABLE;
579 val &= ~(VIDEO_DIP_ENABLE_AVI |
580 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_SPD);
581
582 I915_WRITE(reg, val);
583 POSTING_READ(reg);
584
585 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
586 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
587 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
588 }
589
590 static bool hdmi_sink_is_deep_color(const struct drm_connector_state *conn_state)
591 {
592 struct drm_connector *connector = conn_state->connector;
593
594 /*
595 * HDMI cloning is only supported on g4x which doesn't
596 * support deep color or GCP infoframes anyway so no
597 * need to worry about multiple HDMI sinks here.
598 */
599
600 return connector->display_info.bpc > 8;
601 }
602
603 /*
604 * Determine if default_phase=1 can be indicated in the GCP infoframe.
605 *
606 * From HDMI specification 1.4a:
607 * - The first pixel of each Video Data Period shall always have a pixel packing phase of 0
608 * - The first pixel following each Video Data Period shall have a pixel packing phase of 0
609 * - The PP bits shall be constant for all GCPs and will be equal to the last packing phase
610 * - The first pixel following every transition of HSYNC or VSYNC shall have a pixel packing
611 * phase of 0
612 */
613 static bool gcp_default_phase_possible(int pipe_bpp,
614 const struct drm_display_mode *mode)
615 {
616 unsigned int pixels_per_group;
617
618 switch (pipe_bpp) {
619 case 30:
620 /* 4 pixels in 5 clocks */
621 pixels_per_group = 4;
622 break;
623 case 36:
624 /* 2 pixels in 3 clocks */
625 pixels_per_group = 2;
626 break;
627 case 48:
628 /* 1 pixel in 2 clocks */
629 pixels_per_group = 1;
630 break;
631 default:
632 /* phase information not relevant for 8bpc */
633 return false;
634 }
635
636 return mode->crtc_hdisplay % pixels_per_group == 0 &&
637 mode->crtc_htotal % pixels_per_group == 0 &&
638 mode->crtc_hblank_start % pixels_per_group == 0 &&
639 mode->crtc_hblank_end % pixels_per_group == 0 &&
640 mode->crtc_hsync_start % pixels_per_group == 0 &&
641 mode->crtc_hsync_end % pixels_per_group == 0 &&
642 ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0 ||
643 mode->crtc_htotal/2 % pixels_per_group == 0);
644 }
645
646 static bool intel_hdmi_set_gcp_infoframe(struct drm_encoder *encoder,
647 const struct intel_crtc_state *crtc_state,
648 const struct drm_connector_state *conn_state)
649 {
650 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
651 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
652 i915_reg_t reg;
653 u32 val = 0;
654
655 if (HAS_DDI(dev_priv))
656 reg = HSW_TVIDEO_DIP_GCP(crtc_state->cpu_transcoder);
657 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
658 reg = VLV_TVIDEO_DIP_GCP(crtc->pipe);
659 else if (HAS_PCH_SPLIT(dev_priv))
660 reg = TVIDEO_DIP_GCP(crtc->pipe);
661 else
662 return false;
663
664 /* Indicate color depth whenever the sink supports deep color */
665 if (hdmi_sink_is_deep_color(conn_state))
666 val |= GCP_COLOR_INDICATION;
667
668 /* Enable default_phase whenever the display mode is suitably aligned */
669 if (gcp_default_phase_possible(crtc_state->pipe_bpp,
670 &crtc_state->base.adjusted_mode))
671 val |= GCP_DEFAULT_PHASE_ENABLE;
672
673 I915_WRITE(reg, val);
674
675 return val != 0;
676 }
677
678 static void ibx_set_infoframes(struct drm_encoder *encoder,
679 bool enable,
680 const struct intel_crtc_state *crtc_state,
681 const struct drm_connector_state *conn_state)
682 {
683 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
684 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
685 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
686 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
687 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
688 u32 val = I915_READ(reg);
689 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
690
691 assert_hdmi_port_disabled(intel_hdmi);
692
693 /* See the big comment in g4x_set_infoframes() */
694 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
695
696 if (!enable) {
697 if (!(val & VIDEO_DIP_ENABLE))
698 return;
699 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
700 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
701 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
702 I915_WRITE(reg, val);
703 POSTING_READ(reg);
704 return;
705 }
706
707 if (port != (val & VIDEO_DIP_PORT_MASK)) {
708 WARN(val & VIDEO_DIP_ENABLE,
709 "DIP already enabled on port %c\n",
710 (val & VIDEO_DIP_PORT_MASK) >> 29);
711 val &= ~VIDEO_DIP_PORT_MASK;
712 val |= port;
713 }
714
715 val |= VIDEO_DIP_ENABLE;
716 val &= ~(VIDEO_DIP_ENABLE_AVI |
717 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
718 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
719
720 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
721 val |= VIDEO_DIP_ENABLE_GCP;
722
723 I915_WRITE(reg, val);
724 POSTING_READ(reg);
725
726 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
727 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
728 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
729 }
730
731 static void cpt_set_infoframes(struct drm_encoder *encoder,
732 bool enable,
733 const struct intel_crtc_state *crtc_state,
734 const struct drm_connector_state *conn_state)
735 {
736 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
737 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
738 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
739 i915_reg_t reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
740 u32 val = I915_READ(reg);
741
742 assert_hdmi_port_disabled(intel_hdmi);
743
744 /* See the big comment in g4x_set_infoframes() */
745 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
746
747 if (!enable) {
748 if (!(val & VIDEO_DIP_ENABLE))
749 return;
750 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
751 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
752 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
753 I915_WRITE(reg, val);
754 POSTING_READ(reg);
755 return;
756 }
757
758 /* Set both together, unset both together: see the spec. */
759 val |= VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI;
760 val &= ~(VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
761 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
762
763 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
764 val |= VIDEO_DIP_ENABLE_GCP;
765
766 I915_WRITE(reg, val);
767 POSTING_READ(reg);
768
769 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
770 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
771 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
772 }
773
774 static void vlv_set_infoframes(struct drm_encoder *encoder,
775 bool enable,
776 const struct intel_crtc_state *crtc_state,
777 const struct drm_connector_state *conn_state)
778 {
779 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
780 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
781 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
782 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
783 i915_reg_t reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
784 u32 val = I915_READ(reg);
785 u32 port = VIDEO_DIP_PORT(intel_dig_port->port);
786
787 assert_hdmi_port_disabled(intel_hdmi);
788
789 /* See the big comment in g4x_set_infoframes() */
790 val |= VIDEO_DIP_SELECT_AVI | VIDEO_DIP_FREQ_VSYNC;
791
792 if (!enable) {
793 if (!(val & VIDEO_DIP_ENABLE))
794 return;
795 val &= ~(VIDEO_DIP_ENABLE | VIDEO_DIP_ENABLE_AVI |
796 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
797 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
798 I915_WRITE(reg, val);
799 POSTING_READ(reg);
800 return;
801 }
802
803 if (port != (val & VIDEO_DIP_PORT_MASK)) {
804 WARN(val & VIDEO_DIP_ENABLE,
805 "DIP already enabled on port %c\n",
806 (val & VIDEO_DIP_PORT_MASK) >> 29);
807 val &= ~VIDEO_DIP_PORT_MASK;
808 val |= port;
809 }
810
811 val |= VIDEO_DIP_ENABLE;
812 val &= ~(VIDEO_DIP_ENABLE_AVI |
813 VIDEO_DIP_ENABLE_VENDOR | VIDEO_DIP_ENABLE_GAMUT |
814 VIDEO_DIP_ENABLE_SPD | VIDEO_DIP_ENABLE_GCP);
815
816 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
817 val |= VIDEO_DIP_ENABLE_GCP;
818
819 I915_WRITE(reg, val);
820 POSTING_READ(reg);
821
822 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
823 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
824 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
825 }
826
827 static void hsw_set_infoframes(struct drm_encoder *encoder,
828 bool enable,
829 const struct intel_crtc_state *crtc_state,
830 const struct drm_connector_state *conn_state)
831 {
832 struct drm_i915_private *dev_priv = to_i915(encoder->dev);
833 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(encoder);
834 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
835 u32 val = I915_READ(reg);
836
837 assert_hdmi_port_disabled(intel_hdmi);
838
839 val &= ~(VIDEO_DIP_ENABLE_VSC_HSW | VIDEO_DIP_ENABLE_AVI_HSW |
840 VIDEO_DIP_ENABLE_GCP_HSW | VIDEO_DIP_ENABLE_VS_HSW |
841 VIDEO_DIP_ENABLE_GMP_HSW | VIDEO_DIP_ENABLE_SPD_HSW);
842
843 if (!enable) {
844 I915_WRITE(reg, val);
845 POSTING_READ(reg);
846 return;
847 }
848
849 if (intel_hdmi_set_gcp_infoframe(encoder, crtc_state, conn_state))
850 val |= VIDEO_DIP_ENABLE_GCP_HSW;
851
852 I915_WRITE(reg, val);
853 POSTING_READ(reg);
854
855 intel_hdmi_set_avi_infoframe(encoder, crtc_state);
856 intel_hdmi_set_spd_infoframe(encoder, crtc_state);
857 intel_hdmi_set_hdmi_infoframe(encoder, crtc_state);
858 }
859
860 void intel_dp_dual_mode_set_tmds_output(struct intel_hdmi *hdmi, bool enable)
861 {
862 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
863 struct i2c_adapter *adapter =
864 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
865
866 if (hdmi->dp_dual_mode.type < DRM_DP_DUAL_MODE_TYPE2_DVI)
867 return;
868
869 DRM_DEBUG_KMS("%s DP dual mode adaptor TMDS output\n",
870 enable ? "Enabling" : "Disabling");
871
872 drm_dp_dual_mode_set_tmds_output(hdmi->dp_dual_mode.type,
873 adapter, enable);
874 }
875
876 static void intel_hdmi_prepare(struct intel_encoder *encoder,
877 const struct intel_crtc_state *crtc_state)
878 {
879 struct drm_device *dev = encoder->base.dev;
880 struct drm_i915_private *dev_priv = to_i915(dev);
881 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
882 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
883 const struct drm_display_mode *adjusted_mode = &crtc_state->base.adjusted_mode;
884 u32 hdmi_val;
885
886 intel_dp_dual_mode_set_tmds_output(intel_hdmi, true);
887
888 hdmi_val = SDVO_ENCODING_HDMI;
889 if (!HAS_PCH_SPLIT(dev_priv) && crtc_state->limited_color_range)
890 hdmi_val |= HDMI_COLOR_RANGE_16_235;
891 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
892 hdmi_val |= SDVO_VSYNC_ACTIVE_HIGH;
893 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
894 hdmi_val |= SDVO_HSYNC_ACTIVE_HIGH;
895
896 if (crtc_state->pipe_bpp > 24)
897 hdmi_val |= HDMI_COLOR_FORMAT_12bpc;
898 else
899 hdmi_val |= SDVO_COLOR_FORMAT_8bpc;
900
901 if (crtc_state->has_hdmi_sink)
902 hdmi_val |= HDMI_MODE_SELECT_HDMI;
903
904 if (HAS_PCH_CPT(dev_priv))
905 hdmi_val |= SDVO_PIPE_SEL_CPT(crtc->pipe);
906 else if (IS_CHERRYVIEW(dev_priv))
907 hdmi_val |= SDVO_PIPE_SEL_CHV(crtc->pipe);
908 else
909 hdmi_val |= SDVO_PIPE_SEL(crtc->pipe);
910
911 I915_WRITE(intel_hdmi->hdmi_reg, hdmi_val);
912 POSTING_READ(intel_hdmi->hdmi_reg);
913 }
914
915 static bool intel_hdmi_get_hw_state(struct intel_encoder *encoder,
916 enum pipe *pipe)
917 {
918 struct drm_device *dev = encoder->base.dev;
919 struct drm_i915_private *dev_priv = to_i915(dev);
920 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
921 u32 tmp;
922 bool ret;
923
924 if (!intel_display_power_get_if_enabled(dev_priv,
925 encoder->power_domain))
926 return false;
927
928 ret = false;
929
930 tmp = I915_READ(intel_hdmi->hdmi_reg);
931
932 if (!(tmp & SDVO_ENABLE))
933 goto out;
934
935 if (HAS_PCH_CPT(dev_priv))
936 *pipe = PORT_TO_PIPE_CPT(tmp);
937 else if (IS_CHERRYVIEW(dev_priv))
938 *pipe = SDVO_PORT_TO_PIPE_CHV(tmp);
939 else
940 *pipe = PORT_TO_PIPE(tmp);
941
942 ret = true;
943
944 out:
945 intel_display_power_put(dev_priv, encoder->power_domain);
946
947 return ret;
948 }
949
950 static void intel_hdmi_get_config(struct intel_encoder *encoder,
951 struct intel_crtc_state *pipe_config)
952 {
953 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
954 struct intel_digital_port *intel_dig_port = hdmi_to_dig_port(intel_hdmi);
955 struct drm_device *dev = encoder->base.dev;
956 struct drm_i915_private *dev_priv = to_i915(dev);
957 u32 tmp, flags = 0;
958 int dotclock;
959
960 tmp = I915_READ(intel_hdmi->hdmi_reg);
961
962 if (tmp & SDVO_HSYNC_ACTIVE_HIGH)
963 flags |= DRM_MODE_FLAG_PHSYNC;
964 else
965 flags |= DRM_MODE_FLAG_NHSYNC;
966
967 if (tmp & SDVO_VSYNC_ACTIVE_HIGH)
968 flags |= DRM_MODE_FLAG_PVSYNC;
969 else
970 flags |= DRM_MODE_FLAG_NVSYNC;
971
972 if (tmp & HDMI_MODE_SELECT_HDMI)
973 pipe_config->has_hdmi_sink = true;
974
975 if (intel_dig_port->infoframe_enabled(&encoder->base, pipe_config))
976 pipe_config->has_infoframe = true;
977
978 if (tmp & SDVO_AUDIO_ENABLE)
979 pipe_config->has_audio = true;
980
981 if (!HAS_PCH_SPLIT(dev_priv) &&
982 tmp & HDMI_COLOR_RANGE_16_235)
983 pipe_config->limited_color_range = true;
984
985 pipe_config->base.adjusted_mode.flags |= flags;
986
987 if ((tmp & SDVO_COLOR_FORMAT_MASK) == HDMI_COLOR_FORMAT_12bpc)
988 dotclock = pipe_config->port_clock * 2 / 3;
989 else
990 dotclock = pipe_config->port_clock;
991
992 if (pipe_config->pixel_multiplier)
993 dotclock /= pipe_config->pixel_multiplier;
994
995 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
996
997 pipe_config->lane_count = 4;
998 }
999
1000 static void intel_enable_hdmi_audio(struct intel_encoder *encoder,
1001 const struct intel_crtc_state *pipe_config,
1002 const struct drm_connector_state *conn_state)
1003 {
1004 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1005
1006 WARN_ON(!pipe_config->has_hdmi_sink);
1007 DRM_DEBUG_DRIVER("Enabling HDMI audio on pipe %c\n",
1008 pipe_name(crtc->pipe));
1009 intel_audio_codec_enable(encoder, pipe_config, conn_state);
1010 }
1011
1012 static void g4x_enable_hdmi(struct intel_encoder *encoder,
1013 const struct intel_crtc_state *pipe_config,
1014 const struct drm_connector_state *conn_state)
1015 {
1016 struct drm_device *dev = encoder->base.dev;
1017 struct drm_i915_private *dev_priv = to_i915(dev);
1018 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1019 u32 temp;
1020
1021 temp = I915_READ(intel_hdmi->hdmi_reg);
1022
1023 temp |= SDVO_ENABLE;
1024 if (pipe_config->has_audio)
1025 temp |= SDVO_AUDIO_ENABLE;
1026
1027 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1028 POSTING_READ(intel_hdmi->hdmi_reg);
1029
1030 if (pipe_config->has_audio)
1031 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1032 }
1033
1034 static void ibx_enable_hdmi(struct intel_encoder *encoder,
1035 const struct intel_crtc_state *pipe_config,
1036 const struct drm_connector_state *conn_state)
1037 {
1038 struct drm_device *dev = encoder->base.dev;
1039 struct drm_i915_private *dev_priv = to_i915(dev);
1040 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1041 u32 temp;
1042
1043 temp = I915_READ(intel_hdmi->hdmi_reg);
1044
1045 temp |= SDVO_ENABLE;
1046 if (pipe_config->has_audio)
1047 temp |= SDVO_AUDIO_ENABLE;
1048
1049 /*
1050 * HW workaround, need to write this twice for issue
1051 * that may result in first write getting masked.
1052 */
1053 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1054 POSTING_READ(intel_hdmi->hdmi_reg);
1055 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1056 POSTING_READ(intel_hdmi->hdmi_reg);
1057
1058 /*
1059 * HW workaround, need to toggle enable bit off and on
1060 * for 12bpc with pixel repeat.
1061 *
1062 * FIXME: BSpec says this should be done at the end of
1063 * of the modeset sequence, so not sure if this isn't too soon.
1064 */
1065 if (pipe_config->pipe_bpp > 24 &&
1066 pipe_config->pixel_multiplier > 1) {
1067 I915_WRITE(intel_hdmi->hdmi_reg, temp & ~SDVO_ENABLE);
1068 POSTING_READ(intel_hdmi->hdmi_reg);
1069
1070 /*
1071 * HW workaround, need to write this twice for issue
1072 * that may result in first write getting masked.
1073 */
1074 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1075 POSTING_READ(intel_hdmi->hdmi_reg);
1076 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1077 POSTING_READ(intel_hdmi->hdmi_reg);
1078 }
1079
1080 if (pipe_config->has_audio)
1081 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1082 }
1083
1084 static void cpt_enable_hdmi(struct intel_encoder *encoder,
1085 const struct intel_crtc_state *pipe_config,
1086 const struct drm_connector_state *conn_state)
1087 {
1088 struct drm_device *dev = encoder->base.dev;
1089 struct drm_i915_private *dev_priv = to_i915(dev);
1090 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
1091 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1092 enum pipe pipe = crtc->pipe;
1093 u32 temp;
1094
1095 temp = I915_READ(intel_hdmi->hdmi_reg);
1096
1097 temp |= SDVO_ENABLE;
1098 if (pipe_config->has_audio)
1099 temp |= SDVO_AUDIO_ENABLE;
1100
1101 /*
1102 * WaEnableHDMI8bpcBefore12bpc:snb,ivb
1103 *
1104 * The procedure for 12bpc is as follows:
1105 * 1. disable HDMI clock gating
1106 * 2. enable HDMI with 8bpc
1107 * 3. enable HDMI with 12bpc
1108 * 4. enable HDMI clock gating
1109 */
1110
1111 if (pipe_config->pipe_bpp > 24) {
1112 I915_WRITE(TRANS_CHICKEN1(pipe),
1113 I915_READ(TRANS_CHICKEN1(pipe)) |
1114 TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1115
1116 temp &= ~SDVO_COLOR_FORMAT_MASK;
1117 temp |= SDVO_COLOR_FORMAT_8bpc;
1118 }
1119
1120 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1121 POSTING_READ(intel_hdmi->hdmi_reg);
1122
1123 if (pipe_config->pipe_bpp > 24) {
1124 temp &= ~SDVO_COLOR_FORMAT_MASK;
1125 temp |= HDMI_COLOR_FORMAT_12bpc;
1126
1127 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1128 POSTING_READ(intel_hdmi->hdmi_reg);
1129
1130 I915_WRITE(TRANS_CHICKEN1(pipe),
1131 I915_READ(TRANS_CHICKEN1(pipe)) &
1132 ~TRANS_CHICKEN1_HDMIUNIT_GC_DISABLE);
1133 }
1134
1135 if (pipe_config->has_audio)
1136 intel_enable_hdmi_audio(encoder, pipe_config, conn_state);
1137 }
1138
1139 static void vlv_enable_hdmi(struct intel_encoder *encoder,
1140 const struct intel_crtc_state *pipe_config,
1141 const struct drm_connector_state *conn_state)
1142 {
1143 }
1144
1145 static void intel_disable_hdmi(struct intel_encoder *encoder,
1146 const struct intel_crtc_state *old_crtc_state,
1147 const struct drm_connector_state *old_conn_state)
1148 {
1149 struct drm_device *dev = encoder->base.dev;
1150 struct drm_i915_private *dev_priv = to_i915(dev);
1151 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1152 struct intel_digital_port *intel_dig_port =
1153 hdmi_to_dig_port(intel_hdmi);
1154 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1155 u32 temp;
1156
1157 temp = I915_READ(intel_hdmi->hdmi_reg);
1158
1159 temp &= ~(SDVO_ENABLE | SDVO_AUDIO_ENABLE);
1160 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1161 POSTING_READ(intel_hdmi->hdmi_reg);
1162
1163 /*
1164 * HW workaround for IBX, we need to move the port
1165 * to transcoder A after disabling it to allow the
1166 * matching DP port to be enabled on transcoder A.
1167 */
1168 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B) {
1169 /*
1170 * We get CPU/PCH FIFO underruns on the other pipe when
1171 * doing the workaround. Sweep them under the rug.
1172 */
1173 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1174 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
1175
1176 temp &= ~SDVO_PIPE_B_SELECT;
1177 temp |= SDVO_ENABLE;
1178 /*
1179 * HW workaround, need to write this twice for issue
1180 * that may result in first write getting masked.
1181 */
1182 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1183 POSTING_READ(intel_hdmi->hdmi_reg);
1184 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1185 POSTING_READ(intel_hdmi->hdmi_reg);
1186
1187 temp &= ~SDVO_ENABLE;
1188 I915_WRITE(intel_hdmi->hdmi_reg, temp);
1189 POSTING_READ(intel_hdmi->hdmi_reg);
1190
1191 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
1192 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1193 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
1194 }
1195
1196 intel_dig_port->set_infoframes(&encoder->base, false,
1197 old_crtc_state, old_conn_state);
1198
1199 intel_dp_dual_mode_set_tmds_output(intel_hdmi, false);
1200 }
1201
1202 static void g4x_disable_hdmi(struct intel_encoder *encoder,
1203 const struct intel_crtc_state *old_crtc_state,
1204 const struct drm_connector_state *old_conn_state)
1205 {
1206 if (old_crtc_state->has_audio)
1207 intel_audio_codec_disable(encoder);
1208
1209 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1210 }
1211
1212 static void pch_disable_hdmi(struct intel_encoder *encoder,
1213 const struct intel_crtc_state *old_crtc_state,
1214 const struct drm_connector_state *old_conn_state)
1215 {
1216 if (old_crtc_state->has_audio)
1217 intel_audio_codec_disable(encoder);
1218 }
1219
1220 static void pch_post_disable_hdmi(struct intel_encoder *encoder,
1221 const struct intel_crtc_state *old_crtc_state,
1222 const struct drm_connector_state *old_conn_state)
1223 {
1224 intel_disable_hdmi(encoder, old_crtc_state, old_conn_state);
1225 }
1226
1227 static int intel_hdmi_source_max_tmds_clock(struct drm_i915_private *dev_priv)
1228 {
1229 if (IS_G4X(dev_priv))
1230 return 165000;
1231 else if (IS_GEMINILAKE(dev_priv))
1232 return 594000;
1233 else if (IS_HASWELL(dev_priv) || INTEL_INFO(dev_priv)->gen >= 8)
1234 return 300000;
1235 else
1236 return 225000;
1237 }
1238
1239 static int hdmi_port_clock_limit(struct intel_hdmi *hdmi,
1240 bool respect_downstream_limits,
1241 bool force_dvi)
1242 {
1243 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1244 int max_tmds_clock = intel_hdmi_source_max_tmds_clock(to_i915(dev));
1245
1246 if (respect_downstream_limits) {
1247 struct intel_connector *connector = hdmi->attached_connector;
1248 const struct drm_display_info *info = &connector->base.display_info;
1249
1250 if (hdmi->dp_dual_mode.max_tmds_clock)
1251 max_tmds_clock = min(max_tmds_clock,
1252 hdmi->dp_dual_mode.max_tmds_clock);
1253
1254 if (info->max_tmds_clock)
1255 max_tmds_clock = min(max_tmds_clock,
1256 info->max_tmds_clock);
1257 else if (!hdmi->has_hdmi_sink || force_dvi)
1258 max_tmds_clock = min(max_tmds_clock, 165000);
1259 }
1260
1261 return max_tmds_clock;
1262 }
1263
1264 static enum drm_mode_status
1265 hdmi_port_clock_valid(struct intel_hdmi *hdmi,
1266 int clock, bool respect_downstream_limits,
1267 bool force_dvi)
1268 {
1269 struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
1270
1271 if (clock < 25000)
1272 return MODE_CLOCK_LOW;
1273 if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits, force_dvi))
1274 return MODE_CLOCK_HIGH;
1275
1276 /* BXT DPLL can't generate 223-240 MHz */
1277 if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000)
1278 return MODE_CLOCK_RANGE;
1279
1280 /* CHV DPLL can't generate 216-240 MHz */
1281 if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000)
1282 return MODE_CLOCK_RANGE;
1283
1284 return MODE_OK;
1285 }
1286
1287 static enum drm_mode_status
1288 intel_hdmi_mode_valid(struct drm_connector *connector,
1289 struct drm_display_mode *mode)
1290 {
1291 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1292 struct drm_device *dev = intel_hdmi_to_dev(hdmi);
1293 struct drm_i915_private *dev_priv = to_i915(dev);
1294 enum drm_mode_status status;
1295 int clock;
1296 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq;
1297 bool force_dvi =
1298 READ_ONCE(to_intel_digital_connector_state(connector->state)->force_audio) == HDMI_AUDIO_OFF_DVI;
1299
1300 if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
1301 return MODE_NO_DBLESCAN;
1302
1303 clock = mode->clock;
1304
1305 if ((mode->flags & DRM_MODE_FLAG_3D_MASK) == DRM_MODE_FLAG_3D_FRAME_PACKING)
1306 clock *= 2;
1307
1308 if (clock > max_dotclk)
1309 return MODE_CLOCK_HIGH;
1310
1311 if (mode->flags & DRM_MODE_FLAG_DBLCLK)
1312 clock *= 2;
1313
1314 if (drm_mode_is_420_only(&connector->display_info, mode))
1315 clock /= 2;
1316
1317 /* check if we can do 8bpc */
1318 status = hdmi_port_clock_valid(hdmi, clock, true, force_dvi);
1319
1320 /* if we can't do 8bpc we may still be able to do 12bpc */
1321 if (!HAS_GMCH_DISPLAY(dev_priv) && status != MODE_OK && hdmi->has_hdmi_sink && !force_dvi)
1322 status = hdmi_port_clock_valid(hdmi, clock * 3 / 2, true, force_dvi);
1323
1324 return status;
1325 }
1326
1327 static bool hdmi_12bpc_possible(const struct intel_crtc_state *crtc_state)
1328 {
1329 struct drm_i915_private *dev_priv =
1330 to_i915(crtc_state->base.crtc->dev);
1331 struct drm_atomic_state *state = crtc_state->base.state;
1332 struct drm_connector_state *connector_state;
1333 struct drm_connector *connector;
1334 int i;
1335
1336 if (HAS_GMCH_DISPLAY(dev_priv))
1337 return false;
1338
1339 /*
1340 * HDMI 12bpc affects the clocks, so it's only possible
1341 * when not cloning with other encoder types.
1342 */
1343 if (crtc_state->output_types != 1 << INTEL_OUTPUT_HDMI)
1344 return false;
1345
1346 for_each_new_connector_in_state(state, connector, connector_state, i) {
1347 const struct drm_display_info *info = &connector->display_info;
1348
1349 if (connector_state->crtc != crtc_state->base.crtc)
1350 continue;
1351
1352 if (crtc_state->ycbcr420) {
1353 const struct drm_hdmi_info *hdmi = &info->hdmi;
1354
1355 if (!(hdmi->y420_dc_modes & DRM_EDID_YCBCR420_DC_36))
1356 return false;
1357 } else {
1358 if (!(info->edid_hdmi_dc_modes & DRM_EDID_HDMI_DC_36))
1359 return false;
1360 }
1361 }
1362
1363 /* Display Wa #1139 */
1364 if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1) &&
1365 crtc_state->base.adjusted_mode.htotal > 5460)
1366 return false;
1367
1368 return true;
1369 }
1370
1371 static bool
1372 intel_hdmi_ycbcr420_config(struct drm_connector *connector,
1373 struct intel_crtc_state *config,
1374 int *clock_12bpc, int *clock_8bpc)
1375 {
1376 struct intel_crtc *intel_crtc = to_intel_crtc(config->base.crtc);
1377
1378 if (!connector->ycbcr_420_allowed) {
1379 DRM_ERROR("Platform doesn't support YCBCR420 output\n");
1380 return false;
1381 }
1382
1383 /* YCBCR420 TMDS rate requirement is half the pixel clock */
1384 config->port_clock /= 2;
1385 *clock_12bpc /= 2;
1386 *clock_8bpc /= 2;
1387 config->ycbcr420 = true;
1388
1389 /* YCBCR 420 output conversion needs a scaler */
1390 if (skl_update_scaler_crtc(config)) {
1391 DRM_DEBUG_KMS("Scaler allocation for output failed\n");
1392 return false;
1393 }
1394
1395 intel_pch_panel_fitting(intel_crtc, config,
1396 DRM_MODE_SCALE_FULLSCREEN);
1397
1398 return true;
1399 }
1400
1401 bool intel_hdmi_compute_config(struct intel_encoder *encoder,
1402 struct intel_crtc_state *pipe_config,
1403 struct drm_connector_state *conn_state)
1404 {
1405 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1406 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1407 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1408 struct drm_connector *connector = conn_state->connector;
1409 struct drm_scdc *scdc = &connector->display_info.hdmi.scdc;
1410 struct intel_digital_connector_state *intel_conn_state =
1411 to_intel_digital_connector_state(conn_state);
1412 int clock_8bpc = pipe_config->base.adjusted_mode.crtc_clock;
1413 int clock_12bpc = clock_8bpc * 3 / 2;
1414 int desired_bpp;
1415 bool force_dvi = intel_conn_state->force_audio == HDMI_AUDIO_OFF_DVI;
1416
1417 pipe_config->has_hdmi_sink = !force_dvi && intel_hdmi->has_hdmi_sink;
1418
1419 if (pipe_config->has_hdmi_sink)
1420 pipe_config->has_infoframe = true;
1421
1422 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) {
1423 /* See CEA-861-E - 5.1 Default Encoding Parameters */
1424 pipe_config->limited_color_range =
1425 pipe_config->has_hdmi_sink &&
1426 drm_default_rgb_quant_range(adjusted_mode) ==
1427 HDMI_QUANTIZATION_RANGE_LIMITED;
1428 } else {
1429 pipe_config->limited_color_range =
1430 intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_LIMITED;
1431 }
1432
1433 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
1434 pipe_config->pixel_multiplier = 2;
1435 clock_8bpc *= 2;
1436 clock_12bpc *= 2;
1437 }
1438
1439 if (drm_mode_is_420_only(&connector->display_info, adjusted_mode)) {
1440 if (!intel_hdmi_ycbcr420_config(connector, pipe_config,
1441 &clock_12bpc, &clock_8bpc)) {
1442 DRM_ERROR("Can't support YCBCR420 output\n");
1443 return false;
1444 }
1445 }
1446
1447 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv))
1448 pipe_config->has_pch_encoder = true;
1449
1450 if (pipe_config->has_hdmi_sink) {
1451 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO)
1452 pipe_config->has_audio = intel_hdmi->has_audio;
1453 else
1454 pipe_config->has_audio =
1455 intel_conn_state->force_audio == HDMI_AUDIO_ON;
1456 }
1457
1458 /*
1459 * HDMI is either 12 or 8, so if the display lets 10bpc sneak
1460 * through, clamp it down. Note that g4x/vlv don't support 12bpc hdmi
1461 * outputs. We also need to check that the higher clock still fits
1462 * within limits.
1463 */
1464 if (pipe_config->pipe_bpp > 8*3 && pipe_config->has_hdmi_sink && !force_dvi &&
1465 hdmi_port_clock_valid(intel_hdmi, clock_12bpc, true, force_dvi) == MODE_OK &&
1466 hdmi_12bpc_possible(pipe_config)) {
1467 DRM_DEBUG_KMS("picking bpc to 12 for HDMI output\n");
1468 desired_bpp = 12*3;
1469
1470 /* Need to adjust the port link by 1.5x for 12bpc. */
1471 pipe_config->port_clock = clock_12bpc;
1472 } else {
1473 DRM_DEBUG_KMS("picking bpc to 8 for HDMI output\n");
1474 desired_bpp = 8*3;
1475
1476 pipe_config->port_clock = clock_8bpc;
1477 }
1478
1479 if (!pipe_config->bw_constrained) {
1480 DRM_DEBUG_KMS("forcing pipe bpp to %i for HDMI\n", desired_bpp);
1481 pipe_config->pipe_bpp = desired_bpp;
1482 }
1483
1484 if (hdmi_port_clock_valid(intel_hdmi, pipe_config->port_clock,
1485 false, force_dvi) != MODE_OK) {
1486 DRM_DEBUG_KMS("unsupported HDMI clock, rejecting mode\n");
1487 return false;
1488 }
1489
1490 /* Set user selected PAR to incoming mode's member */
1491 adjusted_mode->picture_aspect_ratio = conn_state->picture_aspect_ratio;
1492
1493 pipe_config->lane_count = 4;
1494
1495 if (scdc->scrambling.supported && IS_GEMINILAKE(dev_priv)) {
1496 if (scdc->scrambling.low_rates)
1497 pipe_config->hdmi_scrambling = true;
1498
1499 if (pipe_config->port_clock > 340000) {
1500 pipe_config->hdmi_scrambling = true;
1501 pipe_config->hdmi_high_tmds_clock_ratio = true;
1502 }
1503 }
1504
1505 return true;
1506 }
1507
1508 static void
1509 intel_hdmi_unset_edid(struct drm_connector *connector)
1510 {
1511 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1512
1513 intel_hdmi->has_hdmi_sink = false;
1514 intel_hdmi->has_audio = false;
1515 intel_hdmi->rgb_quant_range_selectable = false;
1516
1517 intel_hdmi->dp_dual_mode.type = DRM_DP_DUAL_MODE_NONE;
1518 intel_hdmi->dp_dual_mode.max_tmds_clock = 0;
1519
1520 kfree(to_intel_connector(connector)->detect_edid);
1521 to_intel_connector(connector)->detect_edid = NULL;
1522 }
1523
1524 static void
1525 intel_hdmi_dp_dual_mode_detect(struct drm_connector *connector, bool has_edid)
1526 {
1527 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1528 struct intel_hdmi *hdmi = intel_attached_hdmi(connector);
1529 enum port port = hdmi_to_dig_port(hdmi)->port;
1530 struct i2c_adapter *adapter =
1531 intel_gmbus_get_adapter(dev_priv, hdmi->ddc_bus);
1532 enum drm_dp_dual_mode_type type = drm_dp_dual_mode_detect(adapter);
1533
1534 /*
1535 * Type 1 DVI adaptors are not required to implement any
1536 * registers, so we can't always detect their presence.
1537 * Ideally we should be able to check the state of the
1538 * CONFIG1 pin, but no such luck on our hardware.
1539 *
1540 * The only method left to us is to check the VBT to see
1541 * if the port is a dual mode capable DP port. But let's
1542 * only do that when we sucesfully read the EDID, to avoid
1543 * confusing log messages about DP dual mode adaptors when
1544 * there's nothing connected to the port.
1545 */
1546 if (type == DRM_DP_DUAL_MODE_UNKNOWN) {
1547 if (has_edid &&
1548 intel_bios_is_port_dp_dual_mode(dev_priv, port)) {
1549 DRM_DEBUG_KMS("Assuming DP dual mode adaptor presence based on VBT\n");
1550 type = DRM_DP_DUAL_MODE_TYPE1_DVI;
1551 } else {
1552 type = DRM_DP_DUAL_MODE_NONE;
1553 }
1554 }
1555
1556 if (type == DRM_DP_DUAL_MODE_NONE)
1557 return;
1558
1559 hdmi->dp_dual_mode.type = type;
1560 hdmi->dp_dual_mode.max_tmds_clock =
1561 drm_dp_dual_mode_max_tmds_clock(type, adapter);
1562
1563 DRM_DEBUG_KMS("DP dual mode adaptor (%s) detected (max TMDS clock: %d kHz)\n",
1564 drm_dp_get_dual_mode_type_name(type),
1565 hdmi->dp_dual_mode.max_tmds_clock);
1566 }
1567
1568 static bool
1569 intel_hdmi_set_edid(struct drm_connector *connector)
1570 {
1571 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1572 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1573 struct edid *edid;
1574 bool connected = false;
1575
1576 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1577
1578 edid = drm_get_edid(connector,
1579 intel_gmbus_get_adapter(dev_priv,
1580 intel_hdmi->ddc_bus));
1581
1582 intel_hdmi_dp_dual_mode_detect(connector, edid != NULL);
1583
1584 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1585
1586 to_intel_connector(connector)->detect_edid = edid;
1587 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) {
1588 intel_hdmi->rgb_quant_range_selectable =
1589 drm_rgb_quant_range_selectable(edid);
1590
1591 intel_hdmi->has_audio = drm_detect_monitor_audio(edid);
1592 intel_hdmi->has_hdmi_sink = drm_detect_hdmi_monitor(edid);
1593
1594 connected = true;
1595 }
1596
1597 return connected;
1598 }
1599
1600 static enum drm_connector_status
1601 intel_hdmi_detect(struct drm_connector *connector, bool force)
1602 {
1603 enum drm_connector_status status;
1604 struct drm_i915_private *dev_priv = to_i915(connector->dev);
1605
1606 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1607 connector->base.id, connector->name);
1608
1609 intel_display_power_get(dev_priv, POWER_DOMAIN_GMBUS);
1610
1611 intel_hdmi_unset_edid(connector);
1612
1613 if (intel_hdmi_set_edid(connector)) {
1614 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1615
1616 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1617 status = connector_status_connected;
1618 } else
1619 status = connector_status_disconnected;
1620
1621 intel_display_power_put(dev_priv, POWER_DOMAIN_GMBUS);
1622
1623 return status;
1624 }
1625
1626 static void
1627 intel_hdmi_force(struct drm_connector *connector)
1628 {
1629 struct intel_hdmi *intel_hdmi = intel_attached_hdmi(connector);
1630
1631 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
1632 connector->base.id, connector->name);
1633
1634 intel_hdmi_unset_edid(connector);
1635
1636 if (connector->status != connector_status_connected)
1637 return;
1638
1639 intel_hdmi_set_edid(connector);
1640 hdmi_to_dig_port(intel_hdmi)->base.type = INTEL_OUTPUT_HDMI;
1641 }
1642
1643 static int intel_hdmi_get_modes(struct drm_connector *connector)
1644 {
1645 struct edid *edid;
1646
1647 edid = to_intel_connector(connector)->detect_edid;
1648 if (edid == NULL)
1649 return 0;
1650
1651 return intel_connector_update_modes(connector, edid);
1652 }
1653
1654 static void intel_hdmi_pre_enable(struct intel_encoder *encoder,
1655 const struct intel_crtc_state *pipe_config,
1656 const struct drm_connector_state *conn_state)
1657 {
1658 struct intel_digital_port *intel_dig_port =
1659 enc_to_dig_port(&encoder->base);
1660
1661 intel_hdmi_prepare(encoder, pipe_config);
1662
1663 intel_dig_port->set_infoframes(&encoder->base,
1664 pipe_config->has_infoframe,
1665 pipe_config, conn_state);
1666 }
1667
1668 static void vlv_hdmi_pre_enable(struct intel_encoder *encoder,
1669 const struct intel_crtc_state *pipe_config,
1670 const struct drm_connector_state *conn_state)
1671 {
1672 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1673 struct drm_device *dev = encoder->base.dev;
1674 struct drm_i915_private *dev_priv = to_i915(dev);
1675
1676 vlv_phy_pre_encoder_enable(encoder);
1677
1678 /* HDMI 1.0V-2dB */
1679 vlv_set_phy_signal_level(encoder, 0x2b245f5f, 0x00002000, 0x5578b83a,
1680 0x2b247878);
1681
1682 dport->set_infoframes(&encoder->base,
1683 pipe_config->has_infoframe,
1684 pipe_config, conn_state);
1685
1686 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1687
1688 vlv_wait_port_ready(dev_priv, dport, 0x0);
1689 }
1690
1691 static void vlv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1692 const struct intel_crtc_state *pipe_config,
1693 const struct drm_connector_state *conn_state)
1694 {
1695 intel_hdmi_prepare(encoder, pipe_config);
1696
1697 vlv_phy_pre_pll_enable(encoder);
1698 }
1699
1700 static void chv_hdmi_pre_pll_enable(struct intel_encoder *encoder,
1701 const struct intel_crtc_state *pipe_config,
1702 const struct drm_connector_state *conn_state)
1703 {
1704 intel_hdmi_prepare(encoder, pipe_config);
1705
1706 chv_phy_pre_pll_enable(encoder);
1707 }
1708
1709 static void chv_hdmi_post_pll_disable(struct intel_encoder *encoder,
1710 const struct intel_crtc_state *old_crtc_state,
1711 const struct drm_connector_state *old_conn_state)
1712 {
1713 chv_phy_post_pll_disable(encoder);
1714 }
1715
1716 static void vlv_hdmi_post_disable(struct intel_encoder *encoder,
1717 const struct intel_crtc_state *old_crtc_state,
1718 const struct drm_connector_state *old_conn_state)
1719 {
1720 /* Reset lanes to avoid HDMI flicker (VLV w/a) */
1721 vlv_phy_reset_lanes(encoder);
1722 }
1723
1724 static void chv_hdmi_post_disable(struct intel_encoder *encoder,
1725 const struct intel_crtc_state *old_crtc_state,
1726 const struct drm_connector_state *old_conn_state)
1727 {
1728 struct drm_device *dev = encoder->base.dev;
1729 struct drm_i915_private *dev_priv = to_i915(dev);
1730
1731 mutex_lock(&dev_priv->sb_lock);
1732
1733 /* Assert data lane reset */
1734 chv_data_lane_soft_reset(encoder, true);
1735
1736 mutex_unlock(&dev_priv->sb_lock);
1737 }
1738
1739 static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
1740 const struct intel_crtc_state *pipe_config,
1741 const struct drm_connector_state *conn_state)
1742 {
1743 struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1744 struct drm_device *dev = encoder->base.dev;
1745 struct drm_i915_private *dev_priv = to_i915(dev);
1746
1747 chv_phy_pre_encoder_enable(encoder);
1748
1749 /* FIXME: Program the support xxx V-dB */
1750 /* Use 800mV-0dB */
1751 chv_set_phy_signal_level(encoder, 128, 102, false);
1752
1753 dport->set_infoframes(&encoder->base,
1754 pipe_config->has_infoframe,
1755 pipe_config, conn_state);
1756
1757 g4x_enable_hdmi(encoder, pipe_config, conn_state);
1758
1759 vlv_wait_port_ready(dev_priv, dport, 0x0);
1760
1761 /* Second common lane will stay alive on its own now */
1762 chv_phy_release_cl2_override(encoder);
1763 }
1764
1765 static void intel_hdmi_destroy(struct drm_connector *connector)
1766 {
1767 kfree(to_intel_connector(connector)->detect_edid);
1768 drm_connector_cleanup(connector);
1769 kfree(connector);
1770 }
1771
1772 static const struct drm_connector_funcs intel_hdmi_connector_funcs = {
1773 .detect = intel_hdmi_detect,
1774 .force = intel_hdmi_force,
1775 .fill_modes = drm_helper_probe_single_connector_modes,
1776 .atomic_get_property = intel_digital_connector_atomic_get_property,
1777 .atomic_set_property = intel_digital_connector_atomic_set_property,
1778 .late_register = intel_connector_register,
1779 .early_unregister = intel_connector_unregister,
1780 .destroy = intel_hdmi_destroy,
1781 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1782 .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1783 };
1784
1785 static const struct drm_connector_helper_funcs intel_hdmi_connector_helper_funcs = {
1786 .get_modes = intel_hdmi_get_modes,
1787 .mode_valid = intel_hdmi_mode_valid,
1788 .atomic_check = intel_digital_connector_atomic_check,
1789 };
1790
1791 static const struct drm_encoder_funcs intel_hdmi_enc_funcs = {
1792 .destroy = intel_encoder_destroy,
1793 };
1794
1795 static void
1796 intel_hdmi_add_properties(struct intel_hdmi *intel_hdmi, struct drm_connector *connector)
1797 {
1798 intel_attach_force_audio_property(connector);
1799 intel_attach_broadcast_rgb_property(connector);
1800 intel_attach_aspect_ratio_property(connector);
1801 connector->state->picture_aspect_ratio = HDMI_PICTURE_ASPECT_NONE;
1802 }
1803
1804 /*
1805 * intel_hdmi_handle_sink_scrambling: handle sink scrambling/clock ratio setup
1806 * @encoder: intel_encoder
1807 * @connector: drm_connector
1808 * @high_tmds_clock_ratio = bool to indicate if the function needs to set
1809 * or reset the high tmds clock ratio for scrambling
1810 * @scrambling: bool to Indicate if the function needs to set or reset
1811 * sink scrambling
1812 *
1813 * This function handles scrambling on HDMI 2.0 capable sinks.
1814 * If required clock rate is > 340 Mhz && scrambling is supported by sink
1815 * it enables scrambling. This should be called before enabling the HDMI
1816 * 2.0 port, as the sink can choose to disable the scrambling if it doesn't
1817 * detect a scrambled clock within 100 ms.
1818 */
1819 void intel_hdmi_handle_sink_scrambling(struct intel_encoder *encoder,
1820 struct drm_connector *connector,
1821 bool high_tmds_clock_ratio,
1822 bool scrambling)
1823 {
1824 struct intel_hdmi *intel_hdmi = enc_to_intel_hdmi(&encoder->base);
1825 struct drm_i915_private *dev_priv = connector->dev->dev_private;
1826 struct drm_scrambling *sink_scrambling =
1827 &connector->display_info.hdmi.scdc.scrambling;
1828 struct i2c_adapter *adptr = intel_gmbus_get_adapter(dev_priv,
1829 intel_hdmi->ddc_bus);
1830 bool ret;
1831
1832 if (!sink_scrambling->supported)
1833 return;
1834
1835 DRM_DEBUG_KMS("Setting sink scrambling for enc:%s connector:%s\n",
1836 encoder->base.name, connector->name);
1837
1838 /* Set TMDS bit clock ratio to 1/40 or 1/10 */
1839 ret = drm_scdc_set_high_tmds_clock_ratio(adptr, high_tmds_clock_ratio);
1840 if (!ret) {
1841 DRM_ERROR("Set TMDS ratio failed\n");
1842 return;
1843 }
1844
1845 /* Enable/disable sink scrambling */
1846 ret = drm_scdc_set_scrambling(adptr, scrambling);
1847 if (!ret) {
1848 DRM_ERROR("Set sink scrambling failed\n");
1849 return;
1850 }
1851
1852 DRM_DEBUG_KMS("sink scrambling handled\n");
1853 }
1854
1855 static u8 chv_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
1856 {
1857 u8 ddc_pin;
1858
1859 switch (port) {
1860 case PORT_B:
1861 ddc_pin = GMBUS_PIN_DPB;
1862 break;
1863 case PORT_C:
1864 ddc_pin = GMBUS_PIN_DPC;
1865 break;
1866 case PORT_D:
1867 ddc_pin = GMBUS_PIN_DPD_CHV;
1868 break;
1869 default:
1870 MISSING_CASE(port);
1871 ddc_pin = GMBUS_PIN_DPB;
1872 break;
1873 }
1874 return ddc_pin;
1875 }
1876
1877 static u8 bxt_port_to_ddc_pin(struct drm_i915_private *dev_priv, enum port port)
1878 {
1879 u8 ddc_pin;
1880
1881 switch (port) {
1882 case PORT_B:
1883 ddc_pin = GMBUS_PIN_1_BXT;
1884 break;
1885 case PORT_C:
1886 ddc_pin = GMBUS_PIN_2_BXT;
1887 break;
1888 default:
1889 MISSING_CASE(port);
1890 ddc_pin = GMBUS_PIN_1_BXT;
1891 break;
1892 }
1893 return ddc_pin;
1894 }
1895
1896 static u8 cnp_port_to_ddc_pin(struct drm_i915_private *dev_priv,
1897 enum port port)
1898 {
1899 u8 ddc_pin;
1900
1901 switch (port) {
1902 case PORT_B:
1903 ddc_pin = GMBUS_PIN_1_BXT;
1904 break;
1905 case PORT_C:
1906 ddc_pin = GMBUS_PIN_2_BXT;
1907 break;
1908 case PORT_D:
1909 ddc_pin = GMBUS_PIN_4_CNP;
1910 break;
1911 default:
1912 MISSING_CASE(port);
1913 ddc_pin = GMBUS_PIN_1_BXT;
1914 break;
1915 }
1916 return ddc_pin;
1917 }
1918
1919 static u8 g4x_port_to_ddc_pin(struct drm_i915_private *dev_priv,
1920 enum port port)
1921 {
1922 u8 ddc_pin;
1923
1924 switch (port) {
1925 case PORT_B:
1926 ddc_pin = GMBUS_PIN_DPB;
1927 break;
1928 case PORT_C:
1929 ddc_pin = GMBUS_PIN_DPC;
1930 break;
1931 case PORT_D:
1932 ddc_pin = GMBUS_PIN_DPD;
1933 break;
1934 default:
1935 MISSING_CASE(port);
1936 ddc_pin = GMBUS_PIN_DPB;
1937 break;
1938 }
1939 return ddc_pin;
1940 }
1941
1942 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv,
1943 enum port port)
1944 {
1945 const struct ddi_vbt_port_info *info =
1946 &dev_priv->vbt.ddi_port_info[port];
1947 u8 ddc_pin;
1948
1949 if (info->alternate_ddc_pin) {
1950 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n",
1951 info->alternate_ddc_pin, port_name(port));
1952 return info->alternate_ddc_pin;
1953 }
1954
1955 if (IS_CHERRYVIEW(dev_priv))
1956 ddc_pin = chv_port_to_ddc_pin(dev_priv, port);
1957 else if (IS_GEN9_LP(dev_priv))
1958 ddc_pin = bxt_port_to_ddc_pin(dev_priv, port);
1959 else if (HAS_PCH_CNP(dev_priv))
1960 ddc_pin = cnp_port_to_ddc_pin(dev_priv, port);
1961 else
1962 ddc_pin = g4x_port_to_ddc_pin(dev_priv, port);
1963
1964 DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n",
1965 ddc_pin, port_name(port));
1966
1967 return ddc_pin;
1968 }
1969
1970 void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
1971 {
1972 struct drm_i915_private *dev_priv =
1973 to_i915(intel_dig_port->base.base.dev);
1974
1975 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1976 intel_dig_port->write_infoframe = vlv_write_infoframe;
1977 intel_dig_port->set_infoframes = vlv_set_infoframes;
1978 intel_dig_port->infoframe_enabled = vlv_infoframe_enabled;
1979 } else if (IS_G4X(dev_priv)) {
1980 intel_dig_port->write_infoframe = g4x_write_infoframe;
1981 intel_dig_port->set_infoframes = g4x_set_infoframes;
1982 intel_dig_port->infoframe_enabled = g4x_infoframe_enabled;
1983 } else if (HAS_DDI(dev_priv)) {
1984 intel_dig_port->write_infoframe = hsw_write_infoframe;
1985 intel_dig_port->set_infoframes = hsw_set_infoframes;
1986 intel_dig_port->infoframe_enabled = hsw_infoframe_enabled;
1987 } else if (HAS_PCH_IBX(dev_priv)) {
1988 intel_dig_port->write_infoframe = ibx_write_infoframe;
1989 intel_dig_port->set_infoframes = ibx_set_infoframes;
1990 intel_dig_port->infoframe_enabled = ibx_infoframe_enabled;
1991 } else {
1992 intel_dig_port->write_infoframe = cpt_write_infoframe;
1993 intel_dig_port->set_infoframes = cpt_set_infoframes;
1994 intel_dig_port->infoframe_enabled = cpt_infoframe_enabled;
1995 }
1996 }
1997
1998 void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
1999 struct intel_connector *intel_connector)
2000 {
2001 struct drm_connector *connector = &intel_connector->base;
2002 struct intel_hdmi *intel_hdmi = &intel_dig_port->hdmi;
2003 struct intel_encoder *intel_encoder = &intel_dig_port->base;
2004 struct drm_device *dev = intel_encoder->base.dev;
2005 struct drm_i915_private *dev_priv = to_i915(dev);
2006 enum port port = intel_dig_port->port;
2007
2008 DRM_DEBUG_KMS("Adding HDMI connector on port %c\n",
2009 port_name(port));
2010
2011 if (WARN(intel_dig_port->max_lanes < 4,
2012 "Not enough lanes (%d) for HDMI on port %c\n",
2013 intel_dig_port->max_lanes, port_name(port)))
2014 return;
2015
2016 drm_connector_init(dev, connector, &intel_hdmi_connector_funcs,
2017 DRM_MODE_CONNECTOR_HDMIA);
2018 drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
2019
2020 connector->interlace_allowed = 1;
2021 connector->doublescan_allowed = 0;
2022 connector->stereo_allowed = 1;
2023
2024 if (IS_GEMINILAKE(dev_priv))
2025 connector->ycbcr_420_allowed = true;
2026
2027 intel_hdmi->ddc_bus = intel_hdmi_ddc_pin(dev_priv, port);
2028
2029 if (WARN_ON(port == PORT_A))
2030 return;
2031 intel_encoder->hpd_pin = intel_hpd_pin(port);
2032
2033 if (HAS_DDI(dev_priv))
2034 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2035 else
2036 intel_connector->get_hw_state = intel_connector_get_hw_state;
2037
2038 intel_hdmi_add_properties(intel_hdmi, connector);
2039
2040 intel_connector_attach_encoder(intel_connector, intel_encoder);
2041 intel_hdmi->attached_connector = intel_connector;
2042
2043 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2044 * 0xd. Failure to do so will result in spurious interrupts being
2045 * generated on the port when a cable is not attached.
2046 */
2047 if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
2048 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2049 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2050 }
2051 }
2052
2053 void intel_hdmi_init(struct drm_i915_private *dev_priv,
2054 i915_reg_t hdmi_reg, enum port port)
2055 {
2056 struct intel_digital_port *intel_dig_port;
2057 struct intel_encoder *intel_encoder;
2058 struct intel_connector *intel_connector;
2059
2060 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
2061 if (!intel_dig_port)
2062 return;
2063
2064 intel_connector = intel_connector_alloc();
2065 if (!intel_connector) {
2066 kfree(intel_dig_port);
2067 return;
2068 }
2069
2070 intel_encoder = &intel_dig_port->base;
2071
2072 drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
2073 &intel_hdmi_enc_funcs, DRM_MODE_ENCODER_TMDS,
2074 "HDMI %c", port_name(port));
2075
2076 intel_encoder->compute_config = intel_hdmi_compute_config;
2077 if (HAS_PCH_SPLIT(dev_priv)) {
2078 intel_encoder->disable = pch_disable_hdmi;
2079 intel_encoder->post_disable = pch_post_disable_hdmi;
2080 } else {
2081 intel_encoder->disable = g4x_disable_hdmi;
2082 }
2083 intel_encoder->get_hw_state = intel_hdmi_get_hw_state;
2084 intel_encoder->get_config = intel_hdmi_get_config;
2085 if (IS_CHERRYVIEW(dev_priv)) {
2086 intel_encoder->pre_pll_enable = chv_hdmi_pre_pll_enable;
2087 intel_encoder->pre_enable = chv_hdmi_pre_enable;
2088 intel_encoder->enable = vlv_enable_hdmi;
2089 intel_encoder->post_disable = chv_hdmi_post_disable;
2090 intel_encoder->post_pll_disable = chv_hdmi_post_pll_disable;
2091 } else if (IS_VALLEYVIEW(dev_priv)) {
2092 intel_encoder->pre_pll_enable = vlv_hdmi_pre_pll_enable;
2093 intel_encoder->pre_enable = vlv_hdmi_pre_enable;
2094 intel_encoder->enable = vlv_enable_hdmi;
2095 intel_encoder->post_disable = vlv_hdmi_post_disable;
2096 } else {
2097 intel_encoder->pre_enable = intel_hdmi_pre_enable;
2098 if (HAS_PCH_CPT(dev_priv))
2099 intel_encoder->enable = cpt_enable_hdmi;
2100 else if (HAS_PCH_IBX(dev_priv))
2101 intel_encoder->enable = ibx_enable_hdmi;
2102 else
2103 intel_encoder->enable = g4x_enable_hdmi;
2104 }
2105
2106 intel_encoder->type = INTEL_OUTPUT_HDMI;
2107 intel_encoder->power_domain = intel_port_to_power_domain(port);
2108 intel_encoder->port = port;
2109 if (IS_CHERRYVIEW(dev_priv)) {
2110 if (port == PORT_D)
2111 intel_encoder->crtc_mask = 1 << 2;
2112 else
2113 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
2114 } else {
2115 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2116 }
2117 intel_encoder->cloneable = 1 << INTEL_OUTPUT_ANALOG;
2118 /*
2119 * BSpec is unclear about HDMI+HDMI cloning on g4x, but it seems
2120 * to work on real hardware. And since g4x can send infoframes to
2121 * only one port anyway, nothing is lost by allowing it.
2122 */
2123 if (IS_G4X(dev_priv))
2124 intel_encoder->cloneable |= 1 << INTEL_OUTPUT_HDMI;
2125
2126 intel_dig_port->port = port;
2127 intel_dig_port->hdmi.hdmi_reg = hdmi_reg;
2128 intel_dig_port->dp.output_reg = INVALID_MMIO_REG;
2129 intel_dig_port->max_lanes = 4;
2130
2131 intel_infoframe_init(intel_dig_port);
2132
2133 intel_hdmi_init_connector(intel_dig_port, intel_connector);
2134 }
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