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Merge tag 'iio-for-4.18a' of git://git.kernel.org/pub/scm/linux/kernel/git/jic23...
[mirror_ubuntu-disco-kernel.git] / drivers / iio / adc / stm32-dfsdm-adc.c
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * This file is the ADC part of the STM32 DFSDM driver
4 *
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
7 */
8
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/interrupt.h>
12 #include <linux/iio/buffer.h>
13 #include <linux/iio/hw-consumer.h>
14 #include <linux/iio/iio.h>
15 #include <linux/iio/sysfs.h>
16 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/slab.h>
21
22 #include "stm32-dfsdm.h"
23
24 #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
25
26 /* Conversion timeout */
27 #define DFSDM_TIMEOUT_US 100000
28 #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
29
30 /* Oversampling attribute default */
31 #define DFSDM_DEFAULT_OVERSAMPLING 100
32
33 /* Oversampling max values */
34 #define DFSDM_MAX_INT_OVERSAMPLING 256
35 #define DFSDM_MAX_FL_OVERSAMPLING 1024
36
37 /* Max sample resolutions */
38 #define DFSDM_MAX_RES BIT(31)
39 #define DFSDM_DATA_RES BIT(23)
40
41 enum sd_converter_type {
42 DFSDM_AUDIO,
43 DFSDM_IIO,
44 };
45
46 struct stm32_dfsdm_dev_data {
47 int type;
48 int (*init)(struct iio_dev *indio_dev);
49 unsigned int num_channels;
50 const struct regmap_config *regmap_cfg;
51 };
52
53 struct stm32_dfsdm_adc {
54 struct stm32_dfsdm *dfsdm;
55 const struct stm32_dfsdm_dev_data *dev_data;
56 unsigned int fl_id;
57
58 /* ADC specific */
59 unsigned int oversamp;
60 struct iio_hw_consumer *hwc;
61 struct completion completion;
62 u32 *buffer;
63
64 /* Audio specific */
65 unsigned int spi_freq; /* SPI bus clock frequency */
66 unsigned int sample_freq; /* Sample frequency after filter decimation */
67 int (*cb)(const void *data, size_t size, void *cb_priv);
68 void *cb_priv;
69
70 /* DMA */
71 u8 *rx_buf;
72 unsigned int bufi; /* Buffer current position */
73 unsigned int buf_sz; /* Buffer size */
74 struct dma_chan *dma_chan;
75 dma_addr_t dma_buf;
76 };
77
78 struct stm32_dfsdm_str2field {
79 const char *name;
80 unsigned int val;
81 };
82
83 /* DFSDM channel serial interface type */
84 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
85 { "SPI_R", 0 }, /* SPI with data on rising edge */
86 { "SPI_F", 1 }, /* SPI with data on falling edge */
87 { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
88 { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
89 {},
90 };
91
92 /* DFSDM channel clock source */
93 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
94 /* External SPI clock (CLKIN x) */
95 { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
96 /* Internal SPI clock (CLKOUT) */
97 { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
98 /* Internal SPI clock divided by 2 (falling edge) */
99 { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
100 /* Internal SPI clock divided by 2 (falling edge) */
101 { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
102 {},
103 };
104
105 static int stm32_dfsdm_str2val(const char *str,
106 const struct stm32_dfsdm_str2field *list)
107 {
108 const struct stm32_dfsdm_str2field *p = list;
109
110 for (p = list; p && p->name; p++)
111 if (!strcmp(p->name, str))
112 return p->val;
113
114 return -EINVAL;
115 }
116
117 static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl,
118 unsigned int fast, unsigned int oversamp)
119 {
120 unsigned int i, d, fosr, iosr;
121 u64 res;
122 s64 delta;
123 unsigned int m = 1; /* multiplication factor */
124 unsigned int p = fl->ford; /* filter order (ford) */
125
126 pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp);
127 /*
128 * This function tries to compute filter oversampling and integrator
129 * oversampling, base on oversampling ratio requested by user.
130 *
131 * Decimation d depends on the filter order and the oversampling ratios.
132 * ford: filter order
133 * fosr: filter over sampling ratio
134 * iosr: integrator over sampling ratio
135 */
136 if (fl->ford == DFSDM_FASTSINC_ORDER) {
137 m = 2;
138 p = 2;
139 }
140
141 /*
142 * Look for filter and integrator oversampling ratios which allows
143 * to reach 24 bits data output resolution.
144 * Leave as soon as if exact resolution if reached.
145 * Otherwise the higher resolution below 32 bits is kept.
146 */
147 for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
148 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
149 if (fast)
150 d = fosr * iosr;
151 else if (fl->ford == DFSDM_FASTSINC_ORDER)
152 d = fosr * (iosr + 3) + 2;
153 else
154 d = fosr * (iosr - 1 + p) + p;
155
156 if (d > oversamp)
157 break;
158 else if (d != oversamp)
159 continue;
160 /*
161 * Check resolution (limited to signed 32 bits)
162 * res <= 2^31
163 * Sincx filters:
164 * res = m * fosr^p x iosr (with m=1, p=ford)
165 * FastSinc filter
166 * res = m * fosr^p x iosr (with m=2, p=2)
167 */
168 res = fosr;
169 for (i = p - 1; i > 0; i--) {
170 res = res * (u64)fosr;
171 if (res > DFSDM_MAX_RES)
172 break;
173 }
174 if (res > DFSDM_MAX_RES)
175 continue;
176 res = res * (u64)m * (u64)iosr;
177 if (res > DFSDM_MAX_RES)
178 continue;
179
180 delta = res - DFSDM_DATA_RES;
181
182 if (res >= fl->res) {
183 fl->res = res;
184 fl->fosr = fosr;
185 fl->iosr = iosr;
186 fl->fast = fast;
187 pr_debug("%s: fosr = %d, iosr = %d\n",
188 __func__, fl->fosr, fl->iosr);
189 }
190
191 if (!delta)
192 return 0;
193 }
194 }
195
196 if (!fl->fosr)
197 return -EINVAL;
198
199 return 0;
200 }
201
202 static int stm32_dfsdm_start_channel(struct stm32_dfsdm *dfsdm,
203 unsigned int ch_id)
204 {
205 return regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id),
206 DFSDM_CHCFGR1_CHEN_MASK,
207 DFSDM_CHCFGR1_CHEN(1));
208 }
209
210 static void stm32_dfsdm_stop_channel(struct stm32_dfsdm *dfsdm,
211 unsigned int ch_id)
212 {
213 regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id),
214 DFSDM_CHCFGR1_CHEN_MASK, DFSDM_CHCFGR1_CHEN(0));
215 }
216
217 static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
218 struct stm32_dfsdm_channel *ch)
219 {
220 unsigned int id = ch->id;
221 struct regmap *regmap = dfsdm->regmap;
222 int ret;
223
224 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
225 DFSDM_CHCFGR1_SITP_MASK,
226 DFSDM_CHCFGR1_SITP(ch->type));
227 if (ret < 0)
228 return ret;
229 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
230 DFSDM_CHCFGR1_SPICKSEL_MASK,
231 DFSDM_CHCFGR1_SPICKSEL(ch->src));
232 if (ret < 0)
233 return ret;
234 return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
235 DFSDM_CHCFGR1_CHINSEL_MASK,
236 DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
237 }
238
239 static int stm32_dfsdm_start_filter(struct stm32_dfsdm *dfsdm,
240 unsigned int fl_id)
241 {
242 int ret;
243
244 /* Enable filter */
245 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
246 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
247 if (ret < 0)
248 return ret;
249
250 /* Start conversion */
251 return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
252 DFSDM_CR1_RSWSTART_MASK,
253 DFSDM_CR1_RSWSTART(1));
254 }
255
256 static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
257 unsigned int fl_id)
258 {
259 /* Disable conversion */
260 regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
261 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
262 }
263
264 static int stm32_dfsdm_filter_configure(struct stm32_dfsdm *dfsdm,
265 unsigned int fl_id, unsigned int ch_id)
266 {
267 struct regmap *regmap = dfsdm->regmap;
268 struct stm32_dfsdm_filter *fl = &dfsdm->fl_list[fl_id];
269 int ret;
270
271 /* Average integrator oversampling */
272 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
273 DFSDM_FCR_IOSR(fl->iosr - 1));
274 if (ret)
275 return ret;
276
277 /* Filter order and Oversampling */
278 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
279 DFSDM_FCR_FOSR(fl->fosr - 1));
280 if (ret)
281 return ret;
282
283 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
284 DFSDM_FCR_FORD(fl->ford));
285 if (ret)
286 return ret;
287
288 /* No scan mode supported for the moment */
289 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_RCH_MASK,
290 DFSDM_CR1_RCH(ch_id));
291 if (ret)
292 return ret;
293
294 return regmap_update_bits(regmap, DFSDM_CR1(fl_id),
295 DFSDM_CR1_RSYNC_MASK,
296 DFSDM_CR1_RSYNC(fl->sync_mode));
297 }
298
299 static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
300 struct iio_dev *indio_dev,
301 struct iio_chan_spec *ch)
302 {
303 struct stm32_dfsdm_channel *df_ch;
304 const char *of_str;
305 int chan_idx = ch->scan_index;
306 int ret, val;
307
308 ret = of_property_read_u32_index(indio_dev->dev.of_node,
309 "st,adc-channels", chan_idx,
310 &ch->channel);
311 if (ret < 0) {
312 dev_err(&indio_dev->dev,
313 " Error parsing 'st,adc-channels' for idx %d\n",
314 chan_idx);
315 return ret;
316 }
317 if (ch->channel >= dfsdm->num_chs) {
318 dev_err(&indio_dev->dev,
319 " Error bad channel number %d (max = %d)\n",
320 ch->channel, dfsdm->num_chs);
321 return -EINVAL;
322 }
323
324 ret = of_property_read_string_index(indio_dev->dev.of_node,
325 "st,adc-channel-names", chan_idx,
326 &ch->datasheet_name);
327 if (ret < 0) {
328 dev_err(&indio_dev->dev,
329 " Error parsing 'st,adc-channel-names' for idx %d\n",
330 chan_idx);
331 return ret;
332 }
333
334 df_ch = &dfsdm->ch_list[ch->channel];
335 df_ch->id = ch->channel;
336
337 ret = of_property_read_string_index(indio_dev->dev.of_node,
338 "st,adc-channel-types", chan_idx,
339 &of_str);
340 if (!ret) {
341 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
342 if (val < 0)
343 return val;
344 } else {
345 val = 0;
346 }
347 df_ch->type = val;
348
349 ret = of_property_read_string_index(indio_dev->dev.of_node,
350 "st,adc-channel-clk-src", chan_idx,
351 &of_str);
352 if (!ret) {
353 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
354 if (val < 0)
355 return val;
356 } else {
357 val = 0;
358 }
359 df_ch->src = val;
360
361 ret = of_property_read_u32_index(indio_dev->dev.of_node,
362 "st,adc-alt-channel", chan_idx,
363 &df_ch->alt_si);
364 if (ret < 0)
365 df_ch->alt_si = 0;
366
367 return 0;
368 }
369
370 static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
371 uintptr_t priv,
372 const struct iio_chan_spec *chan,
373 char *buf)
374 {
375 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
376
377 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
378 }
379
380 static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
381 uintptr_t priv,
382 const struct iio_chan_spec *chan,
383 const char *buf, size_t len)
384 {
385 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
386 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
387 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
388 unsigned int sample_freq = adc->sample_freq;
389 unsigned int spi_freq;
390 int ret;
391
392 dev_err(&indio_dev->dev, "enter %s\n", __func__);
393 /* If DFSDM is master on SPI, SPI freq can not be updated */
394 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
395 return -EPERM;
396
397 ret = kstrtoint(buf, 0, &spi_freq);
398 if (ret)
399 return ret;
400
401 if (!spi_freq)
402 return -EINVAL;
403
404 if (sample_freq) {
405 if (spi_freq % sample_freq)
406 dev_warn(&indio_dev->dev,
407 "Sampling rate not accurate (%d)\n",
408 spi_freq / (spi_freq / sample_freq));
409
410 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / sample_freq));
411 if (ret < 0) {
412 dev_err(&indio_dev->dev,
413 "No filter parameters that match!\n");
414 return ret;
415 }
416 }
417 adc->spi_freq = spi_freq;
418
419 return len;
420 }
421
422 static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc,
423 const struct iio_chan_spec *chan,
424 bool dma)
425 {
426 struct regmap *regmap = adc->dfsdm->regmap;
427 int ret;
428 unsigned int dma_en = 0, cont_en = 0;
429
430 ret = stm32_dfsdm_start_channel(adc->dfsdm, chan->channel);
431 if (ret < 0)
432 return ret;
433
434 ret = stm32_dfsdm_filter_configure(adc->dfsdm, adc->fl_id,
435 chan->channel);
436 if (ret < 0)
437 goto stop_channels;
438
439 if (dma) {
440 /* Enable DMA transfer*/
441 dma_en = DFSDM_CR1_RDMAEN(1);
442 /* Enable conversion triggered by SPI clock*/
443 cont_en = DFSDM_CR1_RCONT(1);
444 }
445 /* Enable DMA transfer*/
446 ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
447 DFSDM_CR1_RDMAEN_MASK, dma_en);
448 if (ret < 0)
449 goto stop_channels;
450
451 /* Enable conversion triggered by SPI clock*/
452 ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
453 DFSDM_CR1_RCONT_MASK, cont_en);
454 if (ret < 0)
455 goto stop_channels;
456
457 ret = stm32_dfsdm_start_filter(adc->dfsdm, adc->fl_id);
458 if (ret < 0)
459 goto stop_channels;
460
461 return 0;
462
463 stop_channels:
464 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
465 DFSDM_CR1_RDMAEN_MASK, 0);
466
467 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
468 DFSDM_CR1_RCONT_MASK, 0);
469 stm32_dfsdm_stop_channel(adc->dfsdm, chan->channel);
470
471 return ret;
472 }
473
474 static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc,
475 const struct iio_chan_spec *chan)
476 {
477 struct regmap *regmap = adc->dfsdm->regmap;
478
479 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
480
481 /* Clean conversion options */
482 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
483 DFSDM_CR1_RDMAEN_MASK, 0);
484
485 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
486 DFSDM_CR1_RCONT_MASK, 0);
487
488 stm32_dfsdm_stop_channel(adc->dfsdm, chan->channel);
489 }
490
491 static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
492 unsigned int val)
493 {
494 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
495 unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
496
497 /*
498 * DMA cyclic transfers are used, buffer is split into two periods.
499 * There should be :
500 * - always one buffer (period) DMA is working on
501 * - one buffer (period) driver pushed to ASoC side.
502 */
503 watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
504 adc->buf_sz = watermark * 2;
505
506 return 0;
507 }
508
509 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
510 {
511 struct dma_tx_state state;
512 enum dma_status status;
513
514 status = dmaengine_tx_status(adc->dma_chan,
515 adc->dma_chan->cookie,
516 &state);
517 if (status == DMA_IN_PROGRESS) {
518 /* Residue is size in bytes from end of buffer */
519 unsigned int i = adc->buf_sz - state.residue;
520 unsigned int size;
521
522 /* Return available bytes */
523 if (i >= adc->bufi)
524 size = i - adc->bufi;
525 else
526 size = adc->buf_sz + i - adc->bufi;
527
528 return size;
529 }
530
531 return 0;
532 }
533
534 static void stm32_dfsdm_audio_dma_buffer_done(void *data)
535 {
536 struct iio_dev *indio_dev = data;
537 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
538 int available = stm32_dfsdm_adc_dma_residue(adc);
539 size_t old_pos;
540
541 /*
542 * FIXME: In Kernel interface does not support cyclic DMA buffer,and
543 * offers only an interface to push data samples per samples.
544 * For this reason IIO buffer interface is not used and interface is
545 * bypassed using a private callback registered by ASoC.
546 * This should be a temporary solution waiting a cyclic DMA engine
547 * support in IIO.
548 */
549
550 dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
551 adc->bufi, available);
552 old_pos = adc->bufi;
553
554 while (available >= indio_dev->scan_bytes) {
555 u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi];
556
557 /* Mask 8 LSB that contains the channel ID */
558 *buffer = (*buffer & 0xFFFFFF00) << 8;
559 available -= indio_dev->scan_bytes;
560 adc->bufi += indio_dev->scan_bytes;
561 if (adc->bufi >= adc->buf_sz) {
562 if (adc->cb)
563 adc->cb(&adc->rx_buf[old_pos],
564 adc->buf_sz - old_pos, adc->cb_priv);
565 adc->bufi = 0;
566 old_pos = 0;
567 }
568 }
569 if (adc->cb)
570 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
571 adc->cb_priv);
572 }
573
574 static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
575 {
576 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
577 struct dma_async_tx_descriptor *desc;
578 dma_cookie_t cookie;
579 int ret;
580
581 if (!adc->dma_chan)
582 return -EINVAL;
583
584 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
585 adc->buf_sz, adc->buf_sz / 2);
586
587 /* Prepare a DMA cyclic transaction */
588 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
589 adc->dma_buf,
590 adc->buf_sz, adc->buf_sz / 2,
591 DMA_DEV_TO_MEM,
592 DMA_PREP_INTERRUPT);
593 if (!desc)
594 return -EBUSY;
595
596 desc->callback = stm32_dfsdm_audio_dma_buffer_done;
597 desc->callback_param = indio_dev;
598
599 cookie = dmaengine_submit(desc);
600 ret = dma_submit_error(cookie);
601 if (ret) {
602 dmaengine_terminate_all(adc->dma_chan);
603 return ret;
604 }
605
606 /* Issue pending DMA requests */
607 dma_async_issue_pending(adc->dma_chan);
608
609 return 0;
610 }
611
612 static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
613 {
614 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
615 const struct iio_chan_spec *chan = &indio_dev->channels[0];
616 int ret;
617
618 /* Reset adc buffer index */
619 adc->bufi = 0;
620
621 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
622 if (ret < 0)
623 return ret;
624
625 ret = stm32_dfsdm_start_conv(adc, chan, true);
626 if (ret) {
627 dev_err(&indio_dev->dev, "Can't start conversion\n");
628 goto stop_dfsdm;
629 }
630
631 if (adc->dma_chan) {
632 ret = stm32_dfsdm_adc_dma_start(indio_dev);
633 if (ret) {
634 dev_err(&indio_dev->dev, "Can't start DMA\n");
635 goto err_stop_conv;
636 }
637 }
638
639 return 0;
640
641 err_stop_conv:
642 stm32_dfsdm_stop_conv(adc, chan);
643 stop_dfsdm:
644 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
645
646 return ret;
647 }
648
649 static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
650 {
651 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
652 const struct iio_chan_spec *chan = &indio_dev->channels[0];
653
654 if (adc->dma_chan)
655 dmaengine_terminate_all(adc->dma_chan);
656
657 stm32_dfsdm_stop_conv(adc, chan);
658
659 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
660
661 return 0;
662 }
663
664 static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
665 .postenable = &stm32_dfsdm_postenable,
666 .predisable = &stm32_dfsdm_predisable,
667 };
668
669 /**
670 * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
671 * DMA transfer period is achieved.
672 *
673 * @iio_dev: Handle to IIO device.
674 * @cb: Pointer to callback function:
675 * - data: pointer to data buffer
676 * - size: size in byte of the data buffer
677 * - private: pointer to consumer private structure.
678 * @private: Pointer to consumer private structure.
679 */
680 int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
681 int (*cb)(const void *data, size_t size,
682 void *private),
683 void *private)
684 {
685 struct stm32_dfsdm_adc *adc;
686
687 if (!iio_dev)
688 return -EINVAL;
689 adc = iio_priv(iio_dev);
690
691 adc->cb = cb;
692 adc->cb_priv = private;
693
694 return 0;
695 }
696 EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
697
698 /**
699 * stm32_dfsdm_release_buff_cb - unregister buffer callback
700 *
701 * @iio_dev: Handle to IIO device.
702 */
703 int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
704 {
705 struct stm32_dfsdm_adc *adc;
706
707 if (!iio_dev)
708 return -EINVAL;
709 adc = iio_priv(iio_dev);
710
711 adc->cb = NULL;
712 adc->cb_priv = NULL;
713
714 return 0;
715 }
716 EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
717
718 static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
719 const struct iio_chan_spec *chan, int *res)
720 {
721 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
722 long timeout;
723 int ret;
724
725 reinit_completion(&adc->completion);
726
727 adc->buffer = res;
728
729 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
730 if (ret < 0)
731 return ret;
732
733 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
734 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
735 if (ret < 0)
736 goto stop_dfsdm;
737
738 ret = stm32_dfsdm_start_conv(adc, chan, false);
739 if (ret < 0) {
740 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
741 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
742 goto stop_dfsdm;
743 }
744
745 timeout = wait_for_completion_interruptible_timeout(&adc->completion,
746 DFSDM_TIMEOUT);
747
748 /* Mask IRQ for regular conversion achievement*/
749 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
750 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
751
752 if (timeout == 0)
753 ret = -ETIMEDOUT;
754 else if (timeout < 0)
755 ret = timeout;
756 else
757 ret = IIO_VAL_INT;
758
759 stm32_dfsdm_stop_conv(adc, chan);
760
761 stop_dfsdm:
762 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
763
764 return ret;
765 }
766
767 static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
768 struct iio_chan_spec const *chan,
769 int val, int val2, long mask)
770 {
771 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
772 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
773 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
774 unsigned int spi_freq = adc->spi_freq;
775 int ret = -EINVAL;
776
777 switch (mask) {
778 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
779 ret = stm32_dfsdm_set_osrs(fl, 0, val);
780 if (!ret)
781 adc->oversamp = val;
782
783 return ret;
784
785 case IIO_CHAN_INFO_SAMP_FREQ:
786 if (!val)
787 return -EINVAL;
788 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
789 spi_freq = adc->dfsdm->spi_master_freq;
790
791 if (spi_freq % val)
792 dev_warn(&indio_dev->dev,
793 "Sampling rate not accurate (%d)\n",
794 spi_freq / (spi_freq / val));
795
796 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / val));
797 if (ret < 0) {
798 dev_err(&indio_dev->dev,
799 "Not able to find parameter that match!\n");
800 return ret;
801 }
802 adc->sample_freq = val;
803
804 return 0;
805 }
806
807 return -EINVAL;
808 }
809
810 static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
811 struct iio_chan_spec const *chan, int *val,
812 int *val2, long mask)
813 {
814 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
815 int ret;
816
817 switch (mask) {
818 case IIO_CHAN_INFO_RAW:
819 ret = iio_hw_consumer_enable(adc->hwc);
820 if (ret < 0) {
821 dev_err(&indio_dev->dev,
822 "%s: IIO enable failed (channel %d)\n",
823 __func__, chan->channel);
824 return ret;
825 }
826 ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
827 iio_hw_consumer_disable(adc->hwc);
828 if (ret < 0) {
829 dev_err(&indio_dev->dev,
830 "%s: Conversion failed (channel %d)\n",
831 __func__, chan->channel);
832 return ret;
833 }
834 return IIO_VAL_INT;
835
836 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
837 *val = adc->oversamp;
838
839 return IIO_VAL_INT;
840
841 case IIO_CHAN_INFO_SAMP_FREQ:
842 *val = adc->sample_freq;
843
844 return IIO_VAL_INT;
845 }
846
847 return -EINVAL;
848 }
849
850 static const struct iio_info stm32_dfsdm_info_audio = {
851 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
852 .read_raw = stm32_dfsdm_read_raw,
853 .write_raw = stm32_dfsdm_write_raw,
854 };
855
856 static const struct iio_info stm32_dfsdm_info_adc = {
857 .read_raw = stm32_dfsdm_read_raw,
858 .write_raw = stm32_dfsdm_write_raw,
859 };
860
861 static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
862 {
863 struct stm32_dfsdm_adc *adc = arg;
864 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
865 struct regmap *regmap = adc->dfsdm->regmap;
866 unsigned int status, int_en;
867
868 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
869 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
870
871 if (status & DFSDM_ISR_REOCF_MASK) {
872 /* Read the data register clean the IRQ status */
873 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
874 complete(&adc->completion);
875 }
876
877 if (status & DFSDM_ISR_ROVRF_MASK) {
878 if (int_en & DFSDM_CR2_ROVRIE_MASK)
879 dev_warn(&indio_dev->dev, "Overrun detected\n");
880 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
881 DFSDM_ICR_CLRROVRF_MASK,
882 DFSDM_ICR_CLRROVRF_MASK);
883 }
884
885 return IRQ_HANDLED;
886 }
887
888 /*
889 * Define external info for SPI Frequency and audio sampling rate that can be
890 * configured by ASoC driver through consumer.h API
891 */
892 static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
893 /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
894 {
895 .name = "spi_clk_freq",
896 .shared = IIO_SHARED_BY_TYPE,
897 .read = dfsdm_adc_audio_get_spiclk,
898 .write = dfsdm_adc_audio_set_spiclk,
899 },
900 {},
901 };
902
903 static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
904 {
905 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
906
907 if (adc->dma_chan) {
908 dma_free_coherent(adc->dma_chan->device->dev,
909 DFSDM_DMA_BUFFER_SIZE,
910 adc->rx_buf, adc->dma_buf);
911 dma_release_channel(adc->dma_chan);
912 }
913 }
914
915 static int stm32_dfsdm_dma_request(struct iio_dev *indio_dev)
916 {
917 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
918 struct dma_slave_config config = {
919 .src_addr = (dma_addr_t)adc->dfsdm->phys_base +
920 DFSDM_RDATAR(adc->fl_id),
921 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
922 };
923 int ret;
924
925 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
926 if (!adc->dma_chan)
927 return -EINVAL;
928
929 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
930 DFSDM_DMA_BUFFER_SIZE,
931 &adc->dma_buf, GFP_KERNEL);
932 if (!adc->rx_buf) {
933 ret = -ENOMEM;
934 goto err_release;
935 }
936
937 ret = dmaengine_slave_config(adc->dma_chan, &config);
938 if (ret)
939 goto err_free;
940
941 return 0;
942
943 err_free:
944 dma_free_coherent(adc->dma_chan->device->dev, DFSDM_DMA_BUFFER_SIZE,
945 adc->rx_buf, adc->dma_buf);
946 err_release:
947 dma_release_channel(adc->dma_chan);
948
949 return ret;
950 }
951
952 static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
953 struct iio_chan_spec *ch)
954 {
955 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
956 int ret;
957
958 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
959 if (ret < 0)
960 return ret;
961
962 ch->type = IIO_VOLTAGE;
963 ch->indexed = 1;
964
965 /*
966 * IIO_CHAN_INFO_RAW: used to compute regular conversion
967 * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
968 */
969 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
970 ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
971
972 if (adc->dev_data->type == DFSDM_AUDIO) {
973 ch->scan_type.sign = 's';
974 ch->ext_info = dfsdm_adc_audio_ext_info;
975 } else {
976 ch->scan_type.sign = 'u';
977 }
978 ch->scan_type.realbits = 24;
979 ch->scan_type.storagebits = 32;
980
981 return stm32_dfsdm_chan_configure(adc->dfsdm,
982 &adc->dfsdm->ch_list[ch->channel]);
983 }
984
985 static int stm32_dfsdm_audio_init(struct iio_dev *indio_dev)
986 {
987 struct iio_chan_spec *ch;
988 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
989 struct stm32_dfsdm_channel *d_ch;
990 int ret;
991
992 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
993 indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
994
995 ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
996 if (!ch)
997 return -ENOMEM;
998
999 ch->scan_index = 0;
1000
1001 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
1002 if (ret < 0) {
1003 dev_err(&indio_dev->dev, "Channels init failed\n");
1004 return ret;
1005 }
1006 ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1007
1008 d_ch = &adc->dfsdm->ch_list[ch->channel];
1009 if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1010 adc->spi_freq = adc->dfsdm->spi_master_freq;
1011
1012 indio_dev->num_channels = 1;
1013 indio_dev->channels = ch;
1014
1015 return stm32_dfsdm_dma_request(indio_dev);
1016 }
1017
1018 static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev)
1019 {
1020 struct iio_chan_spec *ch;
1021 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1022 int num_ch;
1023 int ret, chan_idx;
1024
1025 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1026 ret = stm32_dfsdm_set_osrs(&adc->dfsdm->fl_list[adc->fl_id], 0,
1027 adc->oversamp);
1028 if (ret < 0)
1029 return ret;
1030
1031 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
1032 "st,adc-channels");
1033 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
1034 dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1035 return num_ch < 0 ? num_ch : -EINVAL;
1036 }
1037
1038 /* Bind to SD modulator IIO device */
1039 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1040 if (IS_ERR(adc->hwc))
1041 return -EPROBE_DEFER;
1042
1043 ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
1044 GFP_KERNEL);
1045 if (!ch)
1046 return -ENOMEM;
1047
1048 for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1049 ch[chan_idx].scan_index = chan_idx;
1050 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
1051 if (ret < 0) {
1052 dev_err(&indio_dev->dev, "Channels init failed\n");
1053 return ret;
1054 }
1055 }
1056
1057 indio_dev->num_channels = num_ch;
1058 indio_dev->channels = ch;
1059
1060 init_completion(&adc->completion);
1061
1062 return 0;
1063 }
1064
1065 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1066 .type = DFSDM_IIO,
1067 .init = stm32_dfsdm_adc_init,
1068 };
1069
1070 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1071 .type = DFSDM_AUDIO,
1072 .init = stm32_dfsdm_audio_init,
1073 };
1074
1075 static const struct of_device_id stm32_dfsdm_adc_match[] = {
1076 {
1077 .compatible = "st,stm32-dfsdm-adc",
1078 .data = &stm32h7_dfsdm_adc_data,
1079 },
1080 {
1081 .compatible = "st,stm32-dfsdm-dmic",
1082 .data = &stm32h7_dfsdm_audio_data,
1083 },
1084 {}
1085 };
1086
1087 static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1088 {
1089 struct device *dev = &pdev->dev;
1090 struct stm32_dfsdm_adc *adc;
1091 struct device_node *np = dev->of_node;
1092 const struct stm32_dfsdm_dev_data *dev_data;
1093 struct iio_dev *iio;
1094 char *name;
1095 int ret, irq, val;
1096
1097 dev_data = of_device_get_match_data(dev);
1098 iio = devm_iio_device_alloc(dev, sizeof(*adc));
1099 if (!iio) {
1100 dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
1101 return -ENOMEM;
1102 }
1103
1104 adc = iio_priv(iio);
1105 adc->dfsdm = dev_get_drvdata(dev->parent);
1106
1107 iio->dev.parent = dev;
1108 iio->dev.of_node = np;
1109 iio->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1110
1111 platform_set_drvdata(pdev, adc);
1112
1113 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1114 if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1115 dev_err(dev, "Missing or bad reg property\n");
1116 return -EINVAL;
1117 }
1118
1119 name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1120 if (!name)
1121 return -ENOMEM;
1122 if (dev_data->type == DFSDM_AUDIO) {
1123 iio->info = &stm32_dfsdm_info_audio;
1124 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1125 } else {
1126 iio->info = &stm32_dfsdm_info_adc;
1127 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1128 }
1129 iio->name = name;
1130
1131 /*
1132 * In a first step IRQs generated for channels are not treated.
1133 * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
1134 */
1135 irq = platform_get_irq(pdev, 0);
1136 ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1137 0, pdev->name, adc);
1138 if (ret < 0) {
1139 dev_err(dev, "Failed to request IRQ\n");
1140 return ret;
1141 }
1142
1143 ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1144 if (ret < 0) {
1145 dev_err(dev, "Failed to set filter order\n");
1146 return ret;
1147 }
1148
1149 adc->dfsdm->fl_list[adc->fl_id].ford = val;
1150
1151 ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1152 if (!ret)
1153 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1154
1155 adc->dev_data = dev_data;
1156 ret = dev_data->init(iio);
1157 if (ret < 0)
1158 return ret;
1159
1160 ret = iio_device_register(iio);
1161 if (ret < 0)
1162 goto err_cleanup;
1163
1164 if (dev_data->type == DFSDM_AUDIO) {
1165 ret = of_platform_populate(np, NULL, NULL, dev);
1166 if (ret < 0) {
1167 dev_err(dev, "Failed to find an audio DAI\n");
1168 goto err_unregister;
1169 }
1170 }
1171
1172 return 0;
1173
1174 err_unregister:
1175 iio_device_unregister(iio);
1176 err_cleanup:
1177 stm32_dfsdm_dma_release(iio);
1178
1179 return ret;
1180 }
1181
1182 static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
1183 {
1184 struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev);
1185 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1186
1187 if (adc->dev_data->type == DFSDM_AUDIO)
1188 of_platform_depopulate(&pdev->dev);
1189 iio_device_unregister(indio_dev);
1190 stm32_dfsdm_dma_release(indio_dev);
1191
1192 return 0;
1193 }
1194
1195 static struct platform_driver stm32_dfsdm_adc_driver = {
1196 .driver = {
1197 .name = "stm32-dfsdm-adc",
1198 .of_match_table = stm32_dfsdm_adc_match,
1199 },
1200 .probe = stm32_dfsdm_adc_probe,
1201 .remove = stm32_dfsdm_adc_remove,
1202 };
1203 module_platform_driver(stm32_dfsdm_adc_driver);
1204
1205 MODULE_DESCRIPTION("STM32 sigma delta ADC");
1206 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
1207 MODULE_LICENSE("GPL v2");
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