2 * Marvell 88E6xxx Ethernet switch single-chip definition
4 * Copyright (c) 2008 Marvell Semiconductor
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
12 #ifndef _MV88E6XXX_CHIP_H
13 #define _MV88E6XXX_CHIP_H
15 #include <linux/if_vlan.h>
16 #include <linux/irq.h>
17 #include <linux/gpio/consumer.h>
18 #include <linux/kthread.h>
19 #include <linux/phy.h>
20 #include <linux/ptp_clock_kernel.h>
21 #include <linux/timecounter.h>
25 #define SMI_CMD_BUSY BIT(15)
26 #define SMI_CMD_CLAUSE_22 BIT(12)
27 #define SMI_CMD_OP_22_WRITE ((1 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
28 #define SMI_CMD_OP_22_READ ((2 << 10) | SMI_CMD_BUSY | SMI_CMD_CLAUSE_22)
29 #define SMI_CMD_OP_45_WRITE_ADDR ((0 << 10) | SMI_CMD_BUSY)
30 #define SMI_CMD_OP_45_WRITE_DATA ((1 << 10) | SMI_CMD_BUSY)
31 #define SMI_CMD_OP_45_READ_DATA ((2 << 10) | SMI_CMD_BUSY)
32 #define SMI_CMD_OP_45_READ_DATA_INC ((3 << 10) | SMI_CMD_BUSY)
35 #define MV88E6XXX_N_FID 4096
37 /* PVT limits for 4-bit port and 5-bit switch */
38 #define MV88E6XXX_MAX_PVT_SWITCHES 32
39 #define MV88E6XXX_MAX_PVT_PORTS 16
41 #define MV88E6XXX_MAX_GPIO 16
43 enum mv88e6xxx_egress_mode
{
44 MV88E6XXX_EGRESS_MODE_UNMODIFIED
,
45 MV88E6XXX_EGRESS_MODE_UNTAGGED
,
46 MV88E6XXX_EGRESS_MODE_TAGGED
,
47 MV88E6XXX_EGRESS_MODE_ETHERTYPE
,
50 enum mv88e6xxx_frame_mode
{
51 MV88E6XXX_FRAME_MODE_NORMAL
,
52 MV88E6XXX_FRAME_MODE_DSA
,
53 MV88E6XXX_FRAME_MODE_PROVIDER
,
54 MV88E6XXX_FRAME_MODE_ETHERTYPE
,
57 /* List of supported models */
58 enum mv88e6xxx_model
{
87 enum mv88e6xxx_family
{
88 MV88E6XXX_FAMILY_NONE
,
89 MV88E6XXX_FAMILY_6065
, /* 6031 6035 6061 6065 */
90 MV88E6XXX_FAMILY_6095
, /* 6092 6095 */
91 MV88E6XXX_FAMILY_6097
, /* 6046 6085 6096 6097 */
92 MV88E6XXX_FAMILY_6165
, /* 6123 6161 6165 */
93 MV88E6XXX_FAMILY_6185
, /* 6108 6121 6122 6131 6152 6155 6182 6185 */
94 MV88E6XXX_FAMILY_6320
, /* 6320 6321 */
95 MV88E6XXX_FAMILY_6341
, /* 6141 6341 */
96 MV88E6XXX_FAMILY_6351
, /* 6171 6175 6350 6351 */
97 MV88E6XXX_FAMILY_6352
, /* 6172 6176 6240 6352 */
98 MV88E6XXX_FAMILY_6390
, /* 6190 6190X 6191 6290 6390 6390X */
101 struct mv88e6xxx_ops
;
103 struct mv88e6xxx_info
{
104 enum mv88e6xxx_family family
;
107 unsigned int num_databases
;
108 unsigned int num_ports
;
109 unsigned int num_internal_phys
;
110 unsigned int num_gpio
;
111 unsigned int max_vid
;
112 unsigned int port_base_addr
;
113 unsigned int phy_base_addr
;
114 unsigned int global1_addr
;
115 unsigned int global2_addr
;
116 unsigned int age_time_coeff
;
117 unsigned int g1_irqs
;
118 unsigned int g2_irqs
;
121 /* Multi-chip Addressing Mode.
122 * Some chips respond to only 2 registers of its own SMI device address
123 * when it is non-zero, and use indirect access to internal registers.
126 enum dsa_tag_protocol tag_protocol
;
128 /* Mask for FromPort and ToPort value of PortVec used in ATU Move
129 * operation. 0 means that the ATU Move operation is not supported.
131 u8 atu_move_port_mask
;
132 const struct mv88e6xxx_ops
*ops
;
138 struct mv88e6xxx_atu_entry
{
145 struct mv88e6xxx_vtu_entry
{
150 u8 member
[DSA_MAX_PORTS
];
151 u8 state
[DSA_MAX_PORTS
];
154 struct mv88e6xxx_bus_ops
;
155 struct mv88e6xxx_irq_ops
;
156 struct mv88e6xxx_gpio_ops
;
157 struct mv88e6xxx_avb_ops
;
158 struct mv88e6xxx_ptp_ops
;
160 struct mv88e6xxx_irq
{
162 struct irq_chip chip
;
163 struct irq_domain
*domain
;
167 /* state flags for mv88e6xxx_port_hwtstamp::state */
169 MV88E6XXX_HWTSTAMP_ENABLED
,
170 MV88E6XXX_HWTSTAMP_TX_IN_PROGRESS
,
173 struct mv88e6xxx_port_hwtstamp
{
177 /* Timestamping state */
180 /* Resources for receive timestamping */
181 struct sk_buff_head rx_queue
;
182 struct sk_buff_head rx_queue2
;
184 /* Resources for transmit timestamping */
185 unsigned long tx_tstamp_start
;
186 struct sk_buff
*tx_skb
;
189 /* Current timestamp configuration */
190 struct hwtstamp_config tstamp_config
;
193 struct mv88e6xxx_port
{
194 struct mv88e6xxx_chip
*chip
;
197 u64 atu_member_violation
;
198 u64 atu_miss_violation
;
199 u64 atu_full_violation
;
200 u64 vtu_member_violation
;
201 u64 vtu_miss_violation
;
206 struct mv88e6xxx_chip
{
207 const struct mv88e6xxx_info
*info
;
209 /* The dsa_switch this private structure is related to */
210 struct dsa_switch
*ds
;
212 /* The device this structure is associated to */
215 /* This mutex protects the access to the switch registers */
216 struct mutex reg_lock
;
218 /* The MII bus and the address on the bus that is used to
219 * communication with the switch
221 const struct mv88e6xxx_bus_ops
*smi_ops
;
225 /* Handles automatic disabling and re-enabling of the PHY
228 const struct mv88e6xxx_bus_ops
*phy_ops
;
229 struct mutex ppu_mutex
;
231 struct work_struct ppu_work
;
232 struct timer_list ppu_timer
;
234 /* This mutex serialises access to the statistics unit.
235 * Hold this mutex over snapshot + dump sequences.
237 struct mutex stats_mutex
;
239 /* A switch may have a GPIO line tied to its reset pin. Parse
240 * this from the device tree, and use it before performing
243 struct gpio_desc
*reset
;
245 /* set to size of eeprom if supported by the switch */
248 /* List of mdio busses */
249 struct list_head mdios
;
251 /* There can be two interrupt controllers, which are chained
252 * off a GPIO as interrupt source
254 struct mv88e6xxx_irq g1_irq
;
255 struct mv88e6xxx_irq g2_irq
;
262 struct kthread_worker
*kworker
;
263 struct kthread_delayed_work irq_poll_work
;
268 /* This cyclecounter abstracts the switch PTP time.
269 * reg_lock must be held for any operation that read()s.
271 struct cyclecounter tstamp_cc
;
272 struct timecounter tstamp_tc
;
273 struct delayed_work overflow_work
;
275 struct ptp_clock
*ptp_clock
;
276 struct ptp_clock_info ptp_clock_info
;
277 struct delayed_work tai_event_work
;
278 struct ptp_pin_desc pin_config
[MV88E6XXX_MAX_GPIO
];
283 /* Per-port timestamping resources. */
284 struct mv88e6xxx_port_hwtstamp port_hwtstamp
[DSA_MAX_PORTS
];
286 /* Array of port structures. */
287 struct mv88e6xxx_port ports
[DSA_MAX_PORTS
];
290 struct mv88e6xxx_bus_ops
{
291 int (*read
)(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16
*val
);
292 int (*write
)(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 val
);
295 struct mv88e6xxx_mdio_bus
{
297 struct mv88e6xxx_chip
*chip
;
298 struct list_head list
;
302 struct mv88e6xxx_ops
{
303 /* Switch Setup Errata, called early in the switch setup to
304 * allow any errata actions to be performed
306 int (*setup_errata
)(struct mv88e6xxx_chip
*chip
);
308 int (*ieee_pri_map
)(struct mv88e6xxx_chip
*chip
);
309 int (*ip_pri_map
)(struct mv88e6xxx_chip
*chip
);
311 /* Ingress Rate Limit unit (IRL) operations */
312 int (*irl_init_all
)(struct mv88e6xxx_chip
*chip
, int port
);
314 int (*get_eeprom
)(struct mv88e6xxx_chip
*chip
,
315 struct ethtool_eeprom
*eeprom
, u8
*data
);
316 int (*set_eeprom
)(struct mv88e6xxx_chip
*chip
,
317 struct ethtool_eeprom
*eeprom
, u8
*data
);
319 int (*set_switch_mac
)(struct mv88e6xxx_chip
*chip
, u8
*addr
);
321 int (*phy_read
)(struct mv88e6xxx_chip
*chip
,
323 int addr
, int reg
, u16
*val
);
324 int (*phy_write
)(struct mv88e6xxx_chip
*chip
,
326 int addr
, int reg
, u16 val
);
328 /* Priority Override Table operations */
329 int (*pot_clear
)(struct mv88e6xxx_chip
*chip
);
331 /* PHY Polling Unit (PPU) operations */
332 int (*ppu_enable
)(struct mv88e6xxx_chip
*chip
);
333 int (*ppu_disable
)(struct mv88e6xxx_chip
*chip
);
335 /* Switch Software Reset */
336 int (*reset
)(struct mv88e6xxx_chip
*chip
);
338 /* RGMII Receive/Transmit Timing Control
339 * Add delay on PHY_INTERFACE_MODE_RGMII_*ID, no delay otherwise.
341 int (*port_set_rgmii_delay
)(struct mv88e6xxx_chip
*chip
, int port
,
342 phy_interface_t mode
);
344 #define LINK_FORCED_DOWN 0
345 #define LINK_FORCED_UP 1
346 #define LINK_UNFORCED -2
348 /* Port's MAC link state
349 * Use LINK_FORCED_UP or LINK_FORCED_DOWN to force link up or down,
350 * or LINK_UNFORCED for normal link detection.
352 int (*port_set_link
)(struct mv88e6xxx_chip
*chip
, int port
, int link
);
354 #define DUPLEX_UNFORCED -2
356 /* Port's MAC duplex mode
358 * Use DUPLEX_HALF or DUPLEX_FULL to force half or full duplex,
359 * or DUPLEX_UNFORCED for normal duplex detection.
361 int (*port_set_duplex
)(struct mv88e6xxx_chip
*chip
, int port
, int dup
);
366 /* Enable/disable sending Pause */
367 int (*port_set_pause
)(struct mv88e6xxx_chip
*chip
, int port
,
370 #define SPEED_MAX INT_MAX
371 #define SPEED_UNFORCED -2
373 /* Port's MAC speed (in Mbps)
375 * Depending on the chip, 10, 100, 200, 1000, 2500, 10000 are valid.
376 * Use SPEED_UNFORCED for normal detection, SPEED_MAX for max value.
378 int (*port_set_speed
)(struct mv88e6xxx_chip
*chip
, int port
, int speed
);
380 int (*port_tag_remap
)(struct mv88e6xxx_chip
*chip
, int port
);
382 int (*port_set_frame_mode
)(struct mv88e6xxx_chip
*chip
, int port
,
383 enum mv88e6xxx_frame_mode mode
);
384 int (*port_set_egress_floods
)(struct mv88e6xxx_chip
*chip
, int port
,
385 bool unicast
, bool multicast
);
386 int (*port_set_ether_type
)(struct mv88e6xxx_chip
*chip
, int port
,
388 int (*port_set_jumbo_size
)(struct mv88e6xxx_chip
*chip
, int port
,
391 int (*port_egress_rate_limiting
)(struct mv88e6xxx_chip
*chip
, int port
);
392 int (*port_pause_limit
)(struct mv88e6xxx_chip
*chip
, int port
, u8 in
,
394 int (*port_disable_learn_limit
)(struct mv88e6xxx_chip
*chip
, int port
);
395 int (*port_disable_pri_override
)(struct mv88e6xxx_chip
*chip
, int port
);
397 /* CMODE control what PHY mode the MAC will use, eg. SGMII, RGMII, etc.
398 * Some chips allow this to be configured on specific ports.
400 int (*port_set_cmode
)(struct mv88e6xxx_chip
*chip
, int port
,
401 phy_interface_t mode
);
402 int (*port_get_cmode
)(struct mv88e6xxx_chip
*chip
, int port
, u8
*cmode
);
404 /* Some devices have a per port register indicating what is
405 * the upstream port this port should forward to.
407 int (*port_set_upstream_port
)(struct mv88e6xxx_chip
*chip
, int port
,
409 /* Return the port link state, as required by phylink */
410 int (*port_link_state
)(struct mv88e6xxx_chip
*chip
, int port
,
411 struct phylink_link_state
*state
);
413 /* Snapshot the statistics for a port. The statistics can then
414 * be read back a leisure but still with a consistent view.
416 int (*stats_snapshot
)(struct mv88e6xxx_chip
*chip
, int port
);
418 /* Set the histogram mode for statistics, when the control registers
419 * are separated out of the STATS_OP register.
421 int (*stats_set_histogram
)(struct mv88e6xxx_chip
*chip
);
423 /* Return the number of strings describing statistics */
424 int (*stats_get_sset_count
)(struct mv88e6xxx_chip
*chip
);
425 int (*stats_get_strings
)(struct mv88e6xxx_chip
*chip
, uint8_t *data
);
426 int (*stats_get_stats
)(struct mv88e6xxx_chip
*chip
, int port
,
428 int (*set_cpu_port
)(struct mv88e6xxx_chip
*chip
, int port
);
429 int (*set_egress_port
)(struct mv88e6xxx_chip
*chip
, int port
);
431 #define MV88E6XXX_CASCADE_PORT_NONE 0xe
432 #define MV88E6XXX_CASCADE_PORT_MULTIPLE 0xf
434 int (*set_cascade_port
)(struct mv88e6xxx_chip
*chip
, int port
);
436 const struct mv88e6xxx_irq_ops
*watchdog_ops
;
438 int (*mgmt_rsvd2cpu
)(struct mv88e6xxx_chip
*chip
);
440 /* Power on/off a SERDES interface */
441 int (*serdes_power
)(struct mv88e6xxx_chip
*chip
, int port
, bool on
);
443 /* SERDES interrupt handling */
444 int (*serdes_irq_setup
)(struct mv88e6xxx_chip
*chip
, int port
);
445 void (*serdes_irq_free
)(struct mv88e6xxx_chip
*chip
, int port
);
447 /* Statistics from the SERDES interface */
448 int (*serdes_get_sset_count
)(struct mv88e6xxx_chip
*chip
, int port
);
449 int (*serdes_get_strings
)(struct mv88e6xxx_chip
*chip
, int port
,
451 int (*serdes_get_stats
)(struct mv88e6xxx_chip
*chip
, int port
,
454 /* VLAN Translation Unit operations */
455 int (*vtu_getnext
)(struct mv88e6xxx_chip
*chip
,
456 struct mv88e6xxx_vtu_entry
*entry
);
457 int (*vtu_loadpurge
)(struct mv88e6xxx_chip
*chip
,
458 struct mv88e6xxx_vtu_entry
*entry
);
460 /* GPIO operations */
461 const struct mv88e6xxx_gpio_ops
*gpio_ops
;
463 /* Interface to the AVB/PTP registers */
464 const struct mv88e6xxx_avb_ops
*avb_ops
;
466 /* Remote Management Unit operations */
467 int (*rmu_disable
)(struct mv88e6xxx_chip
*chip
);
469 /* Precision Time Protocol operations */
470 const struct mv88e6xxx_ptp_ops
*ptp_ops
;
473 void (*phylink_validate
)(struct mv88e6xxx_chip
*chip
, int port
,
475 struct phylink_link_state
*state
);
478 struct mv88e6xxx_irq_ops
{
479 /* Action to be performed when the interrupt happens */
480 int (*irq_action
)(struct mv88e6xxx_chip
*chip
, int irq
);
481 /* Setup the hardware to generate the interrupt */
482 int (*irq_setup
)(struct mv88e6xxx_chip
*chip
);
483 /* Reset the hardware to stop generating the interrupt */
484 void (*irq_free
)(struct mv88e6xxx_chip
*chip
);
487 struct mv88e6xxx_gpio_ops
{
488 /* Get/set data on GPIO pin */
489 int (*get_data
)(struct mv88e6xxx_chip
*chip
, unsigned int pin
);
490 int (*set_data
)(struct mv88e6xxx_chip
*chip
, unsigned int pin
,
493 /* get/set GPIO direction */
494 int (*get_dir
)(struct mv88e6xxx_chip
*chip
, unsigned int pin
);
495 int (*set_dir
)(struct mv88e6xxx_chip
*chip
, unsigned int pin
,
498 /* get/set GPIO pin control */
499 int (*get_pctl
)(struct mv88e6xxx_chip
*chip
, unsigned int pin
,
501 int (*set_pctl
)(struct mv88e6xxx_chip
*chip
, unsigned int pin
,
505 struct mv88e6xxx_avb_ops
{
506 /* Access port-scoped Precision Time Protocol registers */
507 int (*port_ptp_read
)(struct mv88e6xxx_chip
*chip
, int port
, int addr
,
509 int (*port_ptp_write
)(struct mv88e6xxx_chip
*chip
, int port
, int addr
,
512 /* Access global Precision Time Protocol registers */
513 int (*ptp_read
)(struct mv88e6xxx_chip
*chip
, int addr
, u16
*data
,
515 int (*ptp_write
)(struct mv88e6xxx_chip
*chip
, int addr
, u16 data
);
517 /* Access global Time Application Interface registers */
518 int (*tai_read
)(struct mv88e6xxx_chip
*chip
, int addr
, u16
*data
,
520 int (*tai_write
)(struct mv88e6xxx_chip
*chip
, int addr
, u16 data
);
523 struct mv88e6xxx_ptp_ops
{
524 u64 (*clock_read
)(const struct cyclecounter
*cc
);
525 int (*ptp_enable
)(struct ptp_clock_info
*ptp
,
526 struct ptp_clock_request
*rq
, int on
);
527 int (*ptp_verify
)(struct ptp_clock_info
*ptp
, unsigned int pin
,
528 enum ptp_pin_function func
, unsigned int chan
);
529 void (*event_work
)(struct work_struct
*ugly
);
530 int (*port_enable
)(struct mv88e6xxx_chip
*chip
, int port
);
531 int (*port_disable
)(struct mv88e6xxx_chip
*chip
, int port
);
532 int (*global_enable
)(struct mv88e6xxx_chip
*chip
);
533 int (*global_disable
)(struct mv88e6xxx_chip
*chip
);
541 #define STATS_TYPE_PORT BIT(0)
542 #define STATS_TYPE_BANK0 BIT(1)
543 #define STATS_TYPE_BANK1 BIT(2)
545 struct mv88e6xxx_hw_stat
{
546 char string
[ETH_GSTRING_LEN
];
552 static inline bool mv88e6xxx_has_pvt(struct mv88e6xxx_chip
*chip
)
554 return chip
->info
->pvt
;
557 static inline unsigned int mv88e6xxx_num_databases(struct mv88e6xxx_chip
*chip
)
559 return chip
->info
->num_databases
;
562 static inline unsigned int mv88e6xxx_num_ports(struct mv88e6xxx_chip
*chip
)
564 return chip
->info
->num_ports
;
567 static inline u16
mv88e6xxx_port_mask(struct mv88e6xxx_chip
*chip
)
569 return GENMASK(mv88e6xxx_num_ports(chip
) - 1, 0);
572 static inline unsigned int mv88e6xxx_num_gpio(struct mv88e6xxx_chip
*chip
)
574 return chip
->info
->num_gpio
;
577 int mv88e6xxx_read(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16
*val
);
578 int mv88e6xxx_write(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 val
);
579 int mv88e6xxx_update(struct mv88e6xxx_chip
*chip
, int addr
, int reg
,
581 int mv88e6xxx_wait(struct mv88e6xxx_chip
*chip
, int addr
, int reg
, u16 mask
);
582 struct mii_bus
*mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip
*chip
);
584 #endif /* _MV88E6XXX_CHIP_H */