2 * Marvell 88E6xxx Switch Port Registers support
4 * Copyright (c) 2008 Marvell Semiconductor
6 * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
7 * Vivien Didelot <vivien.didelot@savoirfairelinux.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
15 #include <linux/bitfield.h>
16 #include <linux/if_bridge.h>
17 #include <linux/phy.h>
22 int mv88e6xxx_port_read(struct mv88e6xxx_chip
*chip
, int port
, int reg
,
25 int addr
= chip
->info
->port_base_addr
+ port
;
27 return mv88e6xxx_read(chip
, addr
, reg
, val
);
30 int mv88e6xxx_port_write(struct mv88e6xxx_chip
*chip
, int port
, int reg
,
33 int addr
= chip
->info
->port_base_addr
+ port
;
35 return mv88e6xxx_write(chip
, addr
, reg
, val
);
38 /* Offset 0x01: MAC (or PCS or Physical) Control Register
40 * Link, Duplex and Flow Control have one force bit, one value bit.
42 * For port's MAC speed, ForceSpd (or SpdValue) bits 1:0 program the value.
43 * Alternative values require the 200BASE (or AltSpeed) bit 12 set.
44 * Newer chips need a ForcedSpd bit 13 set to consider the value.
47 static int mv88e6xxx_port_set_rgmii_delay(struct mv88e6xxx_chip
*chip
, int port
,
53 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_MAC_CTL
, ®
);
57 reg
&= ~(MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK
|
58 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK
);
61 case PHY_INTERFACE_MODE_RGMII_RXID
:
62 reg
|= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK
;
64 case PHY_INTERFACE_MODE_RGMII_TXID
:
65 reg
|= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK
;
67 case PHY_INTERFACE_MODE_RGMII_ID
:
68 reg
|= MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK
|
69 MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK
;
71 case PHY_INTERFACE_MODE_RGMII
:
77 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_MAC_CTL
, reg
);
81 dev_dbg(chip
->dev
, "p%d: delay RXCLK %s, TXCLK %s\n", port
,
82 reg
& MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_RXCLK
? "yes" : "no",
83 reg
& MV88E6XXX_PORT_MAC_CTL_RGMII_DELAY_TXCLK
? "yes" : "no");
88 int mv88e6352_port_set_rgmii_delay(struct mv88e6xxx_chip
*chip
, int port
,
94 return mv88e6xxx_port_set_rgmii_delay(chip
, port
, mode
);
97 int mv88e6390_port_set_rgmii_delay(struct mv88e6xxx_chip
*chip
, int port
,
103 return mv88e6xxx_port_set_rgmii_delay(chip
, port
, mode
);
106 int mv88e6xxx_port_set_link(struct mv88e6xxx_chip
*chip
, int port
, int link
)
111 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_MAC_CTL
, ®
);
115 reg
&= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_LINK
|
116 MV88E6XXX_PORT_MAC_CTL_LINK_UP
);
119 case LINK_FORCED_DOWN
:
120 reg
|= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK
;
123 reg
|= MV88E6XXX_PORT_MAC_CTL_FORCE_LINK
|
124 MV88E6XXX_PORT_MAC_CTL_LINK_UP
;
127 /* normal link detection */
133 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_MAC_CTL
, reg
);
137 dev_dbg(chip
->dev
, "p%d: %s link %s\n", port
,
138 reg
& MV88E6XXX_PORT_MAC_CTL_FORCE_LINK
? "Force" : "Unforce",
139 reg
& MV88E6XXX_PORT_MAC_CTL_LINK_UP
? "up" : "down");
144 int mv88e6xxx_port_set_duplex(struct mv88e6xxx_chip
*chip
, int port
, int dup
)
149 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_MAC_CTL
, ®
);
153 reg
&= ~(MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX
|
154 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL
);
158 reg
|= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX
;
161 reg
|= MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX
|
162 MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL
;
164 case DUPLEX_UNFORCED
:
165 /* normal duplex detection */
171 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_MAC_CTL
, reg
);
175 dev_dbg(chip
->dev
, "p%d: %s %s duplex\n", port
,
176 reg
& MV88E6XXX_PORT_MAC_CTL_FORCE_DUPLEX
? "Force" : "Unforce",
177 reg
& MV88E6XXX_PORT_MAC_CTL_DUPLEX_FULL
? "full" : "half");
182 static int mv88e6xxx_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
,
183 int speed
, bool alt_bit
, bool force_bit
)
190 ctrl
= MV88E6XXX_PORT_MAC_CTL_SPEED_10
;
193 ctrl
= MV88E6XXX_PORT_MAC_CTL_SPEED_100
;
197 ctrl
= MV88E6XXX_PORT_MAC_CTL_SPEED_100
|
198 MV88E6390_PORT_MAC_CTL_ALTSPEED
;
200 ctrl
= MV88E6065_PORT_MAC_CTL_SPEED_200
;
203 ctrl
= MV88E6XXX_PORT_MAC_CTL_SPEED_1000
;
206 ctrl
= MV88E6390_PORT_MAC_CTL_SPEED_10000
|
207 MV88E6390_PORT_MAC_CTL_ALTSPEED
;
210 /* all bits set, fall through... */
212 ctrl
= MV88E6XXX_PORT_MAC_CTL_SPEED_UNFORCED
;
218 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_MAC_CTL
, ®
);
222 reg
&= ~MV88E6XXX_PORT_MAC_CTL_SPEED_MASK
;
224 reg
&= ~MV88E6390_PORT_MAC_CTL_ALTSPEED
;
226 reg
&= ~MV88E6390_PORT_MAC_CTL_FORCE_SPEED
;
227 if (speed
!= SPEED_UNFORCED
)
228 ctrl
|= MV88E6390_PORT_MAC_CTL_FORCE_SPEED
;
232 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_MAC_CTL
, reg
);
237 dev_dbg(chip
->dev
, "p%d: Speed set to %d Mbps\n", port
, speed
);
239 dev_dbg(chip
->dev
, "p%d: Speed unforced\n", port
);
244 /* Support 10, 100, 200 Mbps (e.g. 88E6065 family) */
245 int mv88e6065_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
, int speed
)
247 if (speed
== SPEED_MAX
)
253 /* Setting 200 Mbps on port 0 to 3 selects 100 Mbps */
254 return mv88e6xxx_port_set_speed(chip
, port
, speed
, false, false);
257 /* Support 10, 100, 1000 Mbps (e.g. 88E6185 family) */
258 int mv88e6185_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
, int speed
)
260 if (speed
== SPEED_MAX
)
263 if (speed
== 200 || speed
> 1000)
266 return mv88e6xxx_port_set_speed(chip
, port
, speed
, false, false);
269 /* Support 10, 100, 200, 1000 Mbps (e.g. 88E6352 family) */
270 int mv88e6352_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
, int speed
)
272 if (speed
== SPEED_MAX
)
278 if (speed
== 200 && port
< 5)
281 return mv88e6xxx_port_set_speed(chip
, port
, speed
, true, false);
284 /* Support 10, 100, 200, 1000, 2500 Mbps (e.g. 88E6390) */
285 int mv88e6390_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
, int speed
)
287 if (speed
== SPEED_MAX
)
288 speed
= port
< 9 ? 1000 : 2500;
293 if (speed
== 200 && port
!= 0)
296 if (speed
== 2500 && port
< 9)
299 return mv88e6xxx_port_set_speed(chip
, port
, speed
, true, true);
302 /* Support 10, 100, 200, 1000, 2500, 10000 Mbps (e.g. 88E6190X) */
303 int mv88e6390x_port_set_speed(struct mv88e6xxx_chip
*chip
, int port
, int speed
)
305 if (speed
== SPEED_MAX
)
306 speed
= port
< 9 ? 1000 : 10000;
308 if (speed
== 200 && port
!= 0)
311 if (speed
>= 2500 && port
< 9)
314 return mv88e6xxx_port_set_speed(chip
, port
, speed
, true, true);
317 int mv88e6390x_port_set_cmode(struct mv88e6xxx_chip
*chip
, int port
,
318 phy_interface_t mode
)
324 if (mode
== PHY_INTERFACE_MODE_NA
)
327 if (port
!= 9 && port
!= 10)
331 case PHY_INTERFACE_MODE_1000BASEX
:
332 cmode
= MV88E6XXX_PORT_STS_CMODE_1000BASE_X
;
334 case PHY_INTERFACE_MODE_SGMII
:
335 cmode
= MV88E6XXX_PORT_STS_CMODE_SGMII
;
337 case PHY_INTERFACE_MODE_2500BASEX
:
338 cmode
= MV88E6XXX_PORT_STS_CMODE_2500BASEX
;
340 case PHY_INTERFACE_MODE_XGMII
:
341 cmode
= MV88E6XXX_PORT_STS_CMODE_XAUI
;
343 case PHY_INTERFACE_MODE_RXAUI
:
344 cmode
= MV88E6XXX_PORT_STS_CMODE_RXAUI
;
351 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_STS
, ®
);
355 reg
&= ~MV88E6XXX_PORT_STS_CMODE_MASK
;
358 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_STS
, reg
);
366 int mv88e6xxx_port_get_cmode(struct mv88e6xxx_chip
*chip
, int port
, u8
*cmode
)
371 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_STS
, ®
);
375 *cmode
= reg
& MV88E6XXX_PORT_STS_CMODE_MASK
;
380 /* Offset 0x02: Jamming Control
382 * Do not limit the period of time that this port can be paused for by
383 * the remote end or the period of time that this port can pause the
386 int mv88e6097_port_pause_limit(struct mv88e6xxx_chip
*chip
, int port
, u8 in
,
389 return mv88e6xxx_port_write(chip
, port
, MV88E6097_PORT_JAM_CTL
,
393 int mv88e6390_port_pause_limit(struct mv88e6xxx_chip
*chip
, int port
, u8 in
,
398 err
= mv88e6xxx_port_write(chip
, port
, MV88E6390_PORT_FLOW_CTL
,
399 MV88E6390_PORT_FLOW_CTL_UPDATE
|
400 MV88E6390_PORT_FLOW_CTL_LIMIT_IN
| in
);
404 return mv88e6xxx_port_write(chip
, port
, MV88E6390_PORT_FLOW_CTL
,
405 MV88E6390_PORT_FLOW_CTL_UPDATE
|
406 MV88E6390_PORT_FLOW_CTL_LIMIT_OUT
| out
);
409 /* Offset 0x04: Port Control Register */
411 static const char * const mv88e6xxx_port_state_names
[] = {
412 [MV88E6XXX_PORT_CTL0_STATE_DISABLED
] = "Disabled",
413 [MV88E6XXX_PORT_CTL0_STATE_BLOCKING
] = "Blocking/Listening",
414 [MV88E6XXX_PORT_CTL0_STATE_LEARNING
] = "Learning",
415 [MV88E6XXX_PORT_CTL0_STATE_FORWARDING
] = "Forwarding",
418 int mv88e6xxx_port_set_state(struct mv88e6xxx_chip
*chip
, int port
, u8 state
)
423 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL0
, ®
);
427 reg
&= ~MV88E6XXX_PORT_CTL0_STATE_MASK
;
430 case BR_STATE_DISABLED
:
431 state
= MV88E6XXX_PORT_CTL0_STATE_DISABLED
;
433 case BR_STATE_BLOCKING
:
434 case BR_STATE_LISTENING
:
435 state
= MV88E6XXX_PORT_CTL0_STATE_BLOCKING
;
437 case BR_STATE_LEARNING
:
438 state
= MV88E6XXX_PORT_CTL0_STATE_LEARNING
;
440 case BR_STATE_FORWARDING
:
441 state
= MV88E6XXX_PORT_CTL0_STATE_FORWARDING
;
449 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL0
, reg
);
453 dev_dbg(chip
->dev
, "p%d: PortState set to %s\n", port
,
454 mv88e6xxx_port_state_names
[state
]);
459 int mv88e6xxx_port_set_egress_mode(struct mv88e6xxx_chip
*chip
, int port
,
460 enum mv88e6xxx_egress_mode mode
)
465 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL0
, ®
);
469 reg
&= ~MV88E6XXX_PORT_CTL0_EGRESS_MODE_MASK
;
472 case MV88E6XXX_EGRESS_MODE_UNMODIFIED
:
473 reg
|= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNMODIFIED
;
475 case MV88E6XXX_EGRESS_MODE_UNTAGGED
:
476 reg
|= MV88E6XXX_PORT_CTL0_EGRESS_MODE_UNTAGGED
;
478 case MV88E6XXX_EGRESS_MODE_TAGGED
:
479 reg
|= MV88E6XXX_PORT_CTL0_EGRESS_MODE_TAGGED
;
481 case MV88E6XXX_EGRESS_MODE_ETHERTYPE
:
482 reg
|= MV88E6XXX_PORT_CTL0_EGRESS_MODE_ETHER_TYPE_DSA
;
488 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL0
, reg
);
491 int mv88e6085_port_set_frame_mode(struct mv88e6xxx_chip
*chip
, int port
,
492 enum mv88e6xxx_frame_mode mode
)
497 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL0
, ®
);
501 reg
&= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK
;
504 case MV88E6XXX_FRAME_MODE_NORMAL
:
505 reg
|= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL
;
507 case MV88E6XXX_FRAME_MODE_DSA
:
508 reg
|= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA
;
514 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL0
, reg
);
517 int mv88e6351_port_set_frame_mode(struct mv88e6xxx_chip
*chip
, int port
,
518 enum mv88e6xxx_frame_mode mode
)
523 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL0
, ®
);
527 reg
&= ~MV88E6XXX_PORT_CTL0_FRAME_MODE_MASK
;
530 case MV88E6XXX_FRAME_MODE_NORMAL
:
531 reg
|= MV88E6XXX_PORT_CTL0_FRAME_MODE_NORMAL
;
533 case MV88E6XXX_FRAME_MODE_DSA
:
534 reg
|= MV88E6XXX_PORT_CTL0_FRAME_MODE_DSA
;
536 case MV88E6XXX_FRAME_MODE_PROVIDER
:
537 reg
|= MV88E6XXX_PORT_CTL0_FRAME_MODE_PROVIDER
;
539 case MV88E6XXX_FRAME_MODE_ETHERTYPE
:
540 reg
|= MV88E6XXX_PORT_CTL0_FRAME_MODE_ETHER_TYPE_DSA
;
546 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL0
, reg
);
549 static int mv88e6185_port_set_forward_unknown(struct mv88e6xxx_chip
*chip
,
550 int port
, bool unicast
)
555 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL0
, ®
);
560 reg
|= MV88E6185_PORT_CTL0_FORWARD_UNKNOWN
;
562 reg
&= ~MV88E6185_PORT_CTL0_FORWARD_UNKNOWN
;
564 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL0
, reg
);
567 int mv88e6352_port_set_egress_floods(struct mv88e6xxx_chip
*chip
, int port
,
568 bool unicast
, bool multicast
)
573 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL0
, ®
);
577 reg
&= ~MV88E6352_PORT_CTL0_EGRESS_FLOODS_MASK
;
579 if (unicast
&& multicast
)
580 reg
|= MV88E6352_PORT_CTL0_EGRESS_FLOODS_ALL_UNKNOWN_DA
;
582 reg
|= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_MC_DA
;
584 reg
|= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_UC_DA
;
586 reg
|= MV88E6352_PORT_CTL0_EGRESS_FLOODS_NO_UNKNOWN_DA
;
588 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL0
, reg
);
591 /* Offset 0x05: Port Control 1 */
593 int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip
*chip
, int port
,
599 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL1
, &val
);
604 val
|= MV88E6XXX_PORT_CTL1_MESSAGE_PORT
;
606 val
&= ~MV88E6XXX_PORT_CTL1_MESSAGE_PORT
;
608 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL1
, val
);
611 /* Offset 0x06: Port Based VLAN Map */
613 int mv88e6xxx_port_set_vlan_map(struct mv88e6xxx_chip
*chip
, int port
, u16 map
)
615 const u16 mask
= mv88e6xxx_port_mask(chip
);
619 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_BASE_VLAN
, ®
);
626 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_BASE_VLAN
, reg
);
630 dev_dbg(chip
->dev
, "p%d: VLANTable set to %.3x\n", port
, map
);
635 int mv88e6xxx_port_get_fid(struct mv88e6xxx_chip
*chip
, int port
, u16
*fid
)
637 const u16 upper_mask
= (mv88e6xxx_num_databases(chip
) - 1) >> 4;
641 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
642 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_BASE_VLAN
, ®
);
646 *fid
= (reg
& 0xf000) >> 12;
648 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
650 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL1
,
655 *fid
|= (reg
& upper_mask
) << 4;
661 int mv88e6xxx_port_set_fid(struct mv88e6xxx_chip
*chip
, int port
, u16 fid
)
663 const u16 upper_mask
= (mv88e6xxx_num_databases(chip
) - 1) >> 4;
667 if (fid
>= mv88e6xxx_num_databases(chip
))
670 /* Port's default FID lower 4 bits are located in reg 0x06, offset 12 */
671 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_BASE_VLAN
, ®
);
676 reg
|= (fid
& 0x000f) << 12;
678 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_BASE_VLAN
, reg
);
682 /* Port's default FID upper bits are located in reg 0x05, offset 0 */
684 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL1
,
690 reg
|= (fid
>> 4) & upper_mask
;
692 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL1
,
698 dev_dbg(chip
->dev
, "p%d: FID set to %u\n", port
, fid
);
703 /* Offset 0x07: Default Port VLAN ID & Priority */
705 int mv88e6xxx_port_get_pvid(struct mv88e6xxx_chip
*chip
, int port
, u16
*pvid
)
710 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_DEFAULT_VLAN
,
715 *pvid
= reg
& MV88E6XXX_PORT_DEFAULT_VLAN_MASK
;
720 int mv88e6xxx_port_set_pvid(struct mv88e6xxx_chip
*chip
, int port
, u16 pvid
)
725 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_DEFAULT_VLAN
,
730 reg
&= ~MV88E6XXX_PORT_DEFAULT_VLAN_MASK
;
731 reg
|= pvid
& MV88E6XXX_PORT_DEFAULT_VLAN_MASK
;
733 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_DEFAULT_VLAN
,
738 dev_dbg(chip
->dev
, "p%d: DefaultVID set to %u\n", port
, pvid
);
743 /* Offset 0x08: Port Control 2 Register */
745 static const char * const mv88e6xxx_port_8021q_mode_names
[] = {
746 [MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED
] = "Disabled",
747 [MV88E6XXX_PORT_CTL2_8021Q_MODE_FALLBACK
] = "Fallback",
748 [MV88E6XXX_PORT_CTL2_8021Q_MODE_CHECK
] = "Check",
749 [MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE
] = "Secure",
752 static int mv88e6185_port_set_default_forward(struct mv88e6xxx_chip
*chip
,
753 int port
, bool multicast
)
758 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL2
, ®
);
763 reg
|= MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD
;
765 reg
&= ~MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD
;
767 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL2
, reg
);
770 int mv88e6185_port_set_egress_floods(struct mv88e6xxx_chip
*chip
, int port
,
771 bool unicast
, bool multicast
)
775 err
= mv88e6185_port_set_forward_unknown(chip
, port
, unicast
);
779 return mv88e6185_port_set_default_forward(chip
, port
, multicast
);
782 int mv88e6095_port_set_upstream_port(struct mv88e6xxx_chip
*chip
, int port
,
788 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL2
, ®
);
792 reg
&= ~MV88E6095_PORT_CTL2_CPU_PORT_MASK
;
793 reg
|= upstream_port
;
795 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL2
, reg
);
798 int mv88e6xxx_port_set_8021q_mode(struct mv88e6xxx_chip
*chip
, int port
,
804 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL2
, ®
);
808 reg
&= ~MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK
;
809 reg
|= mode
& MV88E6XXX_PORT_CTL2_8021Q_MODE_MASK
;
811 err
= mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL2
, reg
);
815 dev_dbg(chip
->dev
, "p%d: 802.1QMode set to %s\n", port
,
816 mv88e6xxx_port_8021q_mode_names
[mode
]);
821 int mv88e6xxx_port_set_map_da(struct mv88e6xxx_chip
*chip
, int port
)
826 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL2
, ®
);
830 reg
|= MV88E6XXX_PORT_CTL2_MAP_DA
;
832 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL2
, reg
);
835 int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip
*chip
, int port
,
841 err
= mv88e6xxx_port_read(chip
, port
, MV88E6XXX_PORT_CTL2
, ®
);
845 reg
&= ~MV88E6XXX_PORT_CTL2_JUMBO_MODE_MASK
;
848 reg
|= MV88E6XXX_PORT_CTL2_JUMBO_MODE_1522
;
849 else if (size
<= 2048)
850 reg
|= MV88E6XXX_PORT_CTL2_JUMBO_MODE_2048
;
851 else if (size
<= 10240)
852 reg
|= MV88E6XXX_PORT_CTL2_JUMBO_MODE_10240
;
856 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_CTL2
, reg
);
859 /* Offset 0x09: Port Rate Control */
861 int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip
*chip
, int port
)
863 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_EGRESS_RATE_CTL1
,
867 int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip
*chip
, int port
)
869 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_EGRESS_RATE_CTL1
,
873 /* Offset 0x0C: Port ATU Control */
875 int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip
*chip
, int port
)
877 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_ATU_CTL
, 0);
880 /* Offset 0x0D: (Priority) Override Register */
882 int mv88e6xxx_port_disable_pri_override(struct mv88e6xxx_chip
*chip
, int port
)
884 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_PRI_OVERRIDE
, 0);
887 /* Offset 0x0f: Port Ether type */
889 int mv88e6351_port_set_ether_type(struct mv88e6xxx_chip
*chip
, int port
,
892 return mv88e6xxx_port_write(chip
, port
, MV88E6XXX_PORT_ETH_TYPE
, etype
);
895 /* Offset 0x18: Port IEEE Priority Remapping Registers [0-3]
896 * Offset 0x19: Port IEEE Priority Remapping Registers [4-7]
899 int mv88e6095_port_tag_remap(struct mv88e6xxx_chip
*chip
, int port
)
903 /* Use a direct priority mapping for all IEEE tagged frames */
904 err
= mv88e6xxx_port_write(chip
, port
,
905 MV88E6095_PORT_IEEE_PRIO_REMAP_0123
,
910 return mv88e6xxx_port_write(chip
, port
,
911 MV88E6095_PORT_IEEE_PRIO_REMAP_4567
,
915 static int mv88e6xxx_port_ieeepmt_write(struct mv88e6xxx_chip
*chip
,
916 int port
, u16 table
, u8 ptr
, u16 data
)
920 reg
= MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_UPDATE
| table
|
921 (ptr
<< __bf_shf(MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_PTR_MASK
)) |
922 (data
& MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_DATA_MASK
);
924 return mv88e6xxx_port_write(chip
, port
,
925 MV88E6390_PORT_IEEE_PRIO_MAP_TABLE
, reg
);
928 int mv88e6390_port_tag_remap(struct mv88e6xxx_chip
*chip
, int port
)
933 for (i
= 0; i
<= 7; i
++) {
934 table
= MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_INGRESS_PCP
;
935 err
= mv88e6xxx_port_ieeepmt_write(chip
, port
, table
, i
,
940 table
= MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_GREEN_PCP
;
941 err
= mv88e6xxx_port_ieeepmt_write(chip
, port
, table
, i
, i
);
945 table
= MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_YELLOW_PCP
;
946 err
= mv88e6xxx_port_ieeepmt_write(chip
, port
, table
, i
, i
);
950 table
= MV88E6390_PORT_IEEE_PRIO_MAP_TABLE_EGRESS_AVB_PCP
;
951 err
= mv88e6xxx_port_ieeepmt_write(chip
, port
, table
, i
, i
);