1 /******************************************************************************
3 * This file is provided under a dual BSD/GPLv2 license. When using or
4 * redistributing this file, you may do so under either license.
8 * Copyright(c) 2007 - 2015 Intel Corporation. All rights reserved.
9 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
10 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of version 2 of the GNU General Public License as
14 * published by the Free Software Foundation.
16 * This program is distributed in the hope that it will be useful, but
17 * WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
26 * The full GNU General Public License is included in this distribution
27 * in the file called COPYING.
29 * Contact Information:
30 * Intel Linux Wireless <linuxwifi@intel.com>
31 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
35 * Copyright(c) 2005 - 2015 Intel Corporation. All rights reserved.
36 * Copyright(c) 2013 - 2015 Intel Mobile Communications GmbH
37 * Copyright(c) 2016 - 2017 Intel Deutschland GmbH
38 * All rights reserved.
40 * Redistribution and use in source and binary forms, with or without
41 * modification, are permitted provided that the following conditions
44 * * Redistributions of source code must retain the above copyright
45 * notice, this list of conditions and the following disclaimer.
46 * * Redistributions in binary form must reproduce the above copyright
47 * notice, this list of conditions and the following disclaimer in
48 * the documentation and/or other materials provided with the
50 * * Neither the name Intel Corporation nor the names of its
51 * contributors may be used to endorse or promote products derived
52 * from this software without specific prior written permission.
54 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
55 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
56 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
57 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
58 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
59 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
60 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
61 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
62 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
63 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
64 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
66 *****************************************************************************/
67 #include <linux/pci.h>
68 #include <linux/pci-aspm.h>
69 #include <linux/interrupt.h>
70 #include <linux/debugfs.h>
71 #include <linux/sched.h>
72 #include <linux/bitops.h>
73 #include <linux/gfp.h>
74 #include <linux/vmalloc.h>
75 #include <linux/pm_runtime.h>
78 #include "iwl-trans.h"
82 #include "iwl-agn-hw.h"
83 #include "fw/error-dump.h"
87 /* extended range in FW SRAM */
88 #define IWL_FW_MEM_EXTENDED_START 0x40000
89 #define IWL_FW_MEM_EXTENDED_END 0x57FFF
91 static void iwl_trans_pcie_dump_regs(struct iwl_trans
*trans
)
93 #define PCI_DUMP_SIZE 64
95 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
96 struct pci_dev
*pdev
= trans_pcie
->pci_dev
;
97 u32 i
, pos
, alloc_size
, *ptr
, *buf
;
100 if (trans_pcie
->pcie_dbg_dumped_once
)
103 /* Should be a multiple of 4 */
104 BUILD_BUG_ON(PCI_DUMP_SIZE
> 4096 || PCI_DUMP_SIZE
& 0x3);
105 /* Alloc a max size buffer */
106 if (PCI_ERR_ROOT_ERR_SRC
+ 4 > PCI_DUMP_SIZE
)
107 alloc_size
= PCI_ERR_ROOT_ERR_SRC
+ 4 + PREFIX_LEN
;
109 alloc_size
= PCI_DUMP_SIZE
+ PREFIX_LEN
;
110 buf
= kmalloc(alloc_size
, GFP_ATOMIC
);
113 prefix
= (char *)buf
+ alloc_size
- PREFIX_LEN
;
115 IWL_ERR(trans
, "iwlwifi transaction failed, dumping registers\n");
117 /* Print wifi device registers */
118 sprintf(prefix
, "iwlwifi %s: ", pci_name(pdev
));
119 IWL_ERR(trans
, "iwlwifi device config registers:\n");
120 for (i
= 0, ptr
= buf
; i
< PCI_DUMP_SIZE
; i
+= 4, ptr
++)
121 if (pci_read_config_dword(pdev
, i
, ptr
))
123 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
, 32, 4, buf
, i
, 0);
125 IWL_ERR(trans
, "iwlwifi device memory mapped registers:\n");
126 for (i
= 0, ptr
= buf
; i
< PCI_DUMP_SIZE
; i
+= 4, ptr
++)
127 *ptr
= iwl_read32(trans
, i
);
128 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
, 32, 4, buf
, i
, 0);
130 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ERR
);
132 IWL_ERR(trans
, "iwlwifi device AER capability structure:\n");
133 for (i
= 0, ptr
= buf
; i
< PCI_ERR_ROOT_COMMAND
; i
+= 4, ptr
++)
134 if (pci_read_config_dword(pdev
, pos
+ i
, ptr
))
136 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
,
140 /* Print parent device registers next */
141 if (!pdev
->bus
->self
)
144 pdev
= pdev
->bus
->self
;
145 sprintf(prefix
, "iwlwifi %s: ", pci_name(pdev
));
147 IWL_ERR(trans
, "iwlwifi parent port (%s) config registers:\n",
149 for (i
= 0, ptr
= buf
; i
< PCI_DUMP_SIZE
; i
+= 4, ptr
++)
150 if (pci_read_config_dword(pdev
, i
, ptr
))
152 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
, 32, 4, buf
, i
, 0);
154 /* Print root port AER registers */
156 pdev
= pcie_find_root_port(pdev
);
158 pos
= pci_find_ext_capability(pdev
, PCI_EXT_CAP_ID_ERR
);
160 IWL_ERR(trans
, "iwlwifi root port (%s) AER cap structure:\n",
162 sprintf(prefix
, "iwlwifi %s: ", pci_name(pdev
));
163 for (i
= 0, ptr
= buf
; i
<= PCI_ERR_ROOT_ERR_SRC
; i
+= 4, ptr
++)
164 if (pci_read_config_dword(pdev
, pos
+ i
, ptr
))
166 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
, 32,
172 print_hex_dump(KERN_ERR
, prefix
, DUMP_PREFIX_OFFSET
, 32, 4, buf
, i
, 0);
173 IWL_ERR(trans
, "Read failed at 0x%X\n", i
);
175 trans_pcie
->pcie_dbg_dumped_once
= 1;
179 static void iwl_pcie_free_fw_monitor(struct iwl_trans
*trans
)
181 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
183 if (!trans_pcie
->fw_mon_page
)
186 dma_unmap_page(trans
->dev
, trans_pcie
->fw_mon_phys
,
187 trans_pcie
->fw_mon_size
, DMA_FROM_DEVICE
);
188 __free_pages(trans_pcie
->fw_mon_page
,
189 get_order(trans_pcie
->fw_mon_size
));
190 trans_pcie
->fw_mon_page
= NULL
;
191 trans_pcie
->fw_mon_phys
= 0;
192 trans_pcie
->fw_mon_size
= 0;
195 static void iwl_pcie_alloc_fw_monitor(struct iwl_trans
*trans
, u8 max_power
)
197 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
198 struct page
*page
= NULL
;
204 /* default max_power is maximum */
210 if (WARN(max_power
> 26,
211 "External buffer size for monitor is too big %d, check the FW TLV\n",
215 if (trans_pcie
->fw_mon_page
) {
216 dma_sync_single_for_device(trans
->dev
, trans_pcie
->fw_mon_phys
,
217 trans_pcie
->fw_mon_size
,
223 for (power
= max_power
; power
>= 11; power
--) {
227 order
= get_order(size
);
228 page
= alloc_pages(__GFP_COMP
| __GFP_NOWARN
| __GFP_ZERO
,
233 phys
= dma_map_page(trans
->dev
, page
, 0, PAGE_SIZE
<< order
,
235 if (dma_mapping_error(trans
->dev
, phys
)) {
236 __free_pages(page
, order
);
241 "Allocated 0x%08x bytes (order %d) for firmware monitor.\n",
246 if (WARN_ON_ONCE(!page
))
249 if (power
!= max_power
)
251 "Sorry - debug buffer is only %luK while you requested %luK\n",
252 (unsigned long)BIT(power
- 10),
253 (unsigned long)BIT(max_power
- 10));
255 trans_pcie
->fw_mon_page
= page
;
256 trans_pcie
->fw_mon_phys
= phys
;
257 trans_pcie
->fw_mon_size
= size
;
260 static u32
iwl_trans_pcie_read_shr(struct iwl_trans
*trans
, u32 reg
)
262 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
263 ((reg
& 0x0000ffff) | (2 << 28)));
264 return iwl_read32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
);
267 static void iwl_trans_pcie_write_shr(struct iwl_trans
*trans
, u32 reg
, u32 val
)
269 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_DATA_REG
, val
);
270 iwl_write32(trans
, HEEP_CTRL_WRD_PCIEX_CTRL_REG
,
271 ((reg
& 0x0000ffff) | (3 << 28)));
274 static void iwl_pcie_set_pwr(struct iwl_trans
*trans
, bool vaux
)
276 if (trans
->cfg
->apmg_not_supported
)
279 if (vaux
&& pci_pme_capable(to_pci_dev(trans
->dev
), PCI_D3cold
))
280 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
281 APMG_PS_CTRL_VAL_PWR_SRC_VAUX
,
282 ~APMG_PS_CTRL_MSK_PWR_SRC
);
284 iwl_set_bits_mask_prph(trans
, APMG_PS_CTRL_REG
,
285 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN
,
286 ~APMG_PS_CTRL_MSK_PWR_SRC
);
290 #define PCI_CFG_RETRY_TIMEOUT 0x041
292 void iwl_pcie_apm_config(struct iwl_trans
*trans
)
294 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
299 * HW bug W/A for instability in PCIe bus L0S->L1 transition.
300 * Check if BIOS (or OS) enabled L1-ASPM on this device.
301 * If so (likely), disable L0S, so device moves directly L0->L1;
302 * costs negligible amount of power savings.
303 * If not (unlikely), enable L0S, so there is at least some
304 * power savings, even without L1.
306 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_LNKCTL
, &lctl
);
307 if (lctl
& PCI_EXP_LNKCTL_ASPM_L1
)
308 iwl_set_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
310 iwl_clear_bit(trans
, CSR_GIO_REG
, CSR_GIO_REG_VAL_L0S_ENABLED
);
311 trans
->pm_support
= !(lctl
& PCI_EXP_LNKCTL_ASPM_L0S
);
313 pcie_capability_read_word(trans_pcie
->pci_dev
, PCI_EXP_DEVCTL2
, &cap
);
314 trans
->ltr_enabled
= cap
& PCI_EXP_DEVCTL2_LTR_EN
;
315 IWL_DEBUG_POWER(trans
, "L1 %sabled - LTR %sabled\n",
316 (lctl
& PCI_EXP_LNKCTL_ASPM_L1
) ? "En" : "Dis",
317 trans
->ltr_enabled
? "En" : "Dis");
321 * Start up NIC's basic functionality after it has been reset
322 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop())
323 * NOTE: This does not load uCode nor start the embedded processor
325 static int iwl_pcie_apm_init(struct iwl_trans
*trans
)
329 IWL_DEBUG_INFO(trans
, "Init card's basic functions\n");
332 * Use "set_bit" below rather than "write", to preserve any hardware
333 * bits already set by default after reset.
336 /* Disable L0S exit timer (platform NMI Work/Around) */
337 if (trans
->cfg
->device_family
< IWL_DEVICE_FAMILY_8000
)
338 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
339 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER
);
342 * Disable L0s without affecting L1;
343 * don't wait for ICH L0s (ICH bug W/A)
345 iwl_set_bit(trans
, CSR_GIO_CHICKEN_BITS
,
346 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX
);
348 /* Set FH wait threshold to maximum (HW error during stress W/A) */
349 iwl_set_bit(trans
, CSR_DBG_HPET_MEM_REG
, CSR_DBG_HPET_MEM_REG_VAL
);
352 * Enable HAP INTA (interrupt from management bus) to
353 * wake device's PCI Express link L1a -> L0s
355 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
356 CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A
);
358 iwl_pcie_apm_config(trans
);
360 /* Configure analog phase-lock-loop before activating to D0A */
361 if (trans
->cfg
->base_params
->pll_cfg
)
362 iwl_set_bit(trans
, CSR_ANA_PLL_CFG
, CSR50_ANA_PLL_CFG_VAL
);
365 * Set "initialization complete" bit to move adapter from
366 * D0U* --> D0A* (powered-up active) state.
368 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
371 * Wait for clock stabilization; once stabilized, access to
372 * device-internal resources is supported, e.g. iwl_write_prph()
373 * and accesses to uCode SRAM.
375 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
376 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
377 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
, 25000);
379 IWL_ERR(trans
, "Failed to init the card\n");
383 if (trans
->cfg
->host_interrupt_operation_mode
) {
385 * This is a bit of an abuse - This is needed for 7260 / 3160
386 * only check host_interrupt_operation_mode even if this is
387 * not related to host_interrupt_operation_mode.
389 * Enable the oscillator to count wake up time for L1 exit. This
390 * consumes slightly more power (100uA) - but allows to be sure
391 * that we wake up from L1 on time.
393 * This looks weird: read twice the same register, discard the
394 * value, set a bit, and yet again, read that same register
395 * just to discard the value. But that's the way the hardware
398 iwl_read_prph(trans
, OSC_CLK
);
399 iwl_read_prph(trans
, OSC_CLK
);
400 iwl_set_bits_prph(trans
, OSC_CLK
, OSC_CLK_FORCE_CONTROL
);
401 iwl_read_prph(trans
, OSC_CLK
);
402 iwl_read_prph(trans
, OSC_CLK
);
406 * Enable DMA clock and wait for it to stabilize.
408 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0"
409 * bits do not disable clocks. This preserves any hardware
410 * bits already set by default in "CLK_CTRL_REG" after reset.
412 if (!trans
->cfg
->apmg_not_supported
) {
413 iwl_write_prph(trans
, APMG_CLK_EN_REG
,
414 APMG_CLK_VAL_DMA_CLK_RQT
);
417 /* Disable L1-Active */
418 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
419 APMG_PCIDEV_STT_VAL_L1_ACT_DIS
);
421 /* Clear the interrupt in APMG if the NIC is in RFKILL */
422 iwl_write_prph(trans
, APMG_RTC_INT_STT_REG
,
423 APMG_RTC_INT_STT_RFKILL
);
426 set_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
432 * Enable LP XTAL to avoid HW bug where device may consume much power if
433 * FW is not loaded after device reset. LP XTAL is disabled by default
434 * after device HW reset. Do it only if XTAL is fed by internal source.
435 * Configure device's "persistence" mode to avoid resetting XTAL again when
436 * SHRD_HW_RST occurs in S3.
438 static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans
*trans
)
442 u32 apmg_xtal_cfg_reg
;
446 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
447 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
449 iwl_pcie_sw_reset(trans
);
452 * Set "initialization complete" bit to move adapter from
453 * D0U* --> D0A* (powered-up active) state.
455 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
458 * Wait for clock stabilization; once stabilized, access to
459 * device-internal resources is possible.
461 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
462 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
463 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
465 if (WARN_ON(ret
< 0)) {
466 IWL_ERR(trans
, "Access time out - failed to enable LP XTAL\n");
467 /* Release XTAL ON request */
468 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
469 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
474 * Clear "disable persistence" to avoid LP XTAL resetting when
475 * SHRD_HW_RST is applied in S3.
477 iwl_clear_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
478 APMG_PCIDEV_STT_VAL_PERSIST_DIS
);
481 * Force APMG XTAL to be active to prevent its disabling by HW
482 * caused by APMG idle state.
484 apmg_xtal_cfg_reg
= iwl_trans_pcie_read_shr(trans
,
485 SHR_APMG_XTAL_CFG_REG
);
486 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
488 SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
490 iwl_pcie_sw_reset(trans
);
492 /* Enable LP XTAL by indirect access through CSR */
493 apmg_gp1_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_GP1_REG
);
494 iwl_trans_pcie_write_shr(trans
, SHR_APMG_GP1_REG
, apmg_gp1_reg
|
495 SHR_APMG_GP1_WF_XTAL_LP_EN
|
496 SHR_APMG_GP1_CHICKEN_BIT_SELECT
);
498 /* Clear delay line clock power up */
499 dl_cfg_reg
= iwl_trans_pcie_read_shr(trans
, SHR_APMG_DL_CFG_REG
);
500 iwl_trans_pcie_write_shr(trans
, SHR_APMG_DL_CFG_REG
, dl_cfg_reg
&
501 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP
);
504 * Enable persistence mode to avoid LP XTAL resetting when
505 * SHRD_HW_RST is applied in S3.
507 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
508 CSR_HW_IF_CONFIG_REG_PERSIST_MODE
);
511 * Clear "initialization complete" bit to move adapter from
512 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
514 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
515 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
517 /* Activates XTAL resources monitor */
518 __iwl_trans_pcie_set_bit(trans
, CSR_MONITOR_CFG_REG
,
519 CSR_MONITOR_XTAL_RESOURCES
);
521 /* Release XTAL ON request */
522 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
523 CSR_GP_CNTRL_REG_FLAG_XTAL_ON
);
526 /* Release APMG XTAL */
527 iwl_trans_pcie_write_shr(trans
, SHR_APMG_XTAL_CFG_REG
,
529 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ
);
532 void iwl_pcie_apm_stop_master(struct iwl_trans
*trans
)
536 /* stop device's busmaster DMA activity */
537 iwl_set_bit(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_STOP_MASTER
);
539 ret
= iwl_poll_bit(trans
, CSR_RESET
,
540 CSR_RESET_REG_FLAG_MASTER_DISABLED
,
541 CSR_RESET_REG_FLAG_MASTER_DISABLED
, 100);
543 IWL_WARN(trans
, "Master Disable Timed Out, 100 usec\n");
545 IWL_DEBUG_INFO(trans
, "stop master\n");
548 static void iwl_pcie_apm_stop(struct iwl_trans
*trans
, bool op_mode_leave
)
550 IWL_DEBUG_INFO(trans
, "Stop card, put in low power state\n");
553 if (!test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
554 iwl_pcie_apm_init(trans
);
556 /* inform ME that we are leaving */
557 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
)
558 iwl_set_bits_prph(trans
, APMG_PCIDEV_STT_REG
,
559 APMG_PCIDEV_STT_VAL_WAKE_ME
);
560 else if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
) {
561 iwl_set_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
562 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
563 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
564 CSR_HW_IF_CONFIG_REG_PREPARE
|
565 CSR_HW_IF_CONFIG_REG_ENABLE_PME
);
567 iwl_clear_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
568 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
573 clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
);
575 /* Stop device's DMA activity */
576 iwl_pcie_apm_stop_master(trans
);
578 if (trans
->cfg
->lp_xtal_workaround
) {
579 iwl_pcie_apm_lp_xtal_enable(trans
);
583 iwl_pcie_sw_reset(trans
);
586 * Clear "initialization complete" bit to move adapter from
587 * D0A* (powered-up Active) --> D0U* (Uninitialized) state.
589 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
590 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
593 static int iwl_pcie_nic_init(struct iwl_trans
*trans
)
595 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
599 spin_lock(&trans_pcie
->irq_lock
);
600 ret
= iwl_pcie_apm_init(trans
);
601 spin_unlock(&trans_pcie
->irq_lock
);
606 iwl_pcie_set_pwr(trans
, false);
608 iwl_op_mode_nic_config(trans
->op_mode
);
610 /* Allocate the RX queue, or reset if it is already allocated */
611 iwl_pcie_rx_init(trans
);
613 /* Allocate or reset and init all Tx and Command queues */
614 if (iwl_pcie_tx_init(trans
))
617 if (trans
->cfg
->base_params
->shadow_reg_enable
) {
618 /* enable shadow regs in HW */
619 iwl_set_bit(trans
, CSR_MAC_SHADOW_REG_CTRL
, 0x800FFFFF);
620 IWL_DEBUG_INFO(trans
, "Enabling shadow registers in device\n");
626 #define HW_READY_TIMEOUT (50)
628 /* Note: returns poll_bit return value, which is >= 0 if success */
629 static int iwl_pcie_set_hw_ready(struct iwl_trans
*trans
)
633 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
634 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
);
636 /* See if we got it */
637 ret
= iwl_poll_bit(trans
, CSR_HW_IF_CONFIG_REG
,
638 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
639 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY
,
643 iwl_set_bit(trans
, CSR_MBOX_SET_REG
, CSR_MBOX_SET_REG_OS_ALIVE
);
645 IWL_DEBUG_INFO(trans
, "hardware%s ready\n", ret
< 0 ? " not" : "");
649 /* Note: returns standard 0/-ERROR code */
650 int iwl_pcie_prepare_card_hw(struct iwl_trans
*trans
)
656 IWL_DEBUG_INFO(trans
, "iwl_trans_prepare_card_hw enter\n");
658 ret
= iwl_pcie_set_hw_ready(trans
);
659 /* If the card is ready, exit 0 */
663 iwl_set_bit(trans
, CSR_DBG_LINK_PWR_MGMT_REG
,
664 CSR_RESET_LINK_PWR_MGMT_DISABLED
);
665 usleep_range(1000, 2000);
667 for (iter
= 0; iter
< 10; iter
++) {
668 /* If HW is not ready, prepare the conditions to check again */
669 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
670 CSR_HW_IF_CONFIG_REG_PREPARE
);
673 ret
= iwl_pcie_set_hw_ready(trans
);
677 usleep_range(200, 1000);
679 } while (t
< 150000);
683 IWL_ERR(trans
, "Couldn't prepare the card\n");
691 static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans
*trans
,
692 u32 dst_addr
, dma_addr_t phy_addr
,
695 iwl_write32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
696 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE
);
698 iwl_write32(trans
, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL
),
701 iwl_write32(trans
, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL
),
702 phy_addr
& FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK
);
704 iwl_write32(trans
, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL
),
705 (iwl_get_dma_hi_addr(phy_addr
)
706 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT
) | byte_cnt
);
708 iwl_write32(trans
, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL
),
709 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM
) |
710 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX
) |
711 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID
);
713 iwl_write32(trans
, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL
),
714 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE
|
715 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE
|
716 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD
);
719 static int iwl_pcie_load_firmware_chunk(struct iwl_trans
*trans
,
720 u32 dst_addr
, dma_addr_t phy_addr
,
723 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
727 trans_pcie
->ucode_write_complete
= false;
729 if (!iwl_trans_grab_nic_access(trans
, &flags
))
732 iwl_pcie_load_firmware_chunk_fh(trans
, dst_addr
, phy_addr
,
734 iwl_trans_release_nic_access(trans
, &flags
);
736 ret
= wait_event_timeout(trans_pcie
->ucode_write_waitq
,
737 trans_pcie
->ucode_write_complete
, 5 * HZ
);
739 IWL_ERR(trans
, "Failed to load firmware chunk!\n");
740 iwl_trans_pcie_dump_regs(trans
);
747 static int iwl_pcie_load_section(struct iwl_trans
*trans
, u8 section_num
,
748 const struct fw_desc
*section
)
752 u32 offset
, chunk_sz
= min_t(u32
, FH_MEM_TB_MAX_LENGTH
, section
->len
);
755 IWL_DEBUG_FW(trans
, "[%d] uCode section being loaded...\n",
758 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
, &p_addr
,
759 GFP_KERNEL
| __GFP_NOWARN
);
761 IWL_DEBUG_INFO(trans
, "Falling back to small chunks of DMA\n");
762 chunk_sz
= PAGE_SIZE
;
763 v_addr
= dma_alloc_coherent(trans
->dev
, chunk_sz
,
764 &p_addr
, GFP_KERNEL
);
769 for (offset
= 0; offset
< section
->len
; offset
+= chunk_sz
) {
770 u32 copy_size
, dst_addr
;
771 bool extended_addr
= false;
773 copy_size
= min_t(u32
, chunk_sz
, section
->len
- offset
);
774 dst_addr
= section
->offset
+ offset
;
776 if (dst_addr
>= IWL_FW_MEM_EXTENDED_START
&&
777 dst_addr
<= IWL_FW_MEM_EXTENDED_END
)
778 extended_addr
= true;
781 iwl_set_bits_prph(trans
, LMPM_CHICK
,
782 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
784 memcpy(v_addr
, (u8
*)section
->data
+ offset
, copy_size
);
785 ret
= iwl_pcie_load_firmware_chunk(trans
, dst_addr
, p_addr
,
789 iwl_clear_bits_prph(trans
, LMPM_CHICK
,
790 LMPM_CHICK_EXTENDED_ADDR_SPACE
);
794 "Could not load the [%d] uCode section\n",
800 dma_free_coherent(trans
->dev
, chunk_sz
, v_addr
, p_addr
);
804 static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans
*trans
,
805 const struct fw_img
*image
,
807 int *first_ucode_section
)
810 int i
, ret
= 0, sec_num
= 0x1;
811 u32 val
, last_read_idx
= 0;
815 *first_ucode_section
= 0;
818 (*first_ucode_section
)++;
821 for (i
= *first_ucode_section
; i
< image
->num_sec
; i
++) {
825 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
827 * PAGING_SEPARATOR_SECTION delimiter - separate between
828 * CPU2 non paged to CPU2 paging sec.
830 if (!image
->sec
[i
].data
||
831 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
||
832 image
->sec
[i
].offset
== PAGING_SEPARATOR_SECTION
) {
834 "Break since Data not valid or Empty section, sec = %d\n",
839 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
843 /* Notify ucode of loaded section number and status */
844 val
= iwl_read_direct32(trans
, FH_UCODE_LOAD_STATUS
);
845 val
= val
| (sec_num
<< shift_param
);
846 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
, val
);
848 sec_num
= (sec_num
<< 1) | 0x1;
851 *first_ucode_section
= last_read_idx
;
853 iwl_enable_interrupts(trans
);
855 if (trans
->cfg
->use_tfh
) {
857 iwl_write_prph(trans
, UREG_UCODE_LOAD_STATUS
,
860 iwl_write_prph(trans
, UREG_UCODE_LOAD_STATUS
,
864 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
,
867 iwl_write_direct32(trans
, FH_UCODE_LOAD_STATUS
,
874 static int iwl_pcie_load_cpu_sections(struct iwl_trans
*trans
,
875 const struct fw_img
*image
,
877 int *first_ucode_section
)
880 u32 last_read_idx
= 0;
883 *first_ucode_section
= 0;
885 (*first_ucode_section
)++;
887 for (i
= *first_ucode_section
; i
< image
->num_sec
; i
++) {
891 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between
893 * PAGING_SEPARATOR_SECTION delimiter - separate between
894 * CPU2 non paged to CPU2 paging sec.
896 if (!image
->sec
[i
].data
||
897 image
->sec
[i
].offset
== CPU1_CPU2_SEPARATOR_SECTION
||
898 image
->sec
[i
].offset
== PAGING_SEPARATOR_SECTION
) {
900 "Break since Data not valid or Empty section, sec = %d\n",
905 ret
= iwl_pcie_load_section(trans
, i
, &image
->sec
[i
]);
910 *first_ucode_section
= last_read_idx
;
915 void iwl_pcie_apply_destination(struct iwl_trans
*trans
)
917 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
918 const struct iwl_fw_dbg_dest_tlv
*dest
= trans
->dbg_dest_tlv
;
923 "DBG DEST version is %d - expect issues\n",
926 IWL_INFO(trans
, "Applying debug destination %s\n",
927 get_fw_dbg_mode_string(dest
->monitor_mode
));
929 if (dest
->monitor_mode
== EXTERNAL_MODE
)
930 iwl_pcie_alloc_fw_monitor(trans
, dest
->size_power
);
932 IWL_WARN(trans
, "PCI should have external buffer debug\n");
934 for (i
= 0; i
< trans
->dbg_dest_reg_num
; i
++) {
935 u32 addr
= le32_to_cpu(dest
->reg_ops
[i
].addr
);
936 u32 val
= le32_to_cpu(dest
->reg_ops
[i
].val
);
938 switch (dest
->reg_ops
[i
].op
) {
940 iwl_write32(trans
, addr
, val
);
943 iwl_set_bit(trans
, addr
, BIT(val
));
946 iwl_clear_bit(trans
, addr
, BIT(val
));
949 iwl_write_prph(trans
, addr
, val
);
952 iwl_set_bits_prph(trans
, addr
, BIT(val
));
955 iwl_clear_bits_prph(trans
, addr
, BIT(val
));
958 if (iwl_read_prph(trans
, addr
) & BIT(val
)) {
960 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n",
966 IWL_ERR(trans
, "FW debug - unknown OP %d\n",
967 dest
->reg_ops
[i
].op
);
973 if (dest
->monitor_mode
== EXTERNAL_MODE
&& trans_pcie
->fw_mon_size
) {
974 iwl_write_prph(trans
, le32_to_cpu(dest
->base_reg
),
975 trans_pcie
->fw_mon_phys
>> dest
->base_shift
);
976 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
)
977 iwl_write_prph(trans
, le32_to_cpu(dest
->end_reg
),
978 (trans_pcie
->fw_mon_phys
+
979 trans_pcie
->fw_mon_size
- 256) >>
982 iwl_write_prph(trans
, le32_to_cpu(dest
->end_reg
),
983 (trans_pcie
->fw_mon_phys
+
984 trans_pcie
->fw_mon_size
) >>
989 static int iwl_pcie_load_given_ucode(struct iwl_trans
*trans
,
990 const struct fw_img
*image
)
992 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
994 int first_ucode_section
;
996 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
997 image
->is_dual_cpus
? "Dual" : "Single");
999 /* load to FW the binary non secured sections of CPU1 */
1000 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 1, &first_ucode_section
);
1004 if (image
->is_dual_cpus
) {
1005 /* set CPU2 header address */
1006 iwl_write_prph(trans
,
1007 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR
,
1008 LMPM_SECURE_CPU2_HDR_MEM_SPACE
);
1010 /* load to FW the binary sections of CPU2 */
1011 ret
= iwl_pcie_load_cpu_sections(trans
, image
, 2,
1012 &first_ucode_section
);
1017 /* supported for 7000 only for the moment */
1018 if (iwlwifi_mod_params
.fw_monitor
&&
1019 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) {
1020 iwl_pcie_alloc_fw_monitor(trans
, 0);
1022 if (trans_pcie
->fw_mon_size
) {
1023 iwl_write_prph(trans
, MON_BUFF_BASE_ADDR
,
1024 trans_pcie
->fw_mon_phys
>> 4);
1025 iwl_write_prph(trans
, MON_BUFF_END_ADDR
,
1026 (trans_pcie
->fw_mon_phys
+
1027 trans_pcie
->fw_mon_size
) >> 4);
1029 } else if (trans
->dbg_dest_tlv
) {
1030 iwl_pcie_apply_destination(trans
);
1033 iwl_enable_interrupts(trans
);
1035 /* release CPU reset */
1036 iwl_write32(trans
, CSR_RESET
, 0);
1041 static int iwl_pcie_load_given_ucode_8000(struct iwl_trans
*trans
,
1042 const struct fw_img
*image
)
1045 int first_ucode_section
;
1047 IWL_DEBUG_FW(trans
, "working with %s CPU\n",
1048 image
->is_dual_cpus
? "Dual" : "Single");
1050 if (trans
->dbg_dest_tlv
)
1051 iwl_pcie_apply_destination(trans
);
1053 IWL_DEBUG_POWER(trans
, "Original WFPM value = 0x%08X\n",
1054 iwl_read_prph(trans
, WFPM_GP2
));
1057 * Set default value. On resume reading the values that were
1058 * zeored can provide debug data on the resume flow.
1059 * This is for debugging only and has no functional impact.
1061 iwl_write_prph(trans
, WFPM_GP2
, 0x01010101);
1063 /* configure the ucode to be ready to get the secured image */
1064 /* release CPU reset */
1065 iwl_write_prph(trans
, RELEASE_CPU_RESET
, RELEASE_CPU_RESET_BIT
);
1067 /* load to FW the binary Secured sections of CPU1 */
1068 ret
= iwl_pcie_load_cpu_sections_8000(trans
, image
, 1,
1069 &first_ucode_section
);
1073 /* load to FW the binary sections of CPU2 */
1074 return iwl_pcie_load_cpu_sections_8000(trans
, image
, 2,
1075 &first_ucode_section
);
1078 bool iwl_pcie_check_hw_rf_kill(struct iwl_trans
*trans
)
1080 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1081 bool hw_rfkill
= iwl_is_rfkill_set(trans
);
1082 bool prev
= test_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1086 set_bit(STATUS_RFKILL_HW
, &trans
->status
);
1087 set_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1089 clear_bit(STATUS_RFKILL_HW
, &trans
->status
);
1090 if (trans_pcie
->opmode_down
)
1091 clear_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1094 report
= test_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1097 iwl_trans_pcie_rf_kill(trans
, report
);
1102 struct iwl_causes_list
{
1108 static struct iwl_causes_list causes_list
[] = {
1109 {MSIX_FH_INT_CAUSES_D2S_CH0_NUM
, CSR_MSIX_FH_INT_MASK_AD
, 0},
1110 {MSIX_FH_INT_CAUSES_D2S_CH1_NUM
, CSR_MSIX_FH_INT_MASK_AD
, 0x1},
1111 {MSIX_FH_INT_CAUSES_S2D
, CSR_MSIX_FH_INT_MASK_AD
, 0x3},
1112 {MSIX_FH_INT_CAUSES_FH_ERR
, CSR_MSIX_FH_INT_MASK_AD
, 0x5},
1113 {MSIX_HW_INT_CAUSES_REG_ALIVE
, CSR_MSIX_HW_INT_MASK_AD
, 0x10},
1114 {MSIX_HW_INT_CAUSES_REG_WAKEUP
, CSR_MSIX_HW_INT_MASK_AD
, 0x11},
1115 {MSIX_HW_INT_CAUSES_REG_CT_KILL
, CSR_MSIX_HW_INT_MASK_AD
, 0x16},
1116 {MSIX_HW_INT_CAUSES_REG_RF_KILL
, CSR_MSIX_HW_INT_MASK_AD
, 0x17},
1117 {MSIX_HW_INT_CAUSES_REG_PERIODIC
, CSR_MSIX_HW_INT_MASK_AD
, 0x18},
1118 {MSIX_HW_INT_CAUSES_REG_SW_ERR
, CSR_MSIX_HW_INT_MASK_AD
, 0x29},
1119 {MSIX_HW_INT_CAUSES_REG_SCD
, CSR_MSIX_HW_INT_MASK_AD
, 0x2A},
1120 {MSIX_HW_INT_CAUSES_REG_FH_TX
, CSR_MSIX_HW_INT_MASK_AD
, 0x2B},
1121 {MSIX_HW_INT_CAUSES_REG_HW_ERR
, CSR_MSIX_HW_INT_MASK_AD
, 0x2D},
1122 {MSIX_HW_INT_CAUSES_REG_HAP
, CSR_MSIX_HW_INT_MASK_AD
, 0x2E},
1125 static void iwl_pcie_map_non_rx_causes(struct iwl_trans
*trans
)
1127 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1128 int val
= trans_pcie
->def_irq
| MSIX_NON_AUTO_CLEAR_CAUSE
;
1132 * Access all non RX causes and map them to the default irq.
1133 * In case we are missing at least one interrupt vector,
1134 * the first interrupt vector will serve non-RX and FBQ causes.
1136 for (i
= 0; i
< ARRAY_SIZE(causes_list
); i
++) {
1137 iwl_write8(trans
, CSR_MSIX_IVAR(causes_list
[i
].addr
), val
);
1138 iwl_clear_bit(trans
, causes_list
[i
].mask_reg
,
1139 causes_list
[i
].cause_num
);
1143 static void iwl_pcie_map_rx_causes(struct iwl_trans
*trans
)
1145 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1147 trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_FIRST_RSS
? 1 : 0;
1151 * The first RX queue - fallback queue, which is designated for
1152 * management frame, command responses etc, is always mapped to the
1153 * first interrupt vector. The other RX queues are mapped to
1154 * the other (N - 2) interrupt vectors.
1156 val
= BIT(MSIX_FH_INT_CAUSES_Q(0));
1157 for (idx
= 1; idx
< trans
->num_rx_queues
; idx
++) {
1158 iwl_write8(trans
, CSR_MSIX_RX_IVAR(idx
),
1159 MSIX_FH_INT_CAUSES_Q(idx
- offset
));
1160 val
|= BIT(MSIX_FH_INT_CAUSES_Q(idx
));
1162 iwl_write32(trans
, CSR_MSIX_FH_INT_MASK_AD
, ~val
);
1164 val
= MSIX_FH_INT_CAUSES_Q(0);
1165 if (trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_NON_RX
)
1166 val
|= MSIX_NON_AUTO_CLEAR_CAUSE
;
1167 iwl_write8(trans
, CSR_MSIX_RX_IVAR(0), val
);
1169 if (trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_FIRST_RSS
)
1170 iwl_write8(trans
, CSR_MSIX_RX_IVAR(1), val
);
1173 void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie
*trans_pcie
)
1175 struct iwl_trans
*trans
= trans_pcie
->trans
;
1177 if (!trans_pcie
->msix_enabled
) {
1178 if (trans
->cfg
->mq_rx_supported
&&
1179 test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
1180 iwl_write_prph(trans
, UREG_CHICK
,
1181 UREG_CHICK_MSI_ENABLE
);
1185 * The IVAR table needs to be configured again after reset,
1186 * but if the device is disabled, we can't write to
1189 if (test_bit(STATUS_DEVICE_ENABLED
, &trans
->status
))
1190 iwl_write_prph(trans
, UREG_CHICK
, UREG_CHICK_MSIX_ENABLE
);
1193 * Each cause from the causes list above and the RX causes is
1194 * represented as a byte in the IVAR table. The first nibble
1195 * represents the bound interrupt vector of the cause, the second
1196 * represents no auto clear for this cause. This will be set if its
1197 * interrupt vector is bound to serve other causes.
1199 iwl_pcie_map_rx_causes(trans
);
1201 iwl_pcie_map_non_rx_causes(trans
);
1204 static void iwl_pcie_init_msix(struct iwl_trans_pcie
*trans_pcie
)
1206 struct iwl_trans
*trans
= trans_pcie
->trans
;
1208 iwl_pcie_conf_msix_hw(trans_pcie
);
1210 if (!trans_pcie
->msix_enabled
)
1213 trans_pcie
->fh_init_mask
= ~iwl_read32(trans
, CSR_MSIX_FH_INT_MASK_AD
);
1214 trans_pcie
->fh_mask
= trans_pcie
->fh_init_mask
;
1215 trans_pcie
->hw_init_mask
= ~iwl_read32(trans
, CSR_MSIX_HW_INT_MASK_AD
);
1216 trans_pcie
->hw_mask
= trans_pcie
->hw_init_mask
;
1219 static void _iwl_trans_pcie_stop_device(struct iwl_trans
*trans
, bool low_power
)
1221 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1223 lockdep_assert_held(&trans_pcie
->mutex
);
1225 if (trans_pcie
->is_down
)
1228 trans_pcie
->is_down
= true;
1230 /* Stop dbgc before stopping device */
1231 if (trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) {
1232 iwl_set_bits_prph(trans
, MON_BUFF_SAMPLE_CTL
, 0x100);
1234 iwl_write_prph(trans
, DBGC_IN_SAMPLE
, 0);
1236 iwl_write_prph(trans
, DBGC_OUT_CTRL
, 0);
1239 /* tell the device to stop sending interrupts */
1240 iwl_disable_interrupts(trans
);
1242 /* device going down, Stop using ICT table */
1243 iwl_pcie_disable_ict(trans
);
1246 * If a HW restart happens during firmware loading,
1247 * then the firmware loading might call this function
1248 * and later it might be called again due to the
1249 * restart. So don't process again if the device is
1252 if (test_and_clear_bit(STATUS_DEVICE_ENABLED
, &trans
->status
)) {
1253 IWL_DEBUG_INFO(trans
,
1254 "DEVICE_ENABLED bit was set and is now cleared\n");
1255 iwl_pcie_tx_stop(trans
);
1256 iwl_pcie_rx_stop(trans
);
1258 /* Power-down device's busmaster DMA clocks */
1259 if (!trans
->cfg
->apmg_not_supported
) {
1260 iwl_write_prph(trans
, APMG_CLK_DIS_REG
,
1261 APMG_CLK_VAL_DMA_CLK_RQT
);
1266 /* Make sure (redundant) we've released our request to stay awake */
1267 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1268 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1270 /* Stop the device, and put it in low power state */
1271 iwl_pcie_apm_stop(trans
, false);
1273 iwl_pcie_sw_reset(trans
);
1276 * Upon stop, the IVAR table gets erased, so msi-x won't
1277 * work. This causes a bug in RF-KILL flows, since the interrupt
1278 * that enables radio won't fire on the correct irq, and the
1279 * driver won't be able to handle the interrupt.
1280 * Configure the IVAR table again after reset.
1282 iwl_pcie_conf_msix_hw(trans_pcie
);
1285 * Upon stop, the APM issues an interrupt if HW RF kill is set.
1286 * This is a bug in certain verions of the hardware.
1287 * Certain devices also keep sending HW RF kill interrupt all
1288 * the time, unless the interrupt is ACKed even if the interrupt
1289 * should be masked. Re-ACK all the interrupts here.
1291 iwl_disable_interrupts(trans
);
1293 /* clear all status bits */
1294 clear_bit(STATUS_SYNC_HCMD_ACTIVE
, &trans
->status
);
1295 clear_bit(STATUS_INT_ENABLED
, &trans
->status
);
1296 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1299 * Even if we stop the HW, we still want the RF kill
1302 iwl_enable_rfkill_int(trans
);
1304 /* re-take ownership to prevent other users from stealing the device */
1305 iwl_pcie_prepare_card_hw(trans
);
1308 void iwl_pcie_synchronize_irqs(struct iwl_trans
*trans
)
1310 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1312 if (trans_pcie
->msix_enabled
) {
1315 for (i
= 0; i
< trans_pcie
->alloc_vecs
; i
++)
1316 synchronize_irq(trans_pcie
->msix_entries
[i
].vector
);
1318 synchronize_irq(trans_pcie
->pci_dev
->irq
);
1322 static int iwl_trans_pcie_start_fw(struct iwl_trans
*trans
,
1323 const struct fw_img
*fw
, bool run_in_rfkill
)
1325 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1329 /* This may fail if AMT took ownership of the device */
1330 if (iwl_pcie_prepare_card_hw(trans
)) {
1331 IWL_WARN(trans
, "Exit HW not ready\n");
1336 iwl_enable_rfkill_int(trans
);
1338 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1341 * We enabled the RF-Kill interrupt and the handler may very
1342 * well be running. Disable the interrupts to make sure no other
1343 * interrupt can be fired.
1345 iwl_disable_interrupts(trans
);
1347 /* Make sure it finished running */
1348 iwl_pcie_synchronize_irqs(trans
);
1350 mutex_lock(&trans_pcie
->mutex
);
1352 /* If platform's RF_KILL switch is NOT set to KILL */
1353 hw_rfkill
= iwl_pcie_check_hw_rf_kill(trans
);
1354 if (hw_rfkill
&& !run_in_rfkill
) {
1359 /* Someone called stop_device, don't try to start_fw */
1360 if (trans_pcie
->is_down
) {
1362 "Can't start_fw since the HW hasn't been started\n");
1367 /* make sure rfkill handshake bits are cleared */
1368 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1369 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
,
1370 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED
);
1372 /* clear (again), then enable host interrupts */
1373 iwl_write32(trans
, CSR_INT
, 0xFFFFFFFF);
1375 ret
= iwl_pcie_nic_init(trans
);
1377 IWL_ERR(trans
, "Unable to init nic\n");
1382 * Now, we load the firmware and don't want to be interrupted, even
1383 * by the RF-Kill interrupt (hence mask all the interrupt besides the
1384 * FH_TX interrupt which is needed to load the firmware). If the
1385 * RF-Kill switch is toggled, we will find out after having loaded
1386 * the firmware and return the proper value to the caller.
1388 iwl_enable_fw_load_int(trans
);
1390 /* really make sure rfkill handshake bits are cleared */
1391 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1392 iwl_write32(trans
, CSR_UCODE_DRV_GP1_CLR
, CSR_UCODE_SW_BIT_RFKILL
);
1394 /* Load the given image to the HW */
1395 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
)
1396 ret
= iwl_pcie_load_given_ucode_8000(trans
, fw
);
1398 ret
= iwl_pcie_load_given_ucode(trans
, fw
);
1400 /* re-check RF-Kill state since we may have missed the interrupt */
1401 hw_rfkill
= iwl_pcie_check_hw_rf_kill(trans
);
1402 if (hw_rfkill
&& !run_in_rfkill
)
1406 mutex_unlock(&trans_pcie
->mutex
);
1410 static void iwl_trans_pcie_fw_alive(struct iwl_trans
*trans
, u32 scd_addr
)
1412 iwl_pcie_reset_ict(trans
);
1413 iwl_pcie_tx_start(trans
, scd_addr
);
1416 void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans
*trans
,
1422 * Check again since the RF kill state may have changed while
1423 * all the interrupts were disabled, in this case we couldn't
1424 * receive the RF kill interrupt and update the state in the
1426 * Don't call the op_mode if the rkfill state hasn't changed.
1427 * This allows the op_mode to call stop_device from the rfkill
1428 * notification without endless recursion. Under very rare
1429 * circumstances, we might have a small recursion if the rfkill
1430 * state changed exactly now while we were called from stop_device.
1431 * This is very unlikely but can happen and is supported.
1433 hw_rfkill
= iwl_is_rfkill_set(trans
);
1435 set_bit(STATUS_RFKILL_HW
, &trans
->status
);
1436 set_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1438 clear_bit(STATUS_RFKILL_HW
, &trans
->status
);
1439 clear_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1441 if (hw_rfkill
!= was_in_rfkill
)
1442 iwl_trans_pcie_rf_kill(trans
, hw_rfkill
);
1445 static void iwl_trans_pcie_stop_device(struct iwl_trans
*trans
, bool low_power
)
1447 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1450 mutex_lock(&trans_pcie
->mutex
);
1451 trans_pcie
->opmode_down
= true;
1452 was_in_rfkill
= test_bit(STATUS_RFKILL_OPMODE
, &trans
->status
);
1453 _iwl_trans_pcie_stop_device(trans
, low_power
);
1454 iwl_trans_pcie_handle_stop_rfkill(trans
, was_in_rfkill
);
1455 mutex_unlock(&trans_pcie
->mutex
);
1458 void iwl_trans_pcie_rf_kill(struct iwl_trans
*trans
, bool state
)
1460 struct iwl_trans_pcie __maybe_unused
*trans_pcie
=
1461 IWL_TRANS_GET_PCIE_TRANS(trans
);
1463 lockdep_assert_held(&trans_pcie
->mutex
);
1465 IWL_WARN(trans
, "reporting RF_KILL (radio %s)\n",
1466 state
? "disabled" : "enabled");
1467 if (iwl_op_mode_hw_rf_kill(trans
->op_mode
, state
)) {
1468 if (trans
->cfg
->gen2
)
1469 _iwl_trans_pcie_gen2_stop_device(trans
, true);
1471 _iwl_trans_pcie_stop_device(trans
, true);
1475 static void iwl_trans_pcie_d3_suspend(struct iwl_trans
*trans
, bool test
,
1479 /* Enable persistence mode to avoid reset */
1480 iwl_set_bit(trans
, CSR_HW_IF_CONFIG_REG
,
1481 CSR_HW_IF_CONFIG_REG_PERSIST_MODE
);
1484 iwl_disable_interrupts(trans
);
1487 * in testing mode, the host stays awake and the
1488 * hardware won't be reset (not even partially)
1493 iwl_pcie_disable_ict(trans
);
1495 iwl_pcie_synchronize_irqs(trans
);
1497 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1498 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1499 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1500 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1502 iwl_pcie_enable_rx_wake(trans
, false);
1506 * reset TX queues -- some of their registers reset during S3
1507 * so if we don't reset everything here the D3 image would try
1508 * to execute some invalid memory upon resume
1510 iwl_trans_pcie_tx_reset(trans
);
1513 iwl_pcie_set_pwr(trans
, true);
1516 static int iwl_trans_pcie_d3_resume(struct iwl_trans
*trans
,
1517 enum iwl_d3_status
*status
,
1518 bool test
, bool reset
)
1520 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1525 iwl_enable_interrupts(trans
);
1526 *status
= IWL_D3_STATUS_ALIVE
;
1530 iwl_pcie_enable_rx_wake(trans
, true);
1533 * Reconfigure IVAR table in case of MSIX or reset ict table in
1534 * MSI mode since HW reset erased it.
1535 * Also enables interrupts - none will happen as
1536 * the device doesn't know we're waking it up, only when
1537 * the opmode actually tells it after this call.
1539 iwl_pcie_conf_msix_hw(trans_pcie
);
1540 if (!trans_pcie
->msix_enabled
)
1541 iwl_pcie_reset_ict(trans
);
1542 iwl_enable_interrupts(trans
);
1544 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1545 iwl_set_bit(trans
, CSR_GP_CNTRL
, CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
1547 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
)
1550 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1551 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1552 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
1555 IWL_ERR(trans
, "Failed to resume the device (mac ready)\n");
1559 iwl_pcie_set_pwr(trans
, false);
1562 iwl_clear_bit(trans
, CSR_GP_CNTRL
,
1563 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1565 iwl_trans_pcie_tx_reset(trans
);
1567 ret
= iwl_pcie_rx_init(trans
);
1570 "Failed to resume the device (RX reset)\n");
1575 IWL_DEBUG_POWER(trans
, "WFPM value upon resume = 0x%08X\n",
1576 iwl_read_prph(trans
, WFPM_GP2
));
1578 val
= iwl_read32(trans
, CSR_RESET
);
1579 if (val
& CSR_RESET_REG_FLAG_NEVO_RESET
)
1580 *status
= IWL_D3_STATUS_RESET
;
1582 *status
= IWL_D3_STATUS_ALIVE
;
1587 static void iwl_pcie_set_interrupt_capa(struct pci_dev
*pdev
,
1588 struct iwl_trans
*trans
)
1590 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1591 int max_irqs
, num_irqs
, i
, ret
, nr_online_cpus
;
1594 if (!trans
->cfg
->mq_rx_supported
)
1597 nr_online_cpus
= num_online_cpus();
1598 max_irqs
= min_t(u32
, nr_online_cpus
+ 2, IWL_MAX_RX_HW_QUEUES
);
1599 for (i
= 0; i
< max_irqs
; i
++)
1600 trans_pcie
->msix_entries
[i
].entry
= i
;
1602 num_irqs
= pci_enable_msix_range(pdev
, trans_pcie
->msix_entries
,
1603 MSIX_MIN_INTERRUPT_VECTORS
,
1606 IWL_DEBUG_INFO(trans
,
1607 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n",
1611 trans_pcie
->def_irq
= (num_irqs
== max_irqs
) ? num_irqs
- 1 : 0;
1613 IWL_DEBUG_INFO(trans
,
1614 "MSI-X enabled. %d interrupt vectors were allocated\n",
1618 * In case the OS provides fewer interrupts than requested, different
1619 * causes will share the same interrupt vector as follows:
1620 * One interrupt less: non rx causes shared with FBQ.
1621 * Two interrupts less: non rx causes shared with FBQ and RSS.
1622 * More than two interrupts: we will use fewer RSS queues.
1624 if (num_irqs
<= nr_online_cpus
) {
1625 trans_pcie
->trans
->num_rx_queues
= num_irqs
+ 1;
1626 trans_pcie
->shared_vec_mask
= IWL_SHARED_IRQ_NON_RX
|
1627 IWL_SHARED_IRQ_FIRST_RSS
;
1628 } else if (num_irqs
== nr_online_cpus
+ 1) {
1629 trans_pcie
->trans
->num_rx_queues
= num_irqs
;
1630 trans_pcie
->shared_vec_mask
= IWL_SHARED_IRQ_NON_RX
;
1632 trans_pcie
->trans
->num_rx_queues
= num_irqs
- 1;
1635 trans_pcie
->alloc_vecs
= num_irqs
;
1636 trans_pcie
->msix_enabled
= true;
1640 ret
= pci_enable_msi(pdev
);
1642 dev_err(&pdev
->dev
, "pci_enable_msi failed - %d\n", ret
);
1643 /* enable rfkill interrupt: hw bug w/a */
1644 pci_read_config_word(pdev
, PCI_COMMAND
, &pci_cmd
);
1645 if (pci_cmd
& PCI_COMMAND_INTX_DISABLE
) {
1646 pci_cmd
&= ~PCI_COMMAND_INTX_DISABLE
;
1647 pci_write_config_word(pdev
, PCI_COMMAND
, pci_cmd
);
1652 static void iwl_pcie_irq_set_affinity(struct iwl_trans
*trans
)
1654 int iter_rx_q
, i
, ret
, cpu
, offset
;
1655 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1657 i
= trans_pcie
->shared_vec_mask
& IWL_SHARED_IRQ_FIRST_RSS
? 0 : 1;
1658 iter_rx_q
= trans_pcie
->trans
->num_rx_queues
- 1 + i
;
1660 for (; i
< iter_rx_q
; i
++) {
1662 * Get the cpu prior to the place to search
1663 * (i.e. return will be > i - 1).
1665 cpu
= cpumask_next(i
- offset
, cpu_online_mask
);
1666 cpumask_set_cpu(cpu
, &trans_pcie
->affinity_mask
[i
]);
1667 ret
= irq_set_affinity_hint(trans_pcie
->msix_entries
[i
].vector
,
1668 &trans_pcie
->affinity_mask
[i
]);
1670 IWL_ERR(trans_pcie
->trans
,
1671 "Failed to set affinity mask for IRQ %d\n",
1676 static const char *queue_name(struct device
*dev
,
1677 struct iwl_trans_pcie
*trans_p
, int i
)
1679 if (trans_p
->shared_vec_mask
) {
1680 int vec
= trans_p
->shared_vec_mask
&
1681 IWL_SHARED_IRQ_FIRST_RSS
? 1 : 0;
1684 return DRV_NAME
": shared IRQ";
1686 return devm_kasprintf(dev
, GFP_KERNEL
,
1687 DRV_NAME
": queue %d", i
+ vec
);
1690 return DRV_NAME
": default queue";
1692 if (i
== trans_p
->alloc_vecs
- 1)
1693 return DRV_NAME
": exception";
1695 return devm_kasprintf(dev
, GFP_KERNEL
,
1696 DRV_NAME
": queue %d", i
);
1699 static int iwl_pcie_init_msix_handler(struct pci_dev
*pdev
,
1700 struct iwl_trans_pcie
*trans_pcie
)
1704 for (i
= 0; i
< trans_pcie
->alloc_vecs
; i
++) {
1706 struct msix_entry
*msix_entry
;
1707 const char *qname
= queue_name(&pdev
->dev
, trans_pcie
, i
);
1712 msix_entry
= &trans_pcie
->msix_entries
[i
];
1713 ret
= devm_request_threaded_irq(&pdev
->dev
,
1716 (i
== trans_pcie
->def_irq
) ?
1717 iwl_pcie_irq_msix_handler
:
1718 iwl_pcie_irq_rx_msix_handler
,
1723 IWL_ERR(trans_pcie
->trans
,
1724 "Error allocating IRQ %d\n", i
);
1729 iwl_pcie_irq_set_affinity(trans_pcie
->trans
);
1734 static int _iwl_trans_pcie_start_hw(struct iwl_trans
*trans
, bool low_power
)
1736 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1739 lockdep_assert_held(&trans_pcie
->mutex
);
1741 err
= iwl_pcie_prepare_card_hw(trans
);
1743 IWL_ERR(trans
, "Error while preparing HW: %d\n", err
);
1747 iwl_pcie_sw_reset(trans
);
1749 err
= iwl_pcie_apm_init(trans
);
1753 iwl_pcie_init_msix(trans_pcie
);
1755 /* From now on, the op_mode will be kept updated about RF kill state */
1756 iwl_enable_rfkill_int(trans
);
1758 trans_pcie
->opmode_down
= false;
1760 /* Set is_down to false here so that...*/
1761 trans_pcie
->is_down
= false;
1763 /* ...rfkill can call stop_device and set it false if needed */
1764 iwl_pcie_check_hw_rf_kill(trans
);
1766 /* Make sure we sync here, because we'll need full access later */
1768 pm_runtime_resume(trans
->dev
);
1773 static int iwl_trans_pcie_start_hw(struct iwl_trans
*trans
, bool low_power
)
1775 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1778 mutex_lock(&trans_pcie
->mutex
);
1779 ret
= _iwl_trans_pcie_start_hw(trans
, low_power
);
1780 mutex_unlock(&trans_pcie
->mutex
);
1785 static void iwl_trans_pcie_op_mode_leave(struct iwl_trans
*trans
)
1787 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1789 mutex_lock(&trans_pcie
->mutex
);
1791 /* disable interrupts - don't enable HW RF kill interrupt */
1792 iwl_disable_interrupts(trans
);
1794 iwl_pcie_apm_stop(trans
, true);
1796 iwl_disable_interrupts(trans
);
1798 iwl_pcie_disable_ict(trans
);
1800 mutex_unlock(&trans_pcie
->mutex
);
1802 iwl_pcie_synchronize_irqs(trans
);
1805 static void iwl_trans_pcie_write8(struct iwl_trans
*trans
, u32 ofs
, u8 val
)
1807 writeb(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1810 static void iwl_trans_pcie_write32(struct iwl_trans
*trans
, u32 ofs
, u32 val
)
1812 writel(val
, IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1815 static u32
iwl_trans_pcie_read32(struct iwl_trans
*trans
, u32 ofs
)
1817 return readl(IWL_TRANS_GET_PCIE_TRANS(trans
)->hw_base
+ ofs
);
1820 static u32
iwl_trans_pcie_read_prph(struct iwl_trans
*trans
, u32 reg
)
1822 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_RADDR
,
1823 ((reg
& 0x000FFFFF) | (3 << 24)));
1824 return iwl_trans_pcie_read32(trans
, HBUS_TARG_PRPH_RDAT
);
1827 static void iwl_trans_pcie_write_prph(struct iwl_trans
*trans
, u32 addr
,
1830 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WADDR
,
1831 ((addr
& 0x000FFFFF) | (3 << 24)));
1832 iwl_trans_pcie_write32(trans
, HBUS_TARG_PRPH_WDAT
, val
);
1835 static void iwl_trans_pcie_configure(struct iwl_trans
*trans
,
1836 const struct iwl_trans_config
*trans_cfg
)
1838 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1840 trans_pcie
->cmd_queue
= trans_cfg
->cmd_queue
;
1841 trans_pcie
->cmd_fifo
= trans_cfg
->cmd_fifo
;
1842 trans_pcie
->cmd_q_wdg_timeout
= trans_cfg
->cmd_q_wdg_timeout
;
1843 if (WARN_ON(trans_cfg
->n_no_reclaim_cmds
> MAX_NO_RECLAIM_CMDS
))
1844 trans_pcie
->n_no_reclaim_cmds
= 0;
1846 trans_pcie
->n_no_reclaim_cmds
= trans_cfg
->n_no_reclaim_cmds
;
1847 if (trans_pcie
->n_no_reclaim_cmds
)
1848 memcpy(trans_pcie
->no_reclaim_cmds
, trans_cfg
->no_reclaim_cmds
,
1849 trans_pcie
->n_no_reclaim_cmds
* sizeof(u8
));
1851 trans_pcie
->rx_buf_size
= trans_cfg
->rx_buf_size
;
1852 trans_pcie
->rx_page_order
=
1853 iwl_trans_get_rb_size_order(trans_pcie
->rx_buf_size
);
1855 trans_pcie
->bc_table_dword
= trans_cfg
->bc_table_dword
;
1856 trans_pcie
->scd_set_active
= trans_cfg
->scd_set_active
;
1857 trans_pcie
->sw_csum_tx
= trans_cfg
->sw_csum_tx
;
1859 trans_pcie
->page_offs
= trans_cfg
->cb_data_offs
;
1860 trans_pcie
->dev_cmd_offs
= trans_cfg
->cb_data_offs
+ sizeof(void *);
1862 trans
->command_groups
= trans_cfg
->command_groups
;
1863 trans
->command_groups_size
= trans_cfg
->command_groups_size
;
1865 /* Initialize NAPI here - it should be before registering to mac80211
1866 * in the opmode but after the HW struct is allocated.
1867 * As this function may be called again in some corner cases don't
1868 * do anything if NAPI was already initialized.
1870 if (trans_pcie
->napi_dev
.reg_state
!= NETREG_DUMMY
)
1871 init_dummy_netdev(&trans_pcie
->napi_dev
);
1874 void iwl_trans_pcie_free(struct iwl_trans
*trans
)
1876 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1879 iwl_pcie_synchronize_irqs(trans
);
1881 if (trans
->cfg
->gen2
)
1882 iwl_pcie_gen2_tx_free(trans
);
1884 iwl_pcie_tx_free(trans
);
1885 iwl_pcie_rx_free(trans
);
1887 if (trans_pcie
->rba
.alloc_wq
) {
1888 destroy_workqueue(trans_pcie
->rba
.alloc_wq
);
1889 trans_pcie
->rba
.alloc_wq
= NULL
;
1892 if (trans_pcie
->msix_enabled
) {
1893 for (i
= 0; i
< trans_pcie
->alloc_vecs
; i
++) {
1894 irq_set_affinity_hint(
1895 trans_pcie
->msix_entries
[i
].vector
,
1899 trans_pcie
->msix_enabled
= false;
1901 iwl_pcie_free_ict(trans
);
1904 iwl_pcie_free_fw_monitor(trans
);
1906 for_each_possible_cpu(i
) {
1907 struct iwl_tso_hdr_page
*p
=
1908 per_cpu_ptr(trans_pcie
->tso_hdr_page
, i
);
1911 __free_page(p
->page
);
1914 free_percpu(trans_pcie
->tso_hdr_page
);
1915 mutex_destroy(&trans_pcie
->mutex
);
1916 iwl_trans_free(trans
);
1919 static void iwl_trans_pcie_set_pmi(struct iwl_trans
*trans
, bool state
)
1922 set_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1924 clear_bit(STATUS_TPOWER_PMI
, &trans
->status
);
1927 static bool iwl_trans_pcie_grab_nic_access(struct iwl_trans
*trans
,
1928 unsigned long *flags
)
1931 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1933 spin_lock_irqsave(&trans_pcie
->reg_lock
, *flags
);
1935 if (trans_pcie
->cmd_hold_nic_awake
)
1938 /* this bit wakes up the NIC */
1939 __iwl_trans_pcie_set_bit(trans
, CSR_GP_CNTRL
,
1940 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
1941 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
)
1945 * These bits say the device is running, and should keep running for
1946 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
1947 * but they do not indicate that embedded SRAM is restored yet;
1948 * HW with volatile SRAM must save/restore contents to/from
1949 * host DRAM when sleeping/waking for power-saving.
1950 * Each direction takes approximately 1/4 millisecond; with this
1951 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
1952 * series of register accesses are expected (e.g. reading Event Log),
1953 * to keep device from sleeping.
1955 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
1956 * SRAM is okay/restored. We don't check that here because this call
1957 * is just for hardware register access; but GP1 MAC_SLEEP
1958 * check is a good idea before accessing the SRAM of HW with
1959 * volatile SRAM (e.g. reading Event Log).
1961 * 5000 series and later (including 1000 series) have non-volatile SRAM,
1962 * and do not save/restore SRAM when power cycling.
1964 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
1965 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN
,
1966 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
|
1967 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP
), 15000);
1968 if (unlikely(ret
< 0)) {
1969 iwl_trans_pcie_dump_regs(trans
);
1970 iwl_write32(trans
, CSR_RESET
, CSR_RESET_REG_FLAG_FORCE_NMI
);
1972 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n",
1973 iwl_read32(trans
, CSR_GP_CNTRL
));
1974 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
1980 * Fool sparse by faking we release the lock - sparse will
1981 * track nic_access anyway.
1983 __release(&trans_pcie
->reg_lock
);
1987 static void iwl_trans_pcie_release_nic_access(struct iwl_trans
*trans
,
1988 unsigned long *flags
)
1990 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
1992 lockdep_assert_held(&trans_pcie
->reg_lock
);
1995 * Fool sparse by faking we acquiring the lock - sparse will
1996 * track nic_access anyway.
1998 __acquire(&trans_pcie
->reg_lock
);
2000 if (trans_pcie
->cmd_hold_nic_awake
)
2003 __iwl_trans_pcie_clear_bit(trans
, CSR_GP_CNTRL
,
2004 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
);
2006 * Above we read the CSR_GP_CNTRL register, which will flush
2007 * any previous writes, but we need the write that clears the
2008 * MAC_ACCESS_REQ bit to be performed before any other writes
2009 * scheduled on different CPUs (after we drop reg_lock).
2013 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, *flags
);
2016 static int iwl_trans_pcie_read_mem(struct iwl_trans
*trans
, u32 addr
,
2017 void *buf
, int dwords
)
2019 unsigned long flags
;
2023 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
2024 iwl_write32(trans
, HBUS_TARG_MEM_RADDR
, addr
);
2025 for (offs
= 0; offs
< dwords
; offs
++)
2026 vals
[offs
] = iwl_read32(trans
, HBUS_TARG_MEM_RDAT
);
2027 iwl_trans_release_nic_access(trans
, &flags
);
2034 static int iwl_trans_pcie_write_mem(struct iwl_trans
*trans
, u32 addr
,
2035 const void *buf
, int dwords
)
2037 unsigned long flags
;
2039 const u32
*vals
= buf
;
2041 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
2042 iwl_write32(trans
, HBUS_TARG_MEM_WADDR
, addr
);
2043 for (offs
= 0; offs
< dwords
; offs
++)
2044 iwl_write32(trans
, HBUS_TARG_MEM_WDAT
,
2045 vals
? vals
[offs
] : 0);
2046 iwl_trans_release_nic_access(trans
, &flags
);
2053 static void iwl_trans_pcie_freeze_txq_timer(struct iwl_trans
*trans
,
2057 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2060 for_each_set_bit(queue
, &txqs
, BITS_PER_LONG
) {
2061 struct iwl_txq
*txq
= trans_pcie
->txq
[queue
];
2064 spin_lock_bh(&txq
->lock
);
2068 if (txq
->frozen
== freeze
)
2071 IWL_DEBUG_TX_QUEUES(trans
, "%s TXQ %d\n",
2072 freeze
? "Freezing" : "Waking", queue
);
2074 txq
->frozen
= freeze
;
2076 if (txq
->read_ptr
== txq
->write_ptr
)
2080 if (unlikely(time_after(now
,
2081 txq
->stuck_timer
.expires
))) {
2083 * The timer should have fired, maybe it is
2084 * spinning right now on the lock.
2088 /* remember how long until the timer fires */
2089 txq
->frozen_expiry_remainder
=
2090 txq
->stuck_timer
.expires
- now
;
2091 del_timer(&txq
->stuck_timer
);
2096 * Wake a non-empty queue -> arm timer with the
2097 * remainder before it froze
2099 mod_timer(&txq
->stuck_timer
,
2100 now
+ txq
->frozen_expiry_remainder
);
2103 spin_unlock_bh(&txq
->lock
);
2107 static void iwl_trans_pcie_block_txq_ptrs(struct iwl_trans
*trans
, bool block
)
2109 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2112 for (i
= 0; i
< trans
->cfg
->base_params
->num_of_queues
; i
++) {
2113 struct iwl_txq
*txq
= trans_pcie
->txq
[i
];
2115 if (i
== trans_pcie
->cmd_queue
)
2118 spin_lock_bh(&txq
->lock
);
2120 if (!block
&& !(WARN_ON_ONCE(!txq
->block
))) {
2123 iwl_write32(trans
, HBUS_TARG_WRPTR
,
2124 txq
->write_ptr
| (i
<< 8));
2130 spin_unlock_bh(&txq
->lock
);
2134 #define IWL_FLUSH_WAIT_MS 2000
2136 void iwl_trans_pcie_log_scd_error(struct iwl_trans
*trans
, struct iwl_txq
*txq
)
2138 u32 txq_id
= txq
->id
;
2143 if (trans
->cfg
->use_tfh
) {
2144 IWL_ERR(trans
, "Queue %d is stuck %d %d\n", txq_id
,
2145 txq
->read_ptr
, txq
->write_ptr
);
2146 /* TODO: access new SCD registers and dump them */
2150 status
= iwl_read_prph(trans
, SCD_QUEUE_STATUS_BITS(txq_id
));
2151 fifo
= (status
>> SCD_QUEUE_STTS_REG_POS_TXF
) & 0x7;
2152 active
= !!(status
& BIT(SCD_QUEUE_STTS_REG_POS_ACTIVE
));
2155 "Queue %d is %sactive on fifo %d and stuck for %u ms. SW [%d, %d] HW [%d, %d] FH TRB=0x0%x\n",
2156 txq_id
, active
? "" : "in", fifo
,
2157 jiffies_to_msecs(txq
->wd_timeout
),
2158 txq
->read_ptr
, txq
->write_ptr
,
2159 iwl_read_prph(trans
, SCD_QUEUE_RDPTR(txq_id
)) &
2160 (TFD_QUEUE_SIZE_MAX
- 1),
2161 iwl_read_prph(trans
, SCD_QUEUE_WRPTR(txq_id
)) &
2162 (TFD_QUEUE_SIZE_MAX
- 1),
2163 iwl_read_direct32(trans
, FH_TX_TRB_REG(fifo
)));
2166 static int iwl_trans_pcie_wait_txq_empty(struct iwl_trans
*trans
, int txq_idx
)
2168 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2169 struct iwl_txq
*txq
;
2170 unsigned long now
= jiffies
;
2173 if (!test_bit(txq_idx
, trans_pcie
->queue_used
))
2176 IWL_DEBUG_TX_QUEUES(trans
, "Emptying queue %d...\n", txq_idx
);
2177 txq
= trans_pcie
->txq
[txq_idx
];
2178 wr_ptr
= READ_ONCE(txq
->write_ptr
);
2180 while (txq
->read_ptr
!= READ_ONCE(txq
->write_ptr
) &&
2181 !time_after(jiffies
,
2182 now
+ msecs_to_jiffies(IWL_FLUSH_WAIT_MS
))) {
2183 u8 write_ptr
= READ_ONCE(txq
->write_ptr
);
2185 if (WARN_ONCE(wr_ptr
!= write_ptr
,
2186 "WR pointer moved while flushing %d -> %d\n",
2189 usleep_range(1000, 2000);
2192 if (txq
->read_ptr
!= txq
->write_ptr
) {
2194 "fail to flush all tx fifo queues Q %d\n", txq_idx
);
2195 iwl_trans_pcie_log_scd_error(trans
, txq
);
2199 IWL_DEBUG_TX_QUEUES(trans
, "Queue %d is now empty.\n", txq_idx
);
2204 static int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans
*trans
, u32 txq_bm
)
2206 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2210 /* waiting for all the tx frames complete might take a while */
2211 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
2213 if (cnt
== trans_pcie
->cmd_queue
)
2215 if (!test_bit(cnt
, trans_pcie
->queue_used
))
2217 if (!(BIT(cnt
) & txq_bm
))
2220 ret
= iwl_trans_pcie_wait_txq_empty(trans
, cnt
);
2228 static void iwl_trans_pcie_set_bits_mask(struct iwl_trans
*trans
, u32 reg
,
2229 u32 mask
, u32 value
)
2231 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2232 unsigned long flags
;
2234 spin_lock_irqsave(&trans_pcie
->reg_lock
, flags
);
2235 __iwl_trans_pcie_set_bits_mask(trans
, reg
, mask
, value
);
2236 spin_unlock_irqrestore(&trans_pcie
->reg_lock
, flags
);
2239 static void iwl_trans_pcie_ref(struct iwl_trans
*trans
)
2241 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2243 if (iwlwifi_mod_params
.d0i3_disable
)
2246 pm_runtime_get(&trans_pcie
->pci_dev
->dev
);
2249 IWL_DEBUG_RPM(trans
, "runtime usage count: %d\n",
2250 atomic_read(&trans_pcie
->pci_dev
->dev
.power
.usage_count
));
2251 #endif /* CONFIG_PM */
2254 static void iwl_trans_pcie_unref(struct iwl_trans
*trans
)
2256 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2258 if (iwlwifi_mod_params
.d0i3_disable
)
2261 pm_runtime_mark_last_busy(&trans_pcie
->pci_dev
->dev
);
2262 pm_runtime_put_autosuspend(&trans_pcie
->pci_dev
->dev
);
2265 IWL_DEBUG_RPM(trans
, "runtime usage count: %d\n",
2266 atomic_read(&trans_pcie
->pci_dev
->dev
.power
.usage_count
));
2267 #endif /* CONFIG_PM */
2270 static const char *get_csr_string(int cmd
)
2272 #define IWL_CMD(x) case x: return #x
2274 IWL_CMD(CSR_HW_IF_CONFIG_REG
);
2275 IWL_CMD(CSR_INT_COALESCING
);
2277 IWL_CMD(CSR_INT_MASK
);
2278 IWL_CMD(CSR_FH_INT_STATUS
);
2279 IWL_CMD(CSR_GPIO_IN
);
2281 IWL_CMD(CSR_GP_CNTRL
);
2282 IWL_CMD(CSR_HW_REV
);
2283 IWL_CMD(CSR_EEPROM_REG
);
2284 IWL_CMD(CSR_EEPROM_GP
);
2285 IWL_CMD(CSR_OTP_GP_REG
);
2286 IWL_CMD(CSR_GIO_REG
);
2287 IWL_CMD(CSR_GP_UCODE_REG
);
2288 IWL_CMD(CSR_GP_DRIVER_REG
);
2289 IWL_CMD(CSR_UCODE_DRV_GP1
);
2290 IWL_CMD(CSR_UCODE_DRV_GP2
);
2291 IWL_CMD(CSR_LED_REG
);
2292 IWL_CMD(CSR_DRAM_INT_TBL_REG
);
2293 IWL_CMD(CSR_GIO_CHICKEN_BITS
);
2294 IWL_CMD(CSR_ANA_PLL_CFG
);
2295 IWL_CMD(CSR_HW_REV_WA_REG
);
2296 IWL_CMD(CSR_MONITOR_STATUS_REG
);
2297 IWL_CMD(CSR_DBG_HPET_MEM_REG
);
2304 void iwl_pcie_dump_csr(struct iwl_trans
*trans
)
2307 static const u32 csr_tbl
[] = {
2308 CSR_HW_IF_CONFIG_REG
,
2326 CSR_DRAM_INT_TBL_REG
,
2327 CSR_GIO_CHICKEN_BITS
,
2329 CSR_MONITOR_STATUS_REG
,
2331 CSR_DBG_HPET_MEM_REG
2333 IWL_ERR(trans
, "CSR values:\n");
2334 IWL_ERR(trans
, "(2nd byte of CSR_INT_COALESCING is "
2335 "CSR_INT_PERIODIC_REG)\n");
2336 for (i
= 0; i
< ARRAY_SIZE(csr_tbl
); i
++) {
2337 IWL_ERR(trans
, " %25s: 0X%08x\n",
2338 get_csr_string(csr_tbl
[i
]),
2339 iwl_read32(trans
, csr_tbl
[i
]));
2343 #ifdef CONFIG_IWLWIFI_DEBUGFS
2344 /* create and remove of files */
2345 #define DEBUGFS_ADD_FILE(name, parent, mode) do { \
2346 if (!debugfs_create_file(#name, mode, parent, trans, \
2347 &iwl_dbgfs_##name##_ops)) \
2351 /* file operation */
2352 #define DEBUGFS_READ_FILE_OPS(name) \
2353 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2354 .read = iwl_dbgfs_##name##_read, \
2355 .open = simple_open, \
2356 .llseek = generic_file_llseek, \
2359 #define DEBUGFS_WRITE_FILE_OPS(name) \
2360 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2361 .write = iwl_dbgfs_##name##_write, \
2362 .open = simple_open, \
2363 .llseek = generic_file_llseek, \
2366 #define DEBUGFS_READ_WRITE_FILE_OPS(name) \
2367 static const struct file_operations iwl_dbgfs_##name##_ops = { \
2368 .write = iwl_dbgfs_##name##_write, \
2369 .read = iwl_dbgfs_##name##_read, \
2370 .open = simple_open, \
2371 .llseek = generic_file_llseek, \
2374 static ssize_t
iwl_dbgfs_tx_queue_read(struct file
*file
,
2375 char __user
*user_buf
,
2376 size_t count
, loff_t
*ppos
)
2378 struct iwl_trans
*trans
= file
->private_data
;
2379 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2380 struct iwl_txq
*txq
;
2387 bufsz
= sizeof(char) * 75 * trans
->cfg
->base_params
->num_of_queues
;
2389 if (!trans_pcie
->txq_memory
)
2392 buf
= kzalloc(bufsz
, GFP_KERNEL
);
2396 for (cnt
= 0; cnt
< trans
->cfg
->base_params
->num_of_queues
; cnt
++) {
2397 txq
= trans_pcie
->txq
[cnt
];
2398 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2399 "hwq %.2d: read=%u write=%u use=%d stop=%d need_update=%d frozen=%d%s\n",
2400 cnt
, txq
->read_ptr
, txq
->write_ptr
,
2401 !!test_bit(cnt
, trans_pcie
->queue_used
),
2402 !!test_bit(cnt
, trans_pcie
->queue_stopped
),
2403 txq
->need_update
, txq
->frozen
,
2404 (cnt
== trans_pcie
->cmd_queue
? " HCMD" : ""));
2406 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2411 static ssize_t
iwl_dbgfs_rx_queue_read(struct file
*file
,
2412 char __user
*user_buf
,
2413 size_t count
, loff_t
*ppos
)
2415 struct iwl_trans
*trans
= file
->private_data
;
2416 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2418 int pos
= 0, i
, ret
;
2419 size_t bufsz
= sizeof(buf
);
2421 bufsz
= sizeof(char) * 121 * trans
->num_rx_queues
;
2423 if (!trans_pcie
->rxq
)
2426 buf
= kzalloc(bufsz
, GFP_KERNEL
);
2430 for (i
= 0; i
< trans
->num_rx_queues
&& pos
< bufsz
; i
++) {
2431 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[i
];
2433 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "queue#: %2d\n",
2435 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\tread: %u\n",
2437 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\twrite: %u\n",
2439 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\twrite_actual: %u\n",
2441 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\tneed_update: %2d\n",
2443 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "\tfree_count: %u\n",
2446 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2447 "\tclosed_rb_num: %u\n",
2448 le16_to_cpu(rxq
->rb_stts
->closed_rb_num
) &
2451 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2452 "\tclosed_rb_num: Not Allocated\n");
2455 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2461 static ssize_t
iwl_dbgfs_interrupt_read(struct file
*file
,
2462 char __user
*user_buf
,
2463 size_t count
, loff_t
*ppos
)
2465 struct iwl_trans
*trans
= file
->private_data
;
2466 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2467 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
2471 int bufsz
= 24 * 64; /* 24 items * 64 char per item */
2474 buf
= kzalloc(bufsz
, GFP_KERNEL
);
2478 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2479 "Interrupt Statistics Report:\n");
2481 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "HW Error:\t\t\t %u\n",
2483 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "SW Error:\t\t\t %u\n",
2485 if (isr_stats
->sw
|| isr_stats
->hw
) {
2486 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2487 "\tLast Restarting Code: 0x%X\n",
2488 isr_stats
->err_code
);
2490 #ifdef CONFIG_IWLWIFI_DEBUG
2491 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Frame transmitted:\t\t %u\n",
2493 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Alive interrupt:\t\t %u\n",
2496 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2497 "HW RF KILL switch toggled:\t %u\n", isr_stats
->rfkill
);
2499 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "CT KILL:\t\t\t %u\n",
2502 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Wakeup Interrupt:\t\t %u\n",
2505 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
,
2506 "Rx command responses:\t\t %u\n", isr_stats
->rx
);
2508 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Tx/FH interrupt:\t\t %u\n",
2511 pos
+= scnprintf(buf
+ pos
, bufsz
- pos
, "Unexpected INTA:\t\t %u\n",
2512 isr_stats
->unhandled
);
2514 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2519 static ssize_t
iwl_dbgfs_interrupt_write(struct file
*file
,
2520 const char __user
*user_buf
,
2521 size_t count
, loff_t
*ppos
)
2523 struct iwl_trans
*trans
= file
->private_data
;
2524 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2525 struct isr_statistics
*isr_stats
= &trans_pcie
->isr_stats
;
2529 ret
= kstrtou32_from_user(user_buf
, count
, 16, &reset_flag
);
2532 if (reset_flag
== 0)
2533 memset(isr_stats
, 0, sizeof(*isr_stats
));
2538 static ssize_t
iwl_dbgfs_csr_write(struct file
*file
,
2539 const char __user
*user_buf
,
2540 size_t count
, loff_t
*ppos
)
2542 struct iwl_trans
*trans
= file
->private_data
;
2544 iwl_pcie_dump_csr(trans
);
2549 static ssize_t
iwl_dbgfs_fh_reg_read(struct file
*file
,
2550 char __user
*user_buf
,
2551 size_t count
, loff_t
*ppos
)
2553 struct iwl_trans
*trans
= file
->private_data
;
2557 ret
= iwl_dump_fh(trans
, &buf
);
2562 ret
= simple_read_from_buffer(user_buf
, count
, ppos
, buf
, ret
);
2567 static ssize_t
iwl_dbgfs_rfkill_read(struct file
*file
,
2568 char __user
*user_buf
,
2569 size_t count
, loff_t
*ppos
)
2571 struct iwl_trans
*trans
= file
->private_data
;
2572 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2576 pos
= scnprintf(buf
, sizeof(buf
), "debug: %d\nhw: %d\n",
2577 trans_pcie
->debug_rfkill
,
2578 !(iwl_read32(trans
, CSR_GP_CNTRL
) &
2579 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW
));
2581 return simple_read_from_buffer(user_buf
, count
, ppos
, buf
, pos
);
2584 static ssize_t
iwl_dbgfs_rfkill_write(struct file
*file
,
2585 const char __user
*user_buf
,
2586 size_t count
, loff_t
*ppos
)
2588 struct iwl_trans
*trans
= file
->private_data
;
2589 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2590 bool old
= trans_pcie
->debug_rfkill
;
2593 ret
= kstrtobool_from_user(user_buf
, count
, &trans_pcie
->debug_rfkill
);
2596 if (old
== trans_pcie
->debug_rfkill
)
2598 IWL_WARN(trans
, "changing debug rfkill %d->%d\n",
2599 old
, trans_pcie
->debug_rfkill
);
2600 iwl_pcie_handle_rfkill_irq(trans
);
2605 DEBUGFS_READ_WRITE_FILE_OPS(interrupt
);
2606 DEBUGFS_READ_FILE_OPS(fh_reg
);
2607 DEBUGFS_READ_FILE_OPS(rx_queue
);
2608 DEBUGFS_READ_FILE_OPS(tx_queue
);
2609 DEBUGFS_WRITE_FILE_OPS(csr
);
2610 DEBUGFS_READ_WRITE_FILE_OPS(rfkill
);
2612 /* Create the debugfs files and directories */
2613 int iwl_trans_pcie_dbgfs_register(struct iwl_trans
*trans
)
2615 struct dentry
*dir
= trans
->dbgfs_dir
;
2617 DEBUGFS_ADD_FILE(rx_queue
, dir
, S_IRUSR
);
2618 DEBUGFS_ADD_FILE(tx_queue
, dir
, S_IRUSR
);
2619 DEBUGFS_ADD_FILE(interrupt
, dir
, S_IWUSR
| S_IRUSR
);
2620 DEBUGFS_ADD_FILE(csr
, dir
, S_IWUSR
);
2621 DEBUGFS_ADD_FILE(fh_reg
, dir
, S_IRUSR
);
2622 DEBUGFS_ADD_FILE(rfkill
, dir
, S_IWUSR
| S_IRUSR
);
2626 IWL_ERR(trans
, "failed to create the trans debugfs entry\n");
2629 #endif /*CONFIG_IWLWIFI_DEBUGFS */
2631 static u32
iwl_trans_pcie_get_cmdlen(struct iwl_trans
*trans
, void *tfd
)
2633 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2637 for (i
= 0; i
< trans_pcie
->max_tbs
; i
++)
2638 cmdlen
+= iwl_pcie_tfd_tb_get_len(trans
, tfd
, i
);
2643 static u32
iwl_trans_pcie_dump_rbs(struct iwl_trans
*trans
,
2644 struct iwl_fw_error_dump_data
**data
,
2645 int allocated_rb_nums
)
2647 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2648 int max_len
= PAGE_SIZE
<< trans_pcie
->rx_page_order
;
2649 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2650 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[0];
2651 u32 i
, r
, j
, rb_len
= 0;
2653 spin_lock(&rxq
->lock
);
2655 r
= le16_to_cpu(READ_ONCE(rxq
->rb_stts
->closed_rb_num
)) & 0x0FFF;
2657 for (i
= rxq
->read
, j
= 0;
2658 i
!= r
&& j
< allocated_rb_nums
;
2659 i
= (i
+ 1) & RX_QUEUE_MASK
, j
++) {
2660 struct iwl_rx_mem_buffer
*rxb
= rxq
->queue
[i
];
2661 struct iwl_fw_error_dump_rb
*rb
;
2663 dma_unmap_page(trans
->dev
, rxb
->page_dma
, max_len
,
2666 rb_len
+= sizeof(**data
) + sizeof(*rb
) + max_len
;
2668 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_RB
);
2669 (*data
)->len
= cpu_to_le32(sizeof(*rb
) + max_len
);
2670 rb
= (void *)(*data
)->data
;
2671 rb
->index
= cpu_to_le32(i
);
2672 memcpy(rb
->data
, page_address(rxb
->page
), max_len
);
2673 /* remap the page for the free benefit */
2674 rxb
->page_dma
= dma_map_page(trans
->dev
, rxb
->page
, 0,
2678 *data
= iwl_fw_error_next_data(*data
);
2681 spin_unlock(&rxq
->lock
);
2685 #define IWL_CSR_TO_DUMP (0x250)
2687 static u32
iwl_trans_pcie_dump_csr(struct iwl_trans
*trans
,
2688 struct iwl_fw_error_dump_data
**data
)
2690 u32 csr_len
= sizeof(**data
) + IWL_CSR_TO_DUMP
;
2694 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_CSR
);
2695 (*data
)->len
= cpu_to_le32(IWL_CSR_TO_DUMP
);
2696 val
= (void *)(*data
)->data
;
2698 for (i
= 0; i
< IWL_CSR_TO_DUMP
; i
+= 4)
2699 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
2701 *data
= iwl_fw_error_next_data(*data
);
2706 static u32
iwl_trans_pcie_fh_regs_dump(struct iwl_trans
*trans
,
2707 struct iwl_fw_error_dump_data
**data
)
2709 u32 fh_regs_len
= FH_MEM_UPPER_BOUND
- FH_MEM_LOWER_BOUND
;
2710 unsigned long flags
;
2714 if (!iwl_trans_grab_nic_access(trans
, &flags
))
2717 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS
);
2718 (*data
)->len
= cpu_to_le32(fh_regs_len
);
2719 val
= (void *)(*data
)->data
;
2721 if (!trans
->cfg
->gen2
)
2722 for (i
= FH_MEM_LOWER_BOUND
; i
< FH_MEM_UPPER_BOUND
;
2724 *val
++ = cpu_to_le32(iwl_trans_pcie_read32(trans
, i
));
2726 for (i
= FH_MEM_LOWER_BOUND_GEN2
; i
< FH_MEM_UPPER_BOUND_GEN2
;
2728 *val
++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans
,
2731 iwl_trans_release_nic_access(trans
, &flags
);
2733 *data
= iwl_fw_error_next_data(*data
);
2735 return sizeof(**data
) + fh_regs_len
;
2739 iwl_trans_pci_dump_marbh_monitor(struct iwl_trans
*trans
,
2740 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
,
2743 u32 buf_size_in_dwords
= (monitor_len
>> 2);
2744 u32
*buffer
= (u32
*)fw_mon_data
->data
;
2745 unsigned long flags
;
2748 if (!iwl_trans_grab_nic_access(trans
, &flags
))
2751 iwl_write_prph_no_grab(trans
, MON_DMARB_RD_CTL_ADDR
, 0x1);
2752 for (i
= 0; i
< buf_size_in_dwords
; i
++)
2753 buffer
[i
] = iwl_read_prph_no_grab(trans
,
2754 MON_DMARB_RD_DATA_ADDR
);
2755 iwl_write_prph_no_grab(trans
, MON_DMARB_RD_CTL_ADDR
, 0x0);
2757 iwl_trans_release_nic_access(trans
, &flags
);
2763 iwl_trans_pcie_dump_monitor(struct iwl_trans
*trans
,
2764 struct iwl_fw_error_dump_data
**data
,
2767 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2770 if ((trans_pcie
->fw_mon_page
&&
2771 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_7000
) ||
2772 trans
->dbg_dest_tlv
) {
2773 struct iwl_fw_error_dump_fw_mon
*fw_mon_data
;
2774 u32 base
, write_ptr
, wrap_cnt
;
2776 /* If there was a dest TLV - use the values from there */
2777 if (trans
->dbg_dest_tlv
) {
2779 le32_to_cpu(trans
->dbg_dest_tlv
->write_ptr_reg
);
2780 wrap_cnt
= le32_to_cpu(trans
->dbg_dest_tlv
->wrap_count
);
2781 base
= le32_to_cpu(trans
->dbg_dest_tlv
->base_reg
);
2783 base
= MON_BUFF_BASE_ADDR
;
2784 write_ptr
= MON_BUFF_WRPTR
;
2785 wrap_cnt
= MON_BUFF_CYCLE_CNT
;
2788 (*data
)->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR
);
2789 fw_mon_data
= (void *)(*data
)->data
;
2790 fw_mon_data
->fw_mon_wr_ptr
=
2791 cpu_to_le32(iwl_read_prph(trans
, write_ptr
));
2792 fw_mon_data
->fw_mon_cycle_cnt
=
2793 cpu_to_le32(iwl_read_prph(trans
, wrap_cnt
));
2794 fw_mon_data
->fw_mon_base_ptr
=
2795 cpu_to_le32(iwl_read_prph(trans
, base
));
2797 len
+= sizeof(**data
) + sizeof(*fw_mon_data
);
2798 if (trans_pcie
->fw_mon_page
) {
2800 * The firmware is now asserted, it won't write anything
2801 * to the buffer. CPU can take ownership to fetch the
2802 * data. The buffer will be handed back to the device
2803 * before the firmware will be restarted.
2805 dma_sync_single_for_cpu(trans
->dev
,
2806 trans_pcie
->fw_mon_phys
,
2807 trans_pcie
->fw_mon_size
,
2809 memcpy(fw_mon_data
->data
,
2810 page_address(trans_pcie
->fw_mon_page
),
2811 trans_pcie
->fw_mon_size
);
2813 monitor_len
= trans_pcie
->fw_mon_size
;
2814 } else if (trans
->dbg_dest_tlv
->monitor_mode
== SMEM_MODE
) {
2816 * Update pointers to reflect actual values after
2819 base
= iwl_read_prph(trans
, base
) <<
2820 trans
->dbg_dest_tlv
->base_shift
;
2821 iwl_trans_read_mem(trans
, base
, fw_mon_data
->data
,
2822 monitor_len
/ sizeof(u32
));
2823 } else if (trans
->dbg_dest_tlv
->monitor_mode
== MARBH_MODE
) {
2825 iwl_trans_pci_dump_marbh_monitor(trans
,
2829 /* Didn't match anything - output no monitor data */
2834 (*data
)->len
= cpu_to_le32(monitor_len
+ sizeof(*fw_mon_data
));
2840 static struct iwl_trans_dump_data
2841 *iwl_trans_pcie_dump_data(struct iwl_trans
*trans
,
2842 const struct iwl_fw_dbg_trigger_tlv
*trigger
)
2844 struct iwl_trans_pcie
*trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
2845 struct iwl_fw_error_dump_data
*data
;
2846 struct iwl_txq
*cmdq
= trans_pcie
->txq
[trans_pcie
->cmd_queue
];
2847 struct iwl_fw_error_dump_txcmd
*txcmd
;
2848 struct iwl_trans_dump_data
*dump_data
;
2852 bool dump_rbs
= test_bit(STATUS_FW_ERROR
, &trans
->status
) &&
2853 !trans
->cfg
->mq_rx_supported
;
2855 /* transport dump header */
2856 len
= sizeof(*dump_data
);
2859 len
+= sizeof(*data
) +
2860 cmdq
->n_window
* (sizeof(*txcmd
) + TFD_MAX_PAYLOAD_SIZE
);
2863 if (trans_pcie
->fw_mon_page
) {
2864 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_fw_mon
) +
2865 trans_pcie
->fw_mon_size
;
2866 monitor_len
= trans_pcie
->fw_mon_size
;
2867 } else if (trans
->dbg_dest_tlv
) {
2870 base
= le32_to_cpu(trans
->dbg_dest_tlv
->base_reg
);
2871 end
= le32_to_cpu(trans
->dbg_dest_tlv
->end_reg
);
2873 base
= iwl_read_prph(trans
, base
) <<
2874 trans
->dbg_dest_tlv
->base_shift
;
2875 end
= iwl_read_prph(trans
, end
) <<
2876 trans
->dbg_dest_tlv
->end_shift
;
2878 /* Make "end" point to the actual end */
2879 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
||
2880 trans
->dbg_dest_tlv
->monitor_mode
== MARBH_MODE
)
2881 end
+= (1 << trans
->dbg_dest_tlv
->end_shift
);
2882 monitor_len
= end
- base
;
2883 len
+= sizeof(*data
) + sizeof(struct iwl_fw_error_dump_fw_mon
) +
2889 if (trigger
&& (trigger
->mode
& IWL_FW_DBG_TRIGGER_MONITOR_ONLY
)) {
2890 dump_data
= vzalloc(len
);
2894 data
= (void *)dump_data
->data
;
2895 len
= iwl_trans_pcie_dump_monitor(trans
, &data
, monitor_len
);
2896 dump_data
->len
= len
;
2902 len
+= sizeof(*data
) + IWL_CSR_TO_DUMP
;
2905 if (trans
->cfg
->gen2
)
2906 len
+= sizeof(*data
) +
2907 (FH_MEM_UPPER_BOUND_GEN2
- FH_MEM_LOWER_BOUND_GEN2
);
2909 len
+= sizeof(*data
) +
2910 (FH_MEM_UPPER_BOUND
- FH_MEM_LOWER_BOUND
);
2913 /* Dump RBs is supported only for pre-9000 devices (1 queue) */
2914 struct iwl_rxq
*rxq
= &trans_pcie
->rxq
[0];
2916 num_rbs
= le16_to_cpu(READ_ONCE(rxq
->rb_stts
->closed_rb_num
))
2918 num_rbs
= (num_rbs
- rxq
->read
) & RX_QUEUE_MASK
;
2919 len
+= num_rbs
* (sizeof(*data
) +
2920 sizeof(struct iwl_fw_error_dump_rb
) +
2921 (PAGE_SIZE
<< trans_pcie
->rx_page_order
));
2924 /* Paged memory for gen2 HW */
2925 if (trans
->cfg
->gen2
)
2926 for (i
= 0; i
< trans_pcie
->init_dram
.paging_cnt
; i
++)
2927 len
+= sizeof(*data
) +
2928 sizeof(struct iwl_fw_error_dump_paging
) +
2929 trans_pcie
->init_dram
.paging
[i
].size
;
2931 dump_data
= vzalloc(len
);
2936 data
= (void *)dump_data
->data
;
2937 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD
);
2938 txcmd
= (void *)data
->data
;
2939 spin_lock_bh(&cmdq
->lock
);
2940 ptr
= cmdq
->write_ptr
;
2941 for (i
= 0; i
< cmdq
->n_window
; i
++) {
2942 u8 idx
= iwl_pcie_get_cmd_index(cmdq
, ptr
);
2945 cmdlen
= iwl_trans_pcie_get_cmdlen(trans
, cmdq
->tfds
+
2946 trans_pcie
->tfd_size
* ptr
);
2947 caplen
= min_t(u32
, TFD_MAX_PAYLOAD_SIZE
, cmdlen
);
2950 len
+= sizeof(*txcmd
) + caplen
;
2951 txcmd
->cmdlen
= cpu_to_le32(cmdlen
);
2952 txcmd
->caplen
= cpu_to_le32(caplen
);
2953 memcpy(txcmd
->data
, cmdq
->entries
[idx
].cmd
, caplen
);
2954 txcmd
= (void *)((u8
*)txcmd
->data
+ caplen
);
2957 ptr
= iwl_queue_dec_wrap(ptr
);
2959 spin_unlock_bh(&cmdq
->lock
);
2961 data
->len
= cpu_to_le32(len
);
2962 len
+= sizeof(*data
);
2963 data
= iwl_fw_error_next_data(data
);
2965 len
+= iwl_trans_pcie_dump_csr(trans
, &data
);
2966 len
+= iwl_trans_pcie_fh_regs_dump(trans
, &data
);
2968 len
+= iwl_trans_pcie_dump_rbs(trans
, &data
, num_rbs
);
2970 /* Paged memory for gen2 HW */
2971 if (trans
->cfg
->gen2
) {
2972 for (i
= 0; i
< trans_pcie
->init_dram
.paging_cnt
; i
++) {
2973 struct iwl_fw_error_dump_paging
*paging
;
2975 trans_pcie
->init_dram
.paging
[i
].physical
;
2976 u32 page_len
= trans_pcie
->init_dram
.paging
[i
].size
;
2978 data
->type
= cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING
);
2979 data
->len
= cpu_to_le32(sizeof(*paging
) + page_len
);
2980 paging
= (void *)data
->data
;
2981 paging
->index
= cpu_to_le32(i
);
2982 dma_sync_single_for_cpu(trans
->dev
, addr
, page_len
,
2984 memcpy(paging
->data
,
2985 trans_pcie
->init_dram
.paging
[i
].block
, page_len
);
2986 data
= iwl_fw_error_next_data(data
);
2988 len
+= sizeof(*data
) + sizeof(*paging
) + page_len
;
2992 len
+= iwl_trans_pcie_dump_monitor(trans
, &data
, monitor_len
);
2994 dump_data
->len
= len
;
2999 #ifdef CONFIG_PM_SLEEP
3000 static int iwl_trans_pcie_suspend(struct iwl_trans
*trans
)
3002 if (trans
->runtime_pm_mode
== IWL_PLAT_PM_MODE_D0I3
&&
3003 (trans
->system_pm_mode
== IWL_PLAT_PM_MODE_D0I3
))
3004 return iwl_pci_fw_enter_d0i3(trans
);
3009 static void iwl_trans_pcie_resume(struct iwl_trans
*trans
)
3011 if (trans
->runtime_pm_mode
== IWL_PLAT_PM_MODE_D0I3
&&
3012 (trans
->system_pm_mode
== IWL_PLAT_PM_MODE_D0I3
))
3013 iwl_pci_fw_exit_d0i3(trans
);
3015 #endif /* CONFIG_PM_SLEEP */
3017 #define IWL_TRANS_COMMON_OPS \
3018 .op_mode_leave = iwl_trans_pcie_op_mode_leave, \
3019 .write8 = iwl_trans_pcie_write8, \
3020 .write32 = iwl_trans_pcie_write32, \
3021 .read32 = iwl_trans_pcie_read32, \
3022 .read_prph = iwl_trans_pcie_read_prph, \
3023 .write_prph = iwl_trans_pcie_write_prph, \
3024 .read_mem = iwl_trans_pcie_read_mem, \
3025 .write_mem = iwl_trans_pcie_write_mem, \
3026 .configure = iwl_trans_pcie_configure, \
3027 .set_pmi = iwl_trans_pcie_set_pmi, \
3028 .grab_nic_access = iwl_trans_pcie_grab_nic_access, \
3029 .release_nic_access = iwl_trans_pcie_release_nic_access, \
3030 .set_bits_mask = iwl_trans_pcie_set_bits_mask, \
3031 .ref = iwl_trans_pcie_ref, \
3032 .unref = iwl_trans_pcie_unref, \
3033 .dump_data = iwl_trans_pcie_dump_data, \
3034 .dump_regs = iwl_trans_pcie_dump_regs, \
3035 .d3_suspend = iwl_trans_pcie_d3_suspend, \
3036 .d3_resume = iwl_trans_pcie_d3_resume
3038 #ifdef CONFIG_PM_SLEEP
3039 #define IWL_TRANS_PM_OPS \
3040 .suspend = iwl_trans_pcie_suspend, \
3041 .resume = iwl_trans_pcie_resume,
3043 #define IWL_TRANS_PM_OPS
3044 #endif /* CONFIG_PM_SLEEP */
3046 static const struct iwl_trans_ops trans_ops_pcie
= {
3047 IWL_TRANS_COMMON_OPS
,
3049 .start_hw
= iwl_trans_pcie_start_hw
,
3050 .fw_alive
= iwl_trans_pcie_fw_alive
,
3051 .start_fw
= iwl_trans_pcie_start_fw
,
3052 .stop_device
= iwl_trans_pcie_stop_device
,
3054 .send_cmd
= iwl_trans_pcie_send_hcmd
,
3056 .tx
= iwl_trans_pcie_tx
,
3057 .reclaim
= iwl_trans_pcie_reclaim
,
3059 .txq_disable
= iwl_trans_pcie_txq_disable
,
3060 .txq_enable
= iwl_trans_pcie_txq_enable
,
3062 .txq_set_shared_mode
= iwl_trans_pcie_txq_set_shared_mode
,
3064 .wait_tx_queues_empty
= iwl_trans_pcie_wait_txqs_empty
,
3066 .freeze_txq_timer
= iwl_trans_pcie_freeze_txq_timer
,
3067 .block_txq_ptrs
= iwl_trans_pcie_block_txq_ptrs
,
3070 static const struct iwl_trans_ops trans_ops_pcie_gen2
= {
3071 IWL_TRANS_COMMON_OPS
,
3073 .start_hw
= iwl_trans_pcie_start_hw
,
3074 .fw_alive
= iwl_trans_pcie_gen2_fw_alive
,
3075 .start_fw
= iwl_trans_pcie_gen2_start_fw
,
3076 .stop_device
= iwl_trans_pcie_gen2_stop_device
,
3078 .send_cmd
= iwl_trans_pcie_gen2_send_hcmd
,
3080 .tx
= iwl_trans_pcie_gen2_tx
,
3081 .reclaim
= iwl_trans_pcie_reclaim
,
3083 .txq_alloc
= iwl_trans_pcie_dyn_txq_alloc
,
3084 .txq_free
= iwl_trans_pcie_dyn_txq_free
,
3085 .wait_txq_empty
= iwl_trans_pcie_wait_txq_empty
,
3088 struct iwl_trans
*iwl_trans_pcie_alloc(struct pci_dev
*pdev
,
3089 const struct pci_device_id
*ent
,
3090 const struct iwl_cfg
*cfg
)
3092 struct iwl_trans_pcie
*trans_pcie
;
3093 struct iwl_trans
*trans
;
3096 ret
= pcim_enable_device(pdev
);
3098 return ERR_PTR(ret
);
3101 trans
= iwl_trans_alloc(sizeof(struct iwl_trans_pcie
),
3102 &pdev
->dev
, cfg
, &trans_ops_pcie_gen2
);
3104 trans
= iwl_trans_alloc(sizeof(struct iwl_trans_pcie
),
3105 &pdev
->dev
, cfg
, &trans_ops_pcie
);
3107 return ERR_PTR(-ENOMEM
);
3109 trans_pcie
= IWL_TRANS_GET_PCIE_TRANS(trans
);
3111 trans_pcie
->trans
= trans
;
3112 trans_pcie
->opmode_down
= true;
3113 spin_lock_init(&trans_pcie
->irq_lock
);
3114 spin_lock_init(&trans_pcie
->reg_lock
);
3115 mutex_init(&trans_pcie
->mutex
);
3116 init_waitqueue_head(&trans_pcie
->ucode_write_waitq
);
3117 trans_pcie
->tso_hdr_page
= alloc_percpu(struct iwl_tso_hdr_page
);
3118 if (!trans_pcie
->tso_hdr_page
) {
3124 if (!cfg
->base_params
->pcie_l1_allowed
) {
3126 * W/A - seems to solve weird behavior. We need to remove this
3127 * if we don't want to stay in L1 all the time. This wastes a
3130 pci_disable_link_state(pdev
, PCIE_LINK_STATE_L0S
|
3131 PCIE_LINK_STATE_L1
|
3132 PCIE_LINK_STATE_CLKPM
);
3137 trans_pcie
->max_tbs
= IWL_TFH_NUM_TBS
;
3138 trans_pcie
->tfd_size
= sizeof(struct iwl_tfh_tfd
);
3141 trans_pcie
->max_tbs
= IWL_NUM_OF_TBS
;
3142 trans_pcie
->tfd_size
= sizeof(struct iwl_tfd
);
3144 trans
->max_skb_frags
= IWL_PCIE_MAX_FRAGS(trans_pcie
);
3146 pci_set_master(pdev
);
3148 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(addr_size
));
3150 ret
= pci_set_consistent_dma_mask(pdev
,
3151 DMA_BIT_MASK(addr_size
));
3153 ret
= pci_set_dma_mask(pdev
, DMA_BIT_MASK(32));
3155 ret
= pci_set_consistent_dma_mask(pdev
,
3157 /* both attempts failed: */
3159 dev_err(&pdev
->dev
, "No suitable DMA available\n");
3164 ret
= pcim_iomap_regions_request_all(pdev
, BIT(0), DRV_NAME
);
3166 dev_err(&pdev
->dev
, "pcim_iomap_regions_request_all failed\n");
3170 trans_pcie
->hw_base
= pcim_iomap_table(pdev
)[0];
3171 if (!trans_pcie
->hw_base
) {
3172 dev_err(&pdev
->dev
, "pcim_iomap_table failed\n");
3177 /* We disable the RETRY_TIMEOUT register (0x41) to keep
3178 * PCI Tx retries from interfering with C3 CPU state */
3179 pci_write_config_byte(pdev
, PCI_CFG_RETRY_TIMEOUT
, 0x00);
3181 trans_pcie
->pci_dev
= pdev
;
3182 iwl_disable_interrupts(trans
);
3184 trans
->hw_rev
= iwl_read32(trans
, CSR_HW_REV
);
3186 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have
3187 * changed, and now the revision step also includes bit 0-1 (no more
3188 * "dash" value). To keep hw_rev backwards compatible - we'll store it
3189 * in the old format.
3191 if (trans
->cfg
->device_family
>= IWL_DEVICE_FAMILY_8000
) {
3192 unsigned long flags
;
3194 trans
->hw_rev
= (trans
->hw_rev
& 0xfff0) |
3195 (CSR_HW_REV_STEP(trans
->hw_rev
<< 2) << 2);
3197 ret
= iwl_pcie_prepare_card_hw(trans
);
3199 IWL_WARN(trans
, "Exit HW not ready\n");
3204 * in-order to recognize C step driver should read chip version
3205 * id located at the AUX bus MISC address space.
3207 iwl_set_bit(trans
, CSR_GP_CNTRL
,
3208 CSR_GP_CNTRL_REG_FLAG_INIT_DONE
);
3211 ret
= iwl_poll_bit(trans
, CSR_GP_CNTRL
,
3212 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
3213 CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
,
3216 IWL_DEBUG_INFO(trans
, "Failed to wake up the nic\n");
3220 if (iwl_trans_grab_nic_access(trans
, &flags
)) {
3223 hw_step
= iwl_read_prph_no_grab(trans
, WFPM_CTRL_REG
);
3224 hw_step
|= ENABLE_WFPM
;
3225 iwl_write_prph_no_grab(trans
, WFPM_CTRL_REG
, hw_step
);
3226 hw_step
= iwl_read_prph_no_grab(trans
, AUX_MISC_REG
);
3227 hw_step
= (hw_step
>> HW_STEP_LOCATION_BITS
) & 0xF;
3229 trans
->hw_rev
= (trans
->hw_rev
& 0xFFFFFFF3) |
3230 (SILICON_C_STEP
<< 2);
3231 iwl_trans_release_nic_access(trans
, &flags
);
3236 * 9000-series integrated A-step has a problem with suspend/resume
3237 * and sometimes even causes the whole platform to get stuck. This
3238 * workaround makes the hardware not go into the problematic state.
3240 if (trans
->cfg
->integrated
&&
3241 trans
->cfg
->device_family
== IWL_DEVICE_FAMILY_9000
&&
3242 CSR_HW_REV_STEP(trans
->hw_rev
) == SILICON_A_STEP
)
3243 iwl_set_bit(trans
, CSR_HOST_CHICKEN
,
3244 CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME
);
3246 #if IS_ENABLED(CONFIG_IWLMVM)
3247 trans
->hw_rf_id
= iwl_read32(trans
, CSR_HW_RF_ID
);
3248 if (trans
->hw_rf_id
== CSR_HW_RF_ID_TYPE_HR
) {
3251 hw_status
= iwl_read_prph(trans
, UMAG_GEN_HW_STATUS
);
3252 if (hw_status
& UMAG_GEN_HW_IS_FPGA
)
3253 trans
->cfg
= &iwla000_2ax_cfg_qnj_hr_f0
;
3255 trans
->cfg
= &iwla000_2ac_cfg_hr
;
3259 iwl_pcie_set_interrupt_capa(pdev
, trans
);
3260 trans
->hw_id
= (pdev
->device
<< 16) + pdev
->subsystem_device
;
3261 snprintf(trans
->hw_id_str
, sizeof(trans
->hw_id_str
),
3262 "PCI ID: 0x%04X:0x%04X", pdev
->device
, pdev
->subsystem_device
);
3264 /* Initialize the wait queue for commands */
3265 init_waitqueue_head(&trans_pcie
->wait_command_queue
);
3267 init_waitqueue_head(&trans_pcie
->d0i3_waitq
);
3269 if (trans_pcie
->msix_enabled
) {
3270 ret
= iwl_pcie_init_msix_handler(pdev
, trans_pcie
);
3274 ret
= iwl_pcie_alloc_ict(trans
);
3278 ret
= devm_request_threaded_irq(&pdev
->dev
, pdev
->irq
,
3280 iwl_pcie_irq_handler
,
3281 IRQF_SHARED
, DRV_NAME
, trans
);
3283 IWL_ERR(trans
, "Error allocating IRQ %d\n", pdev
->irq
);
3286 trans_pcie
->inta_mask
= CSR_INI_SET_MASK
;
3289 trans_pcie
->rba
.alloc_wq
= alloc_workqueue("rb_allocator",
3290 WQ_HIGHPRI
| WQ_UNBOUND
, 1);
3291 INIT_WORK(&trans_pcie
->rba
.rx_alloc
, iwl_pcie_rx_allocator_work
);
3293 #ifdef CONFIG_IWLWIFI_PCIE_RTPM
3294 trans
->runtime_pm_mode
= IWL_PLAT_PM_MODE_D0I3
;
3296 trans
->runtime_pm_mode
= IWL_PLAT_PM_MODE_DISABLED
;
3297 #endif /* CONFIG_IWLWIFI_PCIE_RTPM */
3302 iwl_pcie_free_ict(trans
);
3304 free_percpu(trans_pcie
->tso_hdr_page
);
3305 iwl_trans_free(trans
);
3306 return ERR_PTR(ret
);