drivers/pci/pci.h

   1 /* SPDX-License-Identifier: GPL-2.0 */
   2 #ifndef DRIVERS_PCI_H
   3 #define DRIVERS_PCI_H
   4
   5 #include <linux/pci.h>
   6
   7 #define PCI_FIND_CAP_TTL        48
   8
   9 #define PCI_VSEC_ID_INTEL_TBT   0x1234  /* Thunderbolt */
  10
  11 extern const unsigned char pcie_link_speed[];
  12 extern bool pci_early_dump;
  13
  14 bool pcie_cap_has_lnkctl(const struct pci_dev *dev);
  15
  16 /* Functions internal to the PCI core code */
  17
  18 int pci_create_sysfs_dev_files(struct pci_dev *pdev);
  19 void pci_remove_sysfs_dev_files(struct pci_dev *pdev);
  20 #if !defined(CONFIG_DMI) && !defined(CONFIG_ACPI)
  21 static inline void pci_create_firmware_label_files(struct pci_dev *pdev)
  22 { return; }
  23 static inline void pci_remove_firmware_label_files(struct pci_dev *pdev)
  24 { return; }
  25 #else
  26 void pci_create_firmware_label_files(struct pci_dev *pdev);
  27 void pci_remove_firmware_label_files(struct pci_dev *pdev);
  28 #endif
  29 void pci_cleanup_rom(struct pci_dev *dev);
  30
  31 enum pci_mmap_api {
  32         PCI_MMAP_SYSFS, /* mmap on /sys/bus/pci/devices/<BDF>/resource<N> */
  33         PCI_MMAP_PROCFS /* mmap on /proc/bus/pci/<BDF> */
  34 };
  35 int pci_mmap_fits(struct pci_dev *pdev, int resno, struct vm_area_struct *vmai,
  36                   enum pci_mmap_api mmap_api);
  37
  38 int pci_probe_reset_function(struct pci_dev *dev);
  39 int pci_bridge_secondary_bus_reset(struct pci_dev *dev);
  40 int pci_bus_error_reset(struct pci_dev *dev);
  41
  42 /**
  43  * struct pci_platform_pm_ops - Firmware PM callbacks
  44  *
  45  * @bridge_d3: Does the bridge allow entering into D3
  46  *
  47  * @is_manageable: returns 'true' if given device is power manageable by the
  48  *                 platform firmware
  49  *
  50  * @set_state: invokes the platform firmware to set the device's power state
  51  *
  52  * @get_state: queries the platform firmware for a device's current power state
  53  *
  54  * @choose_state: returns PCI power state of given device preferred by the
  55  *                platform; to be used during system-wide transitions from a
  56  *                sleeping state to the working state and vice versa
  57  *
  58  * @set_wakeup: enables/disables wakeup capability for the device
  59  *
  60  * @need_resume: returns 'true' if the given device (which is currently
  61  *               suspended) needs to be resumed to be configured for system
  62  *               wakeup.
  63  *
  64  * If given platform is generally capable of power managing PCI devices, all of
  65  * these callbacks are mandatory.
  66  */
  67 struct pci_platform_pm_ops {
  68         bool (*bridge_d3)(struct pci_dev *dev);
  69         bool (*is_manageable)(struct pci_dev *dev);
  70         int (*set_state)(struct pci_dev *dev, pci_power_t state);
  71         pci_power_t (*get_state)(struct pci_dev *dev);
  72         pci_power_t (*choose_state)(struct pci_dev *dev);
  73         int (*set_wakeup)(struct pci_dev *dev, bool enable);
  74         bool (*need_resume)(struct pci_dev *dev);
  75 };
  76
  77 int pci_set_platform_pm(const struct pci_platform_pm_ops *ops);
  78 void pci_update_current_state(struct pci_dev *dev, pci_power_t state);
  79 void pci_power_up(struct pci_dev *dev);
  80 void pci_disable_enabled_device(struct pci_dev *dev);
  81 int pci_finish_runtime_suspend(struct pci_dev *dev);
  82 void pcie_clear_root_pme_status(struct pci_dev *dev);
  83 int __pci_pme_wakeup(struct pci_dev *dev, void *ign);
  84 void pci_pme_restore(struct pci_dev *dev);
  85 bool pci_dev_keep_suspended(struct pci_dev *dev);
  86 void pci_dev_complete_resume(struct pci_dev *pci_dev);
  87 void pci_config_pm_runtime_get(struct pci_dev *dev);
  88 void pci_config_pm_runtime_put(struct pci_dev *dev);
  89 void pci_pm_init(struct pci_dev *dev);
  90 void pci_ea_init(struct pci_dev *dev);
  91 void pci_allocate_cap_save_buffers(struct pci_dev *dev);
  92 void pci_free_cap_save_buffers(struct pci_dev *dev);
  93 bool pci_bridge_d3_possible(struct pci_dev *dev);
  94 void pci_bridge_d3_update(struct pci_dev *dev);
  95
  96 static inline void pci_wakeup_event(struct pci_dev *dev)
  97 {
  98         /* Wait 100 ms before the system can be put into a sleep state. */
  99         pm_wakeup_event(&dev->dev, 100);
 100 }
 101
 102 static inline bool pci_has_subordinate(struct pci_dev *pci_dev)
 103 {
 104         return !!(pci_dev->subordinate);
 105 }
 106
 107 static inline bool pci_power_manageable(struct pci_dev *pci_dev)
 108 {
 109         /*
 110          * Currently we allow normal PCI devices and PCI bridges transition
 111          * into D3 if their bridge_d3 is set.
 112          */
 113         return !pci_has_subordinate(pci_dev) || pci_dev->bridge_d3;
 114 }
 115
 116 int pci_vpd_init(struct pci_dev *dev);
 117 void pci_vpd_release(struct pci_dev *dev);
 118 void pcie_vpd_create_sysfs_dev_files(struct pci_dev *dev);
 119 void pcie_vpd_remove_sysfs_dev_files(struct pci_dev *dev);
 120
 121 /* PCI /proc functions */
 122 #ifdef CONFIG_PROC_FS
 123 int pci_proc_attach_device(struct pci_dev *dev);
 124 int pci_proc_detach_device(struct pci_dev *dev);
 125 int pci_proc_detach_bus(struct pci_bus *bus);
 126 #else
 127 static inline int pci_proc_attach_device(struct pci_dev *dev) { return 0; }
 128 static inline int pci_proc_detach_device(struct pci_dev *dev) { return 0; }
 129 static inline int pci_proc_detach_bus(struct pci_bus *bus) { return 0; }
 130 #endif
 131
 132 /* Functions for PCI Hotplug drivers to use */
 133 int pci_hp_add_bridge(struct pci_dev *dev);
 134
 135 #ifdef HAVE_PCI_LEGACY
 136 void pci_create_legacy_files(struct pci_bus *bus);
 137 void pci_remove_legacy_files(struct pci_bus *bus);
 138 #else
 139 static inline void pci_create_legacy_files(struct pci_bus *bus) { return; }
 140 static inline void pci_remove_legacy_files(struct pci_bus *bus) { return; }
 141 #endif
 142
 143 /* Lock for read/write access to pci device and bus lists */
 144 extern struct rw_semaphore pci_bus_sem;
 145 extern struct mutex pci_slot_mutex;
 146
 147 extern raw_spinlock_t pci_lock;
 148
 149 extern unsigned int pci_pm_d3_delay;
 150
 151 #ifdef CONFIG_PCI_MSI
 152 void pci_no_msi(void);
 153 #else
 154 static inline void pci_no_msi(void) { }
 155 #endif
 156
 157 static inline void pci_msi_set_enable(struct pci_dev *dev, int enable)
 158 {
 159         u16 control;
 160
 161         pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
 162         control &= ~PCI_MSI_FLAGS_ENABLE;
 163         if (enable)
 164                 control |= PCI_MSI_FLAGS_ENABLE;
 165         pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
 166 }
 167
 168 static inline void pci_msix_clear_and_set_ctrl(struct pci_dev *dev, u16 clear, u16 set)
 169 {
 170         u16 ctrl;
 171
 172         pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &ctrl);
 173         ctrl &= ~clear;
 174         ctrl |= set;
 175         pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, ctrl);
 176 }
 177
 178 void pci_realloc_get_opt(char *);
 179
 180 static inline int pci_no_d1d2(struct pci_dev *dev)
 181 {
 182         unsigned int parent_dstates = 0;
 183
 184         if (dev->bus->self)
 185                 parent_dstates = dev->bus->self->no_d1d2;
 186         return (dev->no_d1d2 || parent_dstates);
 187
 188 }
 189 extern const struct attribute_group *pci_dev_groups[];
 190 extern const struct attribute_group *pcibus_groups[];
 191 extern const struct device_type pci_dev_type;
 192 extern const struct attribute_group *pci_bus_groups[];
 193
 194
 195 /**
 196  * pci_match_one_device - Tell if a PCI device structure has a matching
 197  *                        PCI device id structure
 198  * @id: single PCI device id structure to match
 199  * @dev: the PCI device structure to match against
 200  *
 201  * Returns the matching pci_device_id structure or %NULL if there is no match.
 202  */
 203 static inline const struct pci_device_id *
 204 pci_match_one_device(const struct pci_device_id *id, const struct pci_dev *dev)
 205 {
 206         if ((id->vendor == PCI_ANY_ID || id->vendor == dev->vendor) &&
 207             (id->device == PCI_ANY_ID || id->device == dev->device) &&
 208             (id->subvendor == PCI_ANY_ID || id->subvendor == dev->subsystem_vendor) &&
 209             (id->subdevice == PCI_ANY_ID || id->subdevice == dev->subsystem_device) &&
 210             !((id->class ^ dev->class) & id->class_mask))
 211                 return id;
 212         return NULL;
 213 }
 214
 215 /* PCI slot sysfs helper code */
 216 #define to_pci_slot(s) container_of(s, struct pci_slot, kobj)
 217
 218 extern struct kset *pci_slots_kset;
 219
 220 struct pci_slot_attribute {
 221         struct attribute attr;
 222         ssize_t (*show)(struct pci_slot *, char *);
 223         ssize_t (*store)(struct pci_slot *, const char *, size_t);
 224 };
 225 #define to_pci_slot_attr(s) container_of(s, struct pci_slot_attribute, attr)
 226
 227 enum pci_bar_type {
 228         pci_bar_unknown,        /* Standard PCI BAR probe */
 229         pci_bar_io,             /* An I/O port BAR */
 230         pci_bar_mem32,          /* A 32-bit memory BAR */
 231         pci_bar_mem64,          /* A 64-bit memory BAR */
 232 };
 233
 234 int pci_configure_extended_tags(struct pci_dev *dev, void *ign);
 235 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 236                                 int crs_timeout);
 237 bool pci_bus_generic_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *pl,
 238                                         int crs_timeout);
 239 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *pl, int crs_timeout);
 240
 241 int pci_setup_device(struct pci_dev *dev);
 242 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
 243                     struct resource *res, unsigned int reg);
 244 void pci_configure_ari(struct pci_dev *dev);
 245 void __pci_bus_size_bridges(struct pci_bus *bus,
 246                         struct list_head *realloc_head);
 247 void __pci_bus_assign_resources(const struct pci_bus *bus,
 248                                 struct list_head *realloc_head,
 249                                 struct list_head *fail_head);
 250 bool pci_bus_clip_resource(struct pci_dev *dev, int idx);
 251
 252 void pci_reassigndev_resource_alignment(struct pci_dev *dev);
 253 void pci_disable_bridge_window(struct pci_dev *dev);
 254
 255 /* PCIe link information */
 256 #define PCIE_SPEED2STR(speed) \
 257         ((speed) == PCIE_SPEED_16_0GT ? "16 GT/s" : \
 258          (speed) == PCIE_SPEED_8_0GT ? "8 GT/s" : \
 259          (speed) == PCIE_SPEED_5_0GT ? "5 GT/s" : \
 260          (speed) == PCIE_SPEED_2_5GT ? "2.5 GT/s" : \
 261          "Unknown speed")
 262
 263 /* PCIe speed to Mb/s reduced by encoding overhead */
 264 #define PCIE_SPEED2MBS_ENC(speed) \
 265         ((speed) == PCIE_SPEED_16_0GT ? 16000*128/130 : \
 266          (speed) == PCIE_SPEED_8_0GT  ?  8000*128/130 : \
 267          (speed) == PCIE_SPEED_5_0GT  ?  5000*8/10 : \
 268          (speed) == PCIE_SPEED_2_5GT  ?  2500*8/10 : \
 269          0)
 270
 271 enum pci_bus_speed pcie_get_speed_cap(struct pci_dev *dev);
 272 enum pcie_link_width pcie_get_width_cap(struct pci_dev *dev);
 273 u32 pcie_bandwidth_capable(struct pci_dev *dev, enum pci_bus_speed *speed,
 274                            enum pcie_link_width *width);
 275 void __pcie_print_link_status(struct pci_dev *dev, bool verbose);
 276
 277 /* Single Root I/O Virtualization */
 278 struct pci_sriov {
 279         int             pos;            /* Capability position */
 280         int             nres;           /* Number of resources */
 281         u32             cap;            /* SR-IOV Capabilities */
 282         u16             ctrl;           /* SR-IOV Control */
 283         u16             total_VFs;      /* Total VFs associated with the PF */
 284         u16             initial_VFs;    /* Initial VFs associated with the PF */
 285         u16             num_VFs;        /* Number of VFs available */
 286         u16             offset;         /* First VF Routing ID offset */
 287         u16             stride;         /* Following VF stride */
 288         u16             vf_device;      /* VF device ID */
 289         u32             pgsz;           /* Page size for BAR alignment */
 290         u8              link;           /* Function Dependency Link */
 291         u8              max_VF_buses;   /* Max buses consumed by VFs */
 292         u16             driver_max_VFs; /* Max num VFs driver supports */
 293         struct pci_dev  *dev;           /* Lowest numbered PF */
 294         struct pci_dev  *self;          /* This PF */
 295         u32             cfg_size;       /* VF config space size */
 296         u32             class;          /* VF device */
 297         u8              hdr_type;       /* VF header type */
 298         u16             subsystem_vendor; /* VF subsystem vendor */
 299         u16             subsystem_device; /* VF subsystem device */
 300         resource_size_t barsz[PCI_SRIOV_NUM_BARS];      /* VF BAR size */
 301         bool            drivers_autoprobe; /* Auto probing of VFs by driver */
 302 };
 303
 304 /**
 305  * pci_dev_set_io_state - Set the new error state if possible.
 306  *
 307  * @dev - pci device to set new error_state
 308  * @new - the state we want dev to be in
 309  *
 310  * Must be called with device_lock held.
 311  *
 312  * Returns true if state has been changed to the requested state.
 313  */
 314 static inline bool pci_dev_set_io_state(struct pci_dev *dev,
 315                                         pci_channel_state_t new)
 316 {
 317         bool changed = false;
 318
 319         device_lock_assert(&dev->dev);
 320         switch (new) {
 321         case pci_channel_io_perm_failure:
 322                 switch (dev->error_state) {
 323                 case pci_channel_io_frozen:
 324                 case pci_channel_io_normal:
 325                 case pci_channel_io_perm_failure:
 326                         changed = true;
 327                         break;
 328                 }
 329                 break;
 330         case pci_channel_io_frozen:
 331                 switch (dev->error_state) {
 332                 case pci_channel_io_frozen:
 333                 case pci_channel_io_normal:
 334                         changed = true;
 335                         break;
 336                 }
 337                 break;
 338         case pci_channel_io_normal:
 339                 switch (dev->error_state) {
 340                 case pci_channel_io_frozen:
 341                 case pci_channel_io_normal:
 342                         changed = true;
 343                         break;
 344                 }
 345                 break;
 346         }
 347         if (changed)
 348                 dev->error_state = new;
 349         return changed;
 350 }
 351
 352 static inline int pci_dev_set_disconnected(struct pci_dev *dev, void *unused)
 353 {
 354         device_lock(&dev->dev);
 355         pci_dev_set_io_state(dev, pci_channel_io_perm_failure);
 356         device_unlock(&dev->dev);
 357
 358         return 0;
 359 }
 360
 361 static inline bool pci_dev_is_disconnected(const struct pci_dev *dev)
 362 {
 363         return dev->error_state == pci_channel_io_perm_failure;
 364 }
 365
 366 /* pci_dev priv_flags */
 367 #define PCI_DEV_ADDED 0
 368
 369 static inline void pci_dev_assign_added(struct pci_dev *dev, bool added)
 370 {
 371         assign_bit(PCI_DEV_ADDED, &dev->priv_flags, added);
 372 }
 373
 374 static inline bool pci_dev_is_added(const struct pci_dev *dev)
 375 {
 376         return test_bit(PCI_DEV_ADDED, &dev->priv_flags);
 377 }
 378
 379 #ifdef CONFIG_PCIEAER
 380 #include <linux/aer.h>
 381
 382 #define AER_MAX_MULTI_ERR_DEVICES       5       /* Not likely to have more */
 383
 384 struct aer_err_info {
 385         struct pci_dev *dev[AER_MAX_MULTI_ERR_DEVICES];
 386         int error_dev_num;
 387
 388         unsigned int id:16;
 389
 390         unsigned int severity:2;        /* 0:NONFATAL | 1:FATAL | 2:COR */
 391         unsigned int __pad1:5;
 392         unsigned int multi_error_valid:1;
 393
 394         unsigned int first_error:5;
 395         unsigned int __pad2:2;
 396         unsigned int tlp_header_valid:1;
 397
 398         unsigned int status;            /* COR/UNCOR Error Status */
 399         unsigned int mask;              /* COR/UNCOR Error Mask */
 400         struct aer_header_log_regs tlp; /* TLP Header */
 401 };
 402
 403 int aer_get_device_error_info(struct pci_dev *dev, struct aer_err_info *info);
 404 void aer_print_error(struct pci_dev *dev, struct aer_err_info *info);
 405 #endif  /* CONFIG_PCIEAER */
 406
 407 #ifdef CONFIG_PCIE_DPC
 408 void pci_save_dpc_state(struct pci_dev *dev);
 409 void pci_restore_dpc_state(struct pci_dev *dev);
 410 #else
 411 static inline void pci_save_dpc_state(struct pci_dev *dev) {}
 412 static inline void pci_restore_dpc_state(struct pci_dev *dev) {}
 413 #endif
 414
 415 #ifdef CONFIG_PCI_ATS
 416 void pci_restore_ats_state(struct pci_dev *dev);
 417 #else
 418 static inline void pci_restore_ats_state(struct pci_dev *dev)
 419 {
 420 }
 421 #endif /* CONFIG_PCI_ATS */
 422
 423 #ifdef CONFIG_PCI_IOV
 424 int pci_iov_init(struct pci_dev *dev);
 425 void pci_iov_release(struct pci_dev *dev);
 426 void pci_iov_remove(struct pci_dev *dev);
 427 void pci_iov_update_resource(struct pci_dev *dev, int resno);
 428 resource_size_t pci_sriov_resource_alignment(struct pci_dev *dev, int resno);
 429 void pci_restore_iov_state(struct pci_dev *dev);
 430 int pci_iov_bus_range(struct pci_bus *bus);
 431
 432 #else
 433 static inline int pci_iov_init(struct pci_dev *dev)
 434 {
 435         return -ENODEV;
 436 }
 437 static inline void pci_iov_release(struct pci_dev *dev)
 438
 439 {
 440 }
 441 static inline void pci_iov_remove(struct pci_dev *dev)
 442 {
 443 }
 444 static inline void pci_restore_iov_state(struct pci_dev *dev)
 445 {
 446 }
 447 static inline int pci_iov_bus_range(struct pci_bus *bus)
 448 {
 449         return 0;
 450 }
 451
 452 #endif /* CONFIG_PCI_IOV */
 453
 454 unsigned long pci_cardbus_resource_alignment(struct resource *);
 455
 456 static inline resource_size_t pci_resource_alignment(struct pci_dev *dev,
 457                                                      struct resource *res)
 458 {
 459 #ifdef CONFIG_PCI_IOV
 460         int resno = res - dev->resource;
 461
 462         if (resno >= PCI_IOV_RESOURCES && resno <= PCI_IOV_RESOURCE_END)
 463                 return pci_sriov_resource_alignment(dev, resno);
 464 #endif
 465         if (dev->class >> 8 == PCI_CLASS_BRIDGE_CARDBUS)
 466                 return pci_cardbus_resource_alignment(res);
 467         return resource_alignment(res);
 468 }
 469
 470 void pci_enable_acs(struct pci_dev *dev);
 471 #ifdef CONFIG_PCI_QUIRKS
 472 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags);
 473 int pci_dev_specific_enable_acs(struct pci_dev *dev);
 474 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev);
 475 #else
 476 static inline int pci_dev_specific_acs_enabled(struct pci_dev *dev,
 477                                                u16 acs_flags)
 478 {
 479         return -ENOTTY;
 480 }
 481 static inline int pci_dev_specific_enable_acs(struct pci_dev *dev)
 482 {
 483         return -ENOTTY;
 484 }
 485 static inline int pci_dev_specific_disable_acs_redir(struct pci_dev *dev)
 486 {
 487         return -ENOTTY;
 488 }
 489 #endif
 490
 491 /* PCI error reporting and recovery */
 492 void pcie_do_recovery(struct pci_dev *dev, enum pci_channel_state state,
 493                       u32 service);
 494
 495 bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
 496 #ifdef CONFIG_PCIEASPM
 497 void pcie_aspm_init_link_state(struct pci_dev *pdev);
 498 void pcie_aspm_exit_link_state(struct pci_dev *pdev);
 499 void pcie_aspm_pm_state_change(struct pci_dev *pdev);
 500 void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
 501 #else
 502 static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
 503 static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
 504 static inline void pcie_aspm_pm_state_change(struct pci_dev *pdev) { }
 505 static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
 506 #endif
 507
 508 #ifdef CONFIG_PCIEASPM_DEBUG
 509 void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev);
 510 void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev);
 511 #else
 512 static inline void pcie_aspm_create_sysfs_dev_files(struct pci_dev *pdev) { }
 513 static inline void pcie_aspm_remove_sysfs_dev_files(struct pci_dev *pdev) { }
 514 #endif
 515
 516 #ifdef CONFIG_PCIE_PTM
 517 void pci_ptm_init(struct pci_dev *dev);
 518 #else
 519 static inline void pci_ptm_init(struct pci_dev *dev) { }
 520 #endif
 521
 522 struct pci_dev_reset_methods {
 523         u16 vendor;
 524         u16 device;
 525         int (*reset)(struct pci_dev *dev, int probe);
 526 };
 527
 528 #ifdef CONFIG_PCI_QUIRKS
 529 int pci_dev_specific_reset(struct pci_dev *dev, int probe);
 530 #else
 531 static inline int pci_dev_specific_reset(struct pci_dev *dev, int probe)
 532 {
 533         return -ENOTTY;
 534 }
 535 #endif
 536
 537 #if defined(CONFIG_PCI_QUIRKS) && defined(CONFIG_ARM64)
 538 int acpi_get_rc_resources(struct device *dev, const char *hid, u16 segment,
 539                           struct resource *res);
 540 #endif
 541
 542 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar);
 543 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar);
 544 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size);
 545 static inline u64 pci_rebar_size_to_bytes(int size)
 546 {
 547         return 1ULL << (size + 20);
 548 }
 549
 550 struct device_node;
 551
 552 #ifdef CONFIG_OF
 553 int of_pci_parse_bus_range(struct device_node *node, struct resource *res);
 554 int of_get_pci_domain_nr(struct device_node *node);
 555 int of_pci_get_max_link_speed(struct device_node *node);
 556
 557 #else
 558 static inline int
 559 of_pci_parse_bus_range(struct device_node *node, struct resource *res)
 560 {
 561         return -EINVAL;
 562 }
 563
 564 static inline int
 565 of_get_pci_domain_nr(struct device_node *node)
 566 {
 567         return -1;
 568 }
 569
 570 static inline int
 571 of_pci_get_max_link_speed(struct device_node *node)
 572 {
 573         return -EINVAL;
 574 }
 575 #endif /* CONFIG_OF */
 576
 577 #if defined(CONFIG_OF_ADDRESS)
 578 int devm_of_pci_get_host_bridge_resources(struct device *dev,
 579                         unsigned char busno, unsigned char bus_max,
 580                         struct list_head *resources, resource_size_t *io_base);
 581 #else
 582 static inline int devm_of_pci_get_host_bridge_resources(struct device *dev,
 583                         unsigned char busno, unsigned char bus_max,
 584                         struct list_head *resources, resource_size_t *io_base)
 585 {
 586         return -EINVAL;
 587 }
 588 #endif
 589
 590 #ifdef CONFIG_PCIEAER
 591 void pci_no_aer(void);
 592 void pci_aer_init(struct pci_dev *dev);
 593 void pci_aer_exit(struct pci_dev *dev);
 594 extern const struct attribute_group aer_stats_attr_group;
 595 void pci_aer_clear_fatal_status(struct pci_dev *dev);
 596 void pci_aer_clear_device_status(struct pci_dev *dev);
 597 #else
 598 static inline void pci_no_aer(void) { }
 599 static inline int pci_aer_init(struct pci_dev *d) { return -ENODEV; }
 600 static inline void pci_aer_exit(struct pci_dev *d) { }
 601 static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }
 602 static inline void pci_aer_clear_device_status(struct pci_dev *dev) { }
 603 #endif
 604
 605 #endif /* DRIVERS_PCI_H */