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scsi: qla2xxx: Split the __qla2x00_abort_all_cmds() function
[mirror_ubuntu-disco-kernel.git] / drivers / scsi / qla2xxx / qla_os.c
1 /*
2 * QLogic Fibre Channel HBA Driver
3 * Copyright (c) 2003-2014 QLogic Corporation
4 *
5 * See LICENSE.qla2xxx for copyright and licensing details.
6 */
7 #include "qla_def.h"
8
9 #include <linux/moduleparam.h>
10 #include <linux/vmalloc.h>
11 #include <linux/delay.h>
12 #include <linux/kthread.h>
13 #include <linux/mutex.h>
14 #include <linux/kobject.h>
15 #include <linux/slab.h>
16 #include <linux/blk-mq-pci.h>
17 #include <linux/refcount.h>
18
19 #include <scsi/scsi_tcq.h>
20 #include <scsi/scsicam.h>
21 #include <scsi/scsi_transport.h>
22 #include <scsi/scsi_transport_fc.h>
23
24 #include "qla_target.h"
25
26 /*
27 * Driver version
28 */
29 char qla2x00_version_str[40];
30
31 static int apidev_major;
32
33 /*
34 * SRB allocation cache
35 */
36 struct kmem_cache *srb_cachep;
37
38 /*
39 * CT6 CTX allocation cache
40 */
41 static struct kmem_cache *ctx_cachep;
42 /*
43 * error level for logging
44 */
45 int ql_errlev = ql_log_all;
46
47 static int ql2xenableclass2;
48 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR);
49 MODULE_PARM_DESC(ql2xenableclass2,
50 "Specify if Class 2 operations are supported from the very "
51 "beginning. Default is 0 - class 2 not supported.");
52
53
54 int ql2xlogintimeout = 20;
55 module_param(ql2xlogintimeout, int, S_IRUGO);
56 MODULE_PARM_DESC(ql2xlogintimeout,
57 "Login timeout value in seconds.");
58
59 int qlport_down_retry;
60 module_param(qlport_down_retry, int, S_IRUGO);
61 MODULE_PARM_DESC(qlport_down_retry,
62 "Maximum number of command retries to a port that returns "
63 "a PORT-DOWN status.");
64
65 int ql2xplogiabsentdevice;
66 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR);
67 MODULE_PARM_DESC(ql2xplogiabsentdevice,
68 "Option to enable PLOGI to devices that are not present after "
69 "a Fabric scan. This is needed for several broken switches. "
70 "Default is 0 - no PLOGI. 1 - perfom PLOGI.");
71
72 int ql2xloginretrycount = 0;
73 module_param(ql2xloginretrycount, int, S_IRUGO);
74 MODULE_PARM_DESC(ql2xloginretrycount,
75 "Specify an alternate value for the NVRAM login retry count.");
76
77 int ql2xallocfwdump = 1;
78 module_param(ql2xallocfwdump, int, S_IRUGO);
79 MODULE_PARM_DESC(ql2xallocfwdump,
80 "Option to enable allocation of memory for a firmware dump "
81 "during HBA initialization. Memory allocation requirements "
82 "vary by ISP type. Default is 1 - allocate memory.");
83
84 int ql2xextended_error_logging;
85 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
86 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR);
87 MODULE_PARM_DESC(ql2xextended_error_logging,
88 "Option to enable extended error logging,\n"
89 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n"
90 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n"
91 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n"
92 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n"
93 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n"
94 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n"
95 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n"
96 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n"
97 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n"
98 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n"
99 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n"
100 "\t\t0x1e400000 - Preferred value for capturing essential "
101 "debug information (equivalent to old "
102 "ql2xextended_error_logging=1).\n"
103 "\t\tDo LOGICAL OR of the value to enable more than one level");
104
105 int ql2xshiftctondsd = 6;
106 module_param(ql2xshiftctondsd, int, S_IRUGO);
107 MODULE_PARM_DESC(ql2xshiftctondsd,
108 "Set to control shifting of command type processing "
109 "based on total number of SG elements.");
110
111 int ql2xfdmienable=1;
112 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR);
113 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR);
114 MODULE_PARM_DESC(ql2xfdmienable,
115 "Enables FDMI registrations. "
116 "0 - no FDMI. Default is 1 - perform FDMI.");
117
118 #define MAX_Q_DEPTH 64
119 static int ql2xmaxqdepth = MAX_Q_DEPTH;
120 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR);
121 MODULE_PARM_DESC(ql2xmaxqdepth,
122 "Maximum queue depth to set for each LUN. "
123 "Default is 64.");
124
125 #if (IS_ENABLED(CONFIG_NVME_FC))
126 int ql2xenabledif;
127 #else
128 int ql2xenabledif = 2;
129 #endif
130 module_param(ql2xenabledif, int, S_IRUGO);
131 MODULE_PARM_DESC(ql2xenabledif,
132 " Enable T10-CRC-DIF:\n"
133 " Default is 2.\n"
134 " 0 -- No DIF Support\n"
135 " 1 -- Enable DIF for all types\n"
136 " 2 -- Enable DIF for all types, except Type 0.\n");
137
138 #if (IS_ENABLED(CONFIG_NVME_FC))
139 int ql2xnvmeenable = 1;
140 #else
141 int ql2xnvmeenable;
142 #endif
143 module_param(ql2xnvmeenable, int, 0644);
144 MODULE_PARM_DESC(ql2xnvmeenable,
145 "Enables NVME support. "
146 "0 - no NVMe. Default is Y");
147
148 int ql2xenablehba_err_chk = 2;
149 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR);
150 MODULE_PARM_DESC(ql2xenablehba_err_chk,
151 " Enable T10-CRC-DIF Error isolation by HBA:\n"
152 " Default is 2.\n"
153 " 0 -- Error isolation disabled\n"
154 " 1 -- Error isolation enabled only for DIX Type 0\n"
155 " 2 -- Error isolation enabled for all Types\n");
156
157 int ql2xiidmaenable=1;
158 module_param(ql2xiidmaenable, int, S_IRUGO);
159 MODULE_PARM_DESC(ql2xiidmaenable,
160 "Enables iIDMA settings "
161 "Default is 1 - perform iIDMA. 0 - no iIDMA.");
162
163 int ql2xmqsupport = 1;
164 module_param(ql2xmqsupport, int, S_IRUGO);
165 MODULE_PARM_DESC(ql2xmqsupport,
166 "Enable on demand multiple queue pairs support "
167 "Default is 1 for supported. "
168 "Set it to 0 to turn off mq qpair support.");
169
170 int ql2xfwloadbin;
171 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
172 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR);
173 MODULE_PARM_DESC(ql2xfwloadbin,
174 "Option to specify location from which to load ISP firmware:.\n"
175 " 2 -- load firmware via the request_firmware() (hotplug).\n"
176 " interface.\n"
177 " 1 -- load firmware from flash.\n"
178 " 0 -- use default semantics.\n");
179
180 int ql2xetsenable;
181 module_param(ql2xetsenable, int, S_IRUGO);
182 MODULE_PARM_DESC(ql2xetsenable,
183 "Enables firmware ETS burst."
184 "Default is 0 - skip ETS enablement.");
185
186 int ql2xdbwr = 1;
187 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR);
188 MODULE_PARM_DESC(ql2xdbwr,
189 "Option to specify scheme for request queue posting.\n"
190 " 0 -- Regular doorbell.\n"
191 " 1 -- CAMRAM doorbell (faster).\n");
192
193 int ql2xtargetreset = 1;
194 module_param(ql2xtargetreset, int, S_IRUGO);
195 MODULE_PARM_DESC(ql2xtargetreset,
196 "Enable target reset."
197 "Default is 1 - use hw defaults.");
198
199 int ql2xgffidenable;
200 module_param(ql2xgffidenable, int, S_IRUGO);
201 MODULE_PARM_DESC(ql2xgffidenable,
202 "Enables GFF_ID checks of port type. "
203 "Default is 0 - Do not use GFF_ID information.");
204
205 int ql2xasynctmfenable = 1;
206 module_param(ql2xasynctmfenable, int, S_IRUGO);
207 MODULE_PARM_DESC(ql2xasynctmfenable,
208 "Enables issue of TM IOCBs asynchronously via IOCB mechanism"
209 "Default is 1 - Issue TM IOCBs via mailbox mechanism.");
210
211 int ql2xdontresethba;
212 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR);
213 MODULE_PARM_DESC(ql2xdontresethba,
214 "Option to specify reset behaviour.\n"
215 " 0 (Default) -- Reset on failure.\n"
216 " 1 -- Do not reset on failure.\n");
217
218 uint64_t ql2xmaxlun = MAX_LUNS;
219 module_param(ql2xmaxlun, ullong, S_IRUGO);
220 MODULE_PARM_DESC(ql2xmaxlun,
221 "Defines the maximum LU number to register with the SCSI "
222 "midlayer. Default is 65535.");
223
224 int ql2xmdcapmask = 0x1F;
225 module_param(ql2xmdcapmask, int, S_IRUGO);
226 MODULE_PARM_DESC(ql2xmdcapmask,
227 "Set the Minidump driver capture mask level. "
228 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F.");
229
230 int ql2xmdenable = 1;
231 module_param(ql2xmdenable, int, S_IRUGO);
232 MODULE_PARM_DESC(ql2xmdenable,
233 "Enable/disable MiniDump. "
234 "0 - MiniDump disabled. "
235 "1 (Default) - MiniDump enabled.");
236
237 int ql2xexlogins = 0;
238 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR);
239 MODULE_PARM_DESC(ql2xexlogins,
240 "Number of extended Logins. "
241 "0 (Default)- Disabled.");
242
243 int ql2xexchoffld = 1024;
244 module_param(ql2xexchoffld, uint, 0644);
245 MODULE_PARM_DESC(ql2xexchoffld,
246 "Number of target exchanges.");
247
248 int ql2xiniexchg = 1024;
249 module_param(ql2xiniexchg, uint, 0644);
250 MODULE_PARM_DESC(ql2xiniexchg,
251 "Number of initiator exchanges.");
252
253 int ql2xfwholdabts = 0;
254 module_param(ql2xfwholdabts, int, S_IRUGO);
255 MODULE_PARM_DESC(ql2xfwholdabts,
256 "Allow FW to hold status IOCB until ABTS rsp received. "
257 "0 (Default) Do not set fw option. "
258 "1 - Set fw option to hold ABTS.");
259
260 int ql2xmvasynctoatio = 1;
261 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR);
262 MODULE_PARM_DESC(ql2xmvasynctoatio,
263 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ"
264 "0 (Default). Do not move IOCBs"
265 "1 - Move IOCBs.");
266
267 int ql2xautodetectsfp = 1;
268 module_param(ql2xautodetectsfp, int, 0444);
269 MODULE_PARM_DESC(ql2xautodetectsfp,
270 "Detect SFP range and set appropriate distance.\n"
271 "1 (Default): Enable\n");
272
273 int ql2xenablemsix = 1;
274 module_param(ql2xenablemsix, int, 0444);
275 MODULE_PARM_DESC(ql2xenablemsix,
276 "Set to enable MSI or MSI-X interrupt mechanism.\n"
277 " Default is 1, enable MSI-X interrupt mechanism.\n"
278 " 0 -- enable traditional pin-based mechanism.\n"
279 " 1 -- enable MSI-X interrupt mechanism.\n"
280 " 2 -- enable MSI interrupt mechanism.\n");
281
282 int qla2xuseresexchforels;
283 module_param(qla2xuseresexchforels, int, 0444);
284 MODULE_PARM_DESC(qla2xuseresexchforels,
285 "Reserve 1/2 of emergency exchanges for ELS.\n"
286 " 0 (default): disabled");
287
288 /*
289 * SCSI host template entry points
290 */
291 static int qla2xxx_slave_configure(struct scsi_device * device);
292 static int qla2xxx_slave_alloc(struct scsi_device *);
293 static int qla2xxx_scan_finished(struct Scsi_Host *, unsigned long time);
294 static void qla2xxx_scan_start(struct Scsi_Host *);
295 static void qla2xxx_slave_destroy(struct scsi_device *);
296 static int qla2xxx_queuecommand(struct Scsi_Host *h, struct scsi_cmnd *cmd);
297 static int qla2xxx_eh_abort(struct scsi_cmnd *);
298 static int qla2xxx_eh_device_reset(struct scsi_cmnd *);
299 static int qla2xxx_eh_target_reset(struct scsi_cmnd *);
300 static int qla2xxx_eh_bus_reset(struct scsi_cmnd *);
301 static int qla2xxx_eh_host_reset(struct scsi_cmnd *);
302
303 static void qla2x00_clear_drv_active(struct qla_hw_data *);
304 static void qla2x00_free_device(scsi_qla_host_t *);
305 static int qla2xxx_map_queues(struct Scsi_Host *shost);
306 static void qla2x00_destroy_deferred_work(struct qla_hw_data *);
307
308
309 struct scsi_host_template qla2xxx_driver_template = {
310 .module = THIS_MODULE,
311 .name = QLA2XXX_DRIVER_NAME,
312 .queuecommand = qla2xxx_queuecommand,
313
314 .eh_timed_out = fc_eh_timed_out,
315 .eh_abort_handler = qla2xxx_eh_abort,
316 .eh_device_reset_handler = qla2xxx_eh_device_reset,
317 .eh_target_reset_handler = qla2xxx_eh_target_reset,
318 .eh_bus_reset_handler = qla2xxx_eh_bus_reset,
319 .eh_host_reset_handler = qla2xxx_eh_host_reset,
320
321 .slave_configure = qla2xxx_slave_configure,
322
323 .slave_alloc = qla2xxx_slave_alloc,
324 .slave_destroy = qla2xxx_slave_destroy,
325 .scan_finished = qla2xxx_scan_finished,
326 .scan_start = qla2xxx_scan_start,
327 .change_queue_depth = scsi_change_queue_depth,
328 .map_queues = qla2xxx_map_queues,
329 .this_id = -1,
330 .cmd_per_lun = 3,
331 .use_clustering = ENABLE_CLUSTERING,
332 .sg_tablesize = SG_ALL,
333
334 .max_sectors = 0xFFFF,
335 .shost_attrs = qla2x00_host_attrs,
336
337 .supported_mode = MODE_INITIATOR,
338 .track_queue_depth = 1,
339 };
340
341 static struct scsi_transport_template *qla2xxx_transport_template = NULL;
342 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL;
343
344 /* TODO Convert to inlines
345 *
346 * Timer routines
347 */
348
349 __inline__ void
350 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval)
351 {
352 timer_setup(&vha->timer, qla2x00_timer, 0);
353 vha->timer.expires = jiffies + interval * HZ;
354 add_timer(&vha->timer);
355 vha->timer_active = 1;
356 }
357
358 static inline void
359 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval)
360 {
361 /* Currently used for 82XX only. */
362 if (vha->device_flags & DFLG_DEV_FAILED) {
363 ql_dbg(ql_dbg_timer, vha, 0x600d,
364 "Device in a failed state, returning.\n");
365 return;
366 }
367
368 mod_timer(&vha->timer, jiffies + interval * HZ);
369 }
370
371 static __inline__ void
372 qla2x00_stop_timer(scsi_qla_host_t *vha)
373 {
374 del_timer_sync(&vha->timer);
375 vha->timer_active = 0;
376 }
377
378 static int qla2x00_do_dpc(void *data);
379
380 static void qla2x00_rst_aen(scsi_qla_host_t *);
381
382 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t,
383 struct req_que **, struct rsp_que **);
384 static void qla2x00_free_fw_dump(struct qla_hw_data *);
385 static void qla2x00_mem_free(struct qla_hw_data *);
386 int qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
387 struct qla_qpair *qpair);
388
389 /* -------------------------------------------------------------------------- */
390 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req,
391 struct rsp_que *rsp)
392 {
393 struct qla_hw_data *ha = vha->hw;
394 rsp->qpair = ha->base_qpair;
395 rsp->req = req;
396 ha->base_qpair->hw = ha;
397 ha->base_qpair->req = req;
398 ha->base_qpair->rsp = rsp;
399 ha->base_qpair->vha = vha;
400 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock;
401 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
402 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q];
403 ha->base_qpair->srb_mempool = ha->srb_mempool;
404 INIT_LIST_HEAD(&ha->base_qpair->hints_list);
405 ha->base_qpair->enable_class_2 = ql2xenableclass2;
406 /* init qpair to this cpu. Will adjust at run time. */
407 qla_cpu_update(rsp->qpair, raw_smp_processor_id());
408 ha->base_qpair->pdev = ha->pdev;
409
410 if (IS_QLA27XX(ha) || IS_QLA83XX(ha))
411 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
412 }
413
414 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req,
415 struct rsp_que *rsp)
416 {
417 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
418 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *),
419 GFP_KERNEL);
420 if (!ha->req_q_map) {
421 ql_log(ql_log_fatal, vha, 0x003b,
422 "Unable to allocate memory for request queue ptrs.\n");
423 goto fail_req_map;
424 }
425
426 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *),
427 GFP_KERNEL);
428 if (!ha->rsp_q_map) {
429 ql_log(ql_log_fatal, vha, 0x003c,
430 "Unable to allocate memory for response queue ptrs.\n");
431 goto fail_rsp_map;
432 }
433
434 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
435 if (ha->base_qpair == NULL) {
436 ql_log(ql_log_warn, vha, 0x00e0,
437 "Failed to allocate base queue pair memory.\n");
438 goto fail_base_qpair;
439 }
440
441 qla_init_base_qpair(vha, req, rsp);
442
443 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) {
444 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *),
445 GFP_KERNEL);
446 if (!ha->queue_pair_map) {
447 ql_log(ql_log_fatal, vha, 0x0180,
448 "Unable to allocate memory for queue pair ptrs.\n");
449 goto fail_qpair_map;
450 }
451 }
452
453 /*
454 * Make sure we record at least the request and response queue zero in
455 * case we need to free them if part of the probe fails.
456 */
457 ha->rsp_q_map[0] = rsp;
458 ha->req_q_map[0] = req;
459 set_bit(0, ha->rsp_qid_map);
460 set_bit(0, ha->req_qid_map);
461 return 0;
462
463 fail_qpair_map:
464 kfree(ha->base_qpair);
465 ha->base_qpair = NULL;
466 fail_base_qpair:
467 kfree(ha->rsp_q_map);
468 ha->rsp_q_map = NULL;
469 fail_rsp_map:
470 kfree(ha->req_q_map);
471 ha->req_q_map = NULL;
472 fail_req_map:
473 return -ENOMEM;
474 }
475
476 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req)
477 {
478 if (IS_QLAFX00(ha)) {
479 if (req && req->ring_fx00)
480 dma_free_coherent(&ha->pdev->dev,
481 (req->length_fx00 + 1) * sizeof(request_t),
482 req->ring_fx00, req->dma_fx00);
483 } else if (req && req->ring)
484 dma_free_coherent(&ha->pdev->dev,
485 (req->length + 1) * sizeof(request_t),
486 req->ring, req->dma);
487
488 if (req)
489 kfree(req->outstanding_cmds);
490
491 kfree(req);
492 }
493
494 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp)
495 {
496 if (IS_QLAFX00(ha)) {
497 if (rsp && rsp->ring_fx00)
498 dma_free_coherent(&ha->pdev->dev,
499 (rsp->length_fx00 + 1) * sizeof(request_t),
500 rsp->ring_fx00, rsp->dma_fx00);
501 } else if (rsp && rsp->ring) {
502 dma_free_coherent(&ha->pdev->dev,
503 (rsp->length + 1) * sizeof(response_t),
504 rsp->ring, rsp->dma);
505 }
506 kfree(rsp);
507 }
508
509 static void qla2x00_free_queues(struct qla_hw_data *ha)
510 {
511 struct req_que *req;
512 struct rsp_que *rsp;
513 int cnt;
514 unsigned long flags;
515
516 if (ha->queue_pair_map) {
517 kfree(ha->queue_pair_map);
518 ha->queue_pair_map = NULL;
519 }
520 if (ha->base_qpair) {
521 kfree(ha->base_qpair);
522 ha->base_qpair = NULL;
523 }
524
525 spin_lock_irqsave(&ha->hardware_lock, flags);
526 for (cnt = 0; cnt < ha->max_req_queues; cnt++) {
527 if (!test_bit(cnt, ha->req_qid_map))
528 continue;
529
530 req = ha->req_q_map[cnt];
531 clear_bit(cnt, ha->req_qid_map);
532 ha->req_q_map[cnt] = NULL;
533
534 spin_unlock_irqrestore(&ha->hardware_lock, flags);
535 qla2x00_free_req_que(ha, req);
536 spin_lock_irqsave(&ha->hardware_lock, flags);
537 }
538 spin_unlock_irqrestore(&ha->hardware_lock, flags);
539
540 kfree(ha->req_q_map);
541 ha->req_q_map = NULL;
542
543
544 spin_lock_irqsave(&ha->hardware_lock, flags);
545 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) {
546 if (!test_bit(cnt, ha->rsp_qid_map))
547 continue;
548
549 rsp = ha->rsp_q_map[cnt];
550 clear_bit(cnt, ha->rsp_qid_map);
551 ha->rsp_q_map[cnt] = NULL;
552 spin_unlock_irqrestore(&ha->hardware_lock, flags);
553 qla2x00_free_rsp_que(ha, rsp);
554 spin_lock_irqsave(&ha->hardware_lock, flags);
555 }
556 spin_unlock_irqrestore(&ha->hardware_lock, flags);
557
558 kfree(ha->rsp_q_map);
559 ha->rsp_q_map = NULL;
560 }
561
562 static char *
563 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str)
564 {
565 struct qla_hw_data *ha = vha->hw;
566 static char *pci_bus_modes[] = {
567 "33", "66", "100", "133",
568 };
569 uint16_t pci_bus;
570
571 strcpy(str, "PCI");
572 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9;
573 if (pci_bus) {
574 strcat(str, "-X (");
575 strcat(str, pci_bus_modes[pci_bus]);
576 } else {
577 pci_bus = (ha->pci_attr & BIT_8) >> 8;
578 strcat(str, " (");
579 strcat(str, pci_bus_modes[pci_bus]);
580 }
581 strcat(str, " MHz)");
582
583 return (str);
584 }
585
586 static char *
587 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str)
588 {
589 static char *pci_bus_modes[] = { "33", "66", "100", "133", };
590 struct qla_hw_data *ha = vha->hw;
591 uint32_t pci_bus;
592
593 if (pci_is_pcie(ha->pdev)) {
594 char lwstr[6];
595 uint32_t lstat, lspeed, lwidth;
596
597 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat);
598 lspeed = lstat & PCI_EXP_LNKCAP_SLS;
599 lwidth = (lstat & PCI_EXP_LNKCAP_MLW) >> 4;
600
601 strcpy(str, "PCIe (");
602 switch (lspeed) {
603 case 1:
604 strcat(str, "2.5GT/s ");
605 break;
606 case 2:
607 strcat(str, "5.0GT/s ");
608 break;
609 case 3:
610 strcat(str, "8.0GT/s ");
611 break;
612 default:
613 strcat(str, "<unknown> ");
614 break;
615 }
616 snprintf(lwstr, sizeof(lwstr), "x%d)", lwidth);
617 strcat(str, lwstr);
618
619 return str;
620 }
621
622 strcpy(str, "PCI");
623 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8;
624 if (pci_bus == 0 || pci_bus == 8) {
625 strcat(str, " (");
626 strcat(str, pci_bus_modes[pci_bus >> 3]);
627 } else {
628 strcat(str, "-X ");
629 if (pci_bus & BIT_2)
630 strcat(str, "Mode 2");
631 else
632 strcat(str, "Mode 1");
633 strcat(str, " (");
634 strcat(str, pci_bus_modes[pci_bus & ~BIT_2]);
635 }
636 strcat(str, " MHz)");
637
638 return str;
639 }
640
641 static char *
642 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
643 {
644 char un_str[10];
645 struct qla_hw_data *ha = vha->hw;
646
647 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version,
648 ha->fw_minor_version, ha->fw_subminor_version);
649
650 if (ha->fw_attributes & BIT_9) {
651 strcat(str, "FLX");
652 return (str);
653 }
654
655 switch (ha->fw_attributes & 0xFF) {
656 case 0x7:
657 strcat(str, "EF");
658 break;
659 case 0x17:
660 strcat(str, "TP");
661 break;
662 case 0x37:
663 strcat(str, "IP");
664 break;
665 case 0x77:
666 strcat(str, "VI");
667 break;
668 default:
669 sprintf(un_str, "(%x)", ha->fw_attributes);
670 strcat(str, un_str);
671 break;
672 }
673 if (ha->fw_attributes & 0x100)
674 strcat(str, "X");
675
676 return (str);
677 }
678
679 static char *
680 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size)
681 {
682 struct qla_hw_data *ha = vha->hw;
683
684 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version,
685 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes);
686 return str;
687 }
688
689 void
690 qla2x00_sp_free_dma(void *ptr)
691 {
692 srb_t *sp = ptr;
693 struct qla_hw_data *ha = sp->vha->hw;
694 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
695 void *ctx = GET_CMD_CTX_SP(sp);
696
697 if (sp->flags & SRB_DMA_VALID) {
698 scsi_dma_unmap(cmd);
699 sp->flags &= ~SRB_DMA_VALID;
700 }
701
702 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
703 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
704 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
705 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
706 }
707
708 if (!ctx)
709 goto end;
710
711 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
712 /* List assured to be having elements */
713 qla2x00_clean_dsd_pool(ha, ctx);
714 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
715 }
716
717 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
718 struct crc_context *ctx0 = ctx;
719
720 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma);
721 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
722 }
723
724 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
725 struct ct6_dsd *ctx1 = ctx;
726
727 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
728 ctx1->fcp_cmnd_dma);
729 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
730 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
731 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
732 mempool_free(ctx1, ha->ctx_mempool);
733 }
734
735 end:
736 if (sp->type != SRB_NVME_CMD && sp->type != SRB_NVME_LS) {
737 CMD_SP(cmd) = NULL;
738 qla2x00_rel_sp(sp);
739 }
740 }
741
742 void
743 qla2x00_sp_compl(void *ptr, int res)
744 {
745 srb_t *sp = ptr;
746 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
747
748 cmd->result = res;
749
750 if (atomic_read(&sp->ref_count) == 0) {
751 ql_dbg(ql_dbg_io, sp->vha, 0x3015,
752 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
753 sp, GET_CMD_SP(sp));
754 if (ql2xextended_error_logging & ql_dbg_io)
755 WARN_ON(atomic_read(&sp->ref_count) == 0);
756 return;
757 }
758 if (!atomic_dec_and_test(&sp->ref_count))
759 return;
760
761 sp->free(sp);
762 cmd->scsi_done(cmd);
763 }
764
765 void
766 qla2xxx_qpair_sp_free_dma(void *ptr)
767 {
768 srb_t *sp = (srb_t *)ptr;
769 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
770 struct qla_hw_data *ha = sp->fcport->vha->hw;
771 void *ctx = GET_CMD_CTX_SP(sp);
772
773 if (sp->flags & SRB_DMA_VALID) {
774 scsi_dma_unmap(cmd);
775 sp->flags &= ~SRB_DMA_VALID;
776 }
777
778 if (sp->flags & SRB_CRC_PROT_DMA_VALID) {
779 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd),
780 scsi_prot_sg_count(cmd), cmd->sc_data_direction);
781 sp->flags &= ~SRB_CRC_PROT_DMA_VALID;
782 }
783
784 if (!ctx)
785 goto end;
786
787 if (sp->flags & SRB_CRC_CTX_DSD_VALID) {
788 /* List assured to be having elements */
789 qla2x00_clean_dsd_pool(ha, ctx);
790 sp->flags &= ~SRB_CRC_CTX_DSD_VALID;
791 }
792
793 if (sp->flags & SRB_CRC_CTX_DMA_VALID) {
794 struct crc_context *ctx0 = ctx;
795
796 dma_pool_free(ha->dl_dma_pool, ctx, ctx0->crc_ctx_dma);
797 sp->flags &= ~SRB_CRC_CTX_DMA_VALID;
798 }
799
800 if (sp->flags & SRB_FCP_CMND_DMA_VALID) {
801 struct ct6_dsd *ctx1 = ctx;
802 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd,
803 ctx1->fcp_cmnd_dma);
804 list_splice(&ctx1->dsd_list, &ha->gbl_dsd_list);
805 ha->gbl_dsd_inuse -= ctx1->dsd_use_cnt;
806 ha->gbl_dsd_avail += ctx1->dsd_use_cnt;
807 mempool_free(ctx1, ha->ctx_mempool);
808 }
809 end:
810 CMD_SP(cmd) = NULL;
811 qla2xxx_rel_qpair_sp(sp->qpair, sp);
812 }
813
814 void
815 qla2xxx_qpair_sp_compl(void *ptr, int res)
816 {
817 srb_t *sp = ptr;
818 struct scsi_cmnd *cmd = GET_CMD_SP(sp);
819
820 cmd->result = res;
821
822 if (atomic_read(&sp->ref_count) == 0) {
823 ql_dbg(ql_dbg_io, sp->fcport->vha, 0x3079,
824 "SP reference-count to ZERO -- sp=%p cmd=%p.\n",
825 sp, GET_CMD_SP(sp));
826 if (ql2xextended_error_logging & ql_dbg_io)
827 WARN_ON(atomic_read(&sp->ref_count) == 0);
828 return;
829 }
830 if (!atomic_dec_and_test(&sp->ref_count))
831 return;
832
833 sp->free(sp);
834 cmd->scsi_done(cmd);
835 }
836
837 /* If we are SP1 here, we need to still take and release the host_lock as SP1
838 * does not have the changes necessary to avoid taking host->host_lock.
839 */
840 static int
841 qla2xxx_queuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd)
842 {
843 scsi_qla_host_t *vha = shost_priv(host);
844 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
845 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
846 struct qla_hw_data *ha = vha->hw;
847 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
848 srb_t *sp;
849 int rval;
850 struct qla_qpair *qpair = NULL;
851 uint32_t tag;
852 uint16_t hwq;
853
854 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags))) {
855 cmd->result = DID_NO_CONNECT << 16;
856 goto qc24_fail_command;
857 }
858
859 if (ha->mqenable) {
860 if (shost_use_blk_mq(vha->host)) {
861 tag = blk_mq_unique_tag(cmd->request);
862 hwq = blk_mq_unique_tag_to_hwq(tag);
863 qpair = ha->queue_pair_map[hwq];
864 } else if (vha->vp_idx && vha->qpair) {
865 qpair = vha->qpair;
866 }
867
868 if (qpair)
869 return qla2xxx_mqueuecommand(host, cmd, qpair);
870 }
871
872 if (ha->flags.eeh_busy) {
873 if (ha->flags.pci_channel_io_perm_failure) {
874 ql_dbg(ql_dbg_aer, vha, 0x9010,
875 "PCI Channel IO permanent failure, exiting "
876 "cmd=%p.\n", cmd);
877 cmd->result = DID_NO_CONNECT << 16;
878 } else {
879 ql_dbg(ql_dbg_aer, vha, 0x9011,
880 "EEH_Busy, Requeuing the cmd=%p.\n", cmd);
881 cmd->result = DID_REQUEUE << 16;
882 }
883 goto qc24_fail_command;
884 }
885
886 rval = fc_remote_port_chkready(rport);
887 if (rval) {
888 cmd->result = rval;
889 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003,
890 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
891 cmd, rval);
892 goto qc24_fail_command;
893 }
894
895 if (!vha->flags.difdix_supported &&
896 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) {
897 ql_dbg(ql_dbg_io, vha, 0x3004,
898 "DIF Cap not reg, fail DIF capable cmd's:%p.\n",
899 cmd);
900 cmd->result = DID_NO_CONNECT << 16;
901 goto qc24_fail_command;
902 }
903
904 if (!fcport) {
905 cmd->result = DID_NO_CONNECT << 16;
906 goto qc24_fail_command;
907 }
908
909 if (atomic_read(&fcport->state) != FCS_ONLINE) {
910 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
911 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
912 ql_dbg(ql_dbg_io, vha, 0x3005,
913 "Returning DNC, fcport_state=%d loop_state=%d.\n",
914 atomic_read(&fcport->state),
915 atomic_read(&base_vha->loop_state));
916 cmd->result = DID_NO_CONNECT << 16;
917 goto qc24_fail_command;
918 }
919 goto qc24_target_busy;
920 }
921
922 /*
923 * Return target busy if we've received a non-zero retry_delay_timer
924 * in a FCP_RSP.
925 */
926 if (fcport->retry_delay_timestamp == 0) {
927 /* retry delay not set */
928 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
929 fcport->retry_delay_timestamp = 0;
930 else
931 goto qc24_target_busy;
932
933 sp = qla2x00_get_sp(vha, fcport, GFP_ATOMIC);
934 if (!sp)
935 goto qc24_host_busy;
936
937 sp->u.scmd.cmd = cmd;
938 sp->type = SRB_SCSI_CMD;
939 atomic_set(&sp->ref_count, 1);
940 CMD_SP(cmd) = (void *)sp;
941 sp->free = qla2x00_sp_free_dma;
942 sp->done = qla2x00_sp_compl;
943
944 rval = ha->isp_ops->start_scsi(sp);
945 if (rval != QLA_SUCCESS) {
946 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013,
947 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
948 goto qc24_host_busy_free_sp;
949 }
950
951 return 0;
952
953 qc24_host_busy_free_sp:
954 sp->free(sp);
955
956 qc24_host_busy:
957 return SCSI_MLQUEUE_HOST_BUSY;
958
959 qc24_target_busy:
960 return SCSI_MLQUEUE_TARGET_BUSY;
961
962 qc24_fail_command:
963 cmd->scsi_done(cmd);
964
965 return 0;
966 }
967
968 /* For MQ supported I/O */
969 int
970 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd,
971 struct qla_qpair *qpair)
972 {
973 scsi_qla_host_t *vha = shost_priv(host);
974 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
975 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device));
976 struct qla_hw_data *ha = vha->hw;
977 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
978 srb_t *sp;
979 int rval;
980
981 rval = fc_remote_port_chkready(rport);
982 if (rval) {
983 cmd->result = rval;
984 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076,
985 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n",
986 cmd, rval);
987 goto qc24_fail_command;
988 }
989
990 if (!fcport) {
991 cmd->result = DID_NO_CONNECT << 16;
992 goto qc24_fail_command;
993 }
994
995 if (atomic_read(&fcport->state) != FCS_ONLINE) {
996 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD ||
997 atomic_read(&base_vha->loop_state) == LOOP_DEAD) {
998 ql_dbg(ql_dbg_io, vha, 0x3077,
999 "Returning DNC, fcport_state=%d loop_state=%d.\n",
1000 atomic_read(&fcport->state),
1001 atomic_read(&base_vha->loop_state));
1002 cmd->result = DID_NO_CONNECT << 16;
1003 goto qc24_fail_command;
1004 }
1005 goto qc24_target_busy;
1006 }
1007
1008 /*
1009 * Return target busy if we've received a non-zero retry_delay_timer
1010 * in a FCP_RSP.
1011 */
1012 if (fcport->retry_delay_timestamp == 0) {
1013 /* retry delay not set */
1014 } else if (time_after(jiffies, fcport->retry_delay_timestamp))
1015 fcport->retry_delay_timestamp = 0;
1016 else
1017 goto qc24_target_busy;
1018
1019 sp = qla2xxx_get_qpair_sp(vha, qpair, fcport, GFP_ATOMIC);
1020 if (!sp)
1021 goto qc24_host_busy;
1022
1023 sp->u.scmd.cmd = cmd;
1024 sp->type = SRB_SCSI_CMD;
1025 atomic_set(&sp->ref_count, 1);
1026 CMD_SP(cmd) = (void *)sp;
1027 sp->free = qla2xxx_qpair_sp_free_dma;
1028 sp->done = qla2xxx_qpair_sp_compl;
1029 sp->qpair = qpair;
1030
1031 rval = ha->isp_ops->start_scsi_mq(sp);
1032 if (rval != QLA_SUCCESS) {
1033 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078,
1034 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd);
1035 if (rval == QLA_INTERFACE_ERROR)
1036 goto qc24_fail_command;
1037 goto qc24_host_busy_free_sp;
1038 }
1039
1040 return 0;
1041
1042 qc24_host_busy_free_sp:
1043 sp->free(sp);
1044
1045 qc24_host_busy:
1046 return SCSI_MLQUEUE_HOST_BUSY;
1047
1048 qc24_target_busy:
1049 return SCSI_MLQUEUE_TARGET_BUSY;
1050
1051 qc24_fail_command:
1052 cmd->scsi_done(cmd);
1053
1054 return 0;
1055 }
1056
1057 /*
1058 * qla2x00_eh_wait_on_command
1059 * Waits for the command to be returned by the Firmware for some
1060 * max time.
1061 *
1062 * Input:
1063 * cmd = Scsi Command to wait on.
1064 *
1065 * Return:
1066 * Not Found : 0
1067 * Found : 1
1068 */
1069 static int
1070 qla2x00_eh_wait_on_command(struct scsi_cmnd *cmd)
1071 {
1072 #define ABORT_POLLING_PERIOD 1000
1073 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD))
1074 unsigned long wait_iter = ABORT_WAIT_ITER;
1075 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1076 struct qla_hw_data *ha = vha->hw;
1077 int ret = QLA_SUCCESS;
1078
1079 if (unlikely(pci_channel_offline(ha->pdev)) || ha->flags.eeh_busy) {
1080 ql_dbg(ql_dbg_taskm, vha, 0x8005,
1081 "Return:eh_wait.\n");
1082 return ret;
1083 }
1084
1085 while (CMD_SP(cmd) && wait_iter--) {
1086 msleep(ABORT_POLLING_PERIOD);
1087 }
1088 if (CMD_SP(cmd))
1089 ret = QLA_FUNCTION_FAILED;
1090
1091 return ret;
1092 }
1093
1094 /*
1095 * qla2x00_wait_for_hba_online
1096 * Wait till the HBA is online after going through
1097 * <= MAX_RETRIES_OF_ISP_ABORT or
1098 * finally HBA is disabled ie marked offline
1099 *
1100 * Input:
1101 * ha - pointer to host adapter structure
1102 *
1103 * Note:
1104 * Does context switching-Release SPIN_LOCK
1105 * (if any) before calling this routine.
1106 *
1107 * Return:
1108 * Success (Adapter is online) : 0
1109 * Failed (Adapter is offline/disabled) : 1
1110 */
1111 int
1112 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha)
1113 {
1114 int return_status;
1115 unsigned long wait_online;
1116 struct qla_hw_data *ha = vha->hw;
1117 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1118
1119 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1120 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1121 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1122 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1123 ha->dpc_active) && time_before(jiffies, wait_online)) {
1124
1125 msleep(1000);
1126 }
1127 if (base_vha->flags.online)
1128 return_status = QLA_SUCCESS;
1129 else
1130 return_status = QLA_FUNCTION_FAILED;
1131
1132 return (return_status);
1133 }
1134
1135 static inline int test_fcport_count(scsi_qla_host_t *vha)
1136 {
1137 struct qla_hw_data *ha = vha->hw;
1138 unsigned long flags;
1139 int res;
1140
1141 spin_lock_irqsave(&ha->tgt.sess_lock, flags);
1142 ql_dbg(ql_dbg_init, vha, 0x00ec,
1143 "tgt %p, fcport_count=%d\n",
1144 vha, vha->fcport_count);
1145 res = (vha->fcport_count == 0);
1146 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags);
1147
1148 return res;
1149 }
1150
1151 /*
1152 * qla2x00_wait_for_sess_deletion can only be called from remove_one.
1153 * it has dependency on UNLOADING flag to stop device discovery
1154 */
1155 void
1156 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha)
1157 {
1158 qla2x00_mark_all_devices_lost(vha, 0);
1159
1160 wait_event_timeout(vha->fcport_waitQ, test_fcport_count(vha), 10*HZ);
1161 }
1162
1163 /*
1164 * qla2x00_wait_for_hba_ready
1165 * Wait till the HBA is ready before doing driver unload
1166 *
1167 * Input:
1168 * ha - pointer to host adapter structure
1169 *
1170 * Note:
1171 * Does context switching-Release SPIN_LOCK
1172 * (if any) before calling this routine.
1173 *
1174 */
1175 static void
1176 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha)
1177 {
1178 struct qla_hw_data *ha = vha->hw;
1179 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1180
1181 while ((qla2x00_reset_active(vha) || ha->dpc_active ||
1182 ha->flags.mbox_busy) ||
1183 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) ||
1184 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags)) {
1185 if (test_bit(UNLOADING, &base_vha->dpc_flags))
1186 break;
1187 msleep(1000);
1188 }
1189 }
1190
1191 int
1192 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha)
1193 {
1194 int return_status;
1195 unsigned long wait_reset;
1196 struct qla_hw_data *ha = vha->hw;
1197 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1198
1199 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
1200 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) ||
1201 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) ||
1202 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) ||
1203 ha->dpc_active) && time_before(jiffies, wait_reset)) {
1204
1205 msleep(1000);
1206
1207 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
1208 ha->flags.chip_reset_done)
1209 break;
1210 }
1211 if (ha->flags.chip_reset_done)
1212 return_status = QLA_SUCCESS;
1213 else
1214 return_status = QLA_FUNCTION_FAILED;
1215
1216 return return_status;
1217 }
1218
1219 static int
1220 sp_get(struct srb *sp)
1221 {
1222 if (!refcount_inc_not_zero((refcount_t*)&sp->ref_count))
1223 /* kref get fail */
1224 return ENXIO;
1225 else
1226 return 0;
1227 }
1228
1229 #define ISP_REG_DISCONNECT 0xffffffffU
1230 /**************************************************************************
1231 * qla2x00_isp_reg_stat
1232 *
1233 * Description:
1234 * Read the host status register of ISP before aborting the command.
1235 *
1236 * Input:
1237 * ha = pointer to host adapter structure.
1238 *
1239 *
1240 * Returns:
1241 * Either true or false.
1242 *
1243 * Note: Return true if there is register disconnect.
1244 **************************************************************************/
1245 static inline
1246 uint32_t qla2x00_isp_reg_stat(struct qla_hw_data *ha)
1247 {
1248 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1249 struct device_reg_82xx __iomem *reg82 = &ha->iobase->isp82;
1250
1251 if (IS_P3P_TYPE(ha))
1252 return ((RD_REG_DWORD(&reg82->host_int)) == ISP_REG_DISCONNECT);
1253 else
1254 return ((RD_REG_DWORD(&reg->host_status)) ==
1255 ISP_REG_DISCONNECT);
1256 }
1257
1258 /**************************************************************************
1259 * qla2xxx_eh_abort
1260 *
1261 * Description:
1262 * The abort function will abort the specified command.
1263 *
1264 * Input:
1265 * cmd = Linux SCSI command packet to be aborted.
1266 *
1267 * Returns:
1268 * Either SUCCESS or FAILED.
1269 *
1270 * Note:
1271 * Only return FAILED if command not returned by firmware.
1272 **************************************************************************/
1273 static int
1274 qla2xxx_eh_abort(struct scsi_cmnd *cmd)
1275 {
1276 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1277 srb_t *sp;
1278 int ret;
1279 unsigned int id;
1280 uint64_t lun;
1281 unsigned long flags;
1282 int rval, wait = 0;
1283 struct qla_hw_data *ha = vha->hw;
1284 struct qla_qpair *qpair;
1285
1286 if (qla2x00_isp_reg_stat(ha)) {
1287 ql_log(ql_log_info, vha, 0x8042,
1288 "PCI/Register disconnect, exiting.\n");
1289 return FAILED;
1290 }
1291
1292 ret = fc_block_scsi_eh(cmd);
1293 if (ret != 0)
1294 return ret;
1295 ret = SUCCESS;
1296
1297 sp = (srb_t *) CMD_SP(cmd);
1298 if (!sp)
1299 return SUCCESS;
1300
1301 qpair = sp->qpair;
1302 if (!qpair)
1303 return SUCCESS;
1304
1305 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1306 if (!CMD_SP(cmd)) {
1307 /* there's a chance an interrupt could clear
1308 the ptr as part of done & free */
1309 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1310 return SUCCESS;
1311 }
1312
1313 if (sp_get(sp)){
1314 /* ref_count is already 0 */
1315 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1316 return SUCCESS;
1317 }
1318 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1319
1320 id = cmd->device->id;
1321 lun = cmd->device->lun;
1322
1323 ql_dbg(ql_dbg_taskm, vha, 0x8002,
1324 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n",
1325 vha->host_no, id, lun, sp, cmd, sp->handle);
1326
1327 /* Get a reference to the sp and drop the lock.*/
1328
1329 rval = ha->isp_ops->abort_command(sp);
1330 if (rval) {
1331 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
1332 ret = SUCCESS;
1333 else
1334 ret = FAILED;
1335
1336 ql_dbg(ql_dbg_taskm, vha, 0x8003,
1337 "Abort command mbx failed cmd=%p, rval=%x.\n", cmd, rval);
1338 } else {
1339 ql_dbg(ql_dbg_taskm, vha, 0x8004,
1340 "Abort command mbx success cmd=%p.\n", cmd);
1341 wait = 1;
1342 }
1343
1344 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1345 /*
1346 * Clear the slot in the oustanding_cmds array if we can't find the
1347 * command to reclaim the resources.
1348 */
1349 if (rval == QLA_FUNCTION_PARAMETER_ERROR)
1350 vha->req->outstanding_cmds[sp->handle] = NULL;
1351
1352 /*
1353 * sp->done will do ref_count--
1354 * sp_get() took an extra count above
1355 */
1356 sp->done(sp, DID_RESET << 16);
1357
1358 /* Did the command return during mailbox execution? */
1359 if (ret == FAILED && !CMD_SP(cmd))
1360 ret = SUCCESS;
1361
1362 if (!CMD_SP(cmd))
1363 wait = 0;
1364
1365 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1366
1367 /* Wait for the command to be returned. */
1368 if (wait) {
1369 if (qla2x00_eh_wait_on_command(cmd) != QLA_SUCCESS) {
1370 ql_log(ql_log_warn, vha, 0x8006,
1371 "Abort handler timed out cmd=%p.\n", cmd);
1372 ret = FAILED;
1373 }
1374 }
1375
1376 ql_log(ql_log_info, vha, 0x801c,
1377 "Abort command issued nexus=%ld:%d:%llu -- %d %x.\n",
1378 vha->host_no, id, lun, wait, ret);
1379
1380 return ret;
1381 }
1382
1383 int
1384 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t,
1385 uint64_t l, enum nexus_wait_type type)
1386 {
1387 int cnt, match, status;
1388 unsigned long flags;
1389 struct qla_hw_data *ha = vha->hw;
1390 struct req_que *req;
1391 srb_t *sp;
1392 struct scsi_cmnd *cmd;
1393
1394 status = QLA_SUCCESS;
1395
1396 spin_lock_irqsave(&ha->hardware_lock, flags);
1397 req = vha->req;
1398 for (cnt = 1; status == QLA_SUCCESS &&
1399 cnt < req->num_outstanding_cmds; cnt++) {
1400 sp = req->outstanding_cmds[cnt];
1401 if (!sp)
1402 continue;
1403 if (sp->type != SRB_SCSI_CMD)
1404 continue;
1405 if (vha->vp_idx != sp->vha->vp_idx)
1406 continue;
1407 match = 0;
1408 cmd = GET_CMD_SP(sp);
1409 switch (type) {
1410 case WAIT_HOST:
1411 match = 1;
1412 break;
1413 case WAIT_TARGET:
1414 match = cmd->device->id == t;
1415 break;
1416 case WAIT_LUN:
1417 match = (cmd->device->id == t &&
1418 cmd->device->lun == l);
1419 break;
1420 }
1421 if (!match)
1422 continue;
1423
1424 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1425 status = qla2x00_eh_wait_on_command(cmd);
1426 spin_lock_irqsave(&ha->hardware_lock, flags);
1427 }
1428 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1429
1430 return status;
1431 }
1432
1433 static char *reset_errors[] = {
1434 "HBA not online",
1435 "HBA not ready",
1436 "Task management failed",
1437 "Waiting for command completions",
1438 };
1439
1440 static int
1441 __qla2xxx_eh_generic_reset(char *name, enum nexus_wait_type type,
1442 struct scsi_cmnd *cmd, int (*do_reset)(struct fc_port *, uint64_t, int))
1443 {
1444 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1445 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1446 int err;
1447
1448 if (!fcport) {
1449 return FAILED;
1450 }
1451
1452 err = fc_block_scsi_eh(cmd);
1453 if (err != 0)
1454 return err;
1455
1456 ql_log(ql_log_info, vha, 0x8009,
1457 "%s RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", name, vha->host_no,
1458 cmd->device->id, cmd->device->lun, cmd);
1459
1460 err = 0;
1461 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1462 ql_log(ql_log_warn, vha, 0x800a,
1463 "Wait for hba online failed for cmd=%p.\n", cmd);
1464 goto eh_reset_failed;
1465 }
1466 err = 2;
1467 if (do_reset(fcport, cmd->device->lun, cmd->request->cpu + 1)
1468 != QLA_SUCCESS) {
1469 ql_log(ql_log_warn, vha, 0x800c,
1470 "do_reset failed for cmd=%p.\n", cmd);
1471 goto eh_reset_failed;
1472 }
1473 err = 3;
1474 if (qla2x00_eh_wait_for_pending_commands(vha, cmd->device->id,
1475 cmd->device->lun, type) != QLA_SUCCESS) {
1476 ql_log(ql_log_warn, vha, 0x800d,
1477 "wait for pending cmds failed for cmd=%p.\n", cmd);
1478 goto eh_reset_failed;
1479 }
1480
1481 ql_log(ql_log_info, vha, 0x800e,
1482 "%s RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", name,
1483 vha->host_no, cmd->device->id, cmd->device->lun, cmd);
1484
1485 return SUCCESS;
1486
1487 eh_reset_failed:
1488 ql_log(ql_log_info, vha, 0x800f,
1489 "%s RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", name,
1490 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun,
1491 cmd);
1492 return FAILED;
1493 }
1494
1495 static int
1496 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd)
1497 {
1498 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1499 struct qla_hw_data *ha = vha->hw;
1500
1501 if (qla2x00_isp_reg_stat(ha)) {
1502 ql_log(ql_log_info, vha, 0x803e,
1503 "PCI/Register disconnect, exiting.\n");
1504 return FAILED;
1505 }
1506
1507 return __qla2xxx_eh_generic_reset("DEVICE", WAIT_LUN, cmd,
1508 ha->isp_ops->lun_reset);
1509 }
1510
1511 static int
1512 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd)
1513 {
1514 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1515 struct qla_hw_data *ha = vha->hw;
1516
1517 if (qla2x00_isp_reg_stat(ha)) {
1518 ql_log(ql_log_info, vha, 0x803f,
1519 "PCI/Register disconnect, exiting.\n");
1520 return FAILED;
1521 }
1522
1523 return __qla2xxx_eh_generic_reset("TARGET", WAIT_TARGET, cmd,
1524 ha->isp_ops->target_reset);
1525 }
1526
1527 /**************************************************************************
1528 * qla2xxx_eh_bus_reset
1529 *
1530 * Description:
1531 * The bus reset function will reset the bus and abort any executing
1532 * commands.
1533 *
1534 * Input:
1535 * cmd = Linux SCSI command packet of the command that cause the
1536 * bus reset.
1537 *
1538 * Returns:
1539 * SUCCESS/FAILURE (defined as macro in scsi.h).
1540 *
1541 **************************************************************************/
1542 static int
1543 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd)
1544 {
1545 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1546 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata;
1547 int ret = FAILED;
1548 unsigned int id;
1549 uint64_t lun;
1550 struct qla_hw_data *ha = vha->hw;
1551
1552 if (qla2x00_isp_reg_stat(ha)) {
1553 ql_log(ql_log_info, vha, 0x8040,
1554 "PCI/Register disconnect, exiting.\n");
1555 return FAILED;
1556 }
1557
1558 id = cmd->device->id;
1559 lun = cmd->device->lun;
1560
1561 if (!fcport) {
1562 return ret;
1563 }
1564
1565 ret = fc_block_scsi_eh(cmd);
1566 if (ret != 0)
1567 return ret;
1568 ret = FAILED;
1569
1570 ql_log(ql_log_info, vha, 0x8012,
1571 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1572
1573 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1574 ql_log(ql_log_fatal, vha, 0x8013,
1575 "Wait for hba online failed board disabled.\n");
1576 goto eh_bus_reset_done;
1577 }
1578
1579 if (qla2x00_loop_reset(vha) == QLA_SUCCESS)
1580 ret = SUCCESS;
1581
1582 if (ret == FAILED)
1583 goto eh_bus_reset_done;
1584
1585 /* Flush outstanding commands. */
1586 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) !=
1587 QLA_SUCCESS) {
1588 ql_log(ql_log_warn, vha, 0x8014,
1589 "Wait for pending commands failed.\n");
1590 ret = FAILED;
1591 }
1592
1593 eh_bus_reset_done:
1594 ql_log(ql_log_warn, vha, 0x802b,
1595 "BUS RESET %s nexus=%ld:%d:%llu.\n",
1596 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1597
1598 return ret;
1599 }
1600
1601 /**************************************************************************
1602 * qla2xxx_eh_host_reset
1603 *
1604 * Description:
1605 * The reset function will reset the Adapter.
1606 *
1607 * Input:
1608 * cmd = Linux SCSI command packet of the command that cause the
1609 * adapter reset.
1610 *
1611 * Returns:
1612 * Either SUCCESS or FAILED.
1613 *
1614 * Note:
1615 **************************************************************************/
1616 static int
1617 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd)
1618 {
1619 scsi_qla_host_t *vha = shost_priv(cmd->device->host);
1620 struct qla_hw_data *ha = vha->hw;
1621 int ret = FAILED;
1622 unsigned int id;
1623 uint64_t lun;
1624 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
1625
1626 if (qla2x00_isp_reg_stat(ha)) {
1627 ql_log(ql_log_info, vha, 0x8041,
1628 "PCI/Register disconnect, exiting.\n");
1629 schedule_work(&ha->board_disable);
1630 return SUCCESS;
1631 }
1632
1633 id = cmd->device->id;
1634 lun = cmd->device->lun;
1635
1636 ql_log(ql_log_info, vha, 0x8018,
1637 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun);
1638
1639 /*
1640 * No point in issuing another reset if one is active. Also do not
1641 * attempt a reset if we are updating flash.
1642 */
1643 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING)
1644 goto eh_host_reset_lock;
1645
1646 if (vha != base_vha) {
1647 if (qla2x00_vp_abort_isp(vha))
1648 goto eh_host_reset_lock;
1649 } else {
1650 if (IS_P3P_TYPE(vha->hw)) {
1651 if (!qla82xx_fcoe_ctx_reset(vha)) {
1652 /* Ctx reset success */
1653 ret = SUCCESS;
1654 goto eh_host_reset_lock;
1655 }
1656 /* fall thru if ctx reset failed */
1657 }
1658 if (ha->wq)
1659 flush_workqueue(ha->wq);
1660
1661 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1662 if (ha->isp_ops->abort_isp(base_vha)) {
1663 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1664 /* failed. schedule dpc to try */
1665 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
1666
1667 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) {
1668 ql_log(ql_log_warn, vha, 0x802a,
1669 "wait for hba online failed.\n");
1670 goto eh_host_reset_lock;
1671 }
1672 }
1673 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
1674 }
1675
1676 /* Waiting for command to be returned to OS.*/
1677 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) ==
1678 QLA_SUCCESS)
1679 ret = SUCCESS;
1680
1681 eh_host_reset_lock:
1682 ql_log(ql_log_info, vha, 0x8017,
1683 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n",
1684 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun);
1685
1686 return ret;
1687 }
1688
1689 /*
1690 * qla2x00_loop_reset
1691 * Issue loop reset.
1692 *
1693 * Input:
1694 * ha = adapter block pointer.
1695 *
1696 * Returns:
1697 * 0 = success
1698 */
1699 int
1700 qla2x00_loop_reset(scsi_qla_host_t *vha)
1701 {
1702 int ret;
1703 struct fc_port *fcport;
1704 struct qla_hw_data *ha = vha->hw;
1705
1706 if (IS_QLAFX00(ha)) {
1707 return qlafx00_loop_reset(vha);
1708 }
1709
1710 if (ql2xtargetreset == 1 && ha->flags.enable_target_reset) {
1711 list_for_each_entry(fcport, &vha->vp_fcports, list) {
1712 if (fcport->port_type != FCT_TARGET)
1713 continue;
1714
1715 ret = ha->isp_ops->target_reset(fcport, 0, 0);
1716 if (ret != QLA_SUCCESS) {
1717 ql_dbg(ql_dbg_taskm, vha, 0x802c,
1718 "Bus Reset failed: Reset=%d "
1719 "d_id=%x.\n", ret, fcport->d_id.b24);
1720 }
1721 }
1722 }
1723
1724
1725 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) {
1726 atomic_set(&vha->loop_state, LOOP_DOWN);
1727 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
1728 qla2x00_mark_all_devices_lost(vha, 0);
1729 ret = qla2x00_full_login_lip(vha);
1730 if (ret != QLA_SUCCESS) {
1731 ql_dbg(ql_dbg_taskm, vha, 0x802d,
1732 "full_login_lip=%d.\n", ret);
1733 }
1734 }
1735
1736 if (ha->flags.enable_lip_reset) {
1737 ret = qla2x00_lip_reset(vha);
1738 if (ret != QLA_SUCCESS)
1739 ql_dbg(ql_dbg_taskm, vha, 0x802e,
1740 "lip_reset failed (%d).\n", ret);
1741 }
1742
1743 /* Issue marker command only when we are going to start the I/O */
1744 vha->marker_needed = 1;
1745
1746 return QLA_SUCCESS;
1747 }
1748
1749 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res,
1750 unsigned long *flags)
1751 __releases(qp->qp_lock_ptr)
1752 __acquires(qp->qp_lock_ptr)
1753 {
1754 scsi_qla_host_t *vha = qp->vha;
1755 struct qla_hw_data *ha = vha->hw;
1756
1757 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS) {
1758 if (!sp_get(sp)) {
1759 /* got sp */
1760 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1761 qla_nvme_abort(ha, sp, res);
1762 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1763 }
1764 } else if (GET_CMD_SP(sp) && !ha->flags.eeh_busy &&
1765 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) &&
1766 !qla2x00_isp_reg_stat(ha) && sp->type == SRB_SCSI_CMD) {
1767 /*
1768 * Don't abort commands in adapter during EEH recovery as it's
1769 * not accessible/responding.
1770 *
1771 * Get a reference to the sp and drop the lock. The reference
1772 * ensures this sp->done() call and not the call in
1773 * qla2xxx_eh_abort() ends the SCSI cmd (with result 'res').
1774 */
1775 if (!sp_get(sp)) {
1776 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags);
1777 qla2xxx_eh_abort(GET_CMD_SP(sp));
1778 spin_lock_irqsave(qp->qp_lock_ptr, *flags);
1779 }
1780 }
1781 sp->done(sp, res);
1782 }
1783
1784 static void
1785 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res)
1786 {
1787 int cnt;
1788 unsigned long flags;
1789 srb_t *sp;
1790 scsi_qla_host_t *vha = qp->vha;
1791 struct qla_hw_data *ha = vha->hw;
1792 struct req_que *req;
1793 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt;
1794 struct qla_tgt_cmd *cmd;
1795
1796 if (!ha->req_q_map)
1797 return;
1798 spin_lock_irqsave(qp->qp_lock_ptr, flags);
1799 req = qp->req;
1800 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
1801 sp = req->outstanding_cmds[cnt];
1802 if (sp) {
1803 req->outstanding_cmds[cnt] = NULL;
1804 switch (sp->cmd_type) {
1805 case TYPE_SRB:
1806 qla2x00_abort_srb(qp, sp, res, &flags);
1807 break;
1808 case TYPE_TGT_CMD:
1809 if (!vha->hw->tgt.tgt_ops || !tgt ||
1810 qla_ini_mode_enabled(vha)) {
1811 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003,
1812 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n",
1813 vha->dpc_flags);
1814 continue;
1815 }
1816 cmd = (struct qla_tgt_cmd *)sp;
1817 qlt_abort_cmd_on_host_reset(cmd->vha, cmd);
1818 break;
1819 case TYPE_TGT_TMCMD:
1820 /*
1821 * Currently, only ABTS response gets on the
1822 * outstanding_cmds[]
1823 */
1824 ha->tgt.tgt_ops->free_mcmd(
1825 (struct qla_tgt_mgmt_cmd *)sp);
1826 break;
1827 default:
1828 break;
1829 }
1830 }
1831 }
1832 spin_unlock_irqrestore(qp->qp_lock_ptr, flags);
1833 }
1834
1835 void
1836 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res)
1837 {
1838 int que;
1839 struct qla_hw_data *ha = vha->hw;
1840
1841 __qla2x00_abort_all_cmds(ha->base_qpair, res);
1842
1843 for (que = 0; que < ha->max_qpairs; que++) {
1844 if (!ha->queue_pair_map[que])
1845 continue;
1846
1847 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res);
1848 }
1849 }
1850
1851 static int
1852 qla2xxx_slave_alloc(struct scsi_device *sdev)
1853 {
1854 struct fc_rport *rport = starget_to_rport(scsi_target(sdev));
1855
1856 if (!rport || fc_remote_port_chkready(rport))
1857 return -ENXIO;
1858
1859 sdev->hostdata = *(fc_port_t **)rport->dd_data;
1860
1861 return 0;
1862 }
1863
1864 static int
1865 qla2xxx_slave_configure(struct scsi_device *sdev)
1866 {
1867 scsi_qla_host_t *vha = shost_priv(sdev->host);
1868 struct req_que *req = vha->req;
1869
1870 if (IS_T10_PI_CAPABLE(vha->hw))
1871 blk_queue_update_dma_alignment(sdev->request_queue, 0x7);
1872
1873 scsi_change_queue_depth(sdev, req->max_q_depth);
1874 return 0;
1875 }
1876
1877 static void
1878 qla2xxx_slave_destroy(struct scsi_device *sdev)
1879 {
1880 sdev->hostdata = NULL;
1881 }
1882
1883 /**
1884 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method.
1885 * @ha: HA context
1886 *
1887 * At exit, the @ha's flags.enable_64bit_addressing set to indicated
1888 * supported addressing method.
1889 */
1890 static void
1891 qla2x00_config_dma_addressing(struct qla_hw_data *ha)
1892 {
1893 /* Assume a 32bit DMA mask. */
1894 ha->flags.enable_64bit_addressing = 0;
1895
1896 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) {
1897 /* Any upper-dword bits set? */
1898 if (MSD(dma_get_required_mask(&ha->pdev->dev)) &&
1899 !pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(64))) {
1900 /* Ok, a 64bit DMA mask is applicable. */
1901 ha->flags.enable_64bit_addressing = 1;
1902 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64;
1903 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64;
1904 return;
1905 }
1906 }
1907
1908 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32));
1909 pci_set_consistent_dma_mask(ha->pdev, DMA_BIT_MASK(32));
1910 }
1911
1912 static void
1913 qla2x00_enable_intrs(struct qla_hw_data *ha)
1914 {
1915 unsigned long flags = 0;
1916 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1917
1918 spin_lock_irqsave(&ha->hardware_lock, flags);
1919 ha->interrupts_on = 1;
1920 /* enable risc and host interrupts */
1921 WRT_REG_WORD(&reg->ictrl, ICR_EN_INT | ICR_EN_RISC);
1922 RD_REG_WORD(&reg->ictrl);
1923 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1924
1925 }
1926
1927 static void
1928 qla2x00_disable_intrs(struct qla_hw_data *ha)
1929 {
1930 unsigned long flags = 0;
1931 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
1932
1933 spin_lock_irqsave(&ha->hardware_lock, flags);
1934 ha->interrupts_on = 0;
1935 /* disable risc and host interrupts */
1936 WRT_REG_WORD(&reg->ictrl, 0);
1937 RD_REG_WORD(&reg->ictrl);
1938 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1939 }
1940
1941 static void
1942 qla24xx_enable_intrs(struct qla_hw_data *ha)
1943 {
1944 unsigned long flags = 0;
1945 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1946
1947 spin_lock_irqsave(&ha->hardware_lock, flags);
1948 ha->interrupts_on = 1;
1949 WRT_REG_DWORD(&reg->ictrl, ICRX_EN_RISC_INT);
1950 RD_REG_DWORD(&reg->ictrl);
1951 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1952 }
1953
1954 static void
1955 qla24xx_disable_intrs(struct qla_hw_data *ha)
1956 {
1957 unsigned long flags = 0;
1958 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
1959
1960 if (IS_NOPOLLING_TYPE(ha))
1961 return;
1962 spin_lock_irqsave(&ha->hardware_lock, flags);
1963 ha->interrupts_on = 0;
1964 WRT_REG_DWORD(&reg->ictrl, 0);
1965 RD_REG_DWORD(&reg->ictrl);
1966 spin_unlock_irqrestore(&ha->hardware_lock, flags);
1967 }
1968
1969 static int
1970 qla2x00_iospace_config(struct qla_hw_data *ha)
1971 {
1972 resource_size_t pio;
1973 uint16_t msix;
1974
1975 if (pci_request_selected_regions(ha->pdev, ha->bars,
1976 QLA2XXX_DRIVER_NAME)) {
1977 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011,
1978 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
1979 pci_name(ha->pdev));
1980 goto iospace_error_exit;
1981 }
1982 if (!(ha->bars & 1))
1983 goto skip_pio;
1984
1985 /* We only need PIO for Flash operations on ISP2312 v2 chips. */
1986 pio = pci_resource_start(ha->pdev, 0);
1987 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) {
1988 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
1989 ql_log_pci(ql_log_warn, ha->pdev, 0x0012,
1990 "Invalid pci I/O region size (%s).\n",
1991 pci_name(ha->pdev));
1992 pio = 0;
1993 }
1994 } else {
1995 ql_log_pci(ql_log_warn, ha->pdev, 0x0013,
1996 "Region #0 no a PIO resource (%s).\n",
1997 pci_name(ha->pdev));
1998 pio = 0;
1999 }
2000 ha->pio_address = pio;
2001 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014,
2002 "PIO address=%llu.\n",
2003 (unsigned long long)ha->pio_address);
2004
2005 skip_pio:
2006 /* Use MMIO operations for all accesses. */
2007 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) {
2008 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015,
2009 "Region #1 not an MMIO resource (%s), aborting.\n",
2010 pci_name(ha->pdev));
2011 goto iospace_error_exit;
2012 }
2013 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) {
2014 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016,
2015 "Invalid PCI mem region size (%s), aborting.\n",
2016 pci_name(ha->pdev));
2017 goto iospace_error_exit;
2018 }
2019
2020 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN);
2021 if (!ha->iobase) {
2022 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017,
2023 "Cannot remap MMIO (%s), aborting.\n",
2024 pci_name(ha->pdev));
2025 goto iospace_error_exit;
2026 }
2027
2028 /* Determine queue resources */
2029 ha->max_req_queues = ha->max_rsp_queues = 1;
2030 ha->msix_count = QLA_BASE_VECTORS;
2031 if (!ql2xmqsupport || !ql2xnvmeenable ||
2032 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha)))
2033 goto mqiobase_exit;
2034
2035 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3),
2036 pci_resource_len(ha->pdev, 3));
2037 if (ha->mqiobase) {
2038 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018,
2039 "MQIO Base=%p.\n", ha->mqiobase);
2040 /* Read MSIX vector size of the board */
2041 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix);
2042 ha->msix_count = msix + 1;
2043 /* Max queues are bounded by available msix vectors */
2044 /* MB interrupt uses 1 vector */
2045 ha->max_req_queues = ha->msix_count - 1;
2046 ha->max_rsp_queues = ha->max_req_queues;
2047 /* Queue pairs is the max value minus the base queue pair */
2048 ha->max_qpairs = ha->max_rsp_queues - 1;
2049 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188,
2050 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2051
2052 ql_log_pci(ql_log_info, ha->pdev, 0x001a,
2053 "MSI-X vector count: %d.\n", ha->msix_count);
2054 } else
2055 ql_log_pci(ql_log_info, ha->pdev, 0x001b,
2056 "BAR 3 not enabled.\n");
2057
2058 mqiobase_exit:
2059 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c,
2060 "MSIX Count: %d.\n", ha->msix_count);
2061 return (0);
2062
2063 iospace_error_exit:
2064 return (-ENOMEM);
2065 }
2066
2067
2068 static int
2069 qla83xx_iospace_config(struct qla_hw_data *ha)
2070 {
2071 uint16_t msix;
2072
2073 if (pci_request_selected_regions(ha->pdev, ha->bars,
2074 QLA2XXX_DRIVER_NAME)) {
2075 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117,
2076 "Failed to reserve PIO/MMIO regions (%s), aborting.\n",
2077 pci_name(ha->pdev));
2078
2079 goto iospace_error_exit;
2080 }
2081
2082 /* Use MMIO operations for all accesses. */
2083 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
2084 ql_log_pci(ql_log_warn, ha->pdev, 0x0118,
2085 "Invalid pci I/O region size (%s).\n",
2086 pci_name(ha->pdev));
2087 goto iospace_error_exit;
2088 }
2089 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) {
2090 ql_log_pci(ql_log_warn, ha->pdev, 0x0119,
2091 "Invalid PCI mem region size (%s), aborting\n",
2092 pci_name(ha->pdev));
2093 goto iospace_error_exit;
2094 }
2095
2096 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN);
2097 if (!ha->iobase) {
2098 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a,
2099 "Cannot remap MMIO (%s), aborting.\n",
2100 pci_name(ha->pdev));
2101 goto iospace_error_exit;
2102 }
2103
2104 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */
2105 /* 83XX 26XX always use MQ type access for queues
2106 * - mbar 2, a.k.a region 4 */
2107 ha->max_req_queues = ha->max_rsp_queues = 1;
2108 ha->msix_count = QLA_BASE_VECTORS;
2109 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4),
2110 pci_resource_len(ha->pdev, 4));
2111
2112 if (!ha->mqiobase) {
2113 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d,
2114 "BAR2/region4 not enabled\n");
2115 goto mqiobase_exit;
2116 }
2117
2118 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2),
2119 pci_resource_len(ha->pdev, 2));
2120 if (ha->msixbase) {
2121 /* Read MSIX vector size of the board */
2122 pci_read_config_word(ha->pdev,
2123 QLA_83XX_PCI_MSIX_CONTROL, &msix);
2124 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1;
2125 /*
2126 * By default, driver uses at least two msix vectors
2127 * (default & rspq)
2128 */
2129 if (ql2xmqsupport || ql2xnvmeenable) {
2130 /* MB interrupt uses 1 vector */
2131 ha->max_req_queues = ha->msix_count - 1;
2132
2133 /* ATIOQ needs 1 vector. That's 1 less QPair */
2134 if (QLA_TGT_MODE_ENABLED())
2135 ha->max_req_queues--;
2136
2137 ha->max_rsp_queues = ha->max_req_queues;
2138
2139 /* Queue pairs is the max value minus
2140 * the base queue pair */
2141 ha->max_qpairs = ha->max_req_queues - 1;
2142 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3,
2143 "Max no of queues pairs: %d.\n", ha->max_qpairs);
2144 }
2145 ql_log_pci(ql_log_info, ha->pdev, 0x011c,
2146 "MSI-X vector count: %d.\n", ha->msix_count);
2147 } else
2148 ql_log_pci(ql_log_info, ha->pdev, 0x011e,
2149 "BAR 1 not enabled.\n");
2150
2151 mqiobase_exit:
2152 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f,
2153 "MSIX Count: %d.\n", ha->msix_count);
2154 return 0;
2155
2156 iospace_error_exit:
2157 return -ENOMEM;
2158 }
2159
2160 static struct isp_operations qla2100_isp_ops = {
2161 .pci_config = qla2100_pci_config,
2162 .reset_chip = qla2x00_reset_chip,
2163 .chip_diag = qla2x00_chip_diag,
2164 .config_rings = qla2x00_config_rings,
2165 .reset_adapter = qla2x00_reset_adapter,
2166 .nvram_config = qla2x00_nvram_config,
2167 .update_fw_options = qla2x00_update_fw_options,
2168 .load_risc = qla2x00_load_risc,
2169 .pci_info_str = qla2x00_pci_info_str,
2170 .fw_version_str = qla2x00_fw_version_str,
2171 .intr_handler = qla2100_intr_handler,
2172 .enable_intrs = qla2x00_enable_intrs,
2173 .disable_intrs = qla2x00_disable_intrs,
2174 .abort_command = qla2x00_abort_command,
2175 .target_reset = qla2x00_abort_target,
2176 .lun_reset = qla2x00_lun_reset,
2177 .fabric_login = qla2x00_login_fabric,
2178 .fabric_logout = qla2x00_fabric_logout,
2179 .calc_req_entries = qla2x00_calc_iocbs_32,
2180 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2181 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2182 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2183 .read_nvram = qla2x00_read_nvram_data,
2184 .write_nvram = qla2x00_write_nvram_data,
2185 .fw_dump = qla2100_fw_dump,
2186 .beacon_on = NULL,
2187 .beacon_off = NULL,
2188 .beacon_blink = NULL,
2189 .read_optrom = qla2x00_read_optrom_data,
2190 .write_optrom = qla2x00_write_optrom_data,
2191 .get_flash_version = qla2x00_get_flash_version,
2192 .start_scsi = qla2x00_start_scsi,
2193 .start_scsi_mq = NULL,
2194 .abort_isp = qla2x00_abort_isp,
2195 .iospace_config = qla2x00_iospace_config,
2196 .initialize_adapter = qla2x00_initialize_adapter,
2197 };
2198
2199 static struct isp_operations qla2300_isp_ops = {
2200 .pci_config = qla2300_pci_config,
2201 .reset_chip = qla2x00_reset_chip,
2202 .chip_diag = qla2x00_chip_diag,
2203 .config_rings = qla2x00_config_rings,
2204 .reset_adapter = qla2x00_reset_adapter,
2205 .nvram_config = qla2x00_nvram_config,
2206 .update_fw_options = qla2x00_update_fw_options,
2207 .load_risc = qla2x00_load_risc,
2208 .pci_info_str = qla2x00_pci_info_str,
2209 .fw_version_str = qla2x00_fw_version_str,
2210 .intr_handler = qla2300_intr_handler,
2211 .enable_intrs = qla2x00_enable_intrs,
2212 .disable_intrs = qla2x00_disable_intrs,
2213 .abort_command = qla2x00_abort_command,
2214 .target_reset = qla2x00_abort_target,
2215 .lun_reset = qla2x00_lun_reset,
2216 .fabric_login = qla2x00_login_fabric,
2217 .fabric_logout = qla2x00_fabric_logout,
2218 .calc_req_entries = qla2x00_calc_iocbs_32,
2219 .build_iocbs = qla2x00_build_scsi_iocbs_32,
2220 .prep_ms_iocb = qla2x00_prep_ms_iocb,
2221 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb,
2222 .read_nvram = qla2x00_read_nvram_data,
2223 .write_nvram = qla2x00_write_nvram_data,
2224 .fw_dump = qla2300_fw_dump,
2225 .beacon_on = qla2x00_beacon_on,
2226 .beacon_off = qla2x00_beacon_off,
2227 .beacon_blink = qla2x00_beacon_blink,
2228 .read_optrom = qla2x00_read_optrom_data,
2229 .write_optrom = qla2x00_write_optrom_data,
2230 .get_flash_version = qla2x00_get_flash_version,
2231 .start_scsi = qla2x00_start_scsi,
2232 .start_scsi_mq = NULL,
2233 .abort_isp = qla2x00_abort_isp,
2234 .iospace_config = qla2x00_iospace_config,
2235 .initialize_adapter = qla2x00_initialize_adapter,
2236 };
2237
2238 static struct isp_operations qla24xx_isp_ops = {
2239 .pci_config = qla24xx_pci_config,
2240 .reset_chip = qla24xx_reset_chip,
2241 .chip_diag = qla24xx_chip_diag,
2242 .config_rings = qla24xx_config_rings,
2243 .reset_adapter = qla24xx_reset_adapter,
2244 .nvram_config = qla24xx_nvram_config,
2245 .update_fw_options = qla24xx_update_fw_options,
2246 .load_risc = qla24xx_load_risc,
2247 .pci_info_str = qla24xx_pci_info_str,
2248 .fw_version_str = qla24xx_fw_version_str,
2249 .intr_handler = qla24xx_intr_handler,
2250 .enable_intrs = qla24xx_enable_intrs,
2251 .disable_intrs = qla24xx_disable_intrs,
2252 .abort_command = qla24xx_abort_command,
2253 .target_reset = qla24xx_abort_target,
2254 .lun_reset = qla24xx_lun_reset,
2255 .fabric_login = qla24xx_login_fabric,
2256 .fabric_logout = qla24xx_fabric_logout,
2257 .calc_req_entries = NULL,
2258 .build_iocbs = NULL,
2259 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2260 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2261 .read_nvram = qla24xx_read_nvram_data,
2262 .write_nvram = qla24xx_write_nvram_data,
2263 .fw_dump = qla24xx_fw_dump,
2264 .beacon_on = qla24xx_beacon_on,
2265 .beacon_off = qla24xx_beacon_off,
2266 .beacon_blink = qla24xx_beacon_blink,
2267 .read_optrom = qla24xx_read_optrom_data,
2268 .write_optrom = qla24xx_write_optrom_data,
2269 .get_flash_version = qla24xx_get_flash_version,
2270 .start_scsi = qla24xx_start_scsi,
2271 .start_scsi_mq = NULL,
2272 .abort_isp = qla2x00_abort_isp,
2273 .iospace_config = qla2x00_iospace_config,
2274 .initialize_adapter = qla2x00_initialize_adapter,
2275 };
2276
2277 static struct isp_operations qla25xx_isp_ops = {
2278 .pci_config = qla25xx_pci_config,
2279 .reset_chip = qla24xx_reset_chip,
2280 .chip_diag = qla24xx_chip_diag,
2281 .config_rings = qla24xx_config_rings,
2282 .reset_adapter = qla24xx_reset_adapter,
2283 .nvram_config = qla24xx_nvram_config,
2284 .update_fw_options = qla24xx_update_fw_options,
2285 .load_risc = qla24xx_load_risc,
2286 .pci_info_str = qla24xx_pci_info_str,
2287 .fw_version_str = qla24xx_fw_version_str,
2288 .intr_handler = qla24xx_intr_handler,
2289 .enable_intrs = qla24xx_enable_intrs,
2290 .disable_intrs = qla24xx_disable_intrs,
2291 .abort_command = qla24xx_abort_command,
2292 .target_reset = qla24xx_abort_target,
2293 .lun_reset = qla24xx_lun_reset,
2294 .fabric_login = qla24xx_login_fabric,
2295 .fabric_logout = qla24xx_fabric_logout,
2296 .calc_req_entries = NULL,
2297 .build_iocbs = NULL,
2298 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2299 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2300 .read_nvram = qla25xx_read_nvram_data,
2301 .write_nvram = qla25xx_write_nvram_data,
2302 .fw_dump = qla25xx_fw_dump,
2303 .beacon_on = qla24xx_beacon_on,
2304 .beacon_off = qla24xx_beacon_off,
2305 .beacon_blink = qla24xx_beacon_blink,
2306 .read_optrom = qla25xx_read_optrom_data,
2307 .write_optrom = qla24xx_write_optrom_data,
2308 .get_flash_version = qla24xx_get_flash_version,
2309 .start_scsi = qla24xx_dif_start_scsi,
2310 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2311 .abort_isp = qla2x00_abort_isp,
2312 .iospace_config = qla2x00_iospace_config,
2313 .initialize_adapter = qla2x00_initialize_adapter,
2314 };
2315
2316 static struct isp_operations qla81xx_isp_ops = {
2317 .pci_config = qla25xx_pci_config,
2318 .reset_chip = qla24xx_reset_chip,
2319 .chip_diag = qla24xx_chip_diag,
2320 .config_rings = qla24xx_config_rings,
2321 .reset_adapter = qla24xx_reset_adapter,
2322 .nvram_config = qla81xx_nvram_config,
2323 .update_fw_options = qla81xx_update_fw_options,
2324 .load_risc = qla81xx_load_risc,
2325 .pci_info_str = qla24xx_pci_info_str,
2326 .fw_version_str = qla24xx_fw_version_str,
2327 .intr_handler = qla24xx_intr_handler,
2328 .enable_intrs = qla24xx_enable_intrs,
2329 .disable_intrs = qla24xx_disable_intrs,
2330 .abort_command = qla24xx_abort_command,
2331 .target_reset = qla24xx_abort_target,
2332 .lun_reset = qla24xx_lun_reset,
2333 .fabric_login = qla24xx_login_fabric,
2334 .fabric_logout = qla24xx_fabric_logout,
2335 .calc_req_entries = NULL,
2336 .build_iocbs = NULL,
2337 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2338 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2339 .read_nvram = NULL,
2340 .write_nvram = NULL,
2341 .fw_dump = qla81xx_fw_dump,
2342 .beacon_on = qla24xx_beacon_on,
2343 .beacon_off = qla24xx_beacon_off,
2344 .beacon_blink = qla83xx_beacon_blink,
2345 .read_optrom = qla25xx_read_optrom_data,
2346 .write_optrom = qla24xx_write_optrom_data,
2347 .get_flash_version = qla24xx_get_flash_version,
2348 .start_scsi = qla24xx_dif_start_scsi,
2349 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2350 .abort_isp = qla2x00_abort_isp,
2351 .iospace_config = qla2x00_iospace_config,
2352 .initialize_adapter = qla2x00_initialize_adapter,
2353 };
2354
2355 static struct isp_operations qla82xx_isp_ops = {
2356 .pci_config = qla82xx_pci_config,
2357 .reset_chip = qla82xx_reset_chip,
2358 .chip_diag = qla24xx_chip_diag,
2359 .config_rings = qla82xx_config_rings,
2360 .reset_adapter = qla24xx_reset_adapter,
2361 .nvram_config = qla81xx_nvram_config,
2362 .update_fw_options = qla24xx_update_fw_options,
2363 .load_risc = qla82xx_load_risc,
2364 .pci_info_str = qla24xx_pci_info_str,
2365 .fw_version_str = qla24xx_fw_version_str,
2366 .intr_handler = qla82xx_intr_handler,
2367 .enable_intrs = qla82xx_enable_intrs,
2368 .disable_intrs = qla82xx_disable_intrs,
2369 .abort_command = qla24xx_abort_command,
2370 .target_reset = qla24xx_abort_target,
2371 .lun_reset = qla24xx_lun_reset,
2372 .fabric_login = qla24xx_login_fabric,
2373 .fabric_logout = qla24xx_fabric_logout,
2374 .calc_req_entries = NULL,
2375 .build_iocbs = NULL,
2376 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2377 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2378 .read_nvram = qla24xx_read_nvram_data,
2379 .write_nvram = qla24xx_write_nvram_data,
2380 .fw_dump = qla82xx_fw_dump,
2381 .beacon_on = qla82xx_beacon_on,
2382 .beacon_off = qla82xx_beacon_off,
2383 .beacon_blink = NULL,
2384 .read_optrom = qla82xx_read_optrom_data,
2385 .write_optrom = qla82xx_write_optrom_data,
2386 .get_flash_version = qla82xx_get_flash_version,
2387 .start_scsi = qla82xx_start_scsi,
2388 .start_scsi_mq = NULL,
2389 .abort_isp = qla82xx_abort_isp,
2390 .iospace_config = qla82xx_iospace_config,
2391 .initialize_adapter = qla2x00_initialize_adapter,
2392 };
2393
2394 static struct isp_operations qla8044_isp_ops = {
2395 .pci_config = qla82xx_pci_config,
2396 .reset_chip = qla82xx_reset_chip,
2397 .chip_diag = qla24xx_chip_diag,
2398 .config_rings = qla82xx_config_rings,
2399 .reset_adapter = qla24xx_reset_adapter,
2400 .nvram_config = qla81xx_nvram_config,
2401 .update_fw_options = qla24xx_update_fw_options,
2402 .load_risc = qla82xx_load_risc,
2403 .pci_info_str = qla24xx_pci_info_str,
2404 .fw_version_str = qla24xx_fw_version_str,
2405 .intr_handler = qla8044_intr_handler,
2406 .enable_intrs = qla82xx_enable_intrs,
2407 .disable_intrs = qla82xx_disable_intrs,
2408 .abort_command = qla24xx_abort_command,
2409 .target_reset = qla24xx_abort_target,
2410 .lun_reset = qla24xx_lun_reset,
2411 .fabric_login = qla24xx_login_fabric,
2412 .fabric_logout = qla24xx_fabric_logout,
2413 .calc_req_entries = NULL,
2414 .build_iocbs = NULL,
2415 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2416 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2417 .read_nvram = NULL,
2418 .write_nvram = NULL,
2419 .fw_dump = qla8044_fw_dump,
2420 .beacon_on = qla82xx_beacon_on,
2421 .beacon_off = qla82xx_beacon_off,
2422 .beacon_blink = NULL,
2423 .read_optrom = qla8044_read_optrom_data,
2424 .write_optrom = qla8044_write_optrom_data,
2425 .get_flash_version = qla82xx_get_flash_version,
2426 .start_scsi = qla82xx_start_scsi,
2427 .start_scsi_mq = NULL,
2428 .abort_isp = qla8044_abort_isp,
2429 .iospace_config = qla82xx_iospace_config,
2430 .initialize_adapter = qla2x00_initialize_adapter,
2431 };
2432
2433 static struct isp_operations qla83xx_isp_ops = {
2434 .pci_config = qla25xx_pci_config,
2435 .reset_chip = qla24xx_reset_chip,
2436 .chip_diag = qla24xx_chip_diag,
2437 .config_rings = qla24xx_config_rings,
2438 .reset_adapter = qla24xx_reset_adapter,
2439 .nvram_config = qla81xx_nvram_config,
2440 .update_fw_options = qla81xx_update_fw_options,
2441 .load_risc = qla81xx_load_risc,
2442 .pci_info_str = qla24xx_pci_info_str,
2443 .fw_version_str = qla24xx_fw_version_str,
2444 .intr_handler = qla24xx_intr_handler,
2445 .enable_intrs = qla24xx_enable_intrs,
2446 .disable_intrs = qla24xx_disable_intrs,
2447 .abort_command = qla24xx_abort_command,
2448 .target_reset = qla24xx_abort_target,
2449 .lun_reset = qla24xx_lun_reset,
2450 .fabric_login = qla24xx_login_fabric,
2451 .fabric_logout = qla24xx_fabric_logout,
2452 .calc_req_entries = NULL,
2453 .build_iocbs = NULL,
2454 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2455 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2456 .read_nvram = NULL,
2457 .write_nvram = NULL,
2458 .fw_dump = qla83xx_fw_dump,
2459 .beacon_on = qla24xx_beacon_on,
2460 .beacon_off = qla24xx_beacon_off,
2461 .beacon_blink = qla83xx_beacon_blink,
2462 .read_optrom = qla25xx_read_optrom_data,
2463 .write_optrom = qla24xx_write_optrom_data,
2464 .get_flash_version = qla24xx_get_flash_version,
2465 .start_scsi = qla24xx_dif_start_scsi,
2466 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2467 .abort_isp = qla2x00_abort_isp,
2468 .iospace_config = qla83xx_iospace_config,
2469 .initialize_adapter = qla2x00_initialize_adapter,
2470 };
2471
2472 static struct isp_operations qlafx00_isp_ops = {
2473 .pci_config = qlafx00_pci_config,
2474 .reset_chip = qlafx00_soft_reset,
2475 .chip_diag = qlafx00_chip_diag,
2476 .config_rings = qlafx00_config_rings,
2477 .reset_adapter = qlafx00_soft_reset,
2478 .nvram_config = NULL,
2479 .update_fw_options = NULL,
2480 .load_risc = NULL,
2481 .pci_info_str = qlafx00_pci_info_str,
2482 .fw_version_str = qlafx00_fw_version_str,
2483 .intr_handler = qlafx00_intr_handler,
2484 .enable_intrs = qlafx00_enable_intrs,
2485 .disable_intrs = qlafx00_disable_intrs,
2486 .abort_command = qla24xx_async_abort_command,
2487 .target_reset = qlafx00_abort_target,
2488 .lun_reset = qlafx00_lun_reset,
2489 .fabric_login = NULL,
2490 .fabric_logout = NULL,
2491 .calc_req_entries = NULL,
2492 .build_iocbs = NULL,
2493 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2494 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2495 .read_nvram = qla24xx_read_nvram_data,
2496 .write_nvram = qla24xx_write_nvram_data,
2497 .fw_dump = NULL,
2498 .beacon_on = qla24xx_beacon_on,
2499 .beacon_off = qla24xx_beacon_off,
2500 .beacon_blink = NULL,
2501 .read_optrom = qla24xx_read_optrom_data,
2502 .write_optrom = qla24xx_write_optrom_data,
2503 .get_flash_version = qla24xx_get_flash_version,
2504 .start_scsi = qlafx00_start_scsi,
2505 .start_scsi_mq = NULL,
2506 .abort_isp = qlafx00_abort_isp,
2507 .iospace_config = qlafx00_iospace_config,
2508 .initialize_adapter = qlafx00_initialize_adapter,
2509 };
2510
2511 static struct isp_operations qla27xx_isp_ops = {
2512 .pci_config = qla25xx_pci_config,
2513 .reset_chip = qla24xx_reset_chip,
2514 .chip_diag = qla24xx_chip_diag,
2515 .config_rings = qla24xx_config_rings,
2516 .reset_adapter = qla24xx_reset_adapter,
2517 .nvram_config = qla81xx_nvram_config,
2518 .update_fw_options = qla81xx_update_fw_options,
2519 .load_risc = qla81xx_load_risc,
2520 .pci_info_str = qla24xx_pci_info_str,
2521 .fw_version_str = qla24xx_fw_version_str,
2522 .intr_handler = qla24xx_intr_handler,
2523 .enable_intrs = qla24xx_enable_intrs,
2524 .disable_intrs = qla24xx_disable_intrs,
2525 .abort_command = qla24xx_abort_command,
2526 .target_reset = qla24xx_abort_target,
2527 .lun_reset = qla24xx_lun_reset,
2528 .fabric_login = qla24xx_login_fabric,
2529 .fabric_logout = qla24xx_fabric_logout,
2530 .calc_req_entries = NULL,
2531 .build_iocbs = NULL,
2532 .prep_ms_iocb = qla24xx_prep_ms_iocb,
2533 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb,
2534 .read_nvram = NULL,
2535 .write_nvram = NULL,
2536 .fw_dump = qla27xx_fwdump,
2537 .beacon_on = qla24xx_beacon_on,
2538 .beacon_off = qla24xx_beacon_off,
2539 .beacon_blink = qla83xx_beacon_blink,
2540 .read_optrom = qla25xx_read_optrom_data,
2541 .write_optrom = qla24xx_write_optrom_data,
2542 .get_flash_version = qla24xx_get_flash_version,
2543 .start_scsi = qla24xx_dif_start_scsi,
2544 .start_scsi_mq = qla2xxx_dif_start_scsi_mq,
2545 .abort_isp = qla2x00_abort_isp,
2546 .iospace_config = qla83xx_iospace_config,
2547 .initialize_adapter = qla2x00_initialize_adapter,
2548 };
2549
2550 static inline void
2551 qla2x00_set_isp_flags(struct qla_hw_data *ha)
2552 {
2553 ha->device_type = DT_EXTENDED_IDS;
2554 switch (ha->pdev->device) {
2555 case PCI_DEVICE_ID_QLOGIC_ISP2100:
2556 ha->isp_type |= DT_ISP2100;
2557 ha->device_type &= ~DT_EXTENDED_IDS;
2558 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2559 break;
2560 case PCI_DEVICE_ID_QLOGIC_ISP2200:
2561 ha->isp_type |= DT_ISP2200;
2562 ha->device_type &= ~DT_EXTENDED_IDS;
2563 ha->fw_srisc_address = RISC_START_ADDRESS_2100;
2564 break;
2565 case PCI_DEVICE_ID_QLOGIC_ISP2300:
2566 ha->isp_type |= DT_ISP2300;
2567 ha->device_type |= DT_ZIO_SUPPORTED;
2568 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2569 break;
2570 case PCI_DEVICE_ID_QLOGIC_ISP2312:
2571 ha->isp_type |= DT_ISP2312;
2572 ha->device_type |= DT_ZIO_SUPPORTED;
2573 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2574 break;
2575 case PCI_DEVICE_ID_QLOGIC_ISP2322:
2576 ha->isp_type |= DT_ISP2322;
2577 ha->device_type |= DT_ZIO_SUPPORTED;
2578 if (ha->pdev->subsystem_vendor == 0x1028 &&
2579 ha->pdev->subsystem_device == 0x0170)
2580 ha->device_type |= DT_OEM_001;
2581 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2582 break;
2583 case PCI_DEVICE_ID_QLOGIC_ISP6312:
2584 ha->isp_type |= DT_ISP6312;
2585 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2586 break;
2587 case PCI_DEVICE_ID_QLOGIC_ISP6322:
2588 ha->isp_type |= DT_ISP6322;
2589 ha->fw_srisc_address = RISC_START_ADDRESS_2300;
2590 break;
2591 case PCI_DEVICE_ID_QLOGIC_ISP2422:
2592 ha->isp_type |= DT_ISP2422;
2593 ha->device_type |= DT_ZIO_SUPPORTED;
2594 ha->device_type |= DT_FWI2;
2595 ha->device_type |= DT_IIDMA;
2596 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2597 break;
2598 case PCI_DEVICE_ID_QLOGIC_ISP2432:
2599 ha->isp_type |= DT_ISP2432;
2600 ha->device_type |= DT_ZIO_SUPPORTED;
2601 ha->device_type |= DT_FWI2;
2602 ha->device_type |= DT_IIDMA;
2603 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2604 break;
2605 case PCI_DEVICE_ID_QLOGIC_ISP8432:
2606 ha->isp_type |= DT_ISP8432;
2607 ha->device_type |= DT_ZIO_SUPPORTED;
2608 ha->device_type |= DT_FWI2;
2609 ha->device_type |= DT_IIDMA;
2610 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2611 break;
2612 case PCI_DEVICE_ID_QLOGIC_ISP5422:
2613 ha->isp_type |= DT_ISP5422;
2614 ha->device_type |= DT_FWI2;
2615 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2616 break;
2617 case PCI_DEVICE_ID_QLOGIC_ISP5432:
2618 ha->isp_type |= DT_ISP5432;
2619 ha->device_type |= DT_FWI2;
2620 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2621 break;
2622 case PCI_DEVICE_ID_QLOGIC_ISP2532:
2623 ha->isp_type |= DT_ISP2532;
2624 ha->device_type |= DT_ZIO_SUPPORTED;
2625 ha->device_type |= DT_FWI2;
2626 ha->device_type |= DT_IIDMA;
2627 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2628 break;
2629 case PCI_DEVICE_ID_QLOGIC_ISP8001:
2630 ha->isp_type |= DT_ISP8001;
2631 ha->device_type |= DT_ZIO_SUPPORTED;
2632 ha->device_type |= DT_FWI2;
2633 ha->device_type |= DT_IIDMA;
2634 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2635 break;
2636 case PCI_DEVICE_ID_QLOGIC_ISP8021:
2637 ha->isp_type |= DT_ISP8021;
2638 ha->device_type |= DT_ZIO_SUPPORTED;
2639 ha->device_type |= DT_FWI2;
2640 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2641 /* Initialize 82XX ISP flags */
2642 qla82xx_init_flags(ha);
2643 break;
2644 case PCI_DEVICE_ID_QLOGIC_ISP8044:
2645 ha->isp_type |= DT_ISP8044;
2646 ha->device_type |= DT_ZIO_SUPPORTED;
2647 ha->device_type |= DT_FWI2;
2648 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2649 /* Initialize 82XX ISP flags */
2650 qla82xx_init_flags(ha);
2651 break;
2652 case PCI_DEVICE_ID_QLOGIC_ISP2031:
2653 ha->isp_type |= DT_ISP2031;
2654 ha->device_type |= DT_ZIO_SUPPORTED;
2655 ha->device_type |= DT_FWI2;
2656 ha->device_type |= DT_IIDMA;
2657 ha->device_type |= DT_T10_PI;
2658 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2659 break;
2660 case PCI_DEVICE_ID_QLOGIC_ISP8031:
2661 ha->isp_type |= DT_ISP8031;
2662 ha->device_type |= DT_ZIO_SUPPORTED;
2663 ha->device_type |= DT_FWI2;
2664 ha->device_type |= DT_IIDMA;
2665 ha->device_type |= DT_T10_PI;
2666 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2667 break;
2668 case PCI_DEVICE_ID_QLOGIC_ISPF001:
2669 ha->isp_type |= DT_ISPFX00;
2670 break;
2671 case PCI_DEVICE_ID_QLOGIC_ISP2071:
2672 ha->isp_type |= DT_ISP2071;
2673 ha->device_type |= DT_ZIO_SUPPORTED;
2674 ha->device_type |= DT_FWI2;
2675 ha->device_type |= DT_IIDMA;
2676 ha->device_type |= DT_T10_PI;
2677 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2678 break;
2679 case PCI_DEVICE_ID_QLOGIC_ISP2271:
2680 ha->isp_type |= DT_ISP2271;
2681 ha->device_type |= DT_ZIO_SUPPORTED;
2682 ha->device_type |= DT_FWI2;
2683 ha->device_type |= DT_IIDMA;
2684 ha->device_type |= DT_T10_PI;
2685 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2686 break;
2687 case PCI_DEVICE_ID_QLOGIC_ISP2261:
2688 ha->isp_type |= DT_ISP2261;
2689 ha->device_type |= DT_ZIO_SUPPORTED;
2690 ha->device_type |= DT_FWI2;
2691 ha->device_type |= DT_IIDMA;
2692 ha->device_type |= DT_T10_PI;
2693 ha->fw_srisc_address = RISC_START_ADDRESS_2400;
2694 break;
2695 }
2696
2697 if (IS_QLA82XX(ha))
2698 ha->port_no = ha->portnum & 1;
2699 else {
2700 /* Get adapter physical port no from interrupt pin register. */
2701 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no);
2702 if (IS_QLA27XX(ha))
2703 ha->port_no--;
2704 else
2705 ha->port_no = !(ha->port_no & 1);
2706 }
2707
2708 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b,
2709 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n",
2710 ha->device_type, ha->port_no, ha->fw_srisc_address);
2711 }
2712
2713 static void
2714 qla2xxx_scan_start(struct Scsi_Host *shost)
2715 {
2716 scsi_qla_host_t *vha = shost_priv(shost);
2717
2718 if (vha->hw->flags.running_gold_fw)
2719 return;
2720
2721 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
2722 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
2723 set_bit(RSCN_UPDATE, &vha->dpc_flags);
2724 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags);
2725 }
2726
2727 static int
2728 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time)
2729 {
2730 scsi_qla_host_t *vha = shost_priv(shost);
2731
2732 if (test_bit(UNLOADING, &vha->dpc_flags))
2733 return 1;
2734 if (!vha->host)
2735 return 1;
2736 if (time > vha->hw->loop_reset_delay * HZ)
2737 return 1;
2738
2739 return atomic_read(&vha->loop_state) == LOOP_READY;
2740 }
2741
2742 static void qla2x00_iocb_work_fn(struct work_struct *work)
2743 {
2744 struct scsi_qla_host *vha = container_of(work,
2745 struct scsi_qla_host, iocb_work);
2746 struct qla_hw_data *ha = vha->hw;
2747 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
2748 int i = 2;
2749 unsigned long flags;
2750
2751 if (test_bit(UNLOADING, &base_vha->dpc_flags))
2752 return;
2753
2754 while (!list_empty(&vha->work_list) && i > 0) {
2755 qla2x00_do_work(vha);
2756 i--;
2757 }
2758
2759 spin_lock_irqsave(&vha->work_lock, flags);
2760 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags);
2761 spin_unlock_irqrestore(&vha->work_lock, flags);
2762 }
2763
2764 /*
2765 * PCI driver interface
2766 */
2767 static int
2768 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id)
2769 {
2770 int ret = -ENODEV;
2771 struct Scsi_Host *host;
2772 scsi_qla_host_t *base_vha = NULL;
2773 struct qla_hw_data *ha;
2774 char pci_info[30];
2775 char fw_str[30], wq_name[30];
2776 struct scsi_host_template *sht;
2777 int bars, mem_only = 0;
2778 uint16_t req_length = 0, rsp_length = 0;
2779 struct req_que *req = NULL;
2780 struct rsp_que *rsp = NULL;
2781 int i;
2782
2783 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO);
2784 sht = &qla2xxx_driver_template;
2785 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 ||
2786 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 ||
2787 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 ||
2788 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 ||
2789 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 ||
2790 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 ||
2791 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 ||
2792 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 ||
2793 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 ||
2794 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 ||
2795 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 ||
2796 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 ||
2797 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 ||
2798 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 ||
2799 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261) {
2800 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2801 mem_only = 1;
2802 ql_dbg_pci(ql_dbg_init, pdev, 0x0007,
2803 "Mem only adapter.\n");
2804 }
2805 ql_dbg_pci(ql_dbg_init, pdev, 0x0008,
2806 "Bars=%d.\n", bars);
2807
2808 if (mem_only) {
2809 if (pci_enable_device_mem(pdev))
2810 return ret;
2811 } else {
2812 if (pci_enable_device(pdev))
2813 return ret;
2814 }
2815
2816 /* This may fail but that's ok */
2817 pci_enable_pcie_error_reporting(pdev);
2818
2819 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL);
2820 if (!ha) {
2821 ql_log_pci(ql_log_fatal, pdev, 0x0009,
2822 "Unable to allocate memory for ha.\n");
2823 goto disable_device;
2824 }
2825 ql_dbg_pci(ql_dbg_init, pdev, 0x000a,
2826 "Memory allocated for ha=%p.\n", ha);
2827 ha->pdev = pdev;
2828 INIT_LIST_HEAD(&ha->tgt.q_full_list);
2829 spin_lock_init(&ha->tgt.q_full_lock);
2830 spin_lock_init(&ha->tgt.sess_lock);
2831 spin_lock_init(&ha->tgt.atio_lock);
2832
2833 atomic_set(&ha->nvme_active_aen_cnt, 0);
2834
2835 /* Clear our data area */
2836 ha->bars = bars;
2837 ha->mem_only = mem_only;
2838 spin_lock_init(&ha->hardware_lock);
2839 spin_lock_init(&ha->vport_slock);
2840 mutex_init(&ha->selflogin_lock);
2841 mutex_init(&ha->optrom_mutex);
2842
2843 /* Set ISP-type information. */
2844 qla2x00_set_isp_flags(ha);
2845
2846 /* Set EEH reset type to fundamental if required by hba */
2847 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) ||
2848 IS_QLA83XX(ha) || IS_QLA27XX(ha))
2849 pdev->needs_freset = 1;
2850
2851 ha->prev_topology = 0;
2852 ha->init_cb_size = sizeof(init_cb_t);
2853 ha->link_data_rate = PORT_SPEED_UNKNOWN;
2854 ha->optrom_size = OPTROM_SIZE_2300;
2855 ha->max_exchg = FW_MAX_EXCHANGES_CNT;
2856 atomic_set(&ha->num_pend_mbx_stage1, 0);
2857 atomic_set(&ha->num_pend_mbx_stage2, 0);
2858 atomic_set(&ha->num_pend_mbx_stage3, 0);
2859 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD);
2860 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD;
2861
2862 /* Assign ISP specific operations. */
2863 if (IS_QLA2100(ha)) {
2864 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2865 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100;
2866 req_length = REQUEST_ENTRY_CNT_2100;
2867 rsp_length = RESPONSE_ENTRY_CNT_2100;
2868 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2869 ha->gid_list_info_size = 4;
2870 ha->flash_conf_off = ~0;
2871 ha->flash_data_off = ~0;
2872 ha->nvram_conf_off = ~0;
2873 ha->nvram_data_off = ~0;
2874 ha->isp_ops = &qla2100_isp_ops;
2875 } else if (IS_QLA2200(ha)) {
2876 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2877 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200;
2878 req_length = REQUEST_ENTRY_CNT_2200;
2879 rsp_length = RESPONSE_ENTRY_CNT_2100;
2880 ha->max_loop_id = SNS_LAST_LOOP_ID_2100;
2881 ha->gid_list_info_size = 4;
2882 ha->flash_conf_off = ~0;
2883 ha->flash_data_off = ~0;
2884 ha->nvram_conf_off = ~0;
2885 ha->nvram_data_off = ~0;
2886 ha->isp_ops = &qla2100_isp_ops;
2887 } else if (IS_QLA23XX(ha)) {
2888 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100;
2889 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2890 req_length = REQUEST_ENTRY_CNT_2200;
2891 rsp_length = RESPONSE_ENTRY_CNT_2300;
2892 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2893 ha->gid_list_info_size = 6;
2894 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2895 ha->optrom_size = OPTROM_SIZE_2322;
2896 ha->flash_conf_off = ~0;
2897 ha->flash_data_off = ~0;
2898 ha->nvram_conf_off = ~0;
2899 ha->nvram_data_off = ~0;
2900 ha->isp_ops = &qla2300_isp_ops;
2901 } else if (IS_QLA24XX_TYPE(ha)) {
2902 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2903 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2904 req_length = REQUEST_ENTRY_CNT_24XX;
2905 rsp_length = RESPONSE_ENTRY_CNT_2300;
2906 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2907 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2908 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2909 ha->gid_list_info_size = 8;
2910 ha->optrom_size = OPTROM_SIZE_24XX;
2911 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX;
2912 ha->isp_ops = &qla24xx_isp_ops;
2913 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2914 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2915 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2916 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2917 } else if (IS_QLA25XX(ha)) {
2918 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2919 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2920 req_length = REQUEST_ENTRY_CNT_24XX;
2921 rsp_length = RESPONSE_ENTRY_CNT_2300;
2922 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2923 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2924 ha->init_cb_size = sizeof(struct mid_init_cb_24xx);
2925 ha->gid_list_info_size = 8;
2926 ha->optrom_size = OPTROM_SIZE_25XX;
2927 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2928 ha->isp_ops = &qla25xx_isp_ops;
2929 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2930 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2931 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2932 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2933 } else if (IS_QLA81XX(ha)) {
2934 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2935 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2936 req_length = REQUEST_ENTRY_CNT_24XX;
2937 rsp_length = RESPONSE_ENTRY_CNT_2300;
2938 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2939 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2940 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2941 ha->gid_list_info_size = 8;
2942 ha->optrom_size = OPTROM_SIZE_81XX;
2943 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2944 ha->isp_ops = &qla81xx_isp_ops;
2945 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2946 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2947 ha->nvram_conf_off = ~0;
2948 ha->nvram_data_off = ~0;
2949 } else if (IS_QLA82XX(ha)) {
2950 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2951 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2952 req_length = REQUEST_ENTRY_CNT_82XX;
2953 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2954 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2955 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2956 ha->gid_list_info_size = 8;
2957 ha->optrom_size = OPTROM_SIZE_82XX;
2958 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2959 ha->isp_ops = &qla82xx_isp_ops;
2960 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2961 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2962 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2963 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2964 } else if (IS_QLA8044(ha)) {
2965 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2966 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2967 req_length = REQUEST_ENTRY_CNT_82XX;
2968 rsp_length = RESPONSE_ENTRY_CNT_82XX;
2969 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2970 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2971 ha->gid_list_info_size = 8;
2972 ha->optrom_size = OPTROM_SIZE_83XX;
2973 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2974 ha->isp_ops = &qla8044_isp_ops;
2975 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF;
2976 ha->flash_data_off = FARX_ACCESS_FLASH_DATA;
2977 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF;
2978 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA;
2979 } else if (IS_QLA83XX(ha)) {
2980 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2981 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
2982 ha->mbx_count = MAILBOX_REGISTER_COUNT;
2983 req_length = REQUEST_ENTRY_CNT_83XX;
2984 rsp_length = RESPONSE_ENTRY_CNT_83XX;
2985 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
2986 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
2987 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
2988 ha->gid_list_info_size = 8;
2989 ha->optrom_size = OPTROM_SIZE_83XX;
2990 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
2991 ha->isp_ops = &qla83xx_isp_ops;
2992 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
2993 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
2994 ha->nvram_conf_off = ~0;
2995 ha->nvram_data_off = ~0;
2996 } else if (IS_QLAFX00(ha)) {
2997 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00;
2998 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00;
2999 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00;
3000 req_length = REQUEST_ENTRY_CNT_FX00;
3001 rsp_length = RESPONSE_ENTRY_CNT_FX00;
3002 ha->isp_ops = &qlafx00_isp_ops;
3003 ha->port_down_retry_count = 30; /* default value */
3004 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL;
3005 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL;
3006 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL;
3007 ha->mr.fw_hbt_en = 1;
3008 ha->mr.host_info_resend = false;
3009 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL;
3010 } else if (IS_QLA27XX(ha)) {
3011 ha->portnum = PCI_FUNC(ha->pdev->devfn);
3012 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400;
3013 ha->mbx_count = MAILBOX_REGISTER_COUNT;
3014 req_length = REQUEST_ENTRY_CNT_83XX;
3015 rsp_length = RESPONSE_ENTRY_CNT_83XX;
3016 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX;
3017 ha->max_loop_id = SNS_LAST_LOOP_ID_2300;
3018 ha->init_cb_size = sizeof(struct mid_init_cb_81xx);
3019 ha->gid_list_info_size = 8;
3020 ha->optrom_size = OPTROM_SIZE_83XX;
3021 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX;
3022 ha->isp_ops = &qla27xx_isp_ops;
3023 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX;
3024 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX;
3025 ha->nvram_conf_off = ~0;
3026 ha->nvram_data_off = ~0;
3027 }
3028
3029 ql_dbg_pci(ql_dbg_init, pdev, 0x001e,
3030 "mbx_count=%d, req_length=%d, "
3031 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, "
3032 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, "
3033 "max_fibre_devices=%d.\n",
3034 ha->mbx_count, req_length, rsp_length, ha->max_loop_id,
3035 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size,
3036 ha->nvram_npiv_size, ha->max_fibre_devices);
3037 ql_dbg_pci(ql_dbg_init, pdev, 0x001f,
3038 "isp_ops=%p, flash_conf_off=%d, "
3039 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n",
3040 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off,
3041 ha->nvram_conf_off, ha->nvram_data_off);
3042
3043 /* Configure PCI I/O space */
3044 ret = ha->isp_ops->iospace_config(ha);
3045 if (ret)
3046 goto iospace_config_failed;
3047
3048 ql_log_pci(ql_log_info, pdev, 0x001d,
3049 "Found an ISP%04X irq %d iobase 0x%p.\n",
3050 pdev->device, pdev->irq, ha->iobase);
3051 mutex_init(&ha->vport_lock);
3052 mutex_init(&ha->mq_lock);
3053 init_completion(&ha->mbx_cmd_comp);
3054 complete(&ha->mbx_cmd_comp);
3055 init_completion(&ha->mbx_intr_comp);
3056 init_completion(&ha->dcbx_comp);
3057 init_completion(&ha->lb_portup_comp);
3058
3059 set_bit(0, (unsigned long *) ha->vp_idx_map);
3060
3061 qla2x00_config_dma_addressing(ha);
3062 ql_dbg_pci(ql_dbg_init, pdev, 0x0020,
3063 "64 Bit addressing is %s.\n",
3064 ha->flags.enable_64bit_addressing ? "enable" :
3065 "disable");
3066 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp);
3067 if (ret) {
3068 ql_log_pci(ql_log_fatal, pdev, 0x0031,
3069 "Failed to allocate memory for adapter, aborting.\n");
3070
3071 goto probe_hw_failed;
3072 }
3073
3074 req->max_q_depth = MAX_Q_DEPTH;
3075 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU)
3076 req->max_q_depth = ql2xmaxqdepth;
3077
3078
3079 base_vha = qla2x00_create_host(sht, ha);
3080 if (!base_vha) {
3081 ret = -ENOMEM;
3082 goto probe_hw_failed;
3083 }
3084
3085 pci_set_drvdata(pdev, base_vha);
3086 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3087
3088 host = base_vha->host;
3089 base_vha->req = req;
3090 if (IS_QLA2XXX_MIDTYPE(ha))
3091 base_vha->mgmt_svr_loop_id =
3092 qla2x00_reserve_mgmt_server_loop_id(base_vha);
3093 else
3094 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER +
3095 base_vha->vp_idx;
3096
3097 /* Setup fcport template structure. */
3098 ha->mr.fcport.vha = base_vha;
3099 ha->mr.fcport.port_type = FCT_UNKNOWN;
3100 ha->mr.fcport.loop_id = FC_NO_LOOP_ID;
3101 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED);
3102 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED;
3103 ha->mr.fcport.scan_state = 1;
3104
3105 /* Set the SG table size based on ISP type */
3106 if (!IS_FWI2_CAPABLE(ha)) {
3107 if (IS_QLA2100(ha))
3108 host->sg_tablesize = 32;
3109 } else {
3110 if (!IS_QLA82XX(ha))
3111 host->sg_tablesize = QLA_SG_ALL;
3112 }
3113 host->max_id = ha->max_fibre_devices;
3114 host->cmd_per_lun = 3;
3115 host->unique_id = host->host_no;
3116 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif)
3117 host->max_cmd_len = 32;
3118 else
3119 host->max_cmd_len = MAX_CMDSZ;
3120 host->max_channel = MAX_BUSES - 1;
3121 /* Older HBAs support only 16-bit LUNs */
3122 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) &&
3123 ql2xmaxlun > 0xffff)
3124 host->max_lun = 0xffff;
3125 else
3126 host->max_lun = ql2xmaxlun;
3127 host->transportt = qla2xxx_transport_template;
3128 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC);
3129
3130 ql_dbg(ql_dbg_init, base_vha, 0x0033,
3131 "max_id=%d this_id=%d "
3132 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d "
3133 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id,
3134 host->this_id, host->cmd_per_lun, host->unique_id,
3135 host->max_cmd_len, host->max_channel, host->max_lun,
3136 host->transportt, sht->vendor_id);
3137
3138 INIT_WORK(&base_vha->iocb_work, qla2x00_iocb_work_fn);
3139
3140 /* Set up the irqs */
3141 ret = qla2x00_request_irqs(ha, rsp);
3142 if (ret)
3143 goto probe_failed;
3144
3145 /* Alloc arrays of request and response ring ptrs */
3146 ret = qla2x00_alloc_queues(ha, req, rsp);
3147 if (ret) {
3148 ql_log(ql_log_fatal, base_vha, 0x003d,
3149 "Failed to allocate memory for queue pointers..."
3150 "aborting.\n");
3151 goto probe_failed;
3152 }
3153
3154 if (ha->mqenable && shost_use_blk_mq(host)) {
3155 /* number of hardware queues supported by blk/scsi-mq*/
3156 host->nr_hw_queues = ha->max_qpairs;
3157
3158 ql_dbg(ql_dbg_init, base_vha, 0x0192,
3159 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues);
3160 } else {
3161 if (ql2xnvmeenable) {
3162 host->nr_hw_queues = ha->max_qpairs;
3163 ql_dbg(ql_dbg_init, base_vha, 0x0194,
3164 "FC-NVMe support is enabled, HW queues=%d\n",
3165 host->nr_hw_queues);
3166 } else {
3167 ql_dbg(ql_dbg_init, base_vha, 0x0193,
3168 "blk/scsi-mq disabled.\n");
3169 }
3170 }
3171
3172 qlt_probe_one_stage1(base_vha, ha);
3173
3174 pci_save_state(pdev);
3175
3176 /* Assign back pointers */
3177 rsp->req = req;
3178 req->rsp = rsp;
3179
3180 if (IS_QLAFX00(ha)) {
3181 ha->rsp_q_map[0] = rsp;
3182 ha->req_q_map[0] = req;
3183 set_bit(0, ha->req_qid_map);
3184 set_bit(0, ha->rsp_qid_map);
3185 }
3186
3187 /* FWI2-capable only. */
3188 req->req_q_in = &ha->iobase->isp24.req_q_in;
3189 req->req_q_out = &ha->iobase->isp24.req_q_out;
3190 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in;
3191 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out;
3192 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha)) {
3193 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in;
3194 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out;
3195 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in;
3196 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out;
3197 }
3198
3199 if (IS_QLAFX00(ha)) {
3200 req->req_q_in = &ha->iobase->ispfx00.req_q_in;
3201 req->req_q_out = &ha->iobase->ispfx00.req_q_out;
3202 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in;
3203 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out;
3204 }
3205
3206 if (IS_P3P_TYPE(ha)) {
3207 req->req_q_out = &ha->iobase->isp82.req_q_out[0];
3208 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0];
3209 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0];
3210 }
3211
3212 ql_dbg(ql_dbg_multiq, base_vha, 0xc009,
3213 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3214 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3215 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a,
3216 "req->req_q_in=%p req->req_q_out=%p "
3217 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3218 req->req_q_in, req->req_q_out,
3219 rsp->rsp_q_in, rsp->rsp_q_out);
3220 ql_dbg(ql_dbg_init, base_vha, 0x003e,
3221 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n",
3222 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp);
3223 ql_dbg(ql_dbg_init, base_vha, 0x003f,
3224 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n",
3225 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out);
3226
3227 ha->wq = alloc_workqueue("qla2xxx_wq", 0, 0);
3228
3229 if (ha->isp_ops->initialize_adapter(base_vha)) {
3230 ql_log(ql_log_fatal, base_vha, 0x00d6,
3231 "Failed to initialize adapter - Adapter flags %x.\n",
3232 base_vha->device_flags);
3233
3234 if (IS_QLA82XX(ha)) {
3235 qla82xx_idc_lock(ha);
3236 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3237 QLA8XXX_DEV_FAILED);
3238 qla82xx_idc_unlock(ha);
3239 ql_log(ql_log_fatal, base_vha, 0x00d7,
3240 "HW State: FAILED.\n");
3241 } else if (IS_QLA8044(ha)) {
3242 qla8044_idc_lock(ha);
3243 qla8044_wr_direct(base_vha,
3244 QLA8044_CRB_DEV_STATE_INDEX,
3245 QLA8XXX_DEV_FAILED);
3246 qla8044_idc_unlock(ha);
3247 ql_log(ql_log_fatal, base_vha, 0x0150,
3248 "HW State: FAILED.\n");
3249 }
3250
3251 ret = -ENODEV;
3252 goto probe_failed;
3253 }
3254
3255 if (IS_QLAFX00(ha))
3256 host->can_queue = QLAFX00_MAX_CANQUEUE;
3257 else
3258 host->can_queue = req->num_outstanding_cmds - 10;
3259
3260 ql_dbg(ql_dbg_init, base_vha, 0x0032,
3261 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n",
3262 host->can_queue, base_vha->req,
3263 base_vha->mgmt_svr_loop_id, host->sg_tablesize);
3264
3265 if (ha->mqenable) {
3266 bool mq = false;
3267 bool startit = false;
3268
3269 if (QLA_TGT_MODE_ENABLED()) {
3270 mq = true;
3271 startit = false;
3272 }
3273
3274 if ((ql2x_ini_mode == QLA2XXX_INI_MODE_ENABLED) &&
3275 shost_use_blk_mq(host)) {
3276 mq = true;
3277 startit = true;
3278 }
3279
3280 if (mq) {
3281 /* Create start of day qpairs for Block MQ */
3282 for (i = 0; i < ha->max_qpairs; i++)
3283 qla2xxx_create_qpair(base_vha, 5, 0, startit);
3284 }
3285 }
3286
3287 if (ha->flags.running_gold_fw)
3288 goto skip_dpc;
3289
3290 /*
3291 * Startup the kernel thread for this host adapter
3292 */
3293 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha,
3294 "%s_dpc", base_vha->host_str);
3295 if (IS_ERR(ha->dpc_thread)) {
3296 ql_log(ql_log_fatal, base_vha, 0x00ed,
3297 "Failed to start DPC thread.\n");
3298 ret = PTR_ERR(ha->dpc_thread);
3299 ha->dpc_thread = NULL;
3300 goto probe_failed;
3301 }
3302 ql_dbg(ql_dbg_init, base_vha, 0x00ee,
3303 "DPC thread started successfully.\n");
3304
3305 /*
3306 * If we're not coming up in initiator mode, we might sit for
3307 * a while without waking up the dpc thread, which leads to a
3308 * stuck process warning. So just kick the dpc once here and
3309 * let the kthread start (and go back to sleep in qla2x00_do_dpc).
3310 */
3311 qla2xxx_wake_dpc(base_vha);
3312
3313 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error);
3314
3315 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) {
3316 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no);
3317 ha->dpc_lp_wq = create_singlethread_workqueue(wq_name);
3318 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen);
3319
3320 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no);
3321 ha->dpc_hp_wq = create_singlethread_workqueue(wq_name);
3322 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work);
3323 INIT_WORK(&ha->idc_state_handler,
3324 qla83xx_idc_state_handler_work);
3325 INIT_WORK(&ha->nic_core_unrecoverable,
3326 qla83xx_nic_core_unrecoverable_work);
3327 }
3328
3329 skip_dpc:
3330 list_add_tail(&base_vha->list, &ha->vp_list);
3331 base_vha->host->irq = ha->pdev->irq;
3332
3333 /* Initialized the timer */
3334 qla2x00_start_timer(base_vha, WATCH_INTERVAL);
3335 ql_dbg(ql_dbg_init, base_vha, 0x00ef,
3336 "Started qla2x00_timer with "
3337 "interval=%d.\n", WATCH_INTERVAL);
3338 ql_dbg(ql_dbg_init, base_vha, 0x00f0,
3339 "Detected hba at address=%p.\n",
3340 ha);
3341
3342 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
3343 if (ha->fw_attributes & BIT_4) {
3344 int prot = 0, guard;
3345 base_vha->flags.difdix_supported = 1;
3346 ql_dbg(ql_dbg_init, base_vha, 0x00f1,
3347 "Registering for DIF/DIX type 1 and 3 protection.\n");
3348 if (ql2xenabledif == 1)
3349 prot = SHOST_DIX_TYPE0_PROTECTION;
3350 scsi_host_set_prot(host,
3351 prot | SHOST_DIF_TYPE1_PROTECTION
3352 | SHOST_DIF_TYPE2_PROTECTION
3353 | SHOST_DIF_TYPE3_PROTECTION
3354 | SHOST_DIX_TYPE1_PROTECTION
3355 | SHOST_DIX_TYPE2_PROTECTION
3356 | SHOST_DIX_TYPE3_PROTECTION);
3357
3358 guard = SHOST_DIX_GUARD_CRC;
3359
3360 if (IS_PI_IPGUARD_CAPABLE(ha) &&
3361 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha)))
3362 guard |= SHOST_DIX_GUARD_IP;
3363
3364 scsi_host_set_guard(host, guard);
3365 } else
3366 base_vha->flags.difdix_supported = 0;
3367 }
3368
3369 ha->isp_ops->enable_intrs(ha);
3370
3371 if (IS_QLAFX00(ha)) {
3372 ret = qlafx00_fx_disc(base_vha,
3373 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO);
3374 host->sg_tablesize = (ha->mr.extended_io_enabled) ?
3375 QLA_SG_ALL : 128;
3376 }
3377
3378 ret = scsi_add_host(host, &pdev->dev);
3379 if (ret)
3380 goto probe_failed;
3381
3382 base_vha->flags.init_done = 1;
3383 base_vha->flags.online = 1;
3384 ha->prev_minidump_failed = 0;
3385
3386 ql_dbg(ql_dbg_init, base_vha, 0x00f2,
3387 "Init done and hba is online.\n");
3388
3389 if (qla_ini_mode_enabled(base_vha) ||
3390 qla_dual_mode_enabled(base_vha))
3391 scsi_scan_host(host);
3392 else
3393 ql_dbg(ql_dbg_init, base_vha, 0x0122,
3394 "skipping scsi_scan_host() for non-initiator port\n");
3395
3396 qla2x00_alloc_sysfs_attr(base_vha);
3397
3398 if (IS_QLAFX00(ha)) {
3399 ret = qlafx00_fx_disc(base_vha,
3400 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO);
3401
3402 /* Register system information */
3403 ret = qlafx00_fx_disc(base_vha,
3404 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO);
3405 }
3406
3407 qla2x00_init_host_attr(base_vha);
3408
3409 qla2x00_dfs_setup(base_vha);
3410
3411 ql_log(ql_log_info, base_vha, 0x00fb,
3412 "QLogic %s - %s.\n", ha->model_number, ha->model_desc);
3413 ql_log(ql_log_info, base_vha, 0x00fc,
3414 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n",
3415 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info),
3416 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-',
3417 base_vha->host_no,
3418 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str)));
3419
3420 qlt_add_target(ha, base_vha);
3421
3422 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags);
3423
3424 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3425 return -ENODEV;
3426
3427 if (ha->flags.detected_lr_sfp) {
3428 ql_log(ql_log_info, base_vha, 0xffff,
3429 "Reset chip to pick up LR SFP setting\n");
3430 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
3431 qla2xxx_wake_dpc(base_vha);
3432 }
3433
3434 return 0;
3435
3436 probe_failed:
3437 if (base_vha->timer_active)
3438 qla2x00_stop_timer(base_vha);
3439 base_vha->flags.online = 0;
3440 if (ha->dpc_thread) {
3441 struct task_struct *t = ha->dpc_thread;
3442
3443 ha->dpc_thread = NULL;
3444 kthread_stop(t);
3445 }
3446
3447 qla2x00_free_device(base_vha);
3448 scsi_host_put(base_vha->host);
3449 /*
3450 * Need to NULL out local req/rsp after
3451 * qla2x00_free_device => qla2x00_free_queues frees
3452 * what these are pointing to. Or else we'll
3453 * fall over below in qla2x00_free_req/rsp_que.
3454 */
3455 req = NULL;
3456 rsp = NULL;
3457
3458 probe_hw_failed:
3459 qla2x00_mem_free(ha);
3460 qla2x00_free_req_que(ha, req);
3461 qla2x00_free_rsp_que(ha, rsp);
3462 qla2x00_clear_drv_active(ha);
3463
3464 iospace_config_failed:
3465 if (IS_P3P_TYPE(ha)) {
3466 if (!ha->nx_pcibase)
3467 iounmap((device_reg_t *)ha->nx_pcibase);
3468 if (!ql2xdbwr)
3469 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3470 } else {
3471 if (ha->iobase)
3472 iounmap(ha->iobase);
3473 if (ha->cregbase)
3474 iounmap(ha->cregbase);
3475 }
3476 pci_release_selected_regions(ha->pdev, ha->bars);
3477 kfree(ha);
3478
3479 disable_device:
3480 pci_disable_device(pdev);
3481 return ret;
3482 }
3483
3484 static void
3485 qla2x00_shutdown(struct pci_dev *pdev)
3486 {
3487 scsi_qla_host_t *vha;
3488 struct qla_hw_data *ha;
3489
3490 vha = pci_get_drvdata(pdev);
3491 ha = vha->hw;
3492
3493 ql_log(ql_log_info, vha, 0xfffa,
3494 "Adapter shutdown\n");
3495
3496 /*
3497 * Prevent future board_disable and wait
3498 * until any pending board_disable has completed.
3499 */
3500 set_bit(PFLG_DRIVER_REMOVING, &vha->pci_flags);
3501 cancel_work_sync(&ha->board_disable);
3502
3503 if (!atomic_read(&pdev->enable_cnt))
3504 return;
3505
3506 /* Notify ISPFX00 firmware */
3507 if (IS_QLAFX00(ha))
3508 qlafx00_driver_shutdown(vha, 20);
3509
3510 /* Turn-off FCE trace */
3511 if (ha->flags.fce_enabled) {
3512 qla2x00_disable_fce_trace(vha, NULL, NULL);
3513 ha->flags.fce_enabled = 0;
3514 }
3515
3516 /* Turn-off EFT trace */
3517 if (ha->eft)
3518 qla2x00_disable_eft_trace(vha);
3519
3520 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3521 if (ha->flags.fw_started)
3522 qla2x00_abort_isp_cleanup(vha);
3523 } else {
3524 /* Stop currently executing firmware. */
3525 qla2x00_try_to_stop_firmware(vha);
3526 }
3527
3528 /* Turn adapter off line */
3529 vha->flags.online = 0;
3530
3531 /* turn-off interrupts on the card */
3532 if (ha->interrupts_on) {
3533 vha->flags.init_done = 0;
3534 ha->isp_ops->disable_intrs(ha);
3535 }
3536
3537 qla2x00_free_irqs(vha);
3538
3539 qla2x00_free_fw_dump(ha);
3540
3541 pci_disable_device(pdev);
3542 ql_log(ql_log_info, vha, 0xfffe,
3543 "Adapter shutdown successfully.\n");
3544 }
3545
3546 /* Deletes all the virtual ports for a given ha */
3547 static void
3548 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha)
3549 {
3550 scsi_qla_host_t *vha;
3551 unsigned long flags;
3552
3553 mutex_lock(&ha->vport_lock);
3554 while (ha->cur_vport_count) {
3555 spin_lock_irqsave(&ha->vport_slock, flags);
3556
3557 BUG_ON(base_vha->list.next == &ha->vp_list);
3558 /* This assumes first entry in ha->vp_list is always base vha */
3559 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list);
3560 scsi_host_get(vha->host);
3561
3562 spin_unlock_irqrestore(&ha->vport_slock, flags);
3563 mutex_unlock(&ha->vport_lock);
3564
3565 fc_vport_terminate(vha->fc_vport);
3566 scsi_host_put(vha->host);
3567
3568 mutex_lock(&ha->vport_lock);
3569 }
3570 mutex_unlock(&ha->vport_lock);
3571 }
3572
3573 /* Stops all deferred work threads */
3574 static void
3575 qla2x00_destroy_deferred_work(struct qla_hw_data *ha)
3576 {
3577 /* Cancel all work and destroy DPC workqueues */
3578 if (ha->dpc_lp_wq) {
3579 cancel_work_sync(&ha->idc_aen);
3580 destroy_workqueue(ha->dpc_lp_wq);
3581 ha->dpc_lp_wq = NULL;
3582 }
3583
3584 if (ha->dpc_hp_wq) {
3585 cancel_work_sync(&ha->nic_core_reset);
3586 cancel_work_sync(&ha->idc_state_handler);
3587 cancel_work_sync(&ha->nic_core_unrecoverable);
3588 destroy_workqueue(ha->dpc_hp_wq);
3589 ha->dpc_hp_wq = NULL;
3590 }
3591
3592 /* Kill the kernel thread for this host */
3593 if (ha->dpc_thread) {
3594 struct task_struct *t = ha->dpc_thread;
3595
3596 /*
3597 * qla2xxx_wake_dpc checks for ->dpc_thread
3598 * so we need to zero it out.
3599 */
3600 ha->dpc_thread = NULL;
3601 kthread_stop(t);
3602 }
3603 }
3604
3605 static void
3606 qla2x00_unmap_iobases(struct qla_hw_data *ha)
3607 {
3608 if (IS_QLA82XX(ha)) {
3609
3610 iounmap((device_reg_t *)ha->nx_pcibase);
3611 if (!ql2xdbwr)
3612 iounmap((device_reg_t *)ha->nxdb_wr_ptr);
3613 } else {
3614 if (ha->iobase)
3615 iounmap(ha->iobase);
3616
3617 if (ha->cregbase)
3618 iounmap(ha->cregbase);
3619
3620 if (ha->mqiobase)
3621 iounmap(ha->mqiobase);
3622
3623 if ((IS_QLA83XX(ha) || IS_QLA27XX(ha)) && ha->msixbase)
3624 iounmap(ha->msixbase);
3625 }
3626 }
3627
3628 static void
3629 qla2x00_clear_drv_active(struct qla_hw_data *ha)
3630 {
3631 if (IS_QLA8044(ha)) {
3632 qla8044_idc_lock(ha);
3633 qla8044_clear_drv_active(ha);
3634 qla8044_idc_unlock(ha);
3635 } else if (IS_QLA82XX(ha)) {
3636 qla82xx_idc_lock(ha);
3637 qla82xx_clear_drv_active(ha);
3638 qla82xx_idc_unlock(ha);
3639 }
3640 }
3641
3642 static void
3643 qla2x00_remove_one(struct pci_dev *pdev)
3644 {
3645 scsi_qla_host_t *base_vha;
3646 struct qla_hw_data *ha;
3647
3648 base_vha = pci_get_drvdata(pdev);
3649 ha = base_vha->hw;
3650 ql_log(ql_log_info, base_vha, 0xb079,
3651 "Removing driver\n");
3652
3653 /* Indicate device removal to prevent future board_disable and wait
3654 * until any pending board_disable has completed. */
3655 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags);
3656 cancel_work_sync(&ha->board_disable);
3657
3658 /*
3659 * If the PCI device is disabled then there was a PCI-disconnect and
3660 * qla2x00_disable_board_on_pci_error has taken care of most of the
3661 * resources.
3662 */
3663 if (!atomic_read(&pdev->enable_cnt)) {
3664 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size,
3665 base_vha->gnl.l, base_vha->gnl.ldma);
3666
3667 scsi_host_put(base_vha->host);
3668 kfree(ha);
3669 pci_set_drvdata(pdev, NULL);
3670 return;
3671 }
3672 qla2x00_wait_for_hba_ready(base_vha);
3673
3674 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
3675 if (ha->flags.fw_started)
3676 qla2x00_abort_isp_cleanup(base_vha);
3677 } else if (!IS_QLAFX00(ha)) {
3678 if (IS_QLA8031(ha)) {
3679 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e,
3680 "Clearing fcoe driver presence.\n");
3681 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS)
3682 ql_dbg(ql_dbg_p3p, base_vha, 0xb079,
3683 "Error while clearing DRV-Presence.\n");
3684 }
3685
3686 qla2x00_try_to_stop_firmware(base_vha);
3687 }
3688
3689 qla2x00_wait_for_sess_deletion(base_vha);
3690
3691 /*
3692 * if UNLOAD flag is already set, then continue unload,
3693 * where it was set first.
3694 */
3695 if (test_bit(UNLOADING, &base_vha->dpc_flags))
3696 return;
3697
3698 set_bit(UNLOADING, &base_vha->dpc_flags);
3699
3700 qla_nvme_delete(base_vha);
3701
3702 dma_free_coherent(&ha->pdev->dev,
3703 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma);
3704
3705 vfree(base_vha->scan.l);
3706
3707 if (IS_QLAFX00(ha))
3708 qlafx00_driver_shutdown(base_vha, 20);
3709
3710 qla2x00_delete_all_vps(ha, base_vha);
3711
3712 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
3713
3714 qla2x00_dfs_remove(base_vha);
3715
3716 qla84xx_put_chip(base_vha);
3717
3718 /* Disable timer */
3719 if (base_vha->timer_active)
3720 qla2x00_stop_timer(base_vha);
3721
3722 base_vha->flags.online = 0;
3723
3724 /* free DMA memory */
3725 if (ha->exlogin_buf)
3726 qla2x00_free_exlogin_buffer(ha);
3727
3728 /* free DMA memory */
3729 if (ha->exchoffld_buf)
3730 qla2x00_free_exchoffld_buffer(ha);
3731
3732 qla2x00_destroy_deferred_work(ha);
3733
3734 qlt_remove_target(ha, base_vha);
3735
3736 qla2x00_free_sysfs_attr(base_vha, true);
3737
3738 fc_remove_host(base_vha->host);
3739 qlt_remove_target_resources(ha);
3740
3741 scsi_remove_host(base_vha->host);
3742
3743 qla2x00_free_device(base_vha);
3744
3745 qla2x00_clear_drv_active(ha);
3746
3747 scsi_host_put(base_vha->host);
3748
3749 qla2x00_unmap_iobases(ha);
3750
3751 pci_release_selected_regions(ha->pdev, ha->bars);
3752 kfree(ha);
3753
3754 pci_disable_pcie_error_reporting(pdev);
3755
3756 pci_disable_device(pdev);
3757 }
3758
3759 static void
3760 qla2x00_free_device(scsi_qla_host_t *vha)
3761 {
3762 struct qla_hw_data *ha = vha->hw;
3763
3764 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
3765
3766 /* Disable timer */
3767 if (vha->timer_active)
3768 qla2x00_stop_timer(vha);
3769
3770 qla25xx_delete_queues(vha);
3771 vha->flags.online = 0;
3772
3773 /* turn-off interrupts on the card */
3774 if (ha->interrupts_on) {
3775 vha->flags.init_done = 0;
3776 ha->isp_ops->disable_intrs(ha);
3777 }
3778
3779 qla2x00_free_fcports(vha);
3780
3781 qla2x00_free_irqs(vha);
3782
3783 /* Flush the work queue and remove it */
3784 if (ha->wq) {
3785 flush_workqueue(ha->wq);
3786 destroy_workqueue(ha->wq);
3787 ha->wq = NULL;
3788 }
3789
3790
3791 qla2x00_mem_free(ha);
3792
3793 qla82xx_md_free(vha);
3794
3795 qla2x00_free_queues(ha);
3796 }
3797
3798 void qla2x00_free_fcports(struct scsi_qla_host *vha)
3799 {
3800 fc_port_t *fcport, *tfcport;
3801
3802 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) {
3803 list_del(&fcport->list);
3804 qla2x00_clear_loop_id(fcport);
3805 kfree(fcport);
3806 }
3807 }
3808
3809 static inline void
3810 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport,
3811 int defer)
3812 {
3813 struct fc_rport *rport;
3814 scsi_qla_host_t *base_vha;
3815 unsigned long flags;
3816
3817 if (!fcport->rport)
3818 return;
3819
3820 rport = fcport->rport;
3821 if (defer) {
3822 base_vha = pci_get_drvdata(vha->hw->pdev);
3823 spin_lock_irqsave(vha->host->host_lock, flags);
3824 fcport->drport = rport;
3825 spin_unlock_irqrestore(vha->host->host_lock, flags);
3826 qlt_do_generation_tick(vha, &base_vha->total_fcport_update_gen);
3827 set_bit(FCPORT_UPDATE_NEEDED, &base_vha->dpc_flags);
3828 qla2xxx_wake_dpc(base_vha);
3829 } else {
3830 int now;
3831 if (rport) {
3832 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109,
3833 "%s %8phN. rport %p roles %x\n",
3834 __func__, fcport->port_name, rport,
3835 rport->roles);
3836 fc_remote_port_delete(rport);
3837 }
3838 qlt_do_generation_tick(vha, &now);
3839 }
3840 }
3841
3842 /*
3843 * qla2x00_mark_device_lost Updates fcport state when device goes offline.
3844 *
3845 * Input: ha = adapter block pointer. fcport = port structure pointer.
3846 *
3847 * Return: None.
3848 *
3849 * Context:
3850 */
3851 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport,
3852 int do_login, int defer)
3853 {
3854 if (IS_QLAFX00(vha->hw)) {
3855 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3856 qla2x00_schedule_rport_del(vha, fcport, defer);
3857 return;
3858 }
3859
3860 if (atomic_read(&fcport->state) == FCS_ONLINE &&
3861 vha->vp_idx == fcport->vha->vp_idx) {
3862 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3863 qla2x00_schedule_rport_del(vha, fcport, defer);
3864 }
3865 /*
3866 * We may need to retry the login, so don't change the state of the
3867 * port but do the retries.
3868 */
3869 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD)
3870 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3871
3872 if (!do_login)
3873 return;
3874
3875 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
3876 }
3877
3878 /*
3879 * qla2x00_mark_all_devices_lost
3880 * Updates fcport state when device goes offline.
3881 *
3882 * Input:
3883 * ha = adapter block pointer.
3884 * fcport = port structure pointer.
3885 *
3886 * Return:
3887 * None.
3888 *
3889 * Context:
3890 */
3891 void
3892 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha, int defer)
3893 {
3894 fc_port_t *fcport;
3895
3896 ql_dbg(ql_dbg_disc, vha, 0x20f1,
3897 "Mark all dev lost\n");
3898
3899 list_for_each_entry(fcport, &vha->vp_fcports, list) {
3900 fcport->scan_state = 0;
3901 qlt_schedule_sess_for_deletion(fcport);
3902
3903 if (vha->vp_idx != 0 && vha->vp_idx != fcport->vha->vp_idx)
3904 continue;
3905
3906 /*
3907 * No point in marking the device as lost, if the device is
3908 * already DEAD.
3909 */
3910 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD)
3911 continue;
3912 if (atomic_read(&fcport->state) == FCS_ONLINE) {
3913 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST);
3914 if (defer)
3915 qla2x00_schedule_rport_del(vha, fcport, defer);
3916 else if (vha->vp_idx == fcport->vha->vp_idx)
3917 qla2x00_schedule_rport_del(vha, fcport, defer);
3918 }
3919 }
3920 }
3921
3922 /*
3923 * qla2x00_mem_alloc
3924 * Allocates adapter memory.
3925 *
3926 * Returns:
3927 * 0 = success.
3928 * !0 = failure.
3929 */
3930 static int
3931 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len,
3932 struct req_que **req, struct rsp_que **rsp)
3933 {
3934 char name[16];
3935
3936 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size,
3937 &ha->init_cb_dma, GFP_KERNEL);
3938 if (!ha->init_cb)
3939 goto fail;
3940
3941 if (qlt_mem_alloc(ha) < 0)
3942 goto fail_free_init_cb;
3943
3944 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev,
3945 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL);
3946 if (!ha->gid_list)
3947 goto fail_free_tgt_mem;
3948
3949 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
3950 if (!ha->srb_mempool)
3951 goto fail_free_gid_list;
3952
3953 if (IS_P3P_TYPE(ha)) {
3954 /* Allocate cache for CT6 Ctx. */
3955 if (!ctx_cachep) {
3956 ctx_cachep = kmem_cache_create("qla2xxx_ctx",
3957 sizeof(struct ct6_dsd), 0,
3958 SLAB_HWCACHE_ALIGN, NULL);
3959 if (!ctx_cachep)
3960 goto fail_free_srb_mempool;
3961 }
3962 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ,
3963 ctx_cachep);
3964 if (!ha->ctx_mempool)
3965 goto fail_free_srb_mempool;
3966 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021,
3967 "ctx_cachep=%p ctx_mempool=%p.\n",
3968 ctx_cachep, ha->ctx_mempool);
3969 }
3970
3971 /* Get memory for cached NVRAM */
3972 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL);
3973 if (!ha->nvram)
3974 goto fail_free_ctx_mempool;
3975
3976 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME,
3977 ha->pdev->device);
3978 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3979 DMA_POOL_SIZE, 8, 0);
3980 if (!ha->s_dma_pool)
3981 goto fail_free_nvram;
3982
3983 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022,
3984 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n",
3985 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool);
3986
3987 if (IS_P3P_TYPE(ha) || ql2xenabledif) {
3988 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3989 DSD_LIST_DMA_POOL_SIZE, 8, 0);
3990 if (!ha->dl_dma_pool) {
3991 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023,
3992 "Failed to allocate memory for dl_dma_pool.\n");
3993 goto fail_s_dma_pool;
3994 }
3995
3996 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev,
3997 FCP_CMND_DMA_POOL_SIZE, 8, 0);
3998 if (!ha->fcp_cmnd_dma_pool) {
3999 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024,
4000 "Failed to allocate memory for fcp_cmnd_dma_pool.\n");
4001 goto fail_dl_dma_pool;
4002 }
4003 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025,
4004 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p.\n",
4005 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool);
4006 }
4007
4008 /* Allocate memory for SNS commands */
4009 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4010 /* Get consistent memory allocated for SNS commands */
4011 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev,
4012 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL);
4013 if (!ha->sns_cmd)
4014 goto fail_dma_pool;
4015 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026,
4016 "sns_cmd: %p.\n", ha->sns_cmd);
4017 } else {
4018 /* Get consistent memory allocated for MS IOCB */
4019 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4020 &ha->ms_iocb_dma);
4021 if (!ha->ms_iocb)
4022 goto fail_dma_pool;
4023 /* Get consistent memory allocated for CT SNS commands */
4024 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev,
4025 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL);
4026 if (!ha->ct_sns)
4027 goto fail_free_ms_iocb;
4028 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027,
4029 "ms_iocb=%p ct_sns=%p.\n",
4030 ha->ms_iocb, ha->ct_sns);
4031 }
4032
4033 /* Allocate memory for request ring */
4034 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL);
4035 if (!*req) {
4036 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028,
4037 "Failed to allocate memory for req.\n");
4038 goto fail_req;
4039 }
4040 (*req)->length = req_len;
4041 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev,
4042 ((*req)->length + 1) * sizeof(request_t),
4043 &(*req)->dma, GFP_KERNEL);
4044 if (!(*req)->ring) {
4045 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029,
4046 "Failed to allocate memory for req_ring.\n");
4047 goto fail_req_ring;
4048 }
4049 /* Allocate memory for response ring */
4050 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL);
4051 if (!*rsp) {
4052 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a,
4053 "Failed to allocate memory for rsp.\n");
4054 goto fail_rsp;
4055 }
4056 (*rsp)->hw = ha;
4057 (*rsp)->length = rsp_len;
4058 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev,
4059 ((*rsp)->length + 1) * sizeof(response_t),
4060 &(*rsp)->dma, GFP_KERNEL);
4061 if (!(*rsp)->ring) {
4062 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b,
4063 "Failed to allocate memory for rsp_ring.\n");
4064 goto fail_rsp_ring;
4065 }
4066 (*req)->rsp = *rsp;
4067 (*rsp)->req = *req;
4068 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c,
4069 "req=%p req->length=%d req->ring=%p rsp=%p "
4070 "rsp->length=%d rsp->ring=%p.\n",
4071 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length,
4072 (*rsp)->ring);
4073 /* Allocate memory for NVRAM data for vports */
4074 if (ha->nvram_npiv_size) {
4075 ha->npiv_info = kcalloc(ha->nvram_npiv_size,
4076 sizeof(struct qla_npiv_entry),
4077 GFP_KERNEL);
4078 if (!ha->npiv_info) {
4079 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d,
4080 "Failed to allocate memory for npiv_info.\n");
4081 goto fail_npiv_info;
4082 }
4083 } else
4084 ha->npiv_info = NULL;
4085
4086 /* Get consistent memory allocated for EX-INIT-CB. */
4087 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha)) {
4088 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4089 &ha->ex_init_cb_dma);
4090 if (!ha->ex_init_cb)
4091 goto fail_ex_init_cb;
4092 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e,
4093 "ex_init_cb=%p.\n", ha->ex_init_cb);
4094 }
4095
4096 INIT_LIST_HEAD(&ha->gbl_dsd_list);
4097
4098 /* Get consistent memory allocated for Async Port-Database. */
4099 if (!IS_FWI2_CAPABLE(ha)) {
4100 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL,
4101 &ha->async_pd_dma);
4102 if (!ha->async_pd)
4103 goto fail_async_pd;
4104 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f,
4105 "async_pd=%p.\n", ha->async_pd);
4106 }
4107
4108 INIT_LIST_HEAD(&ha->vp_list);
4109
4110 /* Allocate memory for our loop_id bitmap */
4111 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE),
4112 sizeof(long),
4113 GFP_KERNEL);
4114 if (!ha->loop_id_map)
4115 goto fail_loop_id_map;
4116 else {
4117 qla2x00_set_reserved_loop_ids(ha);
4118 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123,
4119 "loop_id_map=%p.\n", ha->loop_id_map);
4120 }
4121
4122 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev,
4123 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL);
4124 if (!ha->sfp_data) {
4125 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b,
4126 "Unable to allocate memory for SFP read-data.\n");
4127 goto fail_sfp_data;
4128 }
4129
4130 return 0;
4131
4132 fail_sfp_data:
4133 kfree(ha->loop_id_map);
4134 fail_loop_id_map:
4135 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4136 fail_async_pd:
4137 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma);
4138 fail_ex_init_cb:
4139 kfree(ha->npiv_info);
4140 fail_npiv_info:
4141 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) *
4142 sizeof(response_t), (*rsp)->ring, (*rsp)->dma);
4143 (*rsp)->ring = NULL;
4144 (*rsp)->dma = 0;
4145 fail_rsp_ring:
4146 kfree(*rsp);
4147 *rsp = NULL;
4148 fail_rsp:
4149 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) *
4150 sizeof(request_t), (*req)->ring, (*req)->dma);
4151 (*req)->ring = NULL;
4152 (*req)->dma = 0;
4153 fail_req_ring:
4154 kfree(*req);
4155 *req = NULL;
4156 fail_req:
4157 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4158 ha->ct_sns, ha->ct_sns_dma);
4159 ha->ct_sns = NULL;
4160 ha->ct_sns_dma = 0;
4161 fail_free_ms_iocb:
4162 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4163 ha->ms_iocb = NULL;
4164 ha->ms_iocb_dma = 0;
4165
4166 if (ha->sns_cmd)
4167 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4168 ha->sns_cmd, ha->sns_cmd_dma);
4169 fail_dma_pool:
4170 if (IS_QLA82XX(ha) || ql2xenabledif) {
4171 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4172 ha->fcp_cmnd_dma_pool = NULL;
4173 }
4174 fail_dl_dma_pool:
4175 if (IS_QLA82XX(ha) || ql2xenabledif) {
4176 dma_pool_destroy(ha->dl_dma_pool);
4177 ha->dl_dma_pool = NULL;
4178 }
4179 fail_s_dma_pool:
4180 dma_pool_destroy(ha->s_dma_pool);
4181 ha->s_dma_pool = NULL;
4182 fail_free_nvram:
4183 kfree(ha->nvram);
4184 ha->nvram = NULL;
4185 fail_free_ctx_mempool:
4186 if (ha->ctx_mempool)
4187 mempool_destroy(ha->ctx_mempool);
4188 ha->ctx_mempool = NULL;
4189 fail_free_srb_mempool:
4190 if (ha->srb_mempool)
4191 mempool_destroy(ha->srb_mempool);
4192 ha->srb_mempool = NULL;
4193 fail_free_gid_list:
4194 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4195 ha->gid_list,
4196 ha->gid_list_dma);
4197 ha->gid_list = NULL;
4198 ha->gid_list_dma = 0;
4199 fail_free_tgt_mem:
4200 qlt_mem_free(ha);
4201 fail_free_init_cb:
4202 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb,
4203 ha->init_cb_dma);
4204 ha->init_cb = NULL;
4205 ha->init_cb_dma = 0;
4206 fail:
4207 ql_log(ql_log_fatal, NULL, 0x0030,
4208 "Memory allocation failure.\n");
4209 return -ENOMEM;
4210 }
4211
4212 int
4213 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha)
4214 {
4215 int rval;
4216 uint16_t size, max_cnt, temp;
4217 struct qla_hw_data *ha = vha->hw;
4218
4219 /* Return if we don't need to alloacate any extended logins */
4220 if (!ql2xexlogins)
4221 return QLA_SUCCESS;
4222
4223 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha))
4224 return QLA_SUCCESS;
4225
4226 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins);
4227 max_cnt = 0;
4228 rval = qla_get_exlogin_status(vha, &size, &max_cnt);
4229 if (rval != QLA_SUCCESS) {
4230 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029,
4231 "Failed to get exlogin status.\n");
4232 return rval;
4233 }
4234
4235 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins;
4236 temp *= size;
4237
4238 if (temp != ha->exlogin_size) {
4239 qla2x00_free_exlogin_buffer(ha);
4240 ha->exlogin_size = temp;
4241
4242 ql_log(ql_log_info, vha, 0xd024,
4243 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n",
4244 max_cnt, size, temp);
4245
4246 ql_log(ql_log_info, vha, 0xd025,
4247 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size);
4248
4249 /* Get consistent memory for extended logins */
4250 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev,
4251 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL);
4252 if (!ha->exlogin_buf) {
4253 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a,
4254 "Failed to allocate memory for exlogin_buf_dma.\n");
4255 return -ENOMEM;
4256 }
4257 }
4258
4259 /* Now configure the dma buffer */
4260 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma);
4261 if (rval) {
4262 ql_log(ql_log_fatal, vha, 0xd033,
4263 "Setup extended login buffer ****FAILED****.\n");
4264 qla2x00_free_exlogin_buffer(ha);
4265 }
4266
4267 return rval;
4268 }
4269
4270 /*
4271 * qla2x00_free_exlogin_buffer
4272 *
4273 * Input:
4274 * ha = adapter block pointer
4275 */
4276 void
4277 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha)
4278 {
4279 if (ha->exlogin_buf) {
4280 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size,
4281 ha->exlogin_buf, ha->exlogin_buf_dma);
4282 ha->exlogin_buf = NULL;
4283 ha->exlogin_size = 0;
4284 }
4285 }
4286
4287 static void
4288 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt)
4289 {
4290 u32 temp;
4291 struct init_cb_81xx *icb = (struct init_cb_81xx *)&vha->hw->init_cb;
4292 *ret_cnt = FW_DEF_EXCHANGES_CNT;
4293
4294 if (max_cnt > vha->hw->max_exchg)
4295 max_cnt = vha->hw->max_exchg;
4296
4297 if (qla_ini_mode_enabled(vha)) {
4298 if (vha->ql2xiniexchg > max_cnt)
4299 vha->ql2xiniexchg = max_cnt;
4300
4301 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT)
4302 *ret_cnt = vha->ql2xiniexchg;
4303
4304 } else if (qla_tgt_mode_enabled(vha)) {
4305 if (vha->ql2xexchoffld > max_cnt) {
4306 vha->ql2xexchoffld = max_cnt;
4307 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4308 }
4309
4310 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT)
4311 *ret_cnt = vha->ql2xexchoffld;
4312 } else if (qla_dual_mode_enabled(vha)) {
4313 temp = vha->ql2xiniexchg + vha->ql2xexchoffld;
4314 if (temp > max_cnt) {
4315 vha->ql2xiniexchg -= (temp - max_cnt)/2;
4316 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1);
4317 temp = max_cnt;
4318 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4319 }
4320
4321 if (temp > FW_DEF_EXCHANGES_CNT)
4322 *ret_cnt = temp;
4323 }
4324 }
4325
4326 int
4327 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha)
4328 {
4329 int rval;
4330 u16 size, max_cnt;
4331 u32 actual_cnt, totsz;
4332 struct qla_hw_data *ha = vha->hw;
4333
4334 if (!ha->flags.exchoffld_enabled)
4335 return QLA_SUCCESS;
4336
4337 if (!IS_EXCHG_OFFLD_CAPABLE(ha))
4338 return QLA_SUCCESS;
4339
4340 max_cnt = 0;
4341 rval = qla_get_exchoffld_status(vha, &size, &max_cnt);
4342 if (rval != QLA_SUCCESS) {
4343 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012,
4344 "Failed to get exlogin status.\n");
4345 return rval;
4346 }
4347
4348 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt);
4349 ql_log(ql_log_info, vha, 0xd014,
4350 "Actual exchange offload count: %d.\n", actual_cnt);
4351
4352 totsz = actual_cnt * size;
4353
4354 if (totsz != ha->exchoffld_size) {
4355 qla2x00_free_exchoffld_buffer(ha);
4356 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) {
4357 ha->exchoffld_size = 0;
4358 ha->flags.exchoffld_enabled = 0;
4359 return QLA_SUCCESS;
4360 }
4361
4362 ha->exchoffld_size = totsz;
4363
4364 ql_log(ql_log_info, vha, 0xd016,
4365 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n",
4366 max_cnt, actual_cnt, size, totsz);
4367
4368 ql_log(ql_log_info, vha, 0xd017,
4369 "Exchange Buffers requested size = 0x%x\n",
4370 ha->exchoffld_size);
4371
4372 /* Get consistent memory for extended logins */
4373 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev,
4374 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL);
4375 if (!ha->exchoffld_buf) {
4376 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4377 "Failed to allocate memory for Exchange Offload.\n");
4378
4379 if (ha->max_exchg >
4380 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) {
4381 ha->max_exchg -= REDUCE_EXCHANGES_CNT;
4382 } else if (ha->max_exchg >
4383 (FW_DEF_EXCHANGES_CNT + 512)) {
4384 ha->max_exchg -= 512;
4385 } else {
4386 ha->flags.exchoffld_enabled = 0;
4387 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013,
4388 "Disabling Exchange offload due to lack of memory\n");
4389 }
4390 ha->exchoffld_size = 0;
4391
4392 return -ENOMEM;
4393 }
4394 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) {
4395 /* pathological case */
4396 qla2x00_free_exchoffld_buffer(ha);
4397 ha->exchoffld_size = 0;
4398 ha->flags.exchoffld_enabled = 0;
4399 ql_log(ql_log_info, vha, 0xd016,
4400 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n",
4401 ha->exchoffld_size, actual_cnt, size, totsz);
4402 return 0;
4403 }
4404
4405 /* Now configure the dma buffer */
4406 rval = qla_set_exchoffld_mem_cfg(vha);
4407 if (rval) {
4408 ql_log(ql_log_fatal, vha, 0xd02e,
4409 "Setup exchange offload buffer ****FAILED****.\n");
4410 qla2x00_free_exchoffld_buffer(ha);
4411 } else {
4412 /* re-adjust number of target exchange */
4413 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb;
4414
4415 if (qla_ini_mode_enabled(vha))
4416 icb->exchange_count = 0;
4417 else
4418 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld);
4419 }
4420
4421 return rval;
4422 }
4423
4424 /*
4425 * qla2x00_free_exchoffld_buffer
4426 *
4427 * Input:
4428 * ha = adapter block pointer
4429 */
4430 void
4431 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha)
4432 {
4433 if (ha->exchoffld_buf) {
4434 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size,
4435 ha->exchoffld_buf, ha->exchoffld_buf_dma);
4436 ha->exchoffld_buf = NULL;
4437 ha->exchoffld_size = 0;
4438 }
4439 }
4440
4441 /*
4442 * qla2x00_free_fw_dump
4443 * Frees fw dump stuff.
4444 *
4445 * Input:
4446 * ha = adapter block pointer
4447 */
4448 static void
4449 qla2x00_free_fw_dump(struct qla_hw_data *ha)
4450 {
4451 if (ha->fce)
4452 dma_free_coherent(&ha->pdev->dev,
4453 FCE_SIZE, ha->fce, ha->fce_dma);
4454
4455 if (ha->eft)
4456 dma_free_coherent(&ha->pdev->dev,
4457 EFT_SIZE, ha->eft, ha->eft_dma);
4458
4459 if (ha->fw_dump)
4460 vfree(ha->fw_dump);
4461 if (ha->fw_dump_template)
4462 vfree(ha->fw_dump_template);
4463
4464 ha->fce = NULL;
4465 ha->fce_dma = 0;
4466 ha->eft = NULL;
4467 ha->eft_dma = 0;
4468 ha->fw_dumped = 0;
4469 ha->fw_dump_cap_flags = 0;
4470 ha->fw_dump_reading = 0;
4471 ha->fw_dump = NULL;
4472 ha->fw_dump_len = 0;
4473 ha->fw_dump_template = NULL;
4474 ha->fw_dump_template_len = 0;
4475 }
4476
4477 /*
4478 * qla2x00_mem_free
4479 * Frees all adapter allocated memory.
4480 *
4481 * Input:
4482 * ha = adapter block pointer.
4483 */
4484 static void
4485 qla2x00_mem_free(struct qla_hw_data *ha)
4486 {
4487 qla2x00_free_fw_dump(ha);
4488
4489 if (ha->mctp_dump)
4490 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump,
4491 ha->mctp_dump_dma);
4492
4493 if (ha->srb_mempool)
4494 mempool_destroy(ha->srb_mempool);
4495
4496 if (ha->dcbx_tlv)
4497 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE,
4498 ha->dcbx_tlv, ha->dcbx_tlv_dma);
4499
4500 if (ha->xgmac_data)
4501 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE,
4502 ha->xgmac_data, ha->xgmac_data_dma);
4503
4504 if (ha->sns_cmd)
4505 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt),
4506 ha->sns_cmd, ha->sns_cmd_dma);
4507
4508 if (ha->ct_sns)
4509 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt),
4510 ha->ct_sns, ha->ct_sns_dma);
4511
4512 if (ha->sfp_data)
4513 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data,
4514 ha->sfp_data_dma);
4515
4516 if (ha->ms_iocb)
4517 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma);
4518
4519 if (ha->ex_init_cb)
4520 dma_pool_free(ha->s_dma_pool,
4521 ha->ex_init_cb, ha->ex_init_cb_dma);
4522
4523 if (ha->async_pd)
4524 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma);
4525
4526 if (ha->s_dma_pool)
4527 dma_pool_destroy(ha->s_dma_pool);
4528
4529 if (ha->gid_list)
4530 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha),
4531 ha->gid_list, ha->gid_list_dma);
4532
4533 if (IS_QLA82XX(ha)) {
4534 if (!list_empty(&ha->gbl_dsd_list)) {
4535 struct dsd_dma *dsd_ptr, *tdsd_ptr;
4536
4537 /* clean up allocated prev pool */
4538 list_for_each_entry_safe(dsd_ptr,
4539 tdsd_ptr, &ha->gbl_dsd_list, list) {
4540 dma_pool_free(ha->dl_dma_pool,
4541 dsd_ptr->dsd_addr, dsd_ptr->dsd_list_dma);
4542 list_del(&dsd_ptr->list);
4543 kfree(dsd_ptr);
4544 }
4545 }
4546 }
4547
4548 if (ha->dl_dma_pool)
4549 dma_pool_destroy(ha->dl_dma_pool);
4550
4551 if (ha->fcp_cmnd_dma_pool)
4552 dma_pool_destroy(ha->fcp_cmnd_dma_pool);
4553
4554 if (ha->ctx_mempool)
4555 mempool_destroy(ha->ctx_mempool);
4556
4557 qlt_mem_free(ha);
4558
4559 if (ha->init_cb)
4560 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size,
4561 ha->init_cb, ha->init_cb_dma);
4562
4563 vfree(ha->optrom_buffer);
4564 kfree(ha->nvram);
4565 kfree(ha->npiv_info);
4566 kfree(ha->swl);
4567 kfree(ha->loop_id_map);
4568
4569 ha->srb_mempool = NULL;
4570 ha->ctx_mempool = NULL;
4571 ha->sns_cmd = NULL;
4572 ha->sns_cmd_dma = 0;
4573 ha->ct_sns = NULL;
4574 ha->ct_sns_dma = 0;
4575 ha->ms_iocb = NULL;
4576 ha->ms_iocb_dma = 0;
4577 ha->init_cb = NULL;
4578 ha->init_cb_dma = 0;
4579 ha->ex_init_cb = NULL;
4580 ha->ex_init_cb_dma = 0;
4581 ha->async_pd = NULL;
4582 ha->async_pd_dma = 0;
4583 ha->loop_id_map = NULL;
4584 ha->npiv_info = NULL;
4585 ha->optrom_buffer = NULL;
4586 ha->swl = NULL;
4587 ha->nvram = NULL;
4588 ha->mctp_dump = NULL;
4589 ha->dcbx_tlv = NULL;
4590 ha->xgmac_data = NULL;
4591 ha->sfp_data = NULL;
4592
4593 ha->s_dma_pool = NULL;
4594 ha->dl_dma_pool = NULL;
4595 ha->fcp_cmnd_dma_pool = NULL;
4596
4597 ha->gid_list = NULL;
4598 ha->gid_list_dma = 0;
4599
4600 ha->tgt.atio_ring = NULL;
4601 ha->tgt.atio_dma = 0;
4602 ha->tgt.tgt_vp_map = NULL;
4603 }
4604
4605 struct scsi_qla_host *qla2x00_create_host(struct scsi_host_template *sht,
4606 struct qla_hw_data *ha)
4607 {
4608 struct Scsi_Host *host;
4609 struct scsi_qla_host *vha = NULL;
4610
4611 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t));
4612 if (!host) {
4613 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107,
4614 "Failed to allocate host from the scsi layer, aborting.\n");
4615 return NULL;
4616 }
4617
4618 /* Clear our data area */
4619 vha = shost_priv(host);
4620 memset(vha, 0, sizeof(scsi_qla_host_t));
4621
4622 vha->host = host;
4623 vha->host_no = host->host_no;
4624 vha->hw = ha;
4625
4626 vha->qlini_mode = ql2x_ini_mode;
4627 vha->ql2xexchoffld = ql2xexchoffld;
4628 vha->ql2xiniexchg = ql2xiniexchg;
4629
4630 INIT_LIST_HEAD(&vha->vp_fcports);
4631 INIT_LIST_HEAD(&vha->work_list);
4632 INIT_LIST_HEAD(&vha->list);
4633 INIT_LIST_HEAD(&vha->qla_cmd_list);
4634 INIT_LIST_HEAD(&vha->qla_sess_op_cmd_list);
4635 INIT_LIST_HEAD(&vha->logo_list);
4636 INIT_LIST_HEAD(&vha->plogi_ack_list);
4637 INIT_LIST_HEAD(&vha->qp_list);
4638 INIT_LIST_HEAD(&vha->gnl.fcports);
4639 INIT_LIST_HEAD(&vha->nvme_rport_list);
4640 INIT_LIST_HEAD(&vha->gpnid_list);
4641 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn);
4642
4643 spin_lock_init(&vha->work_lock);
4644 spin_lock_init(&vha->cmd_list_lock);
4645 init_waitqueue_head(&vha->fcport_waitQ);
4646 init_waitqueue_head(&vha->vref_waitq);
4647
4648 vha->gnl.size = sizeof(struct get_name_list_extended) *
4649 (ha->max_loop_id + 1);
4650 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev,
4651 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL);
4652 if (!vha->gnl.l) {
4653 ql_log(ql_log_fatal, vha, 0xd04a,
4654 "Alloc failed for name list.\n");
4655 scsi_remove_host(vha->host);
4656 return NULL;
4657 }
4658
4659 /* todo: what about ext login? */
4660 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp);
4661 vha->scan.l = vmalloc(vha->scan.size);
4662 if (!vha->scan.l) {
4663 ql_log(ql_log_fatal, vha, 0xd04a,
4664 "Alloc failed for scan database.\n");
4665 dma_free_coherent(&ha->pdev->dev, vha->gnl.size,
4666 vha->gnl.l, vha->gnl.ldma);
4667 scsi_remove_host(vha->host);
4668 return NULL;
4669 }
4670 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn);
4671
4672 sprintf(vha->host_str, "%s_%ld", QLA2XXX_DRIVER_NAME, vha->host_no);
4673 ql_dbg(ql_dbg_init, vha, 0x0041,
4674 "Allocated the host=%p hw=%p vha=%p dev_name=%s",
4675 vha->host, vha->hw, vha,
4676 dev_name(&(ha->pdev->dev)));
4677
4678 return vha;
4679 }
4680
4681 struct qla_work_evt *
4682 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type)
4683 {
4684 struct qla_work_evt *e;
4685 uint8_t bail;
4686
4687 QLA_VHA_MARK_BUSY(vha, bail);
4688 if (bail)
4689 return NULL;
4690
4691 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC);
4692 if (!e) {
4693 QLA_VHA_MARK_NOT_BUSY(vha);
4694 return NULL;
4695 }
4696
4697 INIT_LIST_HEAD(&e->list);
4698 e->type = type;
4699 e->flags = QLA_EVT_FLAG_FREE;
4700 return e;
4701 }
4702
4703 int
4704 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e)
4705 {
4706 unsigned long flags;
4707 bool q = false;
4708
4709 spin_lock_irqsave(&vha->work_lock, flags);
4710 list_add_tail(&e->list, &vha->work_list);
4711
4712 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
4713 q = true;
4714
4715 spin_unlock_irqrestore(&vha->work_lock, flags);
4716
4717 if (q)
4718 queue_work(vha->hw->wq, &vha->iocb_work);
4719
4720 return QLA_SUCCESS;
4721 }
4722
4723 int
4724 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code,
4725 u32 data)
4726 {
4727 struct qla_work_evt *e;
4728
4729 e = qla2x00_alloc_work(vha, QLA_EVT_AEN);
4730 if (!e)
4731 return QLA_FUNCTION_FAILED;
4732
4733 e->u.aen.code = code;
4734 e->u.aen.data = data;
4735 return qla2x00_post_work(vha, e);
4736 }
4737
4738 int
4739 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb)
4740 {
4741 struct qla_work_evt *e;
4742
4743 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK);
4744 if (!e)
4745 return QLA_FUNCTION_FAILED;
4746
4747 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t));
4748 return qla2x00_post_work(vha, e);
4749 }
4750
4751 #define qla2x00_post_async_work(name, type) \
4752 int qla2x00_post_async_##name##_work( \
4753 struct scsi_qla_host *vha, \
4754 fc_port_t *fcport, uint16_t *data) \
4755 { \
4756 struct qla_work_evt *e; \
4757 \
4758 e = qla2x00_alloc_work(vha, type); \
4759 if (!e) \
4760 return QLA_FUNCTION_FAILED; \
4761 \
4762 e->u.logio.fcport = fcport; \
4763 if (data) { \
4764 e->u.logio.data[0] = data[0]; \
4765 e->u.logio.data[1] = data[1]; \
4766 } \
4767 fcport->flags |= FCF_ASYNC_ACTIVE; \
4768 return qla2x00_post_work(vha, e); \
4769 }
4770
4771 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN);
4772 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT);
4773 qla2x00_post_async_work(logout_done, QLA_EVT_ASYNC_LOGOUT_DONE);
4774 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC);
4775 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO);
4776 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE);
4777
4778 int
4779 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code)
4780 {
4781 struct qla_work_evt *e;
4782
4783 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT);
4784 if (!e)
4785 return QLA_FUNCTION_FAILED;
4786
4787 e->u.uevent.code = code;
4788 return qla2x00_post_work(vha, e);
4789 }
4790
4791 static void
4792 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code)
4793 {
4794 char event_string[40];
4795 char *envp[] = { event_string, NULL };
4796
4797 switch (code) {
4798 case QLA_UEVENT_CODE_FW_DUMP:
4799 snprintf(event_string, sizeof(event_string), "FW_DUMP=%ld",
4800 vha->host_no);
4801 break;
4802 default:
4803 /* do nothing */
4804 break;
4805 }
4806 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp);
4807 }
4808
4809 int
4810 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode,
4811 uint32_t *data, int cnt)
4812 {
4813 struct qla_work_evt *e;
4814
4815 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX);
4816 if (!e)
4817 return QLA_FUNCTION_FAILED;
4818
4819 e->u.aenfx.evtcode = evtcode;
4820 e->u.aenfx.count = cnt;
4821 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt);
4822 return qla2x00_post_work(vha, e);
4823 }
4824
4825 void qla24xx_sched_upd_fcport(fc_port_t *fcport)
4826 {
4827 unsigned long flags;
4828
4829 if (IS_SW_RESV_ADDR(fcport->d_id))
4830 return;
4831
4832 spin_lock_irqsave(&fcport->vha->work_lock, flags);
4833 if (fcport->disc_state == DSC_UPD_FCPORT) {
4834 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
4835 return;
4836 }
4837 fcport->jiffies_at_registration = jiffies;
4838 fcport->sec_since_registration = 0;
4839 fcport->next_disc_state = DSC_DELETED;
4840 fcport->disc_state = DSC_UPD_FCPORT;
4841 spin_unlock_irqrestore(&fcport->vha->work_lock, flags);
4842
4843 queue_work(system_unbound_wq, &fcport->reg_work);
4844 }
4845
4846 static
4847 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e)
4848 {
4849 unsigned long flags;
4850 fc_port_t *fcport = NULL, *tfcp;
4851 struct qlt_plogi_ack_t *pla =
4852 (struct qlt_plogi_ack_t *)e->u.new_sess.pla;
4853 uint8_t free_fcport = 0;
4854
4855 ql_dbg(ql_dbg_disc, vha, 0xffff,
4856 "%s %d %8phC enter\n",
4857 __func__, __LINE__, e->u.new_sess.port_name);
4858
4859 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4860 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1);
4861 if (fcport) {
4862 fcport->d_id = e->u.new_sess.id;
4863 if (pla) {
4864 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4865 memcpy(fcport->node_name,
4866 pla->iocb.u.isp24.u.plogi.node_name,
4867 WWN_SIZE);
4868 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN);
4869 /* we took an extra ref_count to prevent PLOGI ACK when
4870 * fcport/sess has not been created.
4871 */
4872 pla->ref_count--;
4873 }
4874 } else {
4875 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4876 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
4877 if (fcport) {
4878 fcport->d_id = e->u.new_sess.id;
4879 fcport->flags |= FCF_FABRIC_DEVICE;
4880 fcport->fw_login_state = DSC_LS_PLOGI_PEND;
4881 if (e->u.new_sess.fc4_type & FS_FC4TYPE_FCP)
4882 fcport->fc4_type = FC4_TYPE_FCP_SCSI;
4883
4884 if (e->u.new_sess.fc4_type & FS_FC4TYPE_NVME) {
4885 fcport->fc4_type = FC4_TYPE_OTHER;
4886 fcport->fc4f_nvme = FC4_TYPE_NVME;
4887 }
4888
4889 memcpy(fcport->port_name, e->u.new_sess.port_name,
4890 WWN_SIZE);
4891 } else {
4892 ql_dbg(ql_dbg_disc, vha, 0xffff,
4893 "%s %8phC mem alloc fail.\n",
4894 __func__, e->u.new_sess.port_name);
4895
4896 if (pla)
4897 kmem_cache_free(qla_tgt_plogi_cachep, pla);
4898 return;
4899 }
4900
4901 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4902 /* search again to make sure no one else got ahead */
4903 tfcp = qla2x00_find_fcport_by_wwpn(vha,
4904 e->u.new_sess.port_name, 1);
4905 if (tfcp) {
4906 /* should rarily happen */
4907 ql_dbg(ql_dbg_disc, vha, 0xffff,
4908 "%s %8phC found existing fcport b4 add. DS %d LS %d\n",
4909 __func__, tfcp->port_name, tfcp->disc_state,
4910 tfcp->fw_login_state);
4911
4912 free_fcport = 1;
4913 } else {
4914 list_add_tail(&fcport->list, &vha->vp_fcports);
4915
4916 }
4917 if (pla) {
4918 qlt_plogi_ack_link(vha, pla, fcport,
4919 QLT_PLOGI_LINK_SAME_WWN);
4920 pla->ref_count--;
4921 }
4922 }
4923 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4924
4925 if (fcport) {
4926 fcport->id_changed = 1;
4927 fcport->scan_state = QLA_FCPORT_FOUND;
4928 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE);
4929
4930 if (pla) {
4931 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) {
4932 u16 wd3_lo;
4933
4934 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4935 fcport->local = 0;
4936 fcport->loop_id =
4937 le16_to_cpu(
4938 pla->iocb.u.isp24.nport_handle);
4939 fcport->fw_login_state = DSC_LS_PRLI_PEND;
4940 wd3_lo =
4941 le16_to_cpu(
4942 pla->iocb.u.isp24.u.prli.wd3_lo);
4943
4944 if (wd3_lo & BIT_7)
4945 fcport->conf_compl_supported = 1;
4946
4947 if ((wd3_lo & BIT_4) == 0)
4948 fcport->port_type = FCT_INITIATOR;
4949 else
4950 fcport->port_type = FCT_TARGET;
4951 }
4952 qlt_plogi_ack_unref(vha, pla);
4953 } else {
4954 fc_port_t *dfcp = NULL;
4955
4956 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
4957 tfcp = qla2x00_find_fcport_by_nportid(vha,
4958 &e->u.new_sess.id, 1);
4959 if (tfcp && (tfcp != fcport)) {
4960 /*
4961 * We have a conflict fcport with same NportID.
4962 */
4963 ql_dbg(ql_dbg_disc, vha, 0xffff,
4964 "%s %8phC found conflict b4 add. DS %d LS %d\n",
4965 __func__, tfcp->port_name, tfcp->disc_state,
4966 tfcp->fw_login_state);
4967
4968 switch (tfcp->disc_state) {
4969 case DSC_DELETED:
4970 break;
4971 case DSC_DELETE_PEND:
4972 fcport->login_pause = 1;
4973 tfcp->conflict = fcport;
4974 break;
4975 default:
4976 fcport->login_pause = 1;
4977 tfcp->conflict = fcport;
4978 dfcp = tfcp;
4979 break;
4980 }
4981 }
4982 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
4983 if (dfcp)
4984 qlt_schedule_sess_for_deletion(tfcp);
4985
4986
4987 if (N2N_TOPO(vha->hw))
4988 fcport->flags &= ~FCF_FABRIC_DEVICE;
4989
4990 if (N2N_TOPO(vha->hw)) {
4991 if (vha->flags.nvme_enabled) {
4992 fcport->fc4f_nvme = 1;
4993 fcport->n2n_flag = 1;
4994 }
4995 fcport->fw_login_state = 0;
4996 /*
4997 * wait link init done before sending login
4998 */
4999 } else {
5000 qla24xx_fcport_handle_login(vha, fcport);
5001 }
5002 }
5003 }
5004
5005 if (free_fcport) {
5006 qla2x00_free_fcport(fcport);
5007 if (pla)
5008 kmem_cache_free(qla_tgt_plogi_cachep, pla);
5009 }
5010 }
5011
5012 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e)
5013 {
5014 struct srb *sp = e->u.iosb.sp;
5015 int rval;
5016
5017 rval = qla2x00_start_sp(sp);
5018 if (rval != QLA_SUCCESS) {
5019 ql_dbg(ql_dbg_disc, vha, 0x2043,
5020 "%s: %s: Re-issue IOCB failed (%d).\n",
5021 __func__, sp->name, rval);
5022 qla24xx_sp_unmap(vha, sp);
5023 }
5024 }
5025
5026 void
5027 qla2x00_do_work(struct scsi_qla_host *vha)
5028 {
5029 struct qla_work_evt *e, *tmp;
5030 unsigned long flags;
5031 LIST_HEAD(work);
5032
5033 spin_lock_irqsave(&vha->work_lock, flags);
5034 list_splice_init(&vha->work_list, &work);
5035 spin_unlock_irqrestore(&vha->work_lock, flags);
5036
5037 list_for_each_entry_safe(e, tmp, &work, list) {
5038 list_del_init(&e->list);
5039
5040 switch (e->type) {
5041 case QLA_EVT_AEN:
5042 fc_host_post_event(vha->host, fc_get_event_number(),
5043 e->u.aen.code, e->u.aen.data);
5044 break;
5045 case QLA_EVT_IDC_ACK:
5046 qla81xx_idc_ack(vha, e->u.idc_ack.mb);
5047 break;
5048 case QLA_EVT_ASYNC_LOGIN:
5049 qla2x00_async_login(vha, e->u.logio.fcport,
5050 e->u.logio.data);
5051 break;
5052 case QLA_EVT_ASYNC_LOGOUT:
5053 qla2x00_async_logout(vha, e->u.logio.fcport);
5054 break;
5055 case QLA_EVT_ASYNC_LOGOUT_DONE:
5056 qla2x00_async_logout_done(vha, e->u.logio.fcport,
5057 e->u.logio.data);
5058 break;
5059 case QLA_EVT_ASYNC_ADISC:
5060 qla2x00_async_adisc(vha, e->u.logio.fcport,
5061 e->u.logio.data);
5062 break;
5063 case QLA_EVT_UEVENT:
5064 qla2x00_uevent_emit(vha, e->u.uevent.code);
5065 break;
5066 case QLA_EVT_AENFX:
5067 qlafx00_process_aen(vha, e);
5068 break;
5069 case QLA_EVT_GPNID:
5070 qla24xx_async_gpnid(vha, &e->u.gpnid.id);
5071 break;
5072 case QLA_EVT_UNMAP:
5073 qla24xx_sp_unmap(vha, e->u.iosb.sp);
5074 break;
5075 case QLA_EVT_RELOGIN:
5076 qla2x00_relogin(vha);
5077 break;
5078 case QLA_EVT_NEW_SESS:
5079 qla24xx_create_new_sess(vha, e);
5080 break;
5081 case QLA_EVT_GPDB:
5082 qla24xx_async_gpdb(vha, e->u.fcport.fcport,
5083 e->u.fcport.opt);
5084 break;
5085 case QLA_EVT_PRLI:
5086 qla24xx_async_prli(vha, e->u.fcport.fcport);
5087 break;
5088 case QLA_EVT_GPSC:
5089 qla24xx_async_gpsc(vha, e->u.fcport.fcport);
5090 break;
5091 case QLA_EVT_GNL:
5092 qla24xx_async_gnl(vha, e->u.fcport.fcport);
5093 break;
5094 case QLA_EVT_NACK:
5095 qla24xx_do_nack_work(vha, e);
5096 break;
5097 case QLA_EVT_ASYNC_PRLO:
5098 qla2x00_async_prlo(vha, e->u.logio.fcport);
5099 break;
5100 case QLA_EVT_ASYNC_PRLO_DONE:
5101 qla2x00_async_prlo_done(vha, e->u.logio.fcport,
5102 e->u.logio.data);
5103 break;
5104 case QLA_EVT_GPNFT:
5105 qla24xx_async_gpnft(vha, e->u.gpnft.fc4_type,
5106 e->u.gpnft.sp);
5107 break;
5108 case QLA_EVT_GPNFT_DONE:
5109 qla24xx_async_gpnft_done(vha, e->u.iosb.sp);
5110 break;
5111 case QLA_EVT_GNNFT_DONE:
5112 qla24xx_async_gnnft_done(vha, e->u.iosb.sp);
5113 break;
5114 case QLA_EVT_GNNID:
5115 qla24xx_async_gnnid(vha, e->u.fcport.fcport);
5116 break;
5117 case QLA_EVT_GFPNID:
5118 qla24xx_async_gfpnid(vha, e->u.fcport.fcport);
5119 break;
5120 case QLA_EVT_SP_RETRY:
5121 qla_sp_retry(vha, e);
5122 break;
5123 case QLA_EVT_IIDMA:
5124 qla_do_iidma_work(vha, e->u.fcport.fcport);
5125 break;
5126 case QLA_EVT_ELS_PLOGI:
5127 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI,
5128 e->u.fcport.fcport, false);
5129 break;
5130 }
5131 if (e->flags & QLA_EVT_FLAG_FREE)
5132 kfree(e);
5133
5134 /* For each work completed decrement vha ref count */
5135 QLA_VHA_MARK_NOT_BUSY(vha);
5136 }
5137 }
5138
5139 int qla24xx_post_relogin_work(struct scsi_qla_host *vha)
5140 {
5141 struct qla_work_evt *e;
5142
5143 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN);
5144
5145 if (!e) {
5146 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5147 return QLA_FUNCTION_FAILED;
5148 }
5149
5150 return qla2x00_post_work(vha, e);
5151 }
5152
5153 /* Relogins all the fcports of a vport
5154 * Context: dpc thread
5155 */
5156 void qla2x00_relogin(struct scsi_qla_host *vha)
5157 {
5158 fc_port_t *fcport;
5159 int status, relogin_needed = 0;
5160 struct event_arg ea;
5161
5162 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5163 /*
5164 * If the port is not ONLINE then try to login
5165 * to it if we haven't run out of retries.
5166 */
5167 if (atomic_read(&fcport->state) != FCS_ONLINE &&
5168 fcport->login_retry) {
5169 if (fcport->scan_state != QLA_FCPORT_FOUND ||
5170 fcport->disc_state == DSC_LOGIN_COMPLETE)
5171 continue;
5172
5173 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) ||
5174 fcport->disc_state == DSC_DELETE_PEND) {
5175 relogin_needed = 1;
5176 } else {
5177 if (vha->hw->current_topology != ISP_CFG_NL) {
5178 memset(&ea, 0, sizeof(ea));
5179 ea.event = FCME_RELOGIN;
5180 ea.fcport = fcport;
5181 qla2x00_fcport_event_handler(vha, &ea);
5182 } else if (vha->hw->current_topology ==
5183 ISP_CFG_NL) {
5184 fcport->login_retry--;
5185 status =
5186 qla2x00_local_device_login(vha,
5187 fcport);
5188 if (status == QLA_SUCCESS) {
5189 fcport->old_loop_id =
5190 fcport->loop_id;
5191 ql_dbg(ql_dbg_disc, vha, 0x2003,
5192 "Port login OK: logged in ID 0x%x.\n",
5193 fcport->loop_id);
5194 qla2x00_update_fcport
5195 (vha, fcport);
5196 } else if (status == 1) {
5197 set_bit(RELOGIN_NEEDED,
5198 &vha->dpc_flags);
5199 /* retry the login again */
5200 ql_dbg(ql_dbg_disc, vha, 0x2007,
5201 "Retrying %d login again loop_id 0x%x.\n",
5202 fcport->login_retry,
5203 fcport->loop_id);
5204 } else {
5205 fcport->login_retry = 0;
5206 }
5207
5208 if (fcport->login_retry == 0 &&
5209 status != QLA_SUCCESS)
5210 qla2x00_clear_loop_id(fcport);
5211 }
5212 }
5213 }
5214 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5215 break;
5216 }
5217
5218 if (relogin_needed)
5219 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5220
5221 ql_dbg(ql_dbg_disc, vha, 0x400e,
5222 "Relogin end.\n");
5223 }
5224
5225 /* Schedule work on any of the dpc-workqueues */
5226 void
5227 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code)
5228 {
5229 struct qla_hw_data *ha = base_vha->hw;
5230
5231 switch (work_code) {
5232 case MBA_IDC_AEN: /* 0x8200 */
5233 if (ha->dpc_lp_wq)
5234 queue_work(ha->dpc_lp_wq, &ha->idc_aen);
5235 break;
5236
5237 case QLA83XX_NIC_CORE_RESET: /* 0x1 */
5238 if (!ha->flags.nic_core_reset_hdlr_active) {
5239 if (ha->dpc_hp_wq)
5240 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset);
5241 } else
5242 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e,
5243 "NIC Core reset is already active. Skip "
5244 "scheduling it again.\n");
5245 break;
5246 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */
5247 if (ha->dpc_hp_wq)
5248 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler);
5249 break;
5250 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */
5251 if (ha->dpc_hp_wq)
5252 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable);
5253 break;
5254 default:
5255 ql_log(ql_log_warn, base_vha, 0xb05f,
5256 "Unknown work-code=0x%x.\n", work_code);
5257 }
5258
5259 return;
5260 }
5261
5262 /* Work: Perform NIC Core Unrecoverable state handling */
5263 void
5264 qla83xx_nic_core_unrecoverable_work(struct work_struct *work)
5265 {
5266 struct qla_hw_data *ha =
5267 container_of(work, struct qla_hw_data, nic_core_unrecoverable);
5268 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5269 uint32_t dev_state = 0;
5270
5271 qla83xx_idc_lock(base_vha, 0);
5272 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5273 qla83xx_reset_ownership(base_vha);
5274 if (ha->flags.nic_core_reset_owner) {
5275 ha->flags.nic_core_reset_owner = 0;
5276 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5277 QLA8XXX_DEV_FAILED);
5278 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n");
5279 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5280 }
5281 qla83xx_idc_unlock(base_vha, 0);
5282 }
5283
5284 /* Work: Execute IDC state handler */
5285 void
5286 qla83xx_idc_state_handler_work(struct work_struct *work)
5287 {
5288 struct qla_hw_data *ha =
5289 container_of(work, struct qla_hw_data, idc_state_handler);
5290 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5291 uint32_t dev_state = 0;
5292
5293 qla83xx_idc_lock(base_vha, 0);
5294 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5295 if (dev_state == QLA8XXX_DEV_FAILED ||
5296 dev_state == QLA8XXX_DEV_NEED_QUIESCENT)
5297 qla83xx_idc_state_handler(base_vha);
5298 qla83xx_idc_unlock(base_vha, 0);
5299 }
5300
5301 static int
5302 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha)
5303 {
5304 int rval = QLA_SUCCESS;
5305 unsigned long heart_beat_wait = jiffies + (1 * HZ);
5306 uint32_t heart_beat_counter1, heart_beat_counter2;
5307
5308 do {
5309 if (time_after(jiffies, heart_beat_wait)) {
5310 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c,
5311 "Nic Core f/w is not alive.\n");
5312 rval = QLA_FUNCTION_FAILED;
5313 break;
5314 }
5315
5316 qla83xx_idc_lock(base_vha, 0);
5317 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5318 &heart_beat_counter1);
5319 qla83xx_idc_unlock(base_vha, 0);
5320 msleep(100);
5321 qla83xx_idc_lock(base_vha, 0);
5322 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT,
5323 &heart_beat_counter2);
5324 qla83xx_idc_unlock(base_vha, 0);
5325 } while (heart_beat_counter1 == heart_beat_counter2);
5326
5327 return rval;
5328 }
5329
5330 /* Work: Perform NIC Core Reset handling */
5331 void
5332 qla83xx_nic_core_reset_work(struct work_struct *work)
5333 {
5334 struct qla_hw_data *ha =
5335 container_of(work, struct qla_hw_data, nic_core_reset);
5336 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5337 uint32_t dev_state = 0;
5338
5339 if (IS_QLA2031(ha)) {
5340 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS)
5341 ql_log(ql_log_warn, base_vha, 0xb081,
5342 "Failed to dump mctp\n");
5343 return;
5344 }
5345
5346 if (!ha->flags.nic_core_reset_hdlr_active) {
5347 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) {
5348 qla83xx_idc_lock(base_vha, 0);
5349 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5350 &dev_state);
5351 qla83xx_idc_unlock(base_vha, 0);
5352 if (dev_state != QLA8XXX_DEV_NEED_RESET) {
5353 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a,
5354 "Nic Core f/w is alive.\n");
5355 return;
5356 }
5357 }
5358
5359 ha->flags.nic_core_reset_hdlr_active = 1;
5360 if (qla83xx_nic_core_reset(base_vha)) {
5361 /* NIC Core reset failed. */
5362 ql_dbg(ql_dbg_p3p, base_vha, 0xb061,
5363 "NIC Core reset failed.\n");
5364 }
5365 ha->flags.nic_core_reset_hdlr_active = 0;
5366 }
5367 }
5368
5369 /* Work: Handle 8200 IDC aens */
5370 void
5371 qla83xx_service_idc_aen(struct work_struct *work)
5372 {
5373 struct qla_hw_data *ha =
5374 container_of(work, struct qla_hw_data, idc_aen);
5375 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5376 uint32_t dev_state, idc_control;
5377
5378 qla83xx_idc_lock(base_vha, 0);
5379 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5380 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control);
5381 qla83xx_idc_unlock(base_vha, 0);
5382 if (dev_state == QLA8XXX_DEV_NEED_RESET) {
5383 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) {
5384 ql_dbg(ql_dbg_p3p, base_vha, 0xb062,
5385 "Application requested NIC Core Reset.\n");
5386 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5387 } else if (qla83xx_check_nic_core_fw_alive(base_vha) ==
5388 QLA_SUCCESS) {
5389 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b,
5390 "Other protocol driver requested NIC Core Reset.\n");
5391 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET);
5392 }
5393 } else if (dev_state == QLA8XXX_DEV_FAILED ||
5394 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
5395 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER);
5396 }
5397 }
5398
5399 static void
5400 qla83xx_wait_logic(void)
5401 {
5402 int i;
5403
5404 /* Yield CPU */
5405 if (!in_interrupt()) {
5406 /*
5407 * Wait about 200ms before retrying again.
5408 * This controls the number of retries for single
5409 * lock operation.
5410 */
5411 msleep(100);
5412 schedule();
5413 } else {
5414 for (i = 0; i < 20; i++)
5415 cpu_relax(); /* This a nop instr on i386 */
5416 }
5417 }
5418
5419 static int
5420 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha)
5421 {
5422 int rval;
5423 uint32_t data;
5424 uint32_t idc_lck_rcvry_stage_mask = 0x3;
5425 uint32_t idc_lck_rcvry_owner_mask = 0x3c;
5426 struct qla_hw_data *ha = base_vha->hw;
5427 ql_dbg(ql_dbg_p3p, base_vha, 0xb086,
5428 "Trying force recovery of the IDC lock.\n");
5429
5430 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data);
5431 if (rval)
5432 return rval;
5433
5434 if ((data & idc_lck_rcvry_stage_mask) > 0) {
5435 return QLA_SUCCESS;
5436 } else {
5437 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2);
5438 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5439 data);
5440 if (rval)
5441 return rval;
5442
5443 msleep(200);
5444
5445 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY,
5446 &data);
5447 if (rval)
5448 return rval;
5449
5450 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) {
5451 data &= (IDC_LOCK_RECOVERY_STAGE2 |
5452 ~(idc_lck_rcvry_stage_mask));
5453 rval = qla83xx_wr_reg(base_vha,
5454 QLA83XX_IDC_LOCK_RECOVERY, data);
5455 if (rval)
5456 return rval;
5457
5458 /* Forcefully perform IDC UnLock */
5459 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK,
5460 &data);
5461 if (rval)
5462 return rval;
5463 /* Clear lock-id by setting 0xff */
5464 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5465 0xff);
5466 if (rval)
5467 return rval;
5468 /* Clear lock-recovery by setting 0x0 */
5469 rval = qla83xx_wr_reg(base_vha,
5470 QLA83XX_IDC_LOCK_RECOVERY, 0x0);
5471 if (rval)
5472 return rval;
5473 } else
5474 return QLA_SUCCESS;
5475 }
5476
5477 return rval;
5478 }
5479
5480 static int
5481 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha)
5482 {
5483 int rval = QLA_SUCCESS;
5484 uint32_t o_drv_lockid, n_drv_lockid;
5485 unsigned long lock_recovery_timeout;
5486
5487 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT;
5488 retry_lockid:
5489 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid);
5490 if (rval)
5491 goto exit;
5492
5493 /* MAX wait time before forcing IDC Lock recovery = 2 secs */
5494 if (time_after_eq(jiffies, lock_recovery_timeout)) {
5495 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS)
5496 return QLA_SUCCESS;
5497 else
5498 return QLA_FUNCTION_FAILED;
5499 }
5500
5501 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid);
5502 if (rval)
5503 goto exit;
5504
5505 if (o_drv_lockid == n_drv_lockid) {
5506 qla83xx_wait_logic();
5507 goto retry_lockid;
5508 } else
5509 return QLA_SUCCESS;
5510
5511 exit:
5512 return rval;
5513 }
5514
5515 void
5516 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5517 {
5518 uint16_t options = (requester_id << 15) | BIT_6;
5519 uint32_t data;
5520 uint32_t lock_owner;
5521 struct qla_hw_data *ha = base_vha->hw;
5522
5523 /* IDC-lock implementation using driver-lock/lock-id remote registers */
5524 retry_lock:
5525 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data)
5526 == QLA_SUCCESS) {
5527 if (data) {
5528 /* Setting lock-id to our function-number */
5529 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5530 ha->portnum);
5531 } else {
5532 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID,
5533 &lock_owner);
5534 ql_dbg(ql_dbg_p3p, base_vha, 0xb063,
5535 "Failed to acquire IDC lock, acquired by %d, "
5536 "retrying...\n", lock_owner);
5537
5538 /* Retry/Perform IDC-Lock recovery */
5539 if (qla83xx_idc_lock_recovery(base_vha)
5540 == QLA_SUCCESS) {
5541 qla83xx_wait_logic();
5542 goto retry_lock;
5543 } else
5544 ql_log(ql_log_warn, base_vha, 0xb075,
5545 "IDC Lock recovery FAILED.\n");
5546 }
5547
5548 }
5549
5550 return;
5551
5552 /* XXX: IDC-lock implementation using access-control mbx */
5553 retry_lock2:
5554 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5555 ql_dbg(ql_dbg_p3p, base_vha, 0xb072,
5556 "Failed to acquire IDC lock. retrying...\n");
5557 /* Retry/Perform IDC-Lock recovery */
5558 if (qla83xx_idc_lock_recovery(base_vha) == QLA_SUCCESS) {
5559 qla83xx_wait_logic();
5560 goto retry_lock2;
5561 } else
5562 ql_log(ql_log_warn, base_vha, 0xb076,
5563 "IDC Lock recovery FAILED.\n");
5564 }
5565
5566 return;
5567 }
5568
5569 void
5570 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id)
5571 {
5572 #if 0
5573 uint16_t options = (requester_id << 15) | BIT_7;
5574 #endif
5575 uint16_t retry;
5576 uint32_t data;
5577 struct qla_hw_data *ha = base_vha->hw;
5578
5579 /* IDC-unlock implementation using driver-unlock/lock-id
5580 * remote registers
5581 */
5582 retry = 0;
5583 retry_unlock:
5584 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data)
5585 == QLA_SUCCESS) {
5586 if (data == ha->portnum) {
5587 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data);
5588 /* Clearing lock-id by setting 0xff */
5589 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff);
5590 } else if (retry < 10) {
5591 /* SV: XXX: IDC unlock retrying needed here? */
5592
5593 /* Retry for IDC-unlock */
5594 qla83xx_wait_logic();
5595 retry++;
5596 ql_dbg(ql_dbg_p3p, base_vha, 0xb064,
5597 "Failed to release IDC lock, retrying=%d\n", retry);
5598 goto retry_unlock;
5599 }
5600 } else if (retry < 10) {
5601 /* Retry for IDC-unlock */
5602 qla83xx_wait_logic();
5603 retry++;
5604 ql_dbg(ql_dbg_p3p, base_vha, 0xb065,
5605 "Failed to read drv-lockid, retrying=%d\n", retry);
5606 goto retry_unlock;
5607 }
5608
5609 return;
5610
5611 #if 0
5612 /* XXX: IDC-unlock implementation using access-control mbx */
5613 retry = 0;
5614 retry_unlock2:
5615 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) {
5616 if (retry < 10) {
5617 /* Retry for IDC-unlock */
5618 qla83xx_wait_logic();
5619 retry++;
5620 ql_dbg(ql_dbg_p3p, base_vha, 0xb066,
5621 "Failed to release IDC lock, retrying=%d\n", retry);
5622 goto retry_unlock2;
5623 }
5624 }
5625
5626 return;
5627 #endif
5628 }
5629
5630 int
5631 __qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5632 {
5633 int rval = QLA_SUCCESS;
5634 struct qla_hw_data *ha = vha->hw;
5635 uint32_t drv_presence;
5636
5637 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5638 if (rval == QLA_SUCCESS) {
5639 drv_presence |= (1 << ha->portnum);
5640 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5641 drv_presence);
5642 }
5643
5644 return rval;
5645 }
5646
5647 int
5648 qla83xx_set_drv_presence(scsi_qla_host_t *vha)
5649 {
5650 int rval = QLA_SUCCESS;
5651
5652 qla83xx_idc_lock(vha, 0);
5653 rval = __qla83xx_set_drv_presence(vha);
5654 qla83xx_idc_unlock(vha, 0);
5655
5656 return rval;
5657 }
5658
5659 int
5660 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5661 {
5662 int rval = QLA_SUCCESS;
5663 struct qla_hw_data *ha = vha->hw;
5664 uint32_t drv_presence;
5665
5666 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5667 if (rval == QLA_SUCCESS) {
5668 drv_presence &= ~(1 << ha->portnum);
5669 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5670 drv_presence);
5671 }
5672
5673 return rval;
5674 }
5675
5676 int
5677 qla83xx_clear_drv_presence(scsi_qla_host_t *vha)
5678 {
5679 int rval = QLA_SUCCESS;
5680
5681 qla83xx_idc_lock(vha, 0);
5682 rval = __qla83xx_clear_drv_presence(vha);
5683 qla83xx_idc_unlock(vha, 0);
5684
5685 return rval;
5686 }
5687
5688 static void
5689 qla83xx_need_reset_handler(scsi_qla_host_t *vha)
5690 {
5691 struct qla_hw_data *ha = vha->hw;
5692 uint32_t drv_ack, drv_presence;
5693 unsigned long ack_timeout;
5694
5695 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */
5696 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
5697 while (1) {
5698 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
5699 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
5700 if ((drv_ack & drv_presence) == drv_presence)
5701 break;
5702
5703 if (time_after_eq(jiffies, ack_timeout)) {
5704 ql_log(ql_log_warn, vha, 0xb067,
5705 "RESET ACK TIMEOUT! drv_presence=0x%x "
5706 "drv_ack=0x%x\n", drv_presence, drv_ack);
5707 /*
5708 * The function(s) which did not ack in time are forced
5709 * to withdraw any further participation in the IDC
5710 * reset.
5711 */
5712 if (drv_ack != drv_presence)
5713 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE,
5714 drv_ack);
5715 break;
5716 }
5717
5718 qla83xx_idc_unlock(vha, 0);
5719 msleep(1000);
5720 qla83xx_idc_lock(vha, 0);
5721 }
5722
5723 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD);
5724 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n");
5725 }
5726
5727 static int
5728 qla83xx_device_bootstrap(scsi_qla_host_t *vha)
5729 {
5730 int rval = QLA_SUCCESS;
5731 uint32_t idc_control;
5732
5733 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
5734 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n");
5735
5736 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */
5737 __qla83xx_get_idc_control(vha, &idc_control);
5738 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET;
5739 __qla83xx_set_idc_control(vha, 0);
5740
5741 qla83xx_idc_unlock(vha, 0);
5742 rval = qla83xx_restart_nic_firmware(vha);
5743 qla83xx_idc_lock(vha, 0);
5744
5745 if (rval != QLA_SUCCESS) {
5746 ql_log(ql_log_fatal, vha, 0xb06a,
5747 "Failed to restart NIC f/w.\n");
5748 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED);
5749 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n");
5750 } else {
5751 ql_dbg(ql_dbg_p3p, vha, 0xb06c,
5752 "Success in restarting nic f/w.\n");
5753 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY);
5754 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n");
5755 }
5756
5757 return rval;
5758 }
5759
5760 /* Assumes idc_lock always held on entry */
5761 int
5762 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha)
5763 {
5764 struct qla_hw_data *ha = base_vha->hw;
5765 int rval = QLA_SUCCESS;
5766 unsigned long dev_init_timeout;
5767 uint32_t dev_state;
5768
5769 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */
5770 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
5771
5772 while (1) {
5773
5774 if (time_after_eq(jiffies, dev_init_timeout)) {
5775 ql_log(ql_log_warn, base_vha, 0xb06e,
5776 "Initialization TIMEOUT!\n");
5777 /* Init timeout. Disable further NIC Core
5778 * communication.
5779 */
5780 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE,
5781 QLA8XXX_DEV_FAILED);
5782 ql_log(ql_log_info, base_vha, 0xb06f,
5783 "HW State: FAILED.\n");
5784 }
5785
5786 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state);
5787 switch (dev_state) {
5788 case QLA8XXX_DEV_READY:
5789 if (ha->flags.nic_core_reset_owner)
5790 qla83xx_idc_audit(base_vha,
5791 IDC_AUDIT_COMPLETION);
5792 ha->flags.nic_core_reset_owner = 0;
5793 ql_dbg(ql_dbg_p3p, base_vha, 0xb070,
5794 "Reset_owner reset by 0x%x.\n",
5795 ha->portnum);
5796 goto exit;
5797 case QLA8XXX_DEV_COLD:
5798 if (ha->flags.nic_core_reset_owner)
5799 rval = qla83xx_device_bootstrap(base_vha);
5800 else {
5801 /* Wait for AEN to change device-state */
5802 qla83xx_idc_unlock(base_vha, 0);
5803 msleep(1000);
5804 qla83xx_idc_lock(base_vha, 0);
5805 }
5806 break;
5807 case QLA8XXX_DEV_INITIALIZING:
5808 /* Wait for AEN to change device-state */
5809 qla83xx_idc_unlock(base_vha, 0);
5810 msleep(1000);
5811 qla83xx_idc_lock(base_vha, 0);
5812 break;
5813 case QLA8XXX_DEV_NEED_RESET:
5814 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner)
5815 qla83xx_need_reset_handler(base_vha);
5816 else {
5817 /* Wait for AEN to change device-state */
5818 qla83xx_idc_unlock(base_vha, 0);
5819 msleep(1000);
5820 qla83xx_idc_lock(base_vha, 0);
5821 }
5822 /* reset timeout value after need reset handler */
5823 dev_init_timeout = jiffies +
5824 (ha->fcoe_dev_init_timeout * HZ);
5825 break;
5826 case QLA8XXX_DEV_NEED_QUIESCENT:
5827 /* XXX: DEBUG for now */
5828 qla83xx_idc_unlock(base_vha, 0);
5829 msleep(1000);
5830 qla83xx_idc_lock(base_vha, 0);
5831 break;
5832 case QLA8XXX_DEV_QUIESCENT:
5833 /* XXX: DEBUG for now */
5834 if (ha->flags.quiesce_owner)
5835 goto exit;
5836
5837 qla83xx_idc_unlock(base_vha, 0);
5838 msleep(1000);
5839 qla83xx_idc_lock(base_vha, 0);
5840 dev_init_timeout = jiffies +
5841 (ha->fcoe_dev_init_timeout * HZ);
5842 break;
5843 case QLA8XXX_DEV_FAILED:
5844 if (ha->flags.nic_core_reset_owner)
5845 qla83xx_idc_audit(base_vha,
5846 IDC_AUDIT_COMPLETION);
5847 ha->flags.nic_core_reset_owner = 0;
5848 __qla83xx_clear_drv_presence(base_vha);
5849 qla83xx_idc_unlock(base_vha, 0);
5850 qla8xxx_dev_failed_handler(base_vha);
5851 rval = QLA_FUNCTION_FAILED;
5852 qla83xx_idc_lock(base_vha, 0);
5853 goto exit;
5854 case QLA8XXX_BAD_VALUE:
5855 qla83xx_idc_unlock(base_vha, 0);
5856 msleep(1000);
5857 qla83xx_idc_lock(base_vha, 0);
5858 break;
5859 default:
5860 ql_log(ql_log_warn, base_vha, 0xb071,
5861 "Unknown Device State: %x.\n", dev_state);
5862 qla83xx_idc_unlock(base_vha, 0);
5863 qla8xxx_dev_failed_handler(base_vha);
5864 rval = QLA_FUNCTION_FAILED;
5865 qla83xx_idc_lock(base_vha, 0);
5866 goto exit;
5867 }
5868 }
5869
5870 exit:
5871 return rval;
5872 }
5873
5874 void
5875 qla2x00_disable_board_on_pci_error(struct work_struct *work)
5876 {
5877 struct qla_hw_data *ha = container_of(work, struct qla_hw_data,
5878 board_disable);
5879 struct pci_dev *pdev = ha->pdev;
5880 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
5881
5882 /*
5883 * if UNLOAD flag is already set, then continue unload,
5884 * where it was set first.
5885 */
5886 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5887 return;
5888
5889 ql_log(ql_log_warn, base_vha, 0x015b,
5890 "Disabling adapter.\n");
5891
5892 if (!atomic_read(&pdev->enable_cnt)) {
5893 ql_log(ql_log_info, base_vha, 0xfffc,
5894 "PCI device disabled, no action req for PCI error=%lx\n",
5895 base_vha->pci_flags);
5896 return;
5897 }
5898
5899 qla2x00_wait_for_sess_deletion(base_vha);
5900
5901 set_bit(UNLOADING, &base_vha->dpc_flags);
5902
5903 qla2x00_delete_all_vps(ha, base_vha);
5904
5905 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
5906
5907 qla2x00_dfs_remove(base_vha);
5908
5909 qla84xx_put_chip(base_vha);
5910
5911 if (base_vha->timer_active)
5912 qla2x00_stop_timer(base_vha);
5913
5914 base_vha->flags.online = 0;
5915
5916 qla2x00_destroy_deferred_work(ha);
5917
5918 /*
5919 * Do not try to stop beacon blink as it will issue a mailbox
5920 * command.
5921 */
5922 qla2x00_free_sysfs_attr(base_vha, false);
5923
5924 fc_remove_host(base_vha->host);
5925
5926 scsi_remove_host(base_vha->host);
5927
5928 base_vha->flags.init_done = 0;
5929 qla25xx_delete_queues(base_vha);
5930 qla2x00_free_fcports(base_vha);
5931 qla2x00_free_irqs(base_vha);
5932 qla2x00_mem_free(ha);
5933 qla82xx_md_free(base_vha);
5934 qla2x00_free_queues(ha);
5935
5936 qla2x00_unmap_iobases(ha);
5937
5938 pci_release_selected_regions(ha->pdev, ha->bars);
5939 pci_disable_pcie_error_reporting(pdev);
5940 pci_disable_device(pdev);
5941
5942 /*
5943 * Let qla2x00_remove_one cleanup qla_hw_data on device removal.
5944 */
5945 }
5946
5947 /**************************************************************************
5948 * qla2x00_do_dpc
5949 * This kernel thread is a task that is schedule by the interrupt handler
5950 * to perform the background processing for interrupts.
5951 *
5952 * Notes:
5953 * This task always run in the context of a kernel thread. It
5954 * is kick-off by the driver's detect code and starts up
5955 * up one per adapter. It immediately goes to sleep and waits for
5956 * some fibre event. When either the interrupt handler or
5957 * the timer routine detects a event it will one of the task
5958 * bits then wake us up.
5959 **************************************************************************/
5960 static int
5961 qla2x00_do_dpc(void *data)
5962 {
5963 scsi_qla_host_t *base_vha;
5964 struct qla_hw_data *ha;
5965 uint32_t online;
5966 struct qla_qpair *qpair;
5967
5968 ha = (struct qla_hw_data *)data;
5969 base_vha = pci_get_drvdata(ha->pdev);
5970
5971 set_user_nice(current, MIN_NICE);
5972
5973 set_current_state(TASK_INTERRUPTIBLE);
5974 while (!kthread_should_stop()) {
5975 ql_dbg(ql_dbg_dpc, base_vha, 0x4000,
5976 "DPC handler sleeping.\n");
5977
5978 schedule();
5979
5980 if (!base_vha->flags.init_done || ha->flags.mbox_busy)
5981 goto end_loop;
5982
5983 if (ha->flags.eeh_busy) {
5984 ql_dbg(ql_dbg_dpc, base_vha, 0x4003,
5985 "eeh_busy=%d.\n", ha->flags.eeh_busy);
5986 goto end_loop;
5987 }
5988
5989 ha->dpc_active = 1;
5990
5991 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001,
5992 "DPC handler waking up, dpc_flags=0x%lx.\n",
5993 base_vha->dpc_flags);
5994
5995 if (test_bit(UNLOADING, &base_vha->dpc_flags))
5996 break;
5997
5998 if (IS_P3P_TYPE(ha)) {
5999 if (IS_QLA8044(ha)) {
6000 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6001 &base_vha->dpc_flags)) {
6002 qla8044_idc_lock(ha);
6003 qla8044_wr_direct(base_vha,
6004 QLA8044_CRB_DEV_STATE_INDEX,
6005 QLA8XXX_DEV_FAILED);
6006 qla8044_idc_unlock(ha);
6007 ql_log(ql_log_info, base_vha, 0x4004,
6008 "HW State: FAILED.\n");
6009 qla8044_device_state_handler(base_vha);
6010 continue;
6011 }
6012
6013 } else {
6014 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6015 &base_vha->dpc_flags)) {
6016 qla82xx_idc_lock(ha);
6017 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6018 QLA8XXX_DEV_FAILED);
6019 qla82xx_idc_unlock(ha);
6020 ql_log(ql_log_info, base_vha, 0x0151,
6021 "HW State: FAILED.\n");
6022 qla82xx_device_state_handler(base_vha);
6023 continue;
6024 }
6025 }
6026
6027 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED,
6028 &base_vha->dpc_flags)) {
6029
6030 ql_dbg(ql_dbg_dpc, base_vha, 0x4005,
6031 "FCoE context reset scheduled.\n");
6032 if (!(test_and_set_bit(ABORT_ISP_ACTIVE,
6033 &base_vha->dpc_flags))) {
6034 if (qla82xx_fcoe_ctx_reset(base_vha)) {
6035 /* FCoE-ctx reset failed.
6036 * Escalate to chip-reset
6037 */
6038 set_bit(ISP_ABORT_NEEDED,
6039 &base_vha->dpc_flags);
6040 }
6041 clear_bit(ABORT_ISP_ACTIVE,
6042 &base_vha->dpc_flags);
6043 }
6044
6045 ql_dbg(ql_dbg_dpc, base_vha, 0x4006,
6046 "FCoE context reset end.\n");
6047 }
6048 } else if (IS_QLAFX00(ha)) {
6049 if (test_and_clear_bit(ISP_UNRECOVERABLE,
6050 &base_vha->dpc_flags)) {
6051 ql_dbg(ql_dbg_dpc, base_vha, 0x4020,
6052 "Firmware Reset Recovery\n");
6053 if (qlafx00_reset_initialize(base_vha)) {
6054 /* Failed. Abort isp later. */
6055 if (!test_bit(UNLOADING,
6056 &base_vha->dpc_flags)) {
6057 set_bit(ISP_UNRECOVERABLE,
6058 &base_vha->dpc_flags);
6059 ql_dbg(ql_dbg_dpc, base_vha,
6060 0x4021,
6061 "Reset Recovery Failed\n");
6062 }
6063 }
6064 }
6065
6066 if (test_and_clear_bit(FX00_TARGET_SCAN,
6067 &base_vha->dpc_flags)) {
6068 ql_dbg(ql_dbg_dpc, base_vha, 0x4022,
6069 "ISPFx00 Target Scan scheduled\n");
6070 if (qlafx00_rescan_isp(base_vha)) {
6071 if (!test_bit(UNLOADING,
6072 &base_vha->dpc_flags))
6073 set_bit(ISP_UNRECOVERABLE,
6074 &base_vha->dpc_flags);
6075 ql_dbg(ql_dbg_dpc, base_vha, 0x401e,
6076 "ISPFx00 Target Scan Failed\n");
6077 }
6078 ql_dbg(ql_dbg_dpc, base_vha, 0x401f,
6079 "ISPFx00 Target Scan End\n");
6080 }
6081 if (test_and_clear_bit(FX00_HOST_INFO_RESEND,
6082 &base_vha->dpc_flags)) {
6083 ql_dbg(ql_dbg_dpc, base_vha, 0x4023,
6084 "ISPFx00 Host Info resend scheduled\n");
6085 qlafx00_fx_disc(base_vha,
6086 &base_vha->hw->mr.fcport,
6087 FXDISC_REG_HOST_INFO);
6088 }
6089 }
6090
6091 if (test_and_clear_bit(DETECT_SFP_CHANGE,
6092 &base_vha->dpc_flags) &&
6093 !test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) {
6094 qla24xx_detect_sfp(base_vha);
6095
6096 if (ha->flags.detected_lr_sfp !=
6097 ha->flags.using_lr_setting)
6098 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags);
6099 }
6100
6101 if (test_and_clear_bit
6102 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) &&
6103 !test_bit(UNLOADING, &base_vha->dpc_flags)) {
6104 bool do_reset = true;
6105
6106 switch (base_vha->qlini_mode) {
6107 case QLA2XXX_INI_MODE_ENABLED:
6108 break;
6109 case QLA2XXX_INI_MODE_DISABLED:
6110 if (!qla_tgt_mode_enabled(base_vha) &&
6111 !ha->flags.fw_started)
6112 do_reset = false;
6113 break;
6114 case QLA2XXX_INI_MODE_DUAL:
6115 if (!qla_dual_mode_enabled(base_vha) &&
6116 !ha->flags.fw_started)
6117 do_reset = false;
6118 break;
6119 default:
6120 break;
6121 }
6122
6123 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE,
6124 &base_vha->dpc_flags))) {
6125 ql_dbg(ql_dbg_dpc, base_vha, 0x4007,
6126 "ISP abort scheduled.\n");
6127 if (ha->isp_ops->abort_isp(base_vha)) {
6128 /* failed. retry later */
6129 set_bit(ISP_ABORT_NEEDED,
6130 &base_vha->dpc_flags);
6131 }
6132 clear_bit(ABORT_ISP_ACTIVE,
6133 &base_vha->dpc_flags);
6134 ql_dbg(ql_dbg_dpc, base_vha, 0x4008,
6135 "ISP abort end.\n");
6136 }
6137 }
6138
6139 if (test_and_clear_bit(FCPORT_UPDATE_NEEDED,
6140 &base_vha->dpc_flags)) {
6141 qla2x00_update_fcports(base_vha);
6142 }
6143
6144 if (IS_QLAFX00(ha))
6145 goto loop_resync_check;
6146
6147 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) {
6148 ql_dbg(ql_dbg_dpc, base_vha, 0x4009,
6149 "Quiescence mode scheduled.\n");
6150 if (IS_P3P_TYPE(ha)) {
6151 if (IS_QLA82XX(ha))
6152 qla82xx_device_state_handler(base_vha);
6153 if (IS_QLA8044(ha))
6154 qla8044_device_state_handler(base_vha);
6155 clear_bit(ISP_QUIESCE_NEEDED,
6156 &base_vha->dpc_flags);
6157 if (!ha->flags.quiesce_owner) {
6158 qla2x00_perform_loop_resync(base_vha);
6159 if (IS_QLA82XX(ha)) {
6160 qla82xx_idc_lock(ha);
6161 qla82xx_clear_qsnt_ready(
6162 base_vha);
6163 qla82xx_idc_unlock(ha);
6164 } else if (IS_QLA8044(ha)) {
6165 qla8044_idc_lock(ha);
6166 qla8044_clear_qsnt_ready(
6167 base_vha);
6168 qla8044_idc_unlock(ha);
6169 }
6170 }
6171 } else {
6172 clear_bit(ISP_QUIESCE_NEEDED,
6173 &base_vha->dpc_flags);
6174 qla2x00_quiesce_io(base_vha);
6175 }
6176 ql_dbg(ql_dbg_dpc, base_vha, 0x400a,
6177 "Quiescence mode end.\n");
6178 }
6179
6180 if (test_and_clear_bit(RESET_MARKER_NEEDED,
6181 &base_vha->dpc_flags) &&
6182 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) {
6183
6184 ql_dbg(ql_dbg_dpc, base_vha, 0x400b,
6185 "Reset marker scheduled.\n");
6186 qla2x00_rst_aen(base_vha);
6187 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags);
6188 ql_dbg(ql_dbg_dpc, base_vha, 0x400c,
6189 "Reset marker end.\n");
6190 }
6191
6192 /* Retry each device up to login retry count */
6193 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) &&
6194 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) &&
6195 atomic_read(&base_vha->loop_state) != LOOP_DOWN) {
6196
6197 if (!base_vha->relogin_jif ||
6198 time_after_eq(jiffies, base_vha->relogin_jif)) {
6199 base_vha->relogin_jif = jiffies + HZ;
6200 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags);
6201
6202 ql_dbg(ql_dbg_disc, base_vha, 0x400d,
6203 "Relogin scheduled.\n");
6204 qla24xx_post_relogin_work(base_vha);
6205 }
6206 }
6207 loop_resync_check:
6208 if (test_and_clear_bit(LOOP_RESYNC_NEEDED,
6209 &base_vha->dpc_flags)) {
6210
6211 ql_dbg(ql_dbg_dpc, base_vha, 0x400f,
6212 "Loop resync scheduled.\n");
6213
6214 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE,
6215 &base_vha->dpc_flags))) {
6216
6217 qla2x00_loop_resync(base_vha);
6218
6219 clear_bit(LOOP_RESYNC_ACTIVE,
6220 &base_vha->dpc_flags);
6221 }
6222
6223 ql_dbg(ql_dbg_dpc, base_vha, 0x4010,
6224 "Loop resync end.\n");
6225 }
6226
6227 if (IS_QLAFX00(ha))
6228 goto intr_on_check;
6229
6230 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) &&
6231 atomic_read(&base_vha->loop_state) == LOOP_READY) {
6232 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags);
6233 qla2xxx_flash_npiv_conf(base_vha);
6234 }
6235
6236 intr_on_check:
6237 if (!ha->interrupts_on)
6238 ha->isp_ops->enable_intrs(ha);
6239
6240 if (test_and_clear_bit(BEACON_BLINK_NEEDED,
6241 &base_vha->dpc_flags)) {
6242 if (ha->beacon_blink_led == 1)
6243 ha->isp_ops->beacon_blink(base_vha);
6244 }
6245
6246 /* qpair online check */
6247 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED,
6248 &base_vha->dpc_flags)) {
6249 if (ha->flags.eeh_busy ||
6250 ha->flags.pci_channel_io_perm_failure)
6251 online = 0;
6252 else
6253 online = 1;
6254
6255 mutex_lock(&ha->mq_lock);
6256 list_for_each_entry(qpair, &base_vha->qp_list,
6257 qp_list_elem)
6258 qpair->online = online;
6259 mutex_unlock(&ha->mq_lock);
6260 }
6261
6262 if (test_and_clear_bit(SET_NVME_ZIO_THRESHOLD_NEEDED,
6263 &base_vha->dpc_flags)) {
6264 ql_log(ql_log_info, base_vha, 0xffffff,
6265 "nvme: SET ZIO Activity exchange threshold to %d.\n",
6266 ha->nvme_last_rptd_aen);
6267 if (qla27xx_set_zio_threshold(base_vha,
6268 ha->nvme_last_rptd_aen)) {
6269 ql_log(ql_log_info, base_vha, 0xffffff,
6270 "nvme: Unable to SET ZIO Activity exchange threshold to %d.\n",
6271 ha->nvme_last_rptd_aen);
6272 }
6273 }
6274
6275 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED,
6276 &base_vha->dpc_flags)) {
6277 ql_log(ql_log_info, base_vha, 0xffffff,
6278 "SET ZIO Activity exchange threshold to %d.\n",
6279 ha->last_zio_threshold);
6280 qla27xx_set_zio_threshold(base_vha,
6281 ha->last_zio_threshold);
6282 }
6283
6284 if (!IS_QLAFX00(ha))
6285 qla2x00_do_dpc_all_vps(base_vha);
6286
6287 if (test_and_clear_bit(N2N_LINK_RESET,
6288 &base_vha->dpc_flags)) {
6289 qla2x00_lip_reset(base_vha);
6290 }
6291
6292 ha->dpc_active = 0;
6293 end_loop:
6294 set_current_state(TASK_INTERRUPTIBLE);
6295 } /* End of while(1) */
6296 __set_current_state(TASK_RUNNING);
6297
6298 ql_dbg(ql_dbg_dpc, base_vha, 0x4011,
6299 "DPC handler exiting.\n");
6300
6301 /*
6302 * Make sure that nobody tries to wake us up again.
6303 */
6304 ha->dpc_active = 0;
6305
6306 /* Cleanup any residual CTX SRBs. */
6307 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16);
6308
6309 return 0;
6310 }
6311
6312 void
6313 qla2xxx_wake_dpc(struct scsi_qla_host *vha)
6314 {
6315 struct qla_hw_data *ha = vha->hw;
6316 struct task_struct *t = ha->dpc_thread;
6317
6318 if (!test_bit(UNLOADING, &vha->dpc_flags) && t)
6319 wake_up_process(t);
6320 }
6321
6322 /*
6323 * qla2x00_rst_aen
6324 * Processes asynchronous reset.
6325 *
6326 * Input:
6327 * ha = adapter block pointer.
6328 */
6329 static void
6330 qla2x00_rst_aen(scsi_qla_host_t *vha)
6331 {
6332 if (vha->flags.online && !vha->flags.reset_active &&
6333 !atomic_read(&vha->loop_down_timer) &&
6334 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) {
6335 do {
6336 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
6337
6338 /*
6339 * Issue marker command only when we are going to start
6340 * the I/O.
6341 */
6342 vha->marker_needed = 1;
6343 } while (!atomic_read(&vha->loop_down_timer) &&
6344 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)));
6345 }
6346 }
6347
6348 /**************************************************************************
6349 * qla2x00_timer
6350 *
6351 * Description:
6352 * One second timer
6353 *
6354 * Context: Interrupt
6355 ***************************************************************************/
6356 void
6357 qla2x00_timer(struct timer_list *t)
6358 {
6359 scsi_qla_host_t *vha = from_timer(vha, t, timer);
6360 unsigned long cpu_flags = 0;
6361 int start_dpc = 0;
6362 int index;
6363 srb_t *sp;
6364 uint16_t w;
6365 struct qla_hw_data *ha = vha->hw;
6366 struct req_que *req;
6367
6368 if (ha->flags.eeh_busy) {
6369 ql_dbg(ql_dbg_timer, vha, 0x6000,
6370 "EEH = %d, restarting timer.\n",
6371 ha->flags.eeh_busy);
6372 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6373 return;
6374 }
6375
6376 /*
6377 * Hardware read to raise pending EEH errors during mailbox waits. If
6378 * the read returns -1 then disable the board.
6379 */
6380 if (!pci_channel_offline(ha->pdev)) {
6381 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w);
6382 qla2x00_check_reg16_for_disconnect(vha, w);
6383 }
6384
6385 /* Make sure qla82xx_watchdog is run only for physical port */
6386 if (!vha->vp_idx && IS_P3P_TYPE(ha)) {
6387 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags))
6388 start_dpc++;
6389 if (IS_QLA82XX(ha))
6390 qla82xx_watchdog(vha);
6391 else if (IS_QLA8044(ha))
6392 qla8044_watchdog(vha);
6393 }
6394
6395 if (!vha->vp_idx && IS_QLAFX00(ha))
6396 qlafx00_timer_routine(vha);
6397
6398 /* Loop down handler. */
6399 if (atomic_read(&vha->loop_down_timer) > 0 &&
6400 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) &&
6401 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags))
6402 && vha->flags.online) {
6403
6404 if (atomic_read(&vha->loop_down_timer) ==
6405 vha->loop_down_abort_time) {
6406
6407 ql_log(ql_log_info, vha, 0x6008,
6408 "Loop down - aborting the queues before time expires.\n");
6409
6410 if (!IS_QLA2100(ha) && vha->link_down_timeout)
6411 atomic_set(&vha->loop_state, LOOP_DEAD);
6412
6413 /*
6414 * Schedule an ISP abort to return any FCP2-device
6415 * commands.
6416 */
6417 /* NPIV - scan physical port only */
6418 if (!vha->vp_idx) {
6419 spin_lock_irqsave(&ha->hardware_lock,
6420 cpu_flags);
6421 req = ha->req_q_map[0];
6422 for (index = 1;
6423 index < req->num_outstanding_cmds;
6424 index++) {
6425 fc_port_t *sfcp;
6426
6427 sp = req->outstanding_cmds[index];
6428 if (!sp)
6429 continue;
6430 if (sp->cmd_type != TYPE_SRB)
6431 continue;
6432 if (sp->type != SRB_SCSI_CMD)
6433 continue;
6434 sfcp = sp->fcport;
6435 if (!(sfcp->flags & FCF_FCP2_DEVICE))
6436 continue;
6437
6438 if (IS_QLA82XX(ha))
6439 set_bit(FCOE_CTX_RESET_NEEDED,
6440 &vha->dpc_flags);
6441 else
6442 set_bit(ISP_ABORT_NEEDED,
6443 &vha->dpc_flags);
6444 break;
6445 }
6446 spin_unlock_irqrestore(&ha->hardware_lock,
6447 cpu_flags);
6448 }
6449 start_dpc++;
6450 }
6451
6452 /* if the loop has been down for 4 minutes, reinit adapter */
6453 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) {
6454 if (!(vha->device_flags & DFLG_NO_CABLE)) {
6455 ql_log(ql_log_warn, vha, 0x6009,
6456 "Loop down - aborting ISP.\n");
6457
6458 if (IS_QLA82XX(ha))
6459 set_bit(FCOE_CTX_RESET_NEEDED,
6460 &vha->dpc_flags);
6461 else
6462 set_bit(ISP_ABORT_NEEDED,
6463 &vha->dpc_flags);
6464 }
6465 }
6466 ql_dbg(ql_dbg_timer, vha, 0x600a,
6467 "Loop down - seconds remaining %d.\n",
6468 atomic_read(&vha->loop_down_timer));
6469 }
6470 /* Check if beacon LED needs to be blinked for physical host only */
6471 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) {
6472 /* There is no beacon_blink function for ISP82xx */
6473 if (!IS_P3P_TYPE(ha)) {
6474 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags);
6475 start_dpc++;
6476 }
6477 }
6478
6479 /* Process any deferred work. */
6480 if (!list_empty(&vha->work_list)) {
6481 unsigned long flags;
6482 bool q = false;
6483
6484 spin_lock_irqsave(&vha->work_lock, flags);
6485 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags))
6486 q = true;
6487 spin_unlock_irqrestore(&vha->work_lock, flags);
6488 if (q)
6489 queue_work(vha->hw->wq, &vha->iocb_work);
6490 }
6491
6492 /*
6493 * FC-NVME
6494 * see if the active AEN count has changed from what was last reported.
6495 */
6496 if (!vha->vp_idx && (atomic_read(&ha->nvme_active_aen_cnt) !=
6497 ha->nvme_last_rptd_aen) && ha->zio_mode == QLA_ZIO_MODE_6) {
6498 ql_log(ql_log_info, vha, 0x3002,
6499 "nvme: Sched: Set ZIO exchange threshold to %d.\n",
6500 ha->nvme_last_rptd_aen);
6501 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt);
6502 set_bit(SET_NVME_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6503 start_dpc++;
6504 }
6505
6506 if (!vha->vp_idx &&
6507 (atomic_read(&ha->zio_threshold) != ha->last_zio_threshold) &&
6508 (ha->zio_mode == QLA_ZIO_MODE_6) &&
6509 (IS_QLA83XX(ha) || IS_QLA27XX(ha))) {
6510 ql_log(ql_log_info, vha, 0x3002,
6511 "Sched: Set ZIO exchange threshold to %d.\n",
6512 ha->last_zio_threshold);
6513 ha->last_zio_threshold = atomic_read(&ha->zio_threshold);
6514 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags);
6515 start_dpc++;
6516 }
6517
6518 /* Schedule the DPC routine if needed */
6519 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) ||
6520 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) ||
6521 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags) ||
6522 start_dpc ||
6523 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) ||
6524 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) ||
6525 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) ||
6526 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
6527 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) ||
6528 test_bit(RELOGIN_NEEDED, &vha->dpc_flags))) {
6529 ql_dbg(ql_dbg_timer, vha, 0x600b,
6530 "isp_abort_needed=%d loop_resync_needed=%d "
6531 "fcport_update_needed=%d start_dpc=%d "
6532 "reset_marker_needed=%d",
6533 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags),
6534 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags),
6535 test_bit(FCPORT_UPDATE_NEEDED, &vha->dpc_flags),
6536 start_dpc,
6537 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags));
6538 ql_dbg(ql_dbg_timer, vha, 0x600c,
6539 "beacon_blink_needed=%d isp_unrecoverable=%d "
6540 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d "
6541 "relogin_needed=%d.\n",
6542 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags),
6543 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags),
6544 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags),
6545 test_bit(VP_DPC_NEEDED, &vha->dpc_flags),
6546 test_bit(RELOGIN_NEEDED, &vha->dpc_flags));
6547 qla2xxx_wake_dpc(vha);
6548 }
6549
6550 qla2x00_restart_timer(vha, WATCH_INTERVAL);
6551 }
6552
6553 /* Firmware interface routines. */
6554
6555 #define FW_BLOBS 11
6556 #define FW_ISP21XX 0
6557 #define FW_ISP22XX 1
6558 #define FW_ISP2300 2
6559 #define FW_ISP2322 3
6560 #define FW_ISP24XX 4
6561 #define FW_ISP25XX 5
6562 #define FW_ISP81XX 6
6563 #define FW_ISP82XX 7
6564 #define FW_ISP2031 8
6565 #define FW_ISP8031 9
6566 #define FW_ISP27XX 10
6567
6568 #define FW_FILE_ISP21XX "ql2100_fw.bin"
6569 #define FW_FILE_ISP22XX "ql2200_fw.bin"
6570 #define FW_FILE_ISP2300 "ql2300_fw.bin"
6571 #define FW_FILE_ISP2322 "ql2322_fw.bin"
6572 #define FW_FILE_ISP24XX "ql2400_fw.bin"
6573 #define FW_FILE_ISP25XX "ql2500_fw.bin"
6574 #define FW_FILE_ISP81XX "ql8100_fw.bin"
6575 #define FW_FILE_ISP82XX "ql8200_fw.bin"
6576 #define FW_FILE_ISP2031 "ql2600_fw.bin"
6577 #define FW_FILE_ISP8031 "ql8300_fw.bin"
6578 #define FW_FILE_ISP27XX "ql2700_fw.bin"
6579
6580
6581 static DEFINE_MUTEX(qla_fw_lock);
6582
6583 static struct fw_blob qla_fw_blobs[FW_BLOBS] = {
6584 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, },
6585 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, },
6586 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, },
6587 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, },
6588 { .name = FW_FILE_ISP24XX, },
6589 { .name = FW_FILE_ISP25XX, },
6590 { .name = FW_FILE_ISP81XX, },
6591 { .name = FW_FILE_ISP82XX, },
6592 { .name = FW_FILE_ISP2031, },
6593 { .name = FW_FILE_ISP8031, },
6594 { .name = FW_FILE_ISP27XX, },
6595 };
6596
6597 struct fw_blob *
6598 qla2x00_request_firmware(scsi_qla_host_t *vha)
6599 {
6600 struct qla_hw_data *ha = vha->hw;
6601 struct fw_blob *blob;
6602
6603 if (IS_QLA2100(ha)) {
6604 blob = &qla_fw_blobs[FW_ISP21XX];
6605 } else if (IS_QLA2200(ha)) {
6606 blob = &qla_fw_blobs[FW_ISP22XX];
6607 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
6608 blob = &qla_fw_blobs[FW_ISP2300];
6609 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) {
6610 blob = &qla_fw_blobs[FW_ISP2322];
6611 } else if (IS_QLA24XX_TYPE(ha)) {
6612 blob = &qla_fw_blobs[FW_ISP24XX];
6613 } else if (IS_QLA25XX(ha)) {
6614 blob = &qla_fw_blobs[FW_ISP25XX];
6615 } else if (IS_QLA81XX(ha)) {
6616 blob = &qla_fw_blobs[FW_ISP81XX];
6617 } else if (IS_QLA82XX(ha)) {
6618 blob = &qla_fw_blobs[FW_ISP82XX];
6619 } else if (IS_QLA2031(ha)) {
6620 blob = &qla_fw_blobs[FW_ISP2031];
6621 } else if (IS_QLA8031(ha)) {
6622 blob = &qla_fw_blobs[FW_ISP8031];
6623 } else if (IS_QLA27XX(ha)) {
6624 blob = &qla_fw_blobs[FW_ISP27XX];
6625 } else {
6626 return NULL;
6627 }
6628
6629 mutex_lock(&qla_fw_lock);
6630 if (blob->fw)
6631 goto out;
6632
6633 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) {
6634 ql_log(ql_log_warn, vha, 0x0063,
6635 "Failed to load firmware image (%s).\n", blob->name);
6636 blob->fw = NULL;
6637 blob = NULL;
6638 goto out;
6639 }
6640
6641 out:
6642 mutex_unlock(&qla_fw_lock);
6643 return blob;
6644 }
6645
6646 static void
6647 qla2x00_release_firmware(void)
6648 {
6649 int idx;
6650
6651 mutex_lock(&qla_fw_lock);
6652 for (idx = 0; idx < FW_BLOBS; idx++)
6653 release_firmware(qla_fw_blobs[idx].fw);
6654 mutex_unlock(&qla_fw_lock);
6655 }
6656
6657 static pci_ers_result_t
6658 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
6659 {
6660 scsi_qla_host_t *vha = pci_get_drvdata(pdev);
6661 struct qla_hw_data *ha = vha->hw;
6662
6663 ql_dbg(ql_dbg_aer, vha, 0x9000,
6664 "PCI error detected, state %x.\n", state);
6665
6666 if (!atomic_read(&pdev->enable_cnt)) {
6667 ql_log(ql_log_info, vha, 0xffff,
6668 "PCI device is disabled,state %x\n", state);
6669 return PCI_ERS_RESULT_NEED_RESET;
6670 }
6671
6672 switch (state) {
6673 case pci_channel_io_normal:
6674 ha->flags.eeh_busy = 0;
6675 if (ql2xmqsupport || ql2xnvmeenable) {
6676 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6677 qla2xxx_wake_dpc(vha);
6678 }
6679 return PCI_ERS_RESULT_CAN_RECOVER;
6680 case pci_channel_io_frozen:
6681 ha->flags.eeh_busy = 1;
6682 /* For ISP82XX complete any pending mailbox cmd */
6683 if (IS_QLA82XX(ha)) {
6684 ha->flags.isp82xx_fw_hung = 1;
6685 ql_dbg(ql_dbg_aer, vha, 0x9001, "Pci channel io frozen\n");
6686 qla82xx_clear_pending_mbx(vha);
6687 }
6688 qla2x00_free_irqs(vha);
6689 pci_disable_device(pdev);
6690 /* Return back all IOs */
6691 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6692 if (ql2xmqsupport || ql2xnvmeenable) {
6693 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6694 qla2xxx_wake_dpc(vha);
6695 }
6696 return PCI_ERS_RESULT_NEED_RESET;
6697 case pci_channel_io_perm_failure:
6698 ha->flags.pci_channel_io_perm_failure = 1;
6699 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
6700 if (ql2xmqsupport || ql2xnvmeenable) {
6701 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags);
6702 qla2xxx_wake_dpc(vha);
6703 }
6704 return PCI_ERS_RESULT_DISCONNECT;
6705 }
6706 return PCI_ERS_RESULT_NEED_RESET;
6707 }
6708
6709 static pci_ers_result_t
6710 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev)
6711 {
6712 int risc_paused = 0;
6713 uint32_t stat;
6714 unsigned long flags;
6715 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6716 struct qla_hw_data *ha = base_vha->hw;
6717 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
6718 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24;
6719
6720 if (IS_QLA82XX(ha))
6721 return PCI_ERS_RESULT_RECOVERED;
6722
6723 spin_lock_irqsave(&ha->hardware_lock, flags);
6724 if (IS_QLA2100(ha) || IS_QLA2200(ha)){
6725 stat = RD_REG_DWORD(&reg->hccr);
6726 if (stat & HCCR_RISC_PAUSE)
6727 risc_paused = 1;
6728 } else if (IS_QLA23XX(ha)) {
6729 stat = RD_REG_DWORD(&reg->u.isp2300.host_status);
6730 if (stat & HSR_RISC_PAUSED)
6731 risc_paused = 1;
6732 } else if (IS_FWI2_CAPABLE(ha)) {
6733 stat = RD_REG_DWORD(&reg24->host_status);
6734 if (stat & HSRX_RISC_PAUSED)
6735 risc_paused = 1;
6736 }
6737 spin_unlock_irqrestore(&ha->hardware_lock, flags);
6738
6739 if (risc_paused) {
6740 ql_log(ql_log_info, base_vha, 0x9003,
6741 "RISC paused -- mmio_enabled, Dumping firmware.\n");
6742 ha->isp_ops->fw_dump(base_vha, 0);
6743
6744 return PCI_ERS_RESULT_NEED_RESET;
6745 } else
6746 return PCI_ERS_RESULT_RECOVERED;
6747 }
6748
6749 static uint32_t
6750 qla82xx_error_recovery(scsi_qla_host_t *base_vha)
6751 {
6752 uint32_t rval = QLA_FUNCTION_FAILED;
6753 uint32_t drv_active = 0;
6754 struct qla_hw_data *ha = base_vha->hw;
6755 int fn;
6756 struct pci_dev *other_pdev = NULL;
6757
6758 ql_dbg(ql_dbg_aer, base_vha, 0x9006,
6759 "Entered %s.\n", __func__);
6760
6761 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6762
6763 if (base_vha->flags.online) {
6764 /* Abort all outstanding commands,
6765 * so as to be requeued later */
6766 qla2x00_abort_isp_cleanup(base_vha);
6767 }
6768
6769
6770 fn = PCI_FUNC(ha->pdev->devfn);
6771 while (fn > 0) {
6772 fn--;
6773 ql_dbg(ql_dbg_aer, base_vha, 0x9007,
6774 "Finding pci device at function = 0x%x.\n", fn);
6775 other_pdev =
6776 pci_get_domain_bus_and_slot(pci_domain_nr(ha->pdev->bus),
6777 ha->pdev->bus->number, PCI_DEVFN(PCI_SLOT(ha->pdev->devfn),
6778 fn));
6779
6780 if (!other_pdev)
6781 continue;
6782 if (atomic_read(&other_pdev->enable_cnt)) {
6783 ql_dbg(ql_dbg_aer, base_vha, 0x9008,
6784 "Found PCI func available and enable at 0x%x.\n",
6785 fn);
6786 pci_dev_put(other_pdev);
6787 break;
6788 }
6789 pci_dev_put(other_pdev);
6790 }
6791
6792 if (!fn) {
6793 /* Reset owner */
6794 ql_dbg(ql_dbg_aer, base_vha, 0x9009,
6795 "This devfn is reset owner = 0x%x.\n",
6796 ha->pdev->devfn);
6797 qla82xx_idc_lock(ha);
6798
6799 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6800 QLA8XXX_DEV_INITIALIZING);
6801
6802 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
6803 QLA82XX_IDC_VERSION);
6804
6805 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
6806 ql_dbg(ql_dbg_aer, base_vha, 0x900a,
6807 "drv_active = 0x%x.\n", drv_active);
6808
6809 qla82xx_idc_unlock(ha);
6810 /* Reset if device is not already reset
6811 * drv_active would be 0 if a reset has already been done
6812 */
6813 if (drv_active)
6814 rval = qla82xx_start_firmware(base_vha);
6815 else
6816 rval = QLA_SUCCESS;
6817 qla82xx_idc_lock(ha);
6818
6819 if (rval != QLA_SUCCESS) {
6820 ql_log(ql_log_info, base_vha, 0x900b,
6821 "HW State: FAILED.\n");
6822 qla82xx_clear_drv_active(ha);
6823 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6824 QLA8XXX_DEV_FAILED);
6825 } else {
6826 ql_log(ql_log_info, base_vha, 0x900c,
6827 "HW State: READY.\n");
6828 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
6829 QLA8XXX_DEV_READY);
6830 qla82xx_idc_unlock(ha);
6831 ha->flags.isp82xx_fw_hung = 0;
6832 rval = qla82xx_restart_isp(base_vha);
6833 qla82xx_idc_lock(ha);
6834 /* Clear driver state register */
6835 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, 0);
6836 qla82xx_set_drv_active(base_vha);
6837 }
6838 qla82xx_idc_unlock(ha);
6839 } else {
6840 ql_dbg(ql_dbg_aer, base_vha, 0x900d,
6841 "This devfn is not reset owner = 0x%x.\n",
6842 ha->pdev->devfn);
6843 if ((qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE) ==
6844 QLA8XXX_DEV_READY)) {
6845 ha->flags.isp82xx_fw_hung = 0;
6846 rval = qla82xx_restart_isp(base_vha);
6847 qla82xx_idc_lock(ha);
6848 qla82xx_set_drv_active(base_vha);
6849 qla82xx_idc_unlock(ha);
6850 }
6851 }
6852 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6853
6854 return rval;
6855 }
6856
6857 static pci_ers_result_t
6858 qla2xxx_pci_slot_reset(struct pci_dev *pdev)
6859 {
6860 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT;
6861 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6862 struct qla_hw_data *ha = base_vha->hw;
6863 struct rsp_que *rsp;
6864 int rc, retries = 10;
6865
6866 ql_dbg(ql_dbg_aer, base_vha, 0x9004,
6867 "Slot Reset.\n");
6868
6869 /* Workaround: qla2xxx driver which access hardware earlier
6870 * needs error state to be pci_channel_io_online.
6871 * Otherwise mailbox command timesout.
6872 */
6873 pdev->error_state = pci_channel_io_normal;
6874
6875 pci_restore_state(pdev);
6876
6877 /* pci_restore_state() clears the saved_state flag of the device
6878 * save restored state which resets saved_state flag
6879 */
6880 pci_save_state(pdev);
6881
6882 if (ha->mem_only)
6883 rc = pci_enable_device_mem(pdev);
6884 else
6885 rc = pci_enable_device(pdev);
6886
6887 if (rc) {
6888 ql_log(ql_log_warn, base_vha, 0x9005,
6889 "Can't re-enable PCI device after reset.\n");
6890 goto exit_slot_reset;
6891 }
6892
6893 rsp = ha->rsp_q_map[0];
6894 if (qla2x00_request_irqs(ha, rsp))
6895 goto exit_slot_reset;
6896
6897 if (ha->isp_ops->pci_config(base_vha))
6898 goto exit_slot_reset;
6899
6900 if (IS_QLA82XX(ha)) {
6901 if (qla82xx_error_recovery(base_vha) == QLA_SUCCESS) {
6902 ret = PCI_ERS_RESULT_RECOVERED;
6903 goto exit_slot_reset;
6904 } else
6905 goto exit_slot_reset;
6906 }
6907
6908 while (ha->flags.mbox_busy && retries--)
6909 msleep(1000);
6910
6911 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6912 if (ha->isp_ops->abort_isp(base_vha) == QLA_SUCCESS)
6913 ret = PCI_ERS_RESULT_RECOVERED;
6914 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags);
6915
6916
6917 exit_slot_reset:
6918 ql_dbg(ql_dbg_aer, base_vha, 0x900e,
6919 "slot_reset return %x.\n", ret);
6920
6921 return ret;
6922 }
6923
6924 static void
6925 qla2xxx_pci_resume(struct pci_dev *pdev)
6926 {
6927 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev);
6928 struct qla_hw_data *ha = base_vha->hw;
6929 int ret;
6930
6931 ql_dbg(ql_dbg_aer, base_vha, 0x900f,
6932 "pci_resume.\n");
6933
6934 ret = qla2x00_wait_for_hba_online(base_vha);
6935 if (ret != QLA_SUCCESS) {
6936 ql_log(ql_log_fatal, base_vha, 0x9002,
6937 "The device failed to resume I/O from slot/link_reset.\n");
6938 }
6939
6940 ha->flags.eeh_busy = 0;
6941 }
6942
6943 static int qla2xxx_map_queues(struct Scsi_Host *shost)
6944 {
6945 int rc;
6946 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata;
6947
6948 if (USER_CTRL_IRQ(vha->hw))
6949 rc = blk_mq_map_queues(&shost->tag_set);
6950 else
6951 rc = blk_mq_pci_map_queues(&shost->tag_set, vha->hw->pdev, 0);
6952 return rc;
6953 }
6954
6955 static const struct pci_error_handlers qla2xxx_err_handler = {
6956 .error_detected = qla2xxx_pci_error_detected,
6957 .mmio_enabled = qla2xxx_pci_mmio_enabled,
6958 .slot_reset = qla2xxx_pci_slot_reset,
6959 .resume = qla2xxx_pci_resume,
6960 };
6961
6962 static struct pci_device_id qla2xxx_pci_tbl[] = {
6963 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) },
6964 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) },
6965 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) },
6966 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) },
6967 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) },
6968 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) },
6969 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) },
6970 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) },
6971 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) },
6972 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) },
6973 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) },
6974 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) },
6975 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) },
6976 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) },
6977 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) },
6978 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) },
6979 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) },
6980 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) },
6981 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) },
6982 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) },
6983 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) },
6984 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) },
6985 { 0 },
6986 };
6987 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl);
6988
6989 static struct pci_driver qla2xxx_pci_driver = {
6990 .name = QLA2XXX_DRIVER_NAME,
6991 .driver = {
6992 .owner = THIS_MODULE,
6993 },
6994 .id_table = qla2xxx_pci_tbl,
6995 .probe = qla2x00_probe_one,
6996 .remove = qla2x00_remove_one,
6997 .shutdown = qla2x00_shutdown,
6998 .err_handler = &qla2xxx_err_handler,
6999 };
7000
7001 static const struct file_operations apidev_fops = {
7002 .owner = THIS_MODULE,
7003 .llseek = noop_llseek,
7004 };
7005
7006 /**
7007 * qla2x00_module_init - Module initialization.
7008 **/
7009 static int __init
7010 qla2x00_module_init(void)
7011 {
7012 int ret = 0;
7013
7014 /* Allocate cache for SRBs. */
7015 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0,
7016 SLAB_HWCACHE_ALIGN, NULL);
7017 if (srb_cachep == NULL) {
7018 ql_log(ql_log_fatal, NULL, 0x0001,
7019 "Unable to allocate SRB cache...Failing load!.\n");
7020 return -ENOMEM;
7021 }
7022
7023 /* Initialize target kmem_cache and mem_pools */
7024 ret = qlt_init();
7025 if (ret < 0) {
7026 kmem_cache_destroy(srb_cachep);
7027 return ret;
7028 } else if (ret > 0) {
7029 /*
7030 * If initiator mode is explictly disabled by qlt_init(),
7031 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from
7032 * performing scsi_scan_target() during LOOP UP event.
7033 */
7034 qla2xxx_transport_functions.disable_target_scan = 1;
7035 qla2xxx_transport_vport_functions.disable_target_scan = 1;
7036 }
7037
7038 /* Derive version string. */
7039 strcpy(qla2x00_version_str, QLA2XXX_VERSION);
7040 if (ql2xextended_error_logging)
7041 strcat(qla2x00_version_str, "-debug");
7042 if (ql2xextended_error_logging == 1)
7043 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
7044
7045 if (ql2x_ini_mode == QLA2XXX_INI_MODE_DUAL)
7046 qla_insert_tgt_attrs();
7047
7048 qla2xxx_transport_template =
7049 fc_attach_transport(&qla2xxx_transport_functions);
7050 if (!qla2xxx_transport_template) {
7051 kmem_cache_destroy(srb_cachep);
7052 ql_log(ql_log_fatal, NULL, 0x0002,
7053 "fc_attach_transport failed...Failing load!.\n");
7054 qlt_exit();
7055 return -ENODEV;
7056 }
7057
7058 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops);
7059 if (apidev_major < 0) {
7060 ql_log(ql_log_fatal, NULL, 0x0003,
7061 "Unable to register char device %s.\n", QLA2XXX_APIDEV);
7062 }
7063
7064 qla2xxx_transport_vport_template =
7065 fc_attach_transport(&qla2xxx_transport_vport_functions);
7066 if (!qla2xxx_transport_vport_template) {
7067 kmem_cache_destroy(srb_cachep);
7068 qlt_exit();
7069 fc_release_transport(qla2xxx_transport_template);
7070 ql_log(ql_log_fatal, NULL, 0x0004,
7071 "fc_attach_transport vport failed...Failing load!.\n");
7072 return -ENODEV;
7073 }
7074 ql_log(ql_log_info, NULL, 0x0005,
7075 "QLogic Fibre Channel HBA Driver: %s.\n",
7076 qla2x00_version_str);
7077 ret = pci_register_driver(&qla2xxx_pci_driver);
7078 if (ret) {
7079 kmem_cache_destroy(srb_cachep);
7080 qlt_exit();
7081 fc_release_transport(qla2xxx_transport_template);
7082 fc_release_transport(qla2xxx_transport_vport_template);
7083 ql_log(ql_log_fatal, NULL, 0x0006,
7084 "pci_register_driver failed...ret=%d Failing load!.\n",
7085 ret);
7086 }
7087 return ret;
7088 }
7089
7090 /**
7091 * qla2x00_module_exit - Module cleanup.
7092 **/
7093 static void __exit
7094 qla2x00_module_exit(void)
7095 {
7096 unregister_chrdev(apidev_major, QLA2XXX_APIDEV);
7097 pci_unregister_driver(&qla2xxx_pci_driver);
7098 qla2x00_release_firmware();
7099 kmem_cache_destroy(srb_cachep);
7100 qlt_exit();
7101 if (ctx_cachep)
7102 kmem_cache_destroy(ctx_cachep);
7103 fc_release_transport(qla2xxx_transport_template);
7104 fc_release_transport(qla2xxx_transport_vport_template);
7105 }
7106
7107 module_init(qla2x00_module_init);
7108 module_exit(qla2x00_module_exit);
7109
7110 MODULE_AUTHOR("QLogic Corporation");
7111 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver");
7112 MODULE_LICENSE("GPL");
7113 MODULE_VERSION(QLA2XXX_VERSION);
7114 MODULE_FIRMWARE(FW_FILE_ISP21XX);
7115 MODULE_FIRMWARE(FW_FILE_ISP22XX);
7116 MODULE_FIRMWARE(FW_FILE_ISP2300);
7117 MODULE_FIRMWARE(FW_FILE_ISP2322);
7118 MODULE_FIRMWARE(FW_FILE_ISP24XX);
7119 MODULE_FIRMWARE(FW_FILE_ISP25XX);