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powerpc/perf: Avoid spurious PMU interrupts after idle
[mirror_ubuntu-zesty-kernel.git] / drivers / tty / synclinkmp.c
1 /*
2 * $Id: synclinkmp.c,v 4.38 2005/07/15 13:29:44 paulkf Exp $
3 *
4 * Device driver for Microgate SyncLink Multiport
5 * high speed multiprotocol serial adapter.
6 *
7 * written by Paul Fulghum for Microgate Corporation
8 * paulkf@microgate.com
9 *
10 * Microgate and SyncLink are trademarks of Microgate Corporation
11 *
12 * Derived from serial.c written by Theodore Ts'o and Linus Torvalds
13 * This code is released under the GNU General Public License (GPL)
14 *
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
18 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
19 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
20 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
21 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
23 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
25 * OF THE POSSIBILITY OF SUCH DAMAGE.
26 */
27
28 #define VERSION(ver,rel,seq) (((ver)<<16) | ((rel)<<8) | (seq))
29 #if defined(__i386__)
30 # define BREAKPOINT() asm(" int $3");
31 #else
32 # define BREAKPOINT() { }
33 #endif
34
35 #define MAX_DEVICES 12
36
37 #include <linux/module.h>
38 #include <linux/errno.h>
39 #include <linux/signal.h>
40 #include <linux/sched.h>
41 #include <linux/timer.h>
42 #include <linux/interrupt.h>
43 #include <linux/pci.h>
44 #include <linux/tty.h>
45 #include <linux/tty_flip.h>
46 #include <linux/serial.h>
47 #include <linux/major.h>
48 #include <linux/string.h>
49 #include <linux/fcntl.h>
50 #include <linux/ptrace.h>
51 #include <linux/ioport.h>
52 #include <linux/mm.h>
53 #include <linux/seq_file.h>
54 #include <linux/slab.h>
55 #include <linux/netdevice.h>
56 #include <linux/vmalloc.h>
57 #include <linux/init.h>
58 #include <linux/delay.h>
59 #include <linux/ioctl.h>
60
61 #include <asm/io.h>
62 #include <asm/irq.h>
63 #include <asm/dma.h>
64 #include <linux/bitops.h>
65 #include <asm/types.h>
66 #include <linux/termios.h>
67 #include <linux/workqueue.h>
68 #include <linux/hdlc.h>
69 #include <linux/synclink.h>
70
71 #if defined(CONFIG_HDLC) || (defined(CONFIG_HDLC_MODULE) && defined(CONFIG_SYNCLINKMP_MODULE))
72 #define SYNCLINK_GENERIC_HDLC 1
73 #else
74 #define SYNCLINK_GENERIC_HDLC 0
75 #endif
76
77 #define GET_USER(error,value,addr) error = get_user(value,addr)
78 #define COPY_FROM_USER(error,dest,src,size) error = copy_from_user(dest,src,size) ? -EFAULT : 0
79 #define PUT_USER(error,value,addr) error = put_user(value,addr)
80 #define COPY_TO_USER(error,dest,src,size) error = copy_to_user(dest,src,size) ? -EFAULT : 0
81
82 #include <linux/uaccess.h>
83
84 static MGSL_PARAMS default_params = {
85 MGSL_MODE_HDLC, /* unsigned long mode */
86 0, /* unsigned char loopback; */
87 HDLC_FLAG_UNDERRUN_ABORT15, /* unsigned short flags; */
88 HDLC_ENCODING_NRZI_SPACE, /* unsigned char encoding; */
89 0, /* unsigned long clock_speed; */
90 0xff, /* unsigned char addr_filter; */
91 HDLC_CRC_16_CCITT, /* unsigned short crc_type; */
92 HDLC_PREAMBLE_LENGTH_8BITS, /* unsigned char preamble_length; */
93 HDLC_PREAMBLE_PATTERN_NONE, /* unsigned char preamble; */
94 9600, /* unsigned long data_rate; */
95 8, /* unsigned char data_bits; */
96 1, /* unsigned char stop_bits; */
97 ASYNC_PARITY_NONE /* unsigned char parity; */
98 };
99
100 /* size in bytes of DMA data buffers */
101 #define SCABUFSIZE 1024
102 #define SCA_MEM_SIZE 0x40000
103 #define SCA_BASE_SIZE 512
104 #define SCA_REG_SIZE 16
105 #define SCA_MAX_PORTS 4
106 #define SCAMAXDESC 128
107
108 #define BUFFERLISTSIZE 4096
109
110 /* SCA-I style DMA buffer descriptor */
111 typedef struct _SCADESC
112 {
113 u16 next; /* lower l6 bits of next descriptor addr */
114 u16 buf_ptr; /* lower 16 bits of buffer addr */
115 u8 buf_base; /* upper 8 bits of buffer addr */
116 u8 pad1;
117 u16 length; /* length of buffer */
118 u8 status; /* status of buffer */
119 u8 pad2;
120 } SCADESC, *PSCADESC;
121
122 typedef struct _SCADESC_EX
123 {
124 /* device driver bookkeeping section */
125 char *virt_addr; /* virtual address of data buffer */
126 u16 phys_entry; /* lower 16-bits of physical address of this descriptor */
127 } SCADESC_EX, *PSCADESC_EX;
128
129 /* The queue of BH actions to be performed */
130
131 #define BH_RECEIVE 1
132 #define BH_TRANSMIT 2
133 #define BH_STATUS 4
134
135 #define IO_PIN_SHUTDOWN_LIMIT 100
136
137 struct _input_signal_events {
138 int ri_up;
139 int ri_down;
140 int dsr_up;
141 int dsr_down;
142 int dcd_up;
143 int dcd_down;
144 int cts_up;
145 int cts_down;
146 };
147
148 /*
149 * Device instance data structure
150 */
151 typedef struct _synclinkmp_info {
152 void *if_ptr; /* General purpose pointer (used by SPPP) */
153 int magic;
154 struct tty_port port;
155 int line;
156 unsigned short close_delay;
157 unsigned short closing_wait; /* time to wait before closing */
158
159 struct mgsl_icount icount;
160
161 int timeout;
162 int x_char; /* xon/xoff character */
163 u16 read_status_mask1; /* break detection (SR1 indications) */
164 u16 read_status_mask2; /* parity/framing/overun (SR2 indications) */
165 unsigned char ignore_status_mask1; /* break detection (SR1 indications) */
166 unsigned char ignore_status_mask2; /* parity/framing/overun (SR2 indications) */
167 unsigned char *tx_buf;
168 int tx_put;
169 int tx_get;
170 int tx_count;
171
172 wait_queue_head_t status_event_wait_q;
173 wait_queue_head_t event_wait_q;
174 struct timer_list tx_timer; /* HDLC transmit timeout timer */
175 struct _synclinkmp_info *next_device; /* device list link */
176 struct timer_list status_timer; /* input signal status check timer */
177
178 spinlock_t lock; /* spinlock for synchronizing with ISR */
179 struct work_struct task; /* task structure for scheduling bh */
180
181 u32 max_frame_size; /* as set by device config */
182
183 u32 pending_bh;
184
185 bool bh_running; /* Protection from multiple */
186 int isr_overflow;
187 bool bh_requested;
188
189 int dcd_chkcount; /* check counts to prevent */
190 int cts_chkcount; /* too many IRQs if a signal */
191 int dsr_chkcount; /* is floating */
192 int ri_chkcount;
193
194 char *buffer_list; /* virtual address of Rx & Tx buffer lists */
195 unsigned long buffer_list_phys;
196
197 unsigned int rx_buf_count; /* count of total allocated Rx buffers */
198 SCADESC *rx_buf_list; /* list of receive buffer entries */
199 SCADESC_EX rx_buf_list_ex[SCAMAXDESC]; /* list of receive buffer entries */
200 unsigned int current_rx_buf;
201
202 unsigned int tx_buf_count; /* count of total allocated Tx buffers */
203 SCADESC *tx_buf_list; /* list of transmit buffer entries */
204 SCADESC_EX tx_buf_list_ex[SCAMAXDESC]; /* list of transmit buffer entries */
205 unsigned int last_tx_buf;
206
207 unsigned char *tmp_rx_buf;
208 unsigned int tmp_rx_buf_count;
209
210 bool rx_enabled;
211 bool rx_overflow;
212
213 bool tx_enabled;
214 bool tx_active;
215 u32 idle_mode;
216
217 unsigned char ie0_value;
218 unsigned char ie1_value;
219 unsigned char ie2_value;
220 unsigned char ctrlreg_value;
221 unsigned char old_signals;
222
223 char device_name[25]; /* device instance name */
224
225 int port_count;
226 int adapter_num;
227 int port_num;
228
229 struct _synclinkmp_info *port_array[SCA_MAX_PORTS];
230
231 unsigned int bus_type; /* expansion bus type (ISA,EISA,PCI) */
232
233 unsigned int irq_level; /* interrupt level */
234 unsigned long irq_flags;
235 bool irq_requested; /* true if IRQ requested */
236
237 MGSL_PARAMS params; /* communications parameters */
238
239 unsigned char serial_signals; /* current serial signal states */
240
241 bool irq_occurred; /* for diagnostics use */
242 unsigned int init_error; /* Initialization startup error */
243
244 u32 last_mem_alloc;
245 unsigned char* memory_base; /* shared memory address (PCI only) */
246 u32 phys_memory_base;
247 int shared_mem_requested;
248
249 unsigned char* sca_base; /* HD64570 SCA Memory address */
250 u32 phys_sca_base;
251 u32 sca_offset;
252 bool sca_base_requested;
253
254 unsigned char* lcr_base; /* local config registers (PCI only) */
255 u32 phys_lcr_base;
256 u32 lcr_offset;
257 int lcr_mem_requested;
258
259 unsigned char* statctrl_base; /* status/control register memory */
260 u32 phys_statctrl_base;
261 u32 statctrl_offset;
262 bool sca_statctrl_requested;
263
264 u32 misc_ctrl_value;
265 char *flag_buf;
266 bool drop_rts_on_tx_done;
267
268 struct _input_signal_events input_signal_events;
269
270 /* SPPP/Cisco HDLC device parts */
271 int netcount;
272 spinlock_t netlock;
273
274 #if SYNCLINK_GENERIC_HDLC
275 struct net_device *netdev;
276 #endif
277
278 } SLMP_INFO;
279
280 #define MGSL_MAGIC 0x5401
281
282 /*
283 * define serial signal status change macros
284 */
285 #define MISCSTATUS_DCD_LATCHED (SerialSignal_DCD<<8) /* indicates change in DCD */
286 #define MISCSTATUS_RI_LATCHED (SerialSignal_RI<<8) /* indicates change in RI */
287 #define MISCSTATUS_CTS_LATCHED (SerialSignal_CTS<<8) /* indicates change in CTS */
288 #define MISCSTATUS_DSR_LATCHED (SerialSignal_DSR<<8) /* change in DSR */
289
290 /* Common Register macros */
291 #define LPR 0x00
292 #define PABR0 0x02
293 #define PABR1 0x03
294 #define WCRL 0x04
295 #define WCRM 0x05
296 #define WCRH 0x06
297 #define DPCR 0x08
298 #define DMER 0x09
299 #define ISR0 0x10
300 #define ISR1 0x11
301 #define ISR2 0x12
302 #define IER0 0x14
303 #define IER1 0x15
304 #define IER2 0x16
305 #define ITCR 0x18
306 #define INTVR 0x1a
307 #define IMVR 0x1c
308
309 /* MSCI Register macros */
310 #define TRB 0x20
311 #define TRBL 0x20
312 #define TRBH 0x21
313 #define SR0 0x22
314 #define SR1 0x23
315 #define SR2 0x24
316 #define SR3 0x25
317 #define FST 0x26
318 #define IE0 0x28
319 #define IE1 0x29
320 #define IE2 0x2a
321 #define FIE 0x2b
322 #define CMD 0x2c
323 #define MD0 0x2e
324 #define MD1 0x2f
325 #define MD2 0x30
326 #define CTL 0x31
327 #define SA0 0x32
328 #define SA1 0x33
329 #define IDL 0x34
330 #define TMC 0x35
331 #define RXS 0x36
332 #define TXS 0x37
333 #define TRC0 0x38
334 #define TRC1 0x39
335 #define RRC 0x3a
336 #define CST0 0x3c
337 #define CST1 0x3d
338
339 /* Timer Register Macros */
340 #define TCNT 0x60
341 #define TCNTL 0x60
342 #define TCNTH 0x61
343 #define TCONR 0x62
344 #define TCONRL 0x62
345 #define TCONRH 0x63
346 #define TMCS 0x64
347 #define TEPR 0x65
348
349 /* DMA Controller Register macros */
350 #define DARL 0x80
351 #define DARH 0x81
352 #define DARB 0x82
353 #define BAR 0x80
354 #define BARL 0x80
355 #define BARH 0x81
356 #define BARB 0x82
357 #define SAR 0x84
358 #define SARL 0x84
359 #define SARH 0x85
360 #define SARB 0x86
361 #define CPB 0x86
362 #define CDA 0x88
363 #define CDAL 0x88
364 #define CDAH 0x89
365 #define EDA 0x8a
366 #define EDAL 0x8a
367 #define EDAH 0x8b
368 #define BFL 0x8c
369 #define BFLL 0x8c
370 #define BFLH 0x8d
371 #define BCR 0x8e
372 #define BCRL 0x8e
373 #define BCRH 0x8f
374 #define DSR 0x90
375 #define DMR 0x91
376 #define FCT 0x93
377 #define DIR 0x94
378 #define DCMD 0x95
379
380 /* combine with timer or DMA register address */
381 #define TIMER0 0x00
382 #define TIMER1 0x08
383 #define TIMER2 0x10
384 #define TIMER3 0x18
385 #define RXDMA 0x00
386 #define TXDMA 0x20
387
388 /* SCA Command Codes */
389 #define NOOP 0x00
390 #define TXRESET 0x01
391 #define TXENABLE 0x02
392 #define TXDISABLE 0x03
393 #define TXCRCINIT 0x04
394 #define TXCRCEXCL 0x05
395 #define TXEOM 0x06
396 #define TXABORT 0x07
397 #define MPON 0x08
398 #define TXBUFCLR 0x09
399 #define RXRESET 0x11
400 #define RXENABLE 0x12
401 #define RXDISABLE 0x13
402 #define RXCRCINIT 0x14
403 #define RXREJECT 0x15
404 #define SEARCHMP 0x16
405 #define RXCRCEXCL 0x17
406 #define RXCRCCALC 0x18
407 #define CHRESET 0x21
408 #define HUNT 0x31
409
410 /* DMA command codes */
411 #define SWABORT 0x01
412 #define FEICLEAR 0x02
413
414 /* IE0 */
415 #define TXINTE BIT7
416 #define RXINTE BIT6
417 #define TXRDYE BIT1
418 #define RXRDYE BIT0
419
420 /* IE1 & SR1 */
421 #define UDRN BIT7
422 #define IDLE BIT6
423 #define SYNCD BIT4
424 #define FLGD BIT4
425 #define CCTS BIT3
426 #define CDCD BIT2
427 #define BRKD BIT1
428 #define ABTD BIT1
429 #define GAPD BIT1
430 #define BRKE BIT0
431 #define IDLD BIT0
432
433 /* IE2 & SR2 */
434 #define EOM BIT7
435 #define PMP BIT6
436 #define SHRT BIT6
437 #define PE BIT5
438 #define ABT BIT5
439 #define FRME BIT4
440 #define RBIT BIT4
441 #define OVRN BIT3
442 #define CRCE BIT2
443
444
445 /*
446 * Global linked list of SyncLink devices
447 */
448 static SLMP_INFO *synclinkmp_device_list = NULL;
449 static int synclinkmp_adapter_count = -1;
450 static int synclinkmp_device_count = 0;
451
452 /*
453 * Set this param to non-zero to load eax with the
454 * .text section address and breakpoint on module load.
455 * This is useful for use with gdb and add-symbol-file command.
456 */
457 static bool break_on_load = 0;
458
459 /*
460 * Driver major number, defaults to zero to get auto
461 * assigned major number. May be forced as module parameter.
462 */
463 static int ttymajor = 0;
464
465 /*
466 * Array of user specified options for ISA adapters.
467 */
468 static int debug_level = 0;
469 static int maxframe[MAX_DEVICES] = {0,};
470
471 module_param(break_on_load, bool, 0);
472 module_param(ttymajor, int, 0);
473 module_param(debug_level, int, 0);
474 module_param_array(maxframe, int, NULL, 0);
475
476 static char *driver_name = "SyncLink MultiPort driver";
477 static char *driver_version = "$Revision: 4.38 $";
478
479 static int synclinkmp_init_one(struct pci_dev *dev,const struct pci_device_id *ent);
480 static void synclinkmp_remove_one(struct pci_dev *dev);
481
482 static struct pci_device_id synclinkmp_pci_tbl[] = {
483 { PCI_VENDOR_ID_MICROGATE, PCI_DEVICE_ID_MICROGATE_SCA, PCI_ANY_ID, PCI_ANY_ID, },
484 { 0, }, /* terminate list */
485 };
486 MODULE_DEVICE_TABLE(pci, synclinkmp_pci_tbl);
487
488 MODULE_LICENSE("GPL");
489
490 static struct pci_driver synclinkmp_pci_driver = {
491 .name = "synclinkmp",
492 .id_table = synclinkmp_pci_tbl,
493 .probe = synclinkmp_init_one,
494 .remove = synclinkmp_remove_one,
495 };
496
497
498 static struct tty_driver *serial_driver;
499
500 /* number of characters left in xmit buffer before we ask for more */
501 #define WAKEUP_CHARS 256
502
503
504 /* tty callbacks */
505
506 static int open(struct tty_struct *tty, struct file * filp);
507 static void close(struct tty_struct *tty, struct file * filp);
508 static void hangup(struct tty_struct *tty);
509 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios);
510
511 static int write(struct tty_struct *tty, const unsigned char *buf, int count);
512 static int put_char(struct tty_struct *tty, unsigned char ch);
513 static void send_xchar(struct tty_struct *tty, char ch);
514 static void wait_until_sent(struct tty_struct *tty, int timeout);
515 static int write_room(struct tty_struct *tty);
516 static void flush_chars(struct tty_struct *tty);
517 static void flush_buffer(struct tty_struct *tty);
518 static void tx_hold(struct tty_struct *tty);
519 static void tx_release(struct tty_struct *tty);
520
521 static int ioctl(struct tty_struct *tty, unsigned int cmd, unsigned long arg);
522 static int chars_in_buffer(struct tty_struct *tty);
523 static void throttle(struct tty_struct * tty);
524 static void unthrottle(struct tty_struct * tty);
525 static int set_break(struct tty_struct *tty, int break_state);
526
527 #if SYNCLINK_GENERIC_HDLC
528 #define dev_to_port(D) (dev_to_hdlc(D)->priv)
529 static void hdlcdev_tx_done(SLMP_INFO *info);
530 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size);
531 static int hdlcdev_init(SLMP_INFO *info);
532 static void hdlcdev_exit(SLMP_INFO *info);
533 #endif
534
535 /* ioctl handlers */
536
537 static int get_stats(SLMP_INFO *info, struct mgsl_icount __user *user_icount);
538 static int get_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
539 static int set_params(SLMP_INFO *info, MGSL_PARAMS __user *params);
540 static int get_txidle(SLMP_INFO *info, int __user *idle_mode);
541 static int set_txidle(SLMP_INFO *info, int idle_mode);
542 static int tx_enable(SLMP_INFO *info, int enable);
543 static int tx_abort(SLMP_INFO *info);
544 static int rx_enable(SLMP_INFO *info, int enable);
545 static int modem_input_wait(SLMP_INFO *info,int arg);
546 static int wait_mgsl_event(SLMP_INFO *info, int __user *mask_ptr);
547 static int tiocmget(struct tty_struct *tty);
548 static int tiocmset(struct tty_struct *tty,
549 unsigned int set, unsigned int clear);
550 static int set_break(struct tty_struct *tty, int break_state);
551
552 static int add_device(SLMP_INFO *info);
553 static int device_init(int adapter_num, struct pci_dev *pdev);
554 static int claim_resources(SLMP_INFO *info);
555 static void release_resources(SLMP_INFO *info);
556
557 static int startup(SLMP_INFO *info);
558 static int block_til_ready(struct tty_struct *tty, struct file * filp,SLMP_INFO *info);
559 static int carrier_raised(struct tty_port *port);
560 static void shutdown(SLMP_INFO *info);
561 static void program_hw(SLMP_INFO *info);
562 static void change_params(SLMP_INFO *info);
563
564 static bool init_adapter(SLMP_INFO *info);
565 static bool register_test(SLMP_INFO *info);
566 static bool irq_test(SLMP_INFO *info);
567 static bool loopback_test(SLMP_INFO *info);
568 static int adapter_test(SLMP_INFO *info);
569 static bool memory_test(SLMP_INFO *info);
570
571 static void reset_adapter(SLMP_INFO *info);
572 static void reset_port(SLMP_INFO *info);
573 static void async_mode(SLMP_INFO *info);
574 static void hdlc_mode(SLMP_INFO *info);
575
576 static void rx_stop(SLMP_INFO *info);
577 static void rx_start(SLMP_INFO *info);
578 static void rx_reset_buffers(SLMP_INFO *info);
579 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last);
580 static bool rx_get_frame(SLMP_INFO *info);
581
582 static void tx_start(SLMP_INFO *info);
583 static void tx_stop(SLMP_INFO *info);
584 static void tx_load_fifo(SLMP_INFO *info);
585 static void tx_set_idle(SLMP_INFO *info);
586 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count);
587
588 static void get_signals(SLMP_INFO *info);
589 static void set_signals(SLMP_INFO *info);
590 static void enable_loopback(SLMP_INFO *info, int enable);
591 static void set_rate(SLMP_INFO *info, u32 data_rate);
592
593 static int bh_action(SLMP_INFO *info);
594 static void bh_handler(struct work_struct *work);
595 static void bh_receive(SLMP_INFO *info);
596 static void bh_transmit(SLMP_INFO *info);
597 static void bh_status(SLMP_INFO *info);
598 static void isr_timer(SLMP_INFO *info);
599 static void isr_rxint(SLMP_INFO *info);
600 static void isr_rxrdy(SLMP_INFO *info);
601 static void isr_txint(SLMP_INFO *info);
602 static void isr_txrdy(SLMP_INFO *info);
603 static void isr_rxdmaok(SLMP_INFO *info);
604 static void isr_rxdmaerror(SLMP_INFO *info);
605 static void isr_txdmaok(SLMP_INFO *info);
606 static void isr_txdmaerror(SLMP_INFO *info);
607 static void isr_io_pin(SLMP_INFO *info, u16 status);
608
609 static int alloc_dma_bufs(SLMP_INFO *info);
610 static void free_dma_bufs(SLMP_INFO *info);
611 static int alloc_buf_list(SLMP_INFO *info);
612 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *list, SCADESC_EX *list_ex,int count);
613 static int alloc_tmp_rx_buf(SLMP_INFO *info);
614 static void free_tmp_rx_buf(SLMP_INFO *info);
615
616 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count);
617 static void trace_block(SLMP_INFO *info, const char* data, int count, int xmit);
618 static void tx_timeout(unsigned long context);
619 static void status_timeout(unsigned long context);
620
621 static unsigned char read_reg(SLMP_INFO *info, unsigned char addr);
622 static void write_reg(SLMP_INFO *info, unsigned char addr, unsigned char val);
623 static u16 read_reg16(SLMP_INFO *info, unsigned char addr);
624 static void write_reg16(SLMP_INFO *info, unsigned char addr, u16 val);
625 static unsigned char read_status_reg(SLMP_INFO * info);
626 static void write_control_reg(SLMP_INFO * info);
627
628
629 static unsigned char rx_active_fifo_level = 16; // rx request FIFO activation level in bytes
630 static unsigned char tx_active_fifo_level = 16; // tx request FIFO activation level in bytes
631 static unsigned char tx_negate_fifo_level = 32; // tx request FIFO negation level in bytes
632
633 static u32 misc_ctrl_value = 0x007e4040;
634 static u32 lcr1_brdr_value = 0x00800028;
635
636 static u32 read_ahead_count = 8;
637
638 /* DPCR, DMA Priority Control
639 *
640 * 07..05 Not used, must be 0
641 * 04 BRC, bus release condition: 0=all transfers complete
642 * 1=release after 1 xfer on all channels
643 * 03 CCC, channel change condition: 0=every cycle
644 * 1=after each channel completes all xfers
645 * 02..00 PR<2..0>, priority 100=round robin
646 *
647 * 00000100 = 0x00
648 */
649 static unsigned char dma_priority = 0x04;
650
651 // Number of bytes that can be written to shared RAM
652 // in a single write operation
653 static u32 sca_pci_load_interval = 64;
654
655 /*
656 * 1st function defined in .text section. Calling this function in
657 * init_module() followed by a breakpoint allows a remote debugger
658 * (gdb) to get the .text address for the add-symbol-file command.
659 * This allows remote debugging of dynamically loadable modules.
660 */
661 static void* synclinkmp_get_text_ptr(void);
662 static void* synclinkmp_get_text_ptr(void) {return synclinkmp_get_text_ptr;}
663
664 static inline int sanity_check(SLMP_INFO *info,
665 char *name, const char *routine)
666 {
667 #ifdef SANITY_CHECK
668 static const char *badmagic =
669 "Warning: bad magic number for synclinkmp_struct (%s) in %s\n";
670 static const char *badinfo =
671 "Warning: null synclinkmp_struct for (%s) in %s\n";
672
673 if (!info) {
674 printk(badinfo, name, routine);
675 return 1;
676 }
677 if (info->magic != MGSL_MAGIC) {
678 printk(badmagic, name, routine);
679 return 1;
680 }
681 #else
682 if (!info)
683 return 1;
684 #endif
685 return 0;
686 }
687
688 /**
689 * line discipline callback wrappers
690 *
691 * The wrappers maintain line discipline references
692 * while calling into the line discipline.
693 *
694 * ldisc_receive_buf - pass receive data to line discipline
695 */
696
697 static void ldisc_receive_buf(struct tty_struct *tty,
698 const __u8 *data, char *flags, int count)
699 {
700 struct tty_ldisc *ld;
701 if (!tty)
702 return;
703 ld = tty_ldisc_ref(tty);
704 if (ld) {
705 if (ld->ops->receive_buf)
706 ld->ops->receive_buf(tty, data, flags, count);
707 tty_ldisc_deref(ld);
708 }
709 }
710
711 /* tty callbacks */
712
713 static int install(struct tty_driver *driver, struct tty_struct *tty)
714 {
715 SLMP_INFO *info;
716 int line = tty->index;
717
718 if (line >= synclinkmp_device_count) {
719 printk("%s(%d): open with invalid line #%d.\n",
720 __FILE__,__LINE__,line);
721 return -ENODEV;
722 }
723
724 info = synclinkmp_device_list;
725 while (info && info->line != line)
726 info = info->next_device;
727 if (sanity_check(info, tty->name, "open"))
728 return -ENODEV;
729 if (info->init_error) {
730 printk("%s(%d):%s device is not allocated, init error=%d\n",
731 __FILE__, __LINE__, info->device_name,
732 info->init_error);
733 return -ENODEV;
734 }
735
736 tty->driver_data = info;
737
738 return tty_port_install(&info->port, driver, tty);
739 }
740
741 /* Called when a port is opened. Init and enable port.
742 */
743 static int open(struct tty_struct *tty, struct file *filp)
744 {
745 SLMP_INFO *info = tty->driver_data;
746 unsigned long flags;
747 int retval;
748
749 info->port.tty = tty;
750
751 if (debug_level >= DEBUG_LEVEL_INFO)
752 printk("%s(%d):%s open(), old ref count = %d\n",
753 __FILE__,__LINE__,tty->driver->name, info->port.count);
754
755 info->port.low_latency = (info->port.flags & ASYNC_LOW_LATENCY) ? 1 : 0;
756
757 spin_lock_irqsave(&info->netlock, flags);
758 if (info->netcount) {
759 retval = -EBUSY;
760 spin_unlock_irqrestore(&info->netlock, flags);
761 goto cleanup;
762 }
763 info->port.count++;
764 spin_unlock_irqrestore(&info->netlock, flags);
765
766 if (info->port.count == 1) {
767 /* 1st open on this device, init hardware */
768 retval = startup(info);
769 if (retval < 0)
770 goto cleanup;
771 }
772
773 retval = block_til_ready(tty, filp, info);
774 if (retval) {
775 if (debug_level >= DEBUG_LEVEL_INFO)
776 printk("%s(%d):%s block_til_ready() returned %d\n",
777 __FILE__,__LINE__, info->device_name, retval);
778 goto cleanup;
779 }
780
781 if (debug_level >= DEBUG_LEVEL_INFO)
782 printk("%s(%d):%s open() success\n",
783 __FILE__,__LINE__, info->device_name);
784 retval = 0;
785
786 cleanup:
787 if (retval) {
788 if (tty->count == 1)
789 info->port.tty = NULL; /* tty layer will release tty struct */
790 if(info->port.count)
791 info->port.count--;
792 }
793
794 return retval;
795 }
796
797 /* Called when port is closed. Wait for remaining data to be
798 * sent. Disable port and free resources.
799 */
800 static void close(struct tty_struct *tty, struct file *filp)
801 {
802 SLMP_INFO * info = tty->driver_data;
803
804 if (sanity_check(info, tty->name, "close"))
805 return;
806
807 if (debug_level >= DEBUG_LEVEL_INFO)
808 printk("%s(%d):%s close() entry, count=%d\n",
809 __FILE__,__LINE__, info->device_name, info->port.count);
810
811 if (tty_port_close_start(&info->port, tty, filp) == 0)
812 goto cleanup;
813
814 mutex_lock(&info->port.mutex);
815 if (tty_port_initialized(&info->port))
816 wait_until_sent(tty, info->timeout);
817
818 flush_buffer(tty);
819 tty_ldisc_flush(tty);
820 shutdown(info);
821 mutex_unlock(&info->port.mutex);
822
823 tty_port_close_end(&info->port, tty);
824 info->port.tty = NULL;
825 cleanup:
826 if (debug_level >= DEBUG_LEVEL_INFO)
827 printk("%s(%d):%s close() exit, count=%d\n", __FILE__,__LINE__,
828 tty->driver->name, info->port.count);
829 }
830
831 /* Called by tty_hangup() when a hangup is signaled.
832 * This is the same as closing all open descriptors for the port.
833 */
834 static void hangup(struct tty_struct *tty)
835 {
836 SLMP_INFO *info = tty->driver_data;
837 unsigned long flags;
838
839 if (debug_level >= DEBUG_LEVEL_INFO)
840 printk("%s(%d):%s hangup()\n",
841 __FILE__,__LINE__, info->device_name );
842
843 if (sanity_check(info, tty->name, "hangup"))
844 return;
845
846 mutex_lock(&info->port.mutex);
847 flush_buffer(tty);
848 shutdown(info);
849
850 spin_lock_irqsave(&info->port.lock, flags);
851 info->port.count = 0;
852 info->port.tty = NULL;
853 spin_unlock_irqrestore(&info->port.lock, flags);
854 tty_port_set_active(&info->port, 1);
855 mutex_unlock(&info->port.mutex);
856
857 wake_up_interruptible(&info->port.open_wait);
858 }
859
860 /* Set new termios settings
861 */
862 static void set_termios(struct tty_struct *tty, struct ktermios *old_termios)
863 {
864 SLMP_INFO *info = tty->driver_data;
865 unsigned long flags;
866
867 if (debug_level >= DEBUG_LEVEL_INFO)
868 printk("%s(%d):%s set_termios()\n", __FILE__,__LINE__,
869 tty->driver->name );
870
871 change_params(info);
872
873 /* Handle transition to B0 status */
874 if ((old_termios->c_cflag & CBAUD) && !C_BAUD(tty)) {
875 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
876 spin_lock_irqsave(&info->lock,flags);
877 set_signals(info);
878 spin_unlock_irqrestore(&info->lock,flags);
879 }
880
881 /* Handle transition away from B0 status */
882 if (!(old_termios->c_cflag & CBAUD) && C_BAUD(tty)) {
883 info->serial_signals |= SerialSignal_DTR;
884 if (!C_CRTSCTS(tty) || !tty_throttled(tty))
885 info->serial_signals |= SerialSignal_RTS;
886 spin_lock_irqsave(&info->lock,flags);
887 set_signals(info);
888 spin_unlock_irqrestore(&info->lock,flags);
889 }
890
891 /* Handle turning off CRTSCTS */
892 if (old_termios->c_cflag & CRTSCTS && !C_CRTSCTS(tty)) {
893 tty->hw_stopped = 0;
894 tx_release(tty);
895 }
896 }
897
898 /* Send a block of data
899 *
900 * Arguments:
901 *
902 * tty pointer to tty information structure
903 * buf pointer to buffer containing send data
904 * count size of send data in bytes
905 *
906 * Return Value: number of characters written
907 */
908 static int write(struct tty_struct *tty,
909 const unsigned char *buf, int count)
910 {
911 int c, ret = 0;
912 SLMP_INFO *info = tty->driver_data;
913 unsigned long flags;
914
915 if (debug_level >= DEBUG_LEVEL_INFO)
916 printk("%s(%d):%s write() count=%d\n",
917 __FILE__,__LINE__,info->device_name,count);
918
919 if (sanity_check(info, tty->name, "write"))
920 goto cleanup;
921
922 if (!info->tx_buf)
923 goto cleanup;
924
925 if (info->params.mode == MGSL_MODE_HDLC) {
926 if (count > info->max_frame_size) {
927 ret = -EIO;
928 goto cleanup;
929 }
930 if (info->tx_active)
931 goto cleanup;
932 if (info->tx_count) {
933 /* send accumulated data from send_char() calls */
934 /* as frame and wait before accepting more data. */
935 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
936 goto start;
937 }
938 ret = info->tx_count = count;
939 tx_load_dma_buffer(info, buf, count);
940 goto start;
941 }
942
943 for (;;) {
944 c = min_t(int, count,
945 min(info->max_frame_size - info->tx_count - 1,
946 info->max_frame_size - info->tx_put));
947 if (c <= 0)
948 break;
949
950 memcpy(info->tx_buf + info->tx_put, buf, c);
951
952 spin_lock_irqsave(&info->lock,flags);
953 info->tx_put += c;
954 if (info->tx_put >= info->max_frame_size)
955 info->tx_put -= info->max_frame_size;
956 info->tx_count += c;
957 spin_unlock_irqrestore(&info->lock,flags);
958
959 buf += c;
960 count -= c;
961 ret += c;
962 }
963
964 if (info->params.mode == MGSL_MODE_HDLC) {
965 if (count) {
966 ret = info->tx_count = 0;
967 goto cleanup;
968 }
969 tx_load_dma_buffer(info, info->tx_buf, info->tx_count);
970 }
971 start:
972 if (info->tx_count && !tty->stopped && !tty->hw_stopped) {
973 spin_lock_irqsave(&info->lock,flags);
974 if (!info->tx_active)
975 tx_start(info);
976 spin_unlock_irqrestore(&info->lock,flags);
977 }
978
979 cleanup:
980 if (debug_level >= DEBUG_LEVEL_INFO)
981 printk( "%s(%d):%s write() returning=%d\n",
982 __FILE__,__LINE__,info->device_name,ret);
983 return ret;
984 }
985
986 /* Add a character to the transmit buffer.
987 */
988 static int put_char(struct tty_struct *tty, unsigned char ch)
989 {
990 SLMP_INFO *info = tty->driver_data;
991 unsigned long flags;
992 int ret = 0;
993
994 if ( debug_level >= DEBUG_LEVEL_INFO ) {
995 printk( "%s(%d):%s put_char(%d)\n",
996 __FILE__,__LINE__,info->device_name,ch);
997 }
998
999 if (sanity_check(info, tty->name, "put_char"))
1000 return 0;
1001
1002 if (!info->tx_buf)
1003 return 0;
1004
1005 spin_lock_irqsave(&info->lock,flags);
1006
1007 if ( (info->params.mode != MGSL_MODE_HDLC) ||
1008 !info->tx_active ) {
1009
1010 if (info->tx_count < info->max_frame_size - 1) {
1011 info->tx_buf[info->tx_put++] = ch;
1012 if (info->tx_put >= info->max_frame_size)
1013 info->tx_put -= info->max_frame_size;
1014 info->tx_count++;
1015 ret = 1;
1016 }
1017 }
1018
1019 spin_unlock_irqrestore(&info->lock,flags);
1020 return ret;
1021 }
1022
1023 /* Send a high-priority XON/XOFF character
1024 */
1025 static void send_xchar(struct tty_struct *tty, char ch)
1026 {
1027 SLMP_INFO *info = tty->driver_data;
1028 unsigned long flags;
1029
1030 if (debug_level >= DEBUG_LEVEL_INFO)
1031 printk("%s(%d):%s send_xchar(%d)\n",
1032 __FILE__,__LINE__, info->device_name, ch );
1033
1034 if (sanity_check(info, tty->name, "send_xchar"))
1035 return;
1036
1037 info->x_char = ch;
1038 if (ch) {
1039 /* Make sure transmit interrupts are on */
1040 spin_lock_irqsave(&info->lock,flags);
1041 if (!info->tx_enabled)
1042 tx_start(info);
1043 spin_unlock_irqrestore(&info->lock,flags);
1044 }
1045 }
1046
1047 /* Wait until the transmitter is empty.
1048 */
1049 static void wait_until_sent(struct tty_struct *tty, int timeout)
1050 {
1051 SLMP_INFO * info = tty->driver_data;
1052 unsigned long orig_jiffies, char_time;
1053
1054 if (!info )
1055 return;
1056
1057 if (debug_level >= DEBUG_LEVEL_INFO)
1058 printk("%s(%d):%s wait_until_sent() entry\n",
1059 __FILE__,__LINE__, info->device_name );
1060
1061 if (sanity_check(info, tty->name, "wait_until_sent"))
1062 return;
1063
1064 if (!tty_port_initialized(&info->port))
1065 goto exit;
1066
1067 orig_jiffies = jiffies;
1068
1069 /* Set check interval to 1/5 of estimated time to
1070 * send a character, and make it at least 1. The check
1071 * interval should also be less than the timeout.
1072 * Note: use tight timings here to satisfy the NIST-PCTS.
1073 */
1074
1075 if ( info->params.data_rate ) {
1076 char_time = info->timeout/(32 * 5);
1077 if (!char_time)
1078 char_time++;
1079 } else
1080 char_time = 1;
1081
1082 if (timeout)
1083 char_time = min_t(unsigned long, char_time, timeout);
1084
1085 if ( info->params.mode == MGSL_MODE_HDLC ) {
1086 while (info->tx_active) {
1087 msleep_interruptible(jiffies_to_msecs(char_time));
1088 if (signal_pending(current))
1089 break;
1090 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1091 break;
1092 }
1093 } else {
1094 /*
1095 * TODO: determine if there is something similar to USC16C32
1096 * TXSTATUS_ALL_SENT status
1097 */
1098 while ( info->tx_active && info->tx_enabled) {
1099 msleep_interruptible(jiffies_to_msecs(char_time));
1100 if (signal_pending(current))
1101 break;
1102 if (timeout && time_after(jiffies, orig_jiffies + timeout))
1103 break;
1104 }
1105 }
1106
1107 exit:
1108 if (debug_level >= DEBUG_LEVEL_INFO)
1109 printk("%s(%d):%s wait_until_sent() exit\n",
1110 __FILE__,__LINE__, info->device_name );
1111 }
1112
1113 /* Return the count of free bytes in transmit buffer
1114 */
1115 static int write_room(struct tty_struct *tty)
1116 {
1117 SLMP_INFO *info = tty->driver_data;
1118 int ret;
1119
1120 if (sanity_check(info, tty->name, "write_room"))
1121 return 0;
1122
1123 if (info->params.mode == MGSL_MODE_HDLC) {
1124 ret = (info->tx_active) ? 0 : HDLC_MAX_FRAME_SIZE;
1125 } else {
1126 ret = info->max_frame_size - info->tx_count - 1;
1127 if (ret < 0)
1128 ret = 0;
1129 }
1130
1131 if (debug_level >= DEBUG_LEVEL_INFO)
1132 printk("%s(%d):%s write_room()=%d\n",
1133 __FILE__, __LINE__, info->device_name, ret);
1134
1135 return ret;
1136 }
1137
1138 /* enable transmitter and send remaining buffered characters
1139 */
1140 static void flush_chars(struct tty_struct *tty)
1141 {
1142 SLMP_INFO *info = tty->driver_data;
1143 unsigned long flags;
1144
1145 if ( debug_level >= DEBUG_LEVEL_INFO )
1146 printk( "%s(%d):%s flush_chars() entry tx_count=%d\n",
1147 __FILE__,__LINE__,info->device_name,info->tx_count);
1148
1149 if (sanity_check(info, tty->name, "flush_chars"))
1150 return;
1151
1152 if (info->tx_count <= 0 || tty->stopped || tty->hw_stopped ||
1153 !info->tx_buf)
1154 return;
1155
1156 if ( debug_level >= DEBUG_LEVEL_INFO )
1157 printk( "%s(%d):%s flush_chars() entry, starting transmitter\n",
1158 __FILE__,__LINE__,info->device_name );
1159
1160 spin_lock_irqsave(&info->lock,flags);
1161
1162 if (!info->tx_active) {
1163 if ( (info->params.mode == MGSL_MODE_HDLC) &&
1164 info->tx_count ) {
1165 /* operating in synchronous (frame oriented) mode */
1166 /* copy data from circular tx_buf to */
1167 /* transmit DMA buffer. */
1168 tx_load_dma_buffer(info,
1169 info->tx_buf,info->tx_count);
1170 }
1171 tx_start(info);
1172 }
1173
1174 spin_unlock_irqrestore(&info->lock,flags);
1175 }
1176
1177 /* Discard all data in the send buffer
1178 */
1179 static void flush_buffer(struct tty_struct *tty)
1180 {
1181 SLMP_INFO *info = tty->driver_data;
1182 unsigned long flags;
1183
1184 if (debug_level >= DEBUG_LEVEL_INFO)
1185 printk("%s(%d):%s flush_buffer() entry\n",
1186 __FILE__,__LINE__, info->device_name );
1187
1188 if (sanity_check(info, tty->name, "flush_buffer"))
1189 return;
1190
1191 spin_lock_irqsave(&info->lock,flags);
1192 info->tx_count = info->tx_put = info->tx_get = 0;
1193 del_timer(&info->tx_timer);
1194 spin_unlock_irqrestore(&info->lock,flags);
1195
1196 tty_wakeup(tty);
1197 }
1198
1199 /* throttle (stop) transmitter
1200 */
1201 static void tx_hold(struct tty_struct *tty)
1202 {
1203 SLMP_INFO *info = tty->driver_data;
1204 unsigned long flags;
1205
1206 if (sanity_check(info, tty->name, "tx_hold"))
1207 return;
1208
1209 if ( debug_level >= DEBUG_LEVEL_INFO )
1210 printk("%s(%d):%s tx_hold()\n",
1211 __FILE__,__LINE__,info->device_name);
1212
1213 spin_lock_irqsave(&info->lock,flags);
1214 if (info->tx_enabled)
1215 tx_stop(info);
1216 spin_unlock_irqrestore(&info->lock,flags);
1217 }
1218
1219 /* release (start) transmitter
1220 */
1221 static void tx_release(struct tty_struct *tty)
1222 {
1223 SLMP_INFO *info = tty->driver_data;
1224 unsigned long flags;
1225
1226 if (sanity_check(info, tty->name, "tx_release"))
1227 return;
1228
1229 if ( debug_level >= DEBUG_LEVEL_INFO )
1230 printk("%s(%d):%s tx_release()\n",
1231 __FILE__,__LINE__,info->device_name);
1232
1233 spin_lock_irqsave(&info->lock,flags);
1234 if (!info->tx_enabled)
1235 tx_start(info);
1236 spin_unlock_irqrestore(&info->lock,flags);
1237 }
1238
1239 /* Service an IOCTL request
1240 *
1241 * Arguments:
1242 *
1243 * tty pointer to tty instance data
1244 * cmd IOCTL command code
1245 * arg command argument/context
1246 *
1247 * Return Value: 0 if success, otherwise error code
1248 */
1249 static int ioctl(struct tty_struct *tty,
1250 unsigned int cmd, unsigned long arg)
1251 {
1252 SLMP_INFO *info = tty->driver_data;
1253 void __user *argp = (void __user *)arg;
1254
1255 if (debug_level >= DEBUG_LEVEL_INFO)
1256 printk("%s(%d):%s ioctl() cmd=%08X\n", __FILE__,__LINE__,
1257 info->device_name, cmd );
1258
1259 if (sanity_check(info, tty->name, "ioctl"))
1260 return -ENODEV;
1261
1262 if ((cmd != TIOCGSERIAL) && (cmd != TIOCSSERIAL) &&
1263 (cmd != TIOCMIWAIT)) {
1264 if (tty_io_error(tty))
1265 return -EIO;
1266 }
1267
1268 switch (cmd) {
1269 case MGSL_IOCGPARAMS:
1270 return get_params(info, argp);
1271 case MGSL_IOCSPARAMS:
1272 return set_params(info, argp);
1273 case MGSL_IOCGTXIDLE:
1274 return get_txidle(info, argp);
1275 case MGSL_IOCSTXIDLE:
1276 return set_txidle(info, (int)arg);
1277 case MGSL_IOCTXENABLE:
1278 return tx_enable(info, (int)arg);
1279 case MGSL_IOCRXENABLE:
1280 return rx_enable(info, (int)arg);
1281 case MGSL_IOCTXABORT:
1282 return tx_abort(info);
1283 case MGSL_IOCGSTATS:
1284 return get_stats(info, argp);
1285 case MGSL_IOCWAITEVENT:
1286 return wait_mgsl_event(info, argp);
1287 case MGSL_IOCLOOPTXDONE:
1288 return 0; // TODO: Not supported, need to document
1289 /* Wait for modem input (DCD,RI,DSR,CTS) change
1290 * as specified by mask in arg (TIOCM_RNG/DSR/CD/CTS)
1291 */
1292 case TIOCMIWAIT:
1293 return modem_input_wait(info,(int)arg);
1294
1295 /*
1296 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS)
1297 * Return: write counters to the user passed counter struct
1298 * NB: both 1->0 and 0->1 transitions are counted except for
1299 * RI where only 0->1 is counted.
1300 */
1301 default:
1302 return -ENOIOCTLCMD;
1303 }
1304 return 0;
1305 }
1306
1307 static int get_icount(struct tty_struct *tty,
1308 struct serial_icounter_struct *icount)
1309 {
1310 SLMP_INFO *info = tty->driver_data;
1311 struct mgsl_icount cnow; /* kernel counter temps */
1312 unsigned long flags;
1313
1314 spin_lock_irqsave(&info->lock,flags);
1315 cnow = info->icount;
1316 spin_unlock_irqrestore(&info->lock,flags);
1317
1318 icount->cts = cnow.cts;
1319 icount->dsr = cnow.dsr;
1320 icount->rng = cnow.rng;
1321 icount->dcd = cnow.dcd;
1322 icount->rx = cnow.rx;
1323 icount->tx = cnow.tx;
1324 icount->frame = cnow.frame;
1325 icount->overrun = cnow.overrun;
1326 icount->parity = cnow.parity;
1327 icount->brk = cnow.brk;
1328 icount->buf_overrun = cnow.buf_overrun;
1329
1330 return 0;
1331 }
1332
1333 /*
1334 * /proc fs routines....
1335 */
1336
1337 static inline void line_info(struct seq_file *m, SLMP_INFO *info)
1338 {
1339 char stat_buf[30];
1340 unsigned long flags;
1341
1342 seq_printf(m, "%s: SCABase=%08x Mem=%08X StatusControl=%08x LCR=%08X\n"
1343 "\tIRQ=%d MaxFrameSize=%u\n",
1344 info->device_name,
1345 info->phys_sca_base,
1346 info->phys_memory_base,
1347 info->phys_statctrl_base,
1348 info->phys_lcr_base,
1349 info->irq_level,
1350 info->max_frame_size );
1351
1352 /* output current serial signal states */
1353 spin_lock_irqsave(&info->lock,flags);
1354 get_signals(info);
1355 spin_unlock_irqrestore(&info->lock,flags);
1356
1357 stat_buf[0] = 0;
1358 stat_buf[1] = 0;
1359 if (info->serial_signals & SerialSignal_RTS)
1360 strcat(stat_buf, "|RTS");
1361 if (info->serial_signals & SerialSignal_CTS)
1362 strcat(stat_buf, "|CTS");
1363 if (info->serial_signals & SerialSignal_DTR)
1364 strcat(stat_buf, "|DTR");
1365 if (info->serial_signals & SerialSignal_DSR)
1366 strcat(stat_buf, "|DSR");
1367 if (info->serial_signals & SerialSignal_DCD)
1368 strcat(stat_buf, "|CD");
1369 if (info->serial_signals & SerialSignal_RI)
1370 strcat(stat_buf, "|RI");
1371
1372 if (info->params.mode == MGSL_MODE_HDLC) {
1373 seq_printf(m, "\tHDLC txok:%d rxok:%d",
1374 info->icount.txok, info->icount.rxok);
1375 if (info->icount.txunder)
1376 seq_printf(m, " txunder:%d", info->icount.txunder);
1377 if (info->icount.txabort)
1378 seq_printf(m, " txabort:%d", info->icount.txabort);
1379 if (info->icount.rxshort)
1380 seq_printf(m, " rxshort:%d", info->icount.rxshort);
1381 if (info->icount.rxlong)
1382 seq_printf(m, " rxlong:%d", info->icount.rxlong);
1383 if (info->icount.rxover)
1384 seq_printf(m, " rxover:%d", info->icount.rxover);
1385 if (info->icount.rxcrc)
1386 seq_printf(m, " rxlong:%d", info->icount.rxcrc);
1387 } else {
1388 seq_printf(m, "\tASYNC tx:%d rx:%d",
1389 info->icount.tx, info->icount.rx);
1390 if (info->icount.frame)
1391 seq_printf(m, " fe:%d", info->icount.frame);
1392 if (info->icount.parity)
1393 seq_printf(m, " pe:%d", info->icount.parity);
1394 if (info->icount.brk)
1395 seq_printf(m, " brk:%d", info->icount.brk);
1396 if (info->icount.overrun)
1397 seq_printf(m, " oe:%d", info->icount.overrun);
1398 }
1399
1400 /* Append serial signal status to end */
1401 seq_printf(m, " %s\n", stat_buf+1);
1402
1403 seq_printf(m, "\ttxactive=%d bh_req=%d bh_run=%d pending_bh=%x\n",
1404 info->tx_active,info->bh_requested,info->bh_running,
1405 info->pending_bh);
1406 }
1407
1408 /* Called to print information about devices
1409 */
1410 static int synclinkmp_proc_show(struct seq_file *m, void *v)
1411 {
1412 SLMP_INFO *info;
1413
1414 seq_printf(m, "synclinkmp driver:%s\n", driver_version);
1415
1416 info = synclinkmp_device_list;
1417 while( info ) {
1418 line_info(m, info);
1419 info = info->next_device;
1420 }
1421 return 0;
1422 }
1423
1424 static int synclinkmp_proc_open(struct inode *inode, struct file *file)
1425 {
1426 return single_open(file, synclinkmp_proc_show, NULL);
1427 }
1428
1429 static const struct file_operations synclinkmp_proc_fops = {
1430 .owner = THIS_MODULE,
1431 .open = synclinkmp_proc_open,
1432 .read = seq_read,
1433 .llseek = seq_lseek,
1434 .release = single_release,
1435 };
1436
1437 /* Return the count of bytes in transmit buffer
1438 */
1439 static int chars_in_buffer(struct tty_struct *tty)
1440 {
1441 SLMP_INFO *info = tty->driver_data;
1442
1443 if (sanity_check(info, tty->name, "chars_in_buffer"))
1444 return 0;
1445
1446 if (debug_level >= DEBUG_LEVEL_INFO)
1447 printk("%s(%d):%s chars_in_buffer()=%d\n",
1448 __FILE__, __LINE__, info->device_name, info->tx_count);
1449
1450 return info->tx_count;
1451 }
1452
1453 /* Signal remote device to throttle send data (our receive data)
1454 */
1455 static void throttle(struct tty_struct * tty)
1456 {
1457 SLMP_INFO *info = tty->driver_data;
1458 unsigned long flags;
1459
1460 if (debug_level >= DEBUG_LEVEL_INFO)
1461 printk("%s(%d):%s throttle() entry\n",
1462 __FILE__,__LINE__, info->device_name );
1463
1464 if (sanity_check(info, tty->name, "throttle"))
1465 return;
1466
1467 if (I_IXOFF(tty))
1468 send_xchar(tty, STOP_CHAR(tty));
1469
1470 if (C_CRTSCTS(tty)) {
1471 spin_lock_irqsave(&info->lock,flags);
1472 info->serial_signals &= ~SerialSignal_RTS;
1473 set_signals(info);
1474 spin_unlock_irqrestore(&info->lock,flags);
1475 }
1476 }
1477
1478 /* Signal remote device to stop throttling send data (our receive data)
1479 */
1480 static void unthrottle(struct tty_struct * tty)
1481 {
1482 SLMP_INFO *info = tty->driver_data;
1483 unsigned long flags;
1484
1485 if (debug_level >= DEBUG_LEVEL_INFO)
1486 printk("%s(%d):%s unthrottle() entry\n",
1487 __FILE__,__LINE__, info->device_name );
1488
1489 if (sanity_check(info, tty->name, "unthrottle"))
1490 return;
1491
1492 if (I_IXOFF(tty)) {
1493 if (info->x_char)
1494 info->x_char = 0;
1495 else
1496 send_xchar(tty, START_CHAR(tty));
1497 }
1498
1499 if (C_CRTSCTS(tty)) {
1500 spin_lock_irqsave(&info->lock,flags);
1501 info->serial_signals |= SerialSignal_RTS;
1502 set_signals(info);
1503 spin_unlock_irqrestore(&info->lock,flags);
1504 }
1505 }
1506
1507 /* set or clear transmit break condition
1508 * break_state -1=set break condition, 0=clear
1509 */
1510 static int set_break(struct tty_struct *tty, int break_state)
1511 {
1512 unsigned char RegValue;
1513 SLMP_INFO * info = tty->driver_data;
1514 unsigned long flags;
1515
1516 if (debug_level >= DEBUG_LEVEL_INFO)
1517 printk("%s(%d):%s set_break(%d)\n",
1518 __FILE__,__LINE__, info->device_name, break_state);
1519
1520 if (sanity_check(info, tty->name, "set_break"))
1521 return -EINVAL;
1522
1523 spin_lock_irqsave(&info->lock,flags);
1524 RegValue = read_reg(info, CTL);
1525 if (break_state == -1)
1526 RegValue |= BIT3;
1527 else
1528 RegValue &= ~BIT3;
1529 write_reg(info, CTL, RegValue);
1530 spin_unlock_irqrestore(&info->lock,flags);
1531 return 0;
1532 }
1533
1534 #if SYNCLINK_GENERIC_HDLC
1535
1536 /**
1537 * called by generic HDLC layer when protocol selected (PPP, frame relay, etc.)
1538 * set encoding and frame check sequence (FCS) options
1539 *
1540 * dev pointer to network device structure
1541 * encoding serial encoding setting
1542 * parity FCS setting
1543 *
1544 * returns 0 if success, otherwise error code
1545 */
1546 static int hdlcdev_attach(struct net_device *dev, unsigned short encoding,
1547 unsigned short parity)
1548 {
1549 SLMP_INFO *info = dev_to_port(dev);
1550 unsigned char new_encoding;
1551 unsigned short new_crctype;
1552
1553 /* return error if TTY interface open */
1554 if (info->port.count)
1555 return -EBUSY;
1556
1557 switch (encoding)
1558 {
1559 case ENCODING_NRZ: new_encoding = HDLC_ENCODING_NRZ; break;
1560 case ENCODING_NRZI: new_encoding = HDLC_ENCODING_NRZI_SPACE; break;
1561 case ENCODING_FM_MARK: new_encoding = HDLC_ENCODING_BIPHASE_MARK; break;
1562 case ENCODING_FM_SPACE: new_encoding = HDLC_ENCODING_BIPHASE_SPACE; break;
1563 case ENCODING_MANCHESTER: new_encoding = HDLC_ENCODING_BIPHASE_LEVEL; break;
1564 default: return -EINVAL;
1565 }
1566
1567 switch (parity)
1568 {
1569 case PARITY_NONE: new_crctype = HDLC_CRC_NONE; break;
1570 case PARITY_CRC16_PR1_CCITT: new_crctype = HDLC_CRC_16_CCITT; break;
1571 case PARITY_CRC32_PR1_CCITT: new_crctype = HDLC_CRC_32_CCITT; break;
1572 default: return -EINVAL;
1573 }
1574
1575 info->params.encoding = new_encoding;
1576 info->params.crc_type = new_crctype;
1577
1578 /* if network interface up, reprogram hardware */
1579 if (info->netcount)
1580 program_hw(info);
1581
1582 return 0;
1583 }
1584
1585 /**
1586 * called by generic HDLC layer to send frame
1587 *
1588 * skb socket buffer containing HDLC frame
1589 * dev pointer to network device structure
1590 */
1591 static netdev_tx_t hdlcdev_xmit(struct sk_buff *skb,
1592 struct net_device *dev)
1593 {
1594 SLMP_INFO *info = dev_to_port(dev);
1595 unsigned long flags;
1596
1597 if (debug_level >= DEBUG_LEVEL_INFO)
1598 printk(KERN_INFO "%s:hdlc_xmit(%s)\n",__FILE__,dev->name);
1599
1600 /* stop sending until this frame completes */
1601 netif_stop_queue(dev);
1602
1603 /* copy data to device buffers */
1604 info->tx_count = skb->len;
1605 tx_load_dma_buffer(info, skb->data, skb->len);
1606
1607 /* update network statistics */
1608 dev->stats.tx_packets++;
1609 dev->stats.tx_bytes += skb->len;
1610
1611 /* done with socket buffer, so free it */
1612 dev_kfree_skb(skb);
1613
1614 /* save start time for transmit timeout detection */
1615 netif_trans_update(dev);
1616
1617 /* start hardware transmitter if necessary */
1618 spin_lock_irqsave(&info->lock,flags);
1619 if (!info->tx_active)
1620 tx_start(info);
1621 spin_unlock_irqrestore(&info->lock,flags);
1622
1623 return NETDEV_TX_OK;
1624 }
1625
1626 /**
1627 * called by network layer when interface enabled
1628 * claim resources and initialize hardware
1629 *
1630 * dev pointer to network device structure
1631 *
1632 * returns 0 if success, otherwise error code
1633 */
1634 static int hdlcdev_open(struct net_device *dev)
1635 {
1636 SLMP_INFO *info = dev_to_port(dev);
1637 int rc;
1638 unsigned long flags;
1639
1640 if (debug_level >= DEBUG_LEVEL_INFO)
1641 printk("%s:hdlcdev_open(%s)\n",__FILE__,dev->name);
1642
1643 /* generic HDLC layer open processing */
1644 rc = hdlc_open(dev);
1645 if (rc)
1646 return rc;
1647
1648 /* arbitrate between network and tty opens */
1649 spin_lock_irqsave(&info->netlock, flags);
1650 if (info->port.count != 0 || info->netcount != 0) {
1651 printk(KERN_WARNING "%s: hdlc_open returning busy\n", dev->name);
1652 spin_unlock_irqrestore(&info->netlock, flags);
1653 return -EBUSY;
1654 }
1655 info->netcount=1;
1656 spin_unlock_irqrestore(&info->netlock, flags);
1657
1658 /* claim resources and init adapter */
1659 if ((rc = startup(info)) != 0) {
1660 spin_lock_irqsave(&info->netlock, flags);
1661 info->netcount=0;
1662 spin_unlock_irqrestore(&info->netlock, flags);
1663 return rc;
1664 }
1665
1666 /* assert RTS and DTR, apply hardware settings */
1667 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
1668 program_hw(info);
1669
1670 /* enable network layer transmit */
1671 netif_trans_update(dev);
1672 netif_start_queue(dev);
1673
1674 /* inform generic HDLC layer of current DCD status */
1675 spin_lock_irqsave(&info->lock, flags);
1676 get_signals(info);
1677 spin_unlock_irqrestore(&info->lock, flags);
1678 if (info->serial_signals & SerialSignal_DCD)
1679 netif_carrier_on(dev);
1680 else
1681 netif_carrier_off(dev);
1682 return 0;
1683 }
1684
1685 /**
1686 * called by network layer when interface is disabled
1687 * shutdown hardware and release resources
1688 *
1689 * dev pointer to network device structure
1690 *
1691 * returns 0 if success, otherwise error code
1692 */
1693 static int hdlcdev_close(struct net_device *dev)
1694 {
1695 SLMP_INFO *info = dev_to_port(dev);
1696 unsigned long flags;
1697
1698 if (debug_level >= DEBUG_LEVEL_INFO)
1699 printk("%s:hdlcdev_close(%s)\n",__FILE__,dev->name);
1700
1701 netif_stop_queue(dev);
1702
1703 /* shutdown adapter and release resources */
1704 shutdown(info);
1705
1706 hdlc_close(dev);
1707
1708 spin_lock_irqsave(&info->netlock, flags);
1709 info->netcount=0;
1710 spin_unlock_irqrestore(&info->netlock, flags);
1711
1712 return 0;
1713 }
1714
1715 /**
1716 * called by network layer to process IOCTL call to network device
1717 *
1718 * dev pointer to network device structure
1719 * ifr pointer to network interface request structure
1720 * cmd IOCTL command code
1721 *
1722 * returns 0 if success, otherwise error code
1723 */
1724 static int hdlcdev_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1725 {
1726 const size_t size = sizeof(sync_serial_settings);
1727 sync_serial_settings new_line;
1728 sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
1729 SLMP_INFO *info = dev_to_port(dev);
1730 unsigned int flags;
1731
1732 if (debug_level >= DEBUG_LEVEL_INFO)
1733 printk("%s:hdlcdev_ioctl(%s)\n",__FILE__,dev->name);
1734
1735 /* return error if TTY interface open */
1736 if (info->port.count)
1737 return -EBUSY;
1738
1739 if (cmd != SIOCWANDEV)
1740 return hdlc_ioctl(dev, ifr, cmd);
1741
1742 switch(ifr->ifr_settings.type) {
1743 case IF_GET_IFACE: /* return current sync_serial_settings */
1744
1745 ifr->ifr_settings.type = IF_IFACE_SYNC_SERIAL;
1746 if (ifr->ifr_settings.size < size) {
1747 ifr->ifr_settings.size = size; /* data size wanted */
1748 return -ENOBUFS;
1749 }
1750
1751 flags = info->params.flags & (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1752 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1753 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1754 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1755
1756 memset(&new_line, 0, sizeof(new_line));
1757 switch (flags){
1758 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN): new_line.clock_type = CLOCK_EXT; break;
1759 case (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_INT; break;
1760 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG): new_line.clock_type = CLOCK_TXINT; break;
1761 case (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN): new_line.clock_type = CLOCK_TXFROMRX; break;
1762 default: new_line.clock_type = CLOCK_DEFAULT;
1763 }
1764
1765 new_line.clock_rate = info->params.clock_speed;
1766 new_line.loopback = info->params.loopback ? 1:0;
1767
1768 if (copy_to_user(line, &new_line, size))
1769 return -EFAULT;
1770 return 0;
1771
1772 case IF_IFACE_SYNC_SERIAL: /* set sync_serial_settings */
1773
1774 if(!capable(CAP_NET_ADMIN))
1775 return -EPERM;
1776 if (copy_from_user(&new_line, line, size))
1777 return -EFAULT;
1778
1779 switch (new_line.clock_type)
1780 {
1781 case CLOCK_EXT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_TXCPIN; break;
1782 case CLOCK_TXFROMRX: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_RXCPIN; break;
1783 case CLOCK_INT: flags = HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG; break;
1784 case CLOCK_TXINT: flags = HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_TXC_BRG; break;
1785 case CLOCK_DEFAULT: flags = info->params.flags &
1786 (HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1787 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1788 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1789 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN); break;
1790 default: return -EINVAL;
1791 }
1792
1793 if (new_line.loopback != 0 && new_line.loopback != 1)
1794 return -EINVAL;
1795
1796 info->params.flags &= ~(HDLC_FLAG_RXC_RXCPIN | HDLC_FLAG_RXC_DPLL |
1797 HDLC_FLAG_RXC_BRG | HDLC_FLAG_RXC_TXCPIN |
1798 HDLC_FLAG_TXC_TXCPIN | HDLC_FLAG_TXC_DPLL |
1799 HDLC_FLAG_TXC_BRG | HDLC_FLAG_TXC_RXCPIN);
1800 info->params.flags |= flags;
1801
1802 info->params.loopback = new_line.loopback;
1803
1804 if (flags & (HDLC_FLAG_RXC_BRG | HDLC_FLAG_TXC_BRG))
1805 info->params.clock_speed = new_line.clock_rate;
1806 else
1807 info->params.clock_speed = 0;
1808
1809 /* if network interface up, reprogram hardware */
1810 if (info->netcount)
1811 program_hw(info);
1812 return 0;
1813
1814 default:
1815 return hdlc_ioctl(dev, ifr, cmd);
1816 }
1817 }
1818
1819 /**
1820 * called by network layer when transmit timeout is detected
1821 *
1822 * dev pointer to network device structure
1823 */
1824 static void hdlcdev_tx_timeout(struct net_device *dev)
1825 {
1826 SLMP_INFO *info = dev_to_port(dev);
1827 unsigned long flags;
1828
1829 if (debug_level >= DEBUG_LEVEL_INFO)
1830 printk("hdlcdev_tx_timeout(%s)\n",dev->name);
1831
1832 dev->stats.tx_errors++;
1833 dev->stats.tx_aborted_errors++;
1834
1835 spin_lock_irqsave(&info->lock,flags);
1836 tx_stop(info);
1837 spin_unlock_irqrestore(&info->lock,flags);
1838
1839 netif_wake_queue(dev);
1840 }
1841
1842 /**
1843 * called by device driver when transmit completes
1844 * reenable network layer transmit if stopped
1845 *
1846 * info pointer to device instance information
1847 */
1848 static void hdlcdev_tx_done(SLMP_INFO *info)
1849 {
1850 if (netif_queue_stopped(info->netdev))
1851 netif_wake_queue(info->netdev);
1852 }
1853
1854 /**
1855 * called by device driver when frame received
1856 * pass frame to network layer
1857 *
1858 * info pointer to device instance information
1859 * buf pointer to buffer contianing frame data
1860 * size count of data bytes in buf
1861 */
1862 static void hdlcdev_rx(SLMP_INFO *info, char *buf, int size)
1863 {
1864 struct sk_buff *skb = dev_alloc_skb(size);
1865 struct net_device *dev = info->netdev;
1866
1867 if (debug_level >= DEBUG_LEVEL_INFO)
1868 printk("hdlcdev_rx(%s)\n",dev->name);
1869
1870 if (skb == NULL) {
1871 printk(KERN_NOTICE "%s: can't alloc skb, dropping packet\n",
1872 dev->name);
1873 dev->stats.rx_dropped++;
1874 return;
1875 }
1876
1877 memcpy(skb_put(skb, size), buf, size);
1878
1879 skb->protocol = hdlc_type_trans(skb, dev);
1880
1881 dev->stats.rx_packets++;
1882 dev->stats.rx_bytes += size;
1883
1884 netif_rx(skb);
1885 }
1886
1887 static const struct net_device_ops hdlcdev_ops = {
1888 .ndo_open = hdlcdev_open,
1889 .ndo_stop = hdlcdev_close,
1890 .ndo_start_xmit = hdlc_start_xmit,
1891 .ndo_do_ioctl = hdlcdev_ioctl,
1892 .ndo_tx_timeout = hdlcdev_tx_timeout,
1893 };
1894
1895 /**
1896 * called by device driver when adding device instance
1897 * do generic HDLC initialization
1898 *
1899 * info pointer to device instance information
1900 *
1901 * returns 0 if success, otherwise error code
1902 */
1903 static int hdlcdev_init(SLMP_INFO *info)
1904 {
1905 int rc;
1906 struct net_device *dev;
1907 hdlc_device *hdlc;
1908
1909 /* allocate and initialize network and HDLC layer objects */
1910
1911 dev = alloc_hdlcdev(info);
1912 if (!dev) {
1913 printk(KERN_ERR "%s:hdlc device allocation failure\n",__FILE__);
1914 return -ENOMEM;
1915 }
1916
1917 /* for network layer reporting purposes only */
1918 dev->mem_start = info->phys_sca_base;
1919 dev->mem_end = info->phys_sca_base + SCA_BASE_SIZE - 1;
1920 dev->irq = info->irq_level;
1921
1922 /* network layer callbacks and settings */
1923 dev->netdev_ops = &hdlcdev_ops;
1924 dev->watchdog_timeo = 10 * HZ;
1925 dev->tx_queue_len = 50;
1926
1927 /* generic HDLC layer callbacks and settings */
1928 hdlc = dev_to_hdlc(dev);
1929 hdlc->attach = hdlcdev_attach;
1930 hdlc->xmit = hdlcdev_xmit;
1931
1932 /* register objects with HDLC layer */
1933 rc = register_hdlc_device(dev);
1934 if (rc) {
1935 printk(KERN_WARNING "%s:unable to register hdlc device\n",__FILE__);
1936 free_netdev(dev);
1937 return rc;
1938 }
1939
1940 info->netdev = dev;
1941 return 0;
1942 }
1943
1944 /**
1945 * called by device driver when removing device instance
1946 * do generic HDLC cleanup
1947 *
1948 * info pointer to device instance information
1949 */
1950 static void hdlcdev_exit(SLMP_INFO *info)
1951 {
1952 unregister_hdlc_device(info->netdev);
1953 free_netdev(info->netdev);
1954 info->netdev = NULL;
1955 }
1956
1957 #endif /* CONFIG_HDLC */
1958
1959
1960 /* Return next bottom half action to perform.
1961 * Return Value: BH action code or 0 if nothing to do.
1962 */
1963 static int bh_action(SLMP_INFO *info)
1964 {
1965 unsigned long flags;
1966 int rc = 0;
1967
1968 spin_lock_irqsave(&info->lock,flags);
1969
1970 if (info->pending_bh & BH_RECEIVE) {
1971 info->pending_bh &= ~BH_RECEIVE;
1972 rc = BH_RECEIVE;
1973 } else if (info->pending_bh & BH_TRANSMIT) {
1974 info->pending_bh &= ~BH_TRANSMIT;
1975 rc = BH_TRANSMIT;
1976 } else if (info->pending_bh & BH_STATUS) {
1977 info->pending_bh &= ~BH_STATUS;
1978 rc = BH_STATUS;
1979 }
1980
1981 if (!rc) {
1982 /* Mark BH routine as complete */
1983 info->bh_running = false;
1984 info->bh_requested = false;
1985 }
1986
1987 spin_unlock_irqrestore(&info->lock,flags);
1988
1989 return rc;
1990 }
1991
1992 /* Perform bottom half processing of work items queued by ISR.
1993 */
1994 static void bh_handler(struct work_struct *work)
1995 {
1996 SLMP_INFO *info = container_of(work, SLMP_INFO, task);
1997 int action;
1998
1999 if ( debug_level >= DEBUG_LEVEL_BH )
2000 printk( "%s(%d):%s bh_handler() entry\n",
2001 __FILE__,__LINE__,info->device_name);
2002
2003 info->bh_running = true;
2004
2005 while((action = bh_action(info)) != 0) {
2006
2007 /* Process work item */
2008 if ( debug_level >= DEBUG_LEVEL_BH )
2009 printk( "%s(%d):%s bh_handler() work item action=%d\n",
2010 __FILE__,__LINE__,info->device_name, action);
2011
2012 switch (action) {
2013
2014 case BH_RECEIVE:
2015 bh_receive(info);
2016 break;
2017 case BH_TRANSMIT:
2018 bh_transmit(info);
2019 break;
2020 case BH_STATUS:
2021 bh_status(info);
2022 break;
2023 default:
2024 /* unknown work item ID */
2025 printk("%s(%d):%s Unknown work item ID=%08X!\n",
2026 __FILE__,__LINE__,info->device_name,action);
2027 break;
2028 }
2029 }
2030
2031 if ( debug_level >= DEBUG_LEVEL_BH )
2032 printk( "%s(%d):%s bh_handler() exit\n",
2033 __FILE__,__LINE__,info->device_name);
2034 }
2035
2036 static void bh_receive(SLMP_INFO *info)
2037 {
2038 if ( debug_level >= DEBUG_LEVEL_BH )
2039 printk( "%s(%d):%s bh_receive()\n",
2040 __FILE__,__LINE__,info->device_name);
2041
2042 while( rx_get_frame(info) );
2043 }
2044
2045 static void bh_transmit(SLMP_INFO *info)
2046 {
2047 struct tty_struct *tty = info->port.tty;
2048
2049 if ( debug_level >= DEBUG_LEVEL_BH )
2050 printk( "%s(%d):%s bh_transmit() entry\n",
2051 __FILE__,__LINE__,info->device_name);
2052
2053 if (tty)
2054 tty_wakeup(tty);
2055 }
2056
2057 static void bh_status(SLMP_INFO *info)
2058 {
2059 if ( debug_level >= DEBUG_LEVEL_BH )
2060 printk( "%s(%d):%s bh_status() entry\n",
2061 __FILE__,__LINE__,info->device_name);
2062
2063 info->ri_chkcount = 0;
2064 info->dsr_chkcount = 0;
2065 info->dcd_chkcount = 0;
2066 info->cts_chkcount = 0;
2067 }
2068
2069 static void isr_timer(SLMP_INFO * info)
2070 {
2071 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
2072
2073 /* IER2<7..4> = timer<3..0> interrupt enables (0=disabled) */
2074 write_reg(info, IER2, 0);
2075
2076 /* TMCS, Timer Control/Status Register
2077 *
2078 * 07 CMF, Compare match flag (read only) 1=match
2079 * 06 ECMI, CMF Interrupt Enable: 0=disabled
2080 * 05 Reserved, must be 0
2081 * 04 TME, Timer Enable
2082 * 03..00 Reserved, must be 0
2083 *
2084 * 0000 0000
2085 */
2086 write_reg(info, (unsigned char)(timer + TMCS), 0);
2087
2088 info->irq_occurred = true;
2089
2090 if ( debug_level >= DEBUG_LEVEL_ISR )
2091 printk("%s(%d):%s isr_timer()\n",
2092 __FILE__,__LINE__,info->device_name);
2093 }
2094
2095 static void isr_rxint(SLMP_INFO * info)
2096 {
2097 struct tty_struct *tty = info->port.tty;
2098 struct mgsl_icount *icount = &info->icount;
2099 unsigned char status = read_reg(info, SR1) & info->ie1_value & (FLGD + IDLD + CDCD + BRKD);
2100 unsigned char status2 = read_reg(info, SR2) & info->ie2_value & OVRN;
2101
2102 /* clear status bits */
2103 if (status)
2104 write_reg(info, SR1, status);
2105
2106 if (status2)
2107 write_reg(info, SR2, status2);
2108
2109 if ( debug_level >= DEBUG_LEVEL_ISR )
2110 printk("%s(%d):%s isr_rxint status=%02X %02x\n",
2111 __FILE__,__LINE__,info->device_name,status,status2);
2112
2113 if (info->params.mode == MGSL_MODE_ASYNC) {
2114 if (status & BRKD) {
2115 icount->brk++;
2116
2117 /* process break detection if tty control
2118 * is not set to ignore it
2119 */
2120 if (!(status & info->ignore_status_mask1)) {
2121 if (info->read_status_mask1 & BRKD) {
2122 tty_insert_flip_char(&info->port, 0, TTY_BREAK);
2123 if (tty && (info->port.flags & ASYNC_SAK))
2124 do_SAK(tty);
2125 }
2126 }
2127 }
2128 }
2129 else {
2130 if (status & (FLGD|IDLD)) {
2131 if (status & FLGD)
2132 info->icount.exithunt++;
2133 else if (status & IDLD)
2134 info->icount.rxidle++;
2135 wake_up_interruptible(&info->event_wait_q);
2136 }
2137 }
2138
2139 if (status & CDCD) {
2140 /* simulate a common modem status change interrupt
2141 * for our handler
2142 */
2143 get_signals( info );
2144 isr_io_pin(info,
2145 MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD));
2146 }
2147 }
2148
2149 /*
2150 * handle async rx data interrupts
2151 */
2152 static void isr_rxrdy(SLMP_INFO * info)
2153 {
2154 u16 status;
2155 unsigned char DataByte;
2156 struct mgsl_icount *icount = &info->icount;
2157
2158 if ( debug_level >= DEBUG_LEVEL_ISR )
2159 printk("%s(%d):%s isr_rxrdy\n",
2160 __FILE__,__LINE__,info->device_name);
2161
2162 while((status = read_reg(info,CST0)) & BIT0)
2163 {
2164 int flag = 0;
2165 bool over = false;
2166 DataByte = read_reg(info,TRB);
2167
2168 icount->rx++;
2169
2170 if ( status & (PE + FRME + OVRN) ) {
2171 printk("%s(%d):%s rxerr=%04X\n",
2172 __FILE__,__LINE__,info->device_name,status);
2173
2174 /* update error statistics */
2175 if (status & PE)
2176 icount->parity++;
2177 else if (status & FRME)
2178 icount->frame++;
2179 else if (status & OVRN)
2180 icount->overrun++;
2181
2182 /* discard char if tty control flags say so */
2183 if (status & info->ignore_status_mask2)
2184 continue;
2185
2186 status &= info->read_status_mask2;
2187
2188 if (status & PE)
2189 flag = TTY_PARITY;
2190 else if (status & FRME)
2191 flag = TTY_FRAME;
2192 if (status & OVRN) {
2193 /* Overrun is special, since it's
2194 * reported immediately, and doesn't
2195 * affect the current character
2196 */
2197 over = true;
2198 }
2199 } /* end of if (error) */
2200
2201 tty_insert_flip_char(&info->port, DataByte, flag);
2202 if (over)
2203 tty_insert_flip_char(&info->port, 0, TTY_OVERRUN);
2204 }
2205
2206 if ( debug_level >= DEBUG_LEVEL_ISR ) {
2207 printk("%s(%d):%s rx=%d brk=%d parity=%d frame=%d overrun=%d\n",
2208 __FILE__,__LINE__,info->device_name,
2209 icount->rx,icount->brk,icount->parity,
2210 icount->frame,icount->overrun);
2211 }
2212
2213 tty_flip_buffer_push(&info->port);
2214 }
2215
2216 static void isr_txeom(SLMP_INFO * info, unsigned char status)
2217 {
2218 if ( debug_level >= DEBUG_LEVEL_ISR )
2219 printk("%s(%d):%s isr_txeom status=%02x\n",
2220 __FILE__,__LINE__,info->device_name,status);
2221
2222 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2223 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2224 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2225
2226 if (status & UDRN) {
2227 write_reg(info, CMD, TXRESET);
2228 write_reg(info, CMD, TXENABLE);
2229 } else
2230 write_reg(info, CMD, TXBUFCLR);
2231
2232 /* disable and clear tx interrupts */
2233 info->ie0_value &= ~TXRDYE;
2234 info->ie1_value &= ~(IDLE + UDRN);
2235 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2236 write_reg(info, SR1, (unsigned char)(UDRN + IDLE));
2237
2238 if ( info->tx_active ) {
2239 if (info->params.mode != MGSL_MODE_ASYNC) {
2240 if (status & UDRN)
2241 info->icount.txunder++;
2242 else if (status & IDLE)
2243 info->icount.txok++;
2244 }
2245
2246 info->tx_active = false;
2247 info->tx_count = info->tx_put = info->tx_get = 0;
2248
2249 del_timer(&info->tx_timer);
2250
2251 if (info->params.mode != MGSL_MODE_ASYNC && info->drop_rts_on_tx_done ) {
2252 info->serial_signals &= ~SerialSignal_RTS;
2253 info->drop_rts_on_tx_done = false;
2254 set_signals(info);
2255 }
2256
2257 #if SYNCLINK_GENERIC_HDLC
2258 if (info->netcount)
2259 hdlcdev_tx_done(info);
2260 else
2261 #endif
2262 {
2263 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2264 tx_stop(info);
2265 return;
2266 }
2267 info->pending_bh |= BH_TRANSMIT;
2268 }
2269 }
2270 }
2271
2272
2273 /*
2274 * handle tx status interrupts
2275 */
2276 static void isr_txint(SLMP_INFO * info)
2277 {
2278 unsigned char status = read_reg(info, SR1) & info->ie1_value & (UDRN + IDLE + CCTS);
2279
2280 /* clear status bits */
2281 write_reg(info, SR1, status);
2282
2283 if ( debug_level >= DEBUG_LEVEL_ISR )
2284 printk("%s(%d):%s isr_txint status=%02x\n",
2285 __FILE__,__LINE__,info->device_name,status);
2286
2287 if (status & (UDRN + IDLE))
2288 isr_txeom(info, status);
2289
2290 if (status & CCTS) {
2291 /* simulate a common modem status change interrupt
2292 * for our handler
2293 */
2294 get_signals( info );
2295 isr_io_pin(info,
2296 MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS));
2297
2298 }
2299 }
2300
2301 /*
2302 * handle async tx data interrupts
2303 */
2304 static void isr_txrdy(SLMP_INFO * info)
2305 {
2306 if ( debug_level >= DEBUG_LEVEL_ISR )
2307 printk("%s(%d):%s isr_txrdy() tx_count=%d\n",
2308 __FILE__,__LINE__,info->device_name,info->tx_count);
2309
2310 if (info->params.mode != MGSL_MODE_ASYNC) {
2311 /* disable TXRDY IRQ, enable IDLE IRQ */
2312 info->ie0_value &= ~TXRDYE;
2313 info->ie1_value |= IDLE;
2314 write_reg16(info, IE0, (unsigned short)((info->ie1_value << 8) + info->ie0_value));
2315 return;
2316 }
2317
2318 if (info->port.tty && (info->port.tty->stopped || info->port.tty->hw_stopped)) {
2319 tx_stop(info);
2320 return;
2321 }
2322
2323 if ( info->tx_count )
2324 tx_load_fifo( info );
2325 else {
2326 info->tx_active = false;
2327 info->ie0_value &= ~TXRDYE;
2328 write_reg(info, IE0, info->ie0_value);
2329 }
2330
2331 if (info->tx_count < WAKEUP_CHARS)
2332 info->pending_bh |= BH_TRANSMIT;
2333 }
2334
2335 static void isr_rxdmaok(SLMP_INFO * info)
2336 {
2337 /* BIT7 = EOT (end of transfer)
2338 * BIT6 = EOM (end of message/frame)
2339 */
2340 unsigned char status = read_reg(info,RXDMA + DSR) & 0xc0;
2341
2342 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2343 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2344
2345 if ( debug_level >= DEBUG_LEVEL_ISR )
2346 printk("%s(%d):%s isr_rxdmaok(), status=%02x\n",
2347 __FILE__,__LINE__,info->device_name,status);
2348
2349 info->pending_bh |= BH_RECEIVE;
2350 }
2351
2352 static void isr_rxdmaerror(SLMP_INFO * info)
2353 {
2354 /* BIT5 = BOF (buffer overflow)
2355 * BIT4 = COF (counter overflow)
2356 */
2357 unsigned char status = read_reg(info,RXDMA + DSR) & 0x30;
2358
2359 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2360 write_reg(info, RXDMA + DSR, (unsigned char)(status | 1));
2361
2362 if ( debug_level >= DEBUG_LEVEL_ISR )
2363 printk("%s(%d):%s isr_rxdmaerror(), status=%02x\n",
2364 __FILE__,__LINE__,info->device_name,status);
2365
2366 info->rx_overflow = true;
2367 info->pending_bh |= BH_RECEIVE;
2368 }
2369
2370 static void isr_txdmaok(SLMP_INFO * info)
2371 {
2372 unsigned char status_reg1 = read_reg(info, SR1);
2373
2374 write_reg(info, TXDMA + DIR, 0x00); /* disable Tx DMA IRQs */
2375 write_reg(info, TXDMA + DSR, 0xc0); /* clear IRQs and disable DMA */
2376 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2377
2378 if ( debug_level >= DEBUG_LEVEL_ISR )
2379 printk("%s(%d):%s isr_txdmaok(), status=%02x\n",
2380 __FILE__,__LINE__,info->device_name,status_reg1);
2381
2382 /* program TXRDY as FIFO empty flag, enable TXRDY IRQ */
2383 write_reg16(info, TRC0, 0);
2384 info->ie0_value |= TXRDYE;
2385 write_reg(info, IE0, info->ie0_value);
2386 }
2387
2388 static void isr_txdmaerror(SLMP_INFO * info)
2389 {
2390 /* BIT5 = BOF (buffer overflow)
2391 * BIT4 = COF (counter overflow)
2392 */
2393 unsigned char status = read_reg(info,TXDMA + DSR) & 0x30;
2394
2395 /* clear IRQ (BIT0 must be 1 to prevent clearing DE bit) */
2396 write_reg(info, TXDMA + DSR, (unsigned char)(status | 1));
2397
2398 if ( debug_level >= DEBUG_LEVEL_ISR )
2399 printk("%s(%d):%s isr_txdmaerror(), status=%02x\n",
2400 __FILE__,__LINE__,info->device_name,status);
2401 }
2402
2403 /* handle input serial signal changes
2404 */
2405 static void isr_io_pin( SLMP_INFO *info, u16 status )
2406 {
2407 struct mgsl_icount *icount;
2408
2409 if ( debug_level >= DEBUG_LEVEL_ISR )
2410 printk("%s(%d):isr_io_pin status=%04X\n",
2411 __FILE__,__LINE__,status);
2412
2413 if (status & (MISCSTATUS_CTS_LATCHED | MISCSTATUS_DCD_LATCHED |
2414 MISCSTATUS_DSR_LATCHED | MISCSTATUS_RI_LATCHED) ) {
2415 icount = &info->icount;
2416 /* update input line counters */
2417 if (status & MISCSTATUS_RI_LATCHED) {
2418 icount->rng++;
2419 if ( status & SerialSignal_RI )
2420 info->input_signal_events.ri_up++;
2421 else
2422 info->input_signal_events.ri_down++;
2423 }
2424 if (status & MISCSTATUS_DSR_LATCHED) {
2425 icount->dsr++;
2426 if ( status & SerialSignal_DSR )
2427 info->input_signal_events.dsr_up++;
2428 else
2429 info->input_signal_events.dsr_down++;
2430 }
2431 if (status & MISCSTATUS_DCD_LATCHED) {
2432 if ((info->dcd_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2433 info->ie1_value &= ~CDCD;
2434 write_reg(info, IE1, info->ie1_value);
2435 }
2436 icount->dcd++;
2437 if (status & SerialSignal_DCD) {
2438 info->input_signal_events.dcd_up++;
2439 } else
2440 info->input_signal_events.dcd_down++;
2441 #if SYNCLINK_GENERIC_HDLC
2442 if (info->netcount) {
2443 if (status & SerialSignal_DCD)
2444 netif_carrier_on(info->netdev);
2445 else
2446 netif_carrier_off(info->netdev);
2447 }
2448 #endif
2449 }
2450 if (status & MISCSTATUS_CTS_LATCHED)
2451 {
2452 if ((info->cts_chkcount)++ >= IO_PIN_SHUTDOWN_LIMIT) {
2453 info->ie1_value &= ~CCTS;
2454 write_reg(info, IE1, info->ie1_value);
2455 }
2456 icount->cts++;
2457 if ( status & SerialSignal_CTS )
2458 info->input_signal_events.cts_up++;
2459 else
2460 info->input_signal_events.cts_down++;
2461 }
2462 wake_up_interruptible(&info->status_event_wait_q);
2463 wake_up_interruptible(&info->event_wait_q);
2464
2465 if (tty_port_check_carrier(&info->port) &&
2466 (status & MISCSTATUS_DCD_LATCHED) ) {
2467 if ( debug_level >= DEBUG_LEVEL_ISR )
2468 printk("%s CD now %s...", info->device_name,
2469 (status & SerialSignal_DCD) ? "on" : "off");
2470 if (status & SerialSignal_DCD)
2471 wake_up_interruptible(&info->port.open_wait);
2472 else {
2473 if ( debug_level >= DEBUG_LEVEL_ISR )
2474 printk("doing serial hangup...");
2475 if (info->port.tty)
2476 tty_hangup(info->port.tty);
2477 }
2478 }
2479
2480 if (tty_port_cts_enabled(&info->port) &&
2481 (status & MISCSTATUS_CTS_LATCHED) ) {
2482 if ( info->port.tty ) {
2483 if (info->port.tty->hw_stopped) {
2484 if (status & SerialSignal_CTS) {
2485 if ( debug_level >= DEBUG_LEVEL_ISR )
2486 printk("CTS tx start...");
2487 info->port.tty->hw_stopped = 0;
2488 tx_start(info);
2489 info->pending_bh |= BH_TRANSMIT;
2490 return;
2491 }
2492 } else {
2493 if (!(status & SerialSignal_CTS)) {
2494 if ( debug_level >= DEBUG_LEVEL_ISR )
2495 printk("CTS tx stop...");
2496 info->port.tty->hw_stopped = 1;
2497 tx_stop(info);
2498 }
2499 }
2500 }
2501 }
2502 }
2503
2504 info->pending_bh |= BH_STATUS;
2505 }
2506
2507 /* Interrupt service routine entry point.
2508 *
2509 * Arguments:
2510 * irq interrupt number that caused interrupt
2511 * dev_id device ID supplied during interrupt registration
2512 * regs interrupted processor context
2513 */
2514 static irqreturn_t synclinkmp_interrupt(int dummy, void *dev_id)
2515 {
2516 SLMP_INFO *info = dev_id;
2517 unsigned char status, status0, status1=0;
2518 unsigned char dmastatus, dmastatus0, dmastatus1=0;
2519 unsigned char timerstatus0, timerstatus1=0;
2520 unsigned char shift;
2521 unsigned int i;
2522 unsigned short tmp;
2523
2524 if ( debug_level >= DEBUG_LEVEL_ISR )
2525 printk(KERN_DEBUG "%s(%d): synclinkmp_interrupt(%d)entry.\n",
2526 __FILE__, __LINE__, info->irq_level);
2527
2528 spin_lock(&info->lock);
2529
2530 for(;;) {
2531
2532 /* get status for SCA0 (ports 0-1) */
2533 tmp = read_reg16(info, ISR0); /* get ISR0 and ISR1 in one read */
2534 status0 = (unsigned char)tmp;
2535 dmastatus0 = (unsigned char)(tmp>>8);
2536 timerstatus0 = read_reg(info, ISR2);
2537
2538 if ( debug_level >= DEBUG_LEVEL_ISR )
2539 printk(KERN_DEBUG "%s(%d):%s status0=%02x, dmastatus0=%02x, timerstatus0=%02x\n",
2540 __FILE__, __LINE__, info->device_name,
2541 status0, dmastatus0, timerstatus0);
2542
2543 if (info->port_count == 4) {
2544 /* get status for SCA1 (ports 2-3) */
2545 tmp = read_reg16(info->port_array[2], ISR0);
2546 status1 = (unsigned char)tmp;
2547 dmastatus1 = (unsigned char)(tmp>>8);
2548 timerstatus1 = read_reg(info->port_array[2], ISR2);
2549
2550 if ( debug_level >= DEBUG_LEVEL_ISR )
2551 printk("%s(%d):%s status1=%02x, dmastatus1=%02x, timerstatus1=%02x\n",
2552 __FILE__,__LINE__,info->device_name,
2553 status1,dmastatus1,timerstatus1);
2554 }
2555
2556 if (!status0 && !dmastatus0 && !timerstatus0 &&
2557 !status1 && !dmastatus1 && !timerstatus1)
2558 break;
2559
2560 for(i=0; i < info->port_count ; i++) {
2561 if (info->port_array[i] == NULL)
2562 continue;
2563 if (i < 2) {
2564 status = status0;
2565 dmastatus = dmastatus0;
2566 } else {
2567 status = status1;
2568 dmastatus = dmastatus1;
2569 }
2570
2571 shift = i & 1 ? 4 :0;
2572
2573 if (status & BIT0 << shift)
2574 isr_rxrdy(info->port_array[i]);
2575 if (status & BIT1 << shift)
2576 isr_txrdy(info->port_array[i]);
2577 if (status & BIT2 << shift)
2578 isr_rxint(info->port_array[i]);
2579 if (status & BIT3 << shift)
2580 isr_txint(info->port_array[i]);
2581
2582 if (dmastatus & BIT0 << shift)
2583 isr_rxdmaerror(info->port_array[i]);
2584 if (dmastatus & BIT1 << shift)
2585 isr_rxdmaok(info->port_array[i]);
2586 if (dmastatus & BIT2 << shift)
2587 isr_txdmaerror(info->port_array[i]);
2588 if (dmastatus & BIT3 << shift)
2589 isr_txdmaok(info->port_array[i]);
2590 }
2591
2592 if (timerstatus0 & (BIT5 | BIT4))
2593 isr_timer(info->port_array[0]);
2594 if (timerstatus0 & (BIT7 | BIT6))
2595 isr_timer(info->port_array[1]);
2596 if (timerstatus1 & (BIT5 | BIT4))
2597 isr_timer(info->port_array[2]);
2598 if (timerstatus1 & (BIT7 | BIT6))
2599 isr_timer(info->port_array[3]);
2600 }
2601
2602 for(i=0; i < info->port_count ; i++) {
2603 SLMP_INFO * port = info->port_array[i];
2604
2605 /* Request bottom half processing if there's something
2606 * for it to do and the bh is not already running.
2607 *
2608 * Note: startup adapter diags require interrupts.
2609 * do not request bottom half processing if the
2610 * device is not open in a normal mode.
2611 */
2612 if ( port && (port->port.count || port->netcount) &&
2613 port->pending_bh && !port->bh_running &&
2614 !port->bh_requested ) {
2615 if ( debug_level >= DEBUG_LEVEL_ISR )
2616 printk("%s(%d):%s queueing bh task.\n",
2617 __FILE__,__LINE__,port->device_name);
2618 schedule_work(&port->task);
2619 port->bh_requested = true;
2620 }
2621 }
2622
2623 spin_unlock(&info->lock);
2624
2625 if ( debug_level >= DEBUG_LEVEL_ISR )
2626 printk(KERN_DEBUG "%s(%d):synclinkmp_interrupt(%d)exit.\n",
2627 __FILE__, __LINE__, info->irq_level);
2628 return IRQ_HANDLED;
2629 }
2630
2631 /* Initialize and start device.
2632 */
2633 static int startup(SLMP_INFO * info)
2634 {
2635 if ( debug_level >= DEBUG_LEVEL_INFO )
2636 printk("%s(%d):%s tx_releaseup()\n",__FILE__,__LINE__,info->device_name);
2637
2638 if (tty_port_initialized(&info->port))
2639 return 0;
2640
2641 if (!info->tx_buf) {
2642 info->tx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
2643 if (!info->tx_buf) {
2644 printk(KERN_ERR"%s(%d):%s can't allocate transmit buffer\n",
2645 __FILE__,__LINE__,info->device_name);
2646 return -ENOMEM;
2647 }
2648 }
2649
2650 info->pending_bh = 0;
2651
2652 memset(&info->icount, 0, sizeof(info->icount));
2653
2654 /* program hardware for current parameters */
2655 reset_port(info);
2656
2657 change_params(info);
2658
2659 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
2660
2661 if (info->port.tty)
2662 clear_bit(TTY_IO_ERROR, &info->port.tty->flags);
2663
2664 tty_port_set_initialized(&info->port, 1);
2665
2666 return 0;
2667 }
2668
2669 /* Called by close() and hangup() to shutdown hardware
2670 */
2671 static void shutdown(SLMP_INFO * info)
2672 {
2673 unsigned long flags;
2674
2675 if (!tty_port_initialized(&info->port))
2676 return;
2677
2678 if (debug_level >= DEBUG_LEVEL_INFO)
2679 printk("%s(%d):%s synclinkmp_shutdown()\n",
2680 __FILE__,__LINE__, info->device_name );
2681
2682 /* clear status wait queue because status changes */
2683 /* can't happen after shutting down the hardware */
2684 wake_up_interruptible(&info->status_event_wait_q);
2685 wake_up_interruptible(&info->event_wait_q);
2686
2687 del_timer(&info->tx_timer);
2688 del_timer(&info->status_timer);
2689
2690 kfree(info->tx_buf);
2691 info->tx_buf = NULL;
2692
2693 spin_lock_irqsave(&info->lock,flags);
2694
2695 reset_port(info);
2696
2697 if (!info->port.tty || info->port.tty->termios.c_cflag & HUPCL) {
2698 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2699 set_signals(info);
2700 }
2701
2702 spin_unlock_irqrestore(&info->lock,flags);
2703
2704 if (info->port.tty)
2705 set_bit(TTY_IO_ERROR, &info->port.tty->flags);
2706
2707 tty_port_set_initialized(&info->port, 0);
2708 }
2709
2710 static void program_hw(SLMP_INFO *info)
2711 {
2712 unsigned long flags;
2713
2714 spin_lock_irqsave(&info->lock,flags);
2715
2716 rx_stop(info);
2717 tx_stop(info);
2718
2719 info->tx_count = info->tx_put = info->tx_get = 0;
2720
2721 if (info->params.mode == MGSL_MODE_HDLC || info->netcount)
2722 hdlc_mode(info);
2723 else
2724 async_mode(info);
2725
2726 set_signals(info);
2727
2728 info->dcd_chkcount = 0;
2729 info->cts_chkcount = 0;
2730 info->ri_chkcount = 0;
2731 info->dsr_chkcount = 0;
2732
2733 info->ie1_value |= (CDCD|CCTS);
2734 write_reg(info, IE1, info->ie1_value);
2735
2736 get_signals(info);
2737
2738 if (info->netcount || (info->port.tty && info->port.tty->termios.c_cflag & CREAD) )
2739 rx_start(info);
2740
2741 spin_unlock_irqrestore(&info->lock,flags);
2742 }
2743
2744 /* Reconfigure adapter based on new parameters
2745 */
2746 static void change_params(SLMP_INFO *info)
2747 {
2748 unsigned cflag;
2749 int bits_per_char;
2750
2751 if (!info->port.tty)
2752 return;
2753
2754 if (debug_level >= DEBUG_LEVEL_INFO)
2755 printk("%s(%d):%s change_params()\n",
2756 __FILE__,__LINE__, info->device_name );
2757
2758 cflag = info->port.tty->termios.c_cflag;
2759
2760 /* if B0 rate (hangup) specified then negate RTS and DTR */
2761 /* otherwise assert RTS and DTR */
2762 if (cflag & CBAUD)
2763 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
2764 else
2765 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
2766
2767 /* byte size and parity */
2768
2769 switch (cflag & CSIZE) {
2770 case CS5: info->params.data_bits = 5; break;
2771 case CS6: info->params.data_bits = 6; break;
2772 case CS7: info->params.data_bits = 7; break;
2773 case CS8: info->params.data_bits = 8; break;
2774 /* Never happens, but GCC is too dumb to figure it out */
2775 default: info->params.data_bits = 7; break;
2776 }
2777
2778 if (cflag & CSTOPB)
2779 info->params.stop_bits = 2;
2780 else
2781 info->params.stop_bits = 1;
2782
2783 info->params.parity = ASYNC_PARITY_NONE;
2784 if (cflag & PARENB) {
2785 if (cflag & PARODD)
2786 info->params.parity = ASYNC_PARITY_ODD;
2787 else
2788 info->params.parity = ASYNC_PARITY_EVEN;
2789 #ifdef CMSPAR
2790 if (cflag & CMSPAR)
2791 info->params.parity = ASYNC_PARITY_SPACE;
2792 #endif
2793 }
2794
2795 /* calculate number of jiffies to transmit a full
2796 * FIFO (32 bytes) at specified data rate
2797 */
2798 bits_per_char = info->params.data_bits +
2799 info->params.stop_bits + 1;
2800
2801 /* if port data rate is set to 460800 or less then
2802 * allow tty settings to override, otherwise keep the
2803 * current data rate.
2804 */
2805 if (info->params.data_rate <= 460800) {
2806 info->params.data_rate = tty_get_baud_rate(info->port.tty);
2807 }
2808
2809 if ( info->params.data_rate ) {
2810 info->timeout = (32*HZ*bits_per_char) /
2811 info->params.data_rate;
2812 }
2813 info->timeout += HZ/50; /* Add .02 seconds of slop */
2814
2815 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS);
2816 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL);
2817
2818 /* process tty input control flags */
2819
2820 info->read_status_mask2 = OVRN;
2821 if (I_INPCK(info->port.tty))
2822 info->read_status_mask2 |= PE | FRME;
2823 if (I_BRKINT(info->port.tty) || I_PARMRK(info->port.tty))
2824 info->read_status_mask1 |= BRKD;
2825 if (I_IGNPAR(info->port.tty))
2826 info->ignore_status_mask2 |= PE | FRME;
2827 if (I_IGNBRK(info->port.tty)) {
2828 info->ignore_status_mask1 |= BRKD;
2829 /* If ignoring parity and break indicators, ignore
2830 * overruns too. (For real raw support).
2831 */
2832 if (I_IGNPAR(info->port.tty))
2833 info->ignore_status_mask2 |= OVRN;
2834 }
2835
2836 program_hw(info);
2837 }
2838
2839 static int get_stats(SLMP_INFO * info, struct mgsl_icount __user *user_icount)
2840 {
2841 int err;
2842
2843 if (debug_level >= DEBUG_LEVEL_INFO)
2844 printk("%s(%d):%s get_params()\n",
2845 __FILE__,__LINE__, info->device_name);
2846
2847 if (!user_icount) {
2848 memset(&info->icount, 0, sizeof(info->icount));
2849 } else {
2850 mutex_lock(&info->port.mutex);
2851 COPY_TO_USER(err, user_icount, &info->icount, sizeof(struct mgsl_icount));
2852 mutex_unlock(&info->port.mutex);
2853 if (err)
2854 return -EFAULT;
2855 }
2856
2857 return 0;
2858 }
2859
2860 static int get_params(SLMP_INFO * info, MGSL_PARAMS __user *user_params)
2861 {
2862 int err;
2863 if (debug_level >= DEBUG_LEVEL_INFO)
2864 printk("%s(%d):%s get_params()\n",
2865 __FILE__,__LINE__, info->device_name);
2866
2867 mutex_lock(&info->port.mutex);
2868 COPY_TO_USER(err,user_params, &info->params, sizeof(MGSL_PARAMS));
2869 mutex_unlock(&info->port.mutex);
2870 if (err) {
2871 if ( debug_level >= DEBUG_LEVEL_INFO )
2872 printk( "%s(%d):%s get_params() user buffer copy failed\n",
2873 __FILE__,__LINE__,info->device_name);
2874 return -EFAULT;
2875 }
2876
2877 return 0;
2878 }
2879
2880 static int set_params(SLMP_INFO * info, MGSL_PARAMS __user *new_params)
2881 {
2882 unsigned long flags;
2883 MGSL_PARAMS tmp_params;
2884 int err;
2885
2886 if (debug_level >= DEBUG_LEVEL_INFO)
2887 printk("%s(%d):%s set_params\n",
2888 __FILE__,__LINE__,info->device_name );
2889 COPY_FROM_USER(err,&tmp_params, new_params, sizeof(MGSL_PARAMS));
2890 if (err) {
2891 if ( debug_level >= DEBUG_LEVEL_INFO )
2892 printk( "%s(%d):%s set_params() user buffer copy failed\n",
2893 __FILE__,__LINE__,info->device_name);
2894 return -EFAULT;
2895 }
2896
2897 mutex_lock(&info->port.mutex);
2898 spin_lock_irqsave(&info->lock,flags);
2899 memcpy(&info->params,&tmp_params,sizeof(MGSL_PARAMS));
2900 spin_unlock_irqrestore(&info->lock,flags);
2901
2902 change_params(info);
2903 mutex_unlock(&info->port.mutex);
2904
2905 return 0;
2906 }
2907
2908 static int get_txidle(SLMP_INFO * info, int __user *idle_mode)
2909 {
2910 int err;
2911
2912 if (debug_level >= DEBUG_LEVEL_INFO)
2913 printk("%s(%d):%s get_txidle()=%d\n",
2914 __FILE__,__LINE__, info->device_name, info->idle_mode);
2915
2916 COPY_TO_USER(err,idle_mode, &info->idle_mode, sizeof(int));
2917 if (err) {
2918 if ( debug_level >= DEBUG_LEVEL_INFO )
2919 printk( "%s(%d):%s get_txidle() user buffer copy failed\n",
2920 __FILE__,__LINE__,info->device_name);
2921 return -EFAULT;
2922 }
2923
2924 return 0;
2925 }
2926
2927 static int set_txidle(SLMP_INFO * info, int idle_mode)
2928 {
2929 unsigned long flags;
2930
2931 if (debug_level >= DEBUG_LEVEL_INFO)
2932 printk("%s(%d):%s set_txidle(%d)\n",
2933 __FILE__,__LINE__,info->device_name, idle_mode );
2934
2935 spin_lock_irqsave(&info->lock,flags);
2936 info->idle_mode = idle_mode;
2937 tx_set_idle( info );
2938 spin_unlock_irqrestore(&info->lock,flags);
2939 return 0;
2940 }
2941
2942 static int tx_enable(SLMP_INFO * info, int enable)
2943 {
2944 unsigned long flags;
2945
2946 if (debug_level >= DEBUG_LEVEL_INFO)
2947 printk("%s(%d):%s tx_enable(%d)\n",
2948 __FILE__,__LINE__,info->device_name, enable);
2949
2950 spin_lock_irqsave(&info->lock,flags);
2951 if ( enable ) {
2952 if ( !info->tx_enabled ) {
2953 tx_start(info);
2954 }
2955 } else {
2956 if ( info->tx_enabled )
2957 tx_stop(info);
2958 }
2959 spin_unlock_irqrestore(&info->lock,flags);
2960 return 0;
2961 }
2962
2963 /* abort send HDLC frame
2964 */
2965 static int tx_abort(SLMP_INFO * info)
2966 {
2967 unsigned long flags;
2968
2969 if (debug_level >= DEBUG_LEVEL_INFO)
2970 printk("%s(%d):%s tx_abort()\n",
2971 __FILE__,__LINE__,info->device_name);
2972
2973 spin_lock_irqsave(&info->lock,flags);
2974 if ( info->tx_active && info->params.mode == MGSL_MODE_HDLC ) {
2975 info->ie1_value &= ~UDRN;
2976 info->ie1_value |= IDLE;
2977 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
2978 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
2979
2980 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
2981 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
2982
2983 write_reg(info, CMD, TXABORT);
2984 }
2985 spin_unlock_irqrestore(&info->lock,flags);
2986 return 0;
2987 }
2988
2989 static int rx_enable(SLMP_INFO * info, int enable)
2990 {
2991 unsigned long flags;
2992
2993 if (debug_level >= DEBUG_LEVEL_INFO)
2994 printk("%s(%d):%s rx_enable(%d)\n",
2995 __FILE__,__LINE__,info->device_name,enable);
2996
2997 spin_lock_irqsave(&info->lock,flags);
2998 if ( enable ) {
2999 if ( !info->rx_enabled )
3000 rx_start(info);
3001 } else {
3002 if ( info->rx_enabled )
3003 rx_stop(info);
3004 }
3005 spin_unlock_irqrestore(&info->lock,flags);
3006 return 0;
3007 }
3008
3009 /* wait for specified event to occur
3010 */
3011 static int wait_mgsl_event(SLMP_INFO * info, int __user *mask_ptr)
3012 {
3013 unsigned long flags;
3014 int s;
3015 int rc=0;
3016 struct mgsl_icount cprev, cnow;
3017 int events;
3018 int mask;
3019 struct _input_signal_events oldsigs, newsigs;
3020 DECLARE_WAITQUEUE(wait, current);
3021
3022 COPY_FROM_USER(rc,&mask, mask_ptr, sizeof(int));
3023 if (rc) {
3024 return -EFAULT;
3025 }
3026
3027 if (debug_level >= DEBUG_LEVEL_INFO)
3028 printk("%s(%d):%s wait_mgsl_event(%d)\n",
3029 __FILE__,__LINE__,info->device_name,mask);
3030
3031 spin_lock_irqsave(&info->lock,flags);
3032
3033 /* return immediately if state matches requested events */
3034 get_signals(info);
3035 s = info->serial_signals;
3036
3037 events = mask &
3038 ( ((s & SerialSignal_DSR) ? MgslEvent_DsrActive:MgslEvent_DsrInactive) +
3039 ((s & SerialSignal_DCD) ? MgslEvent_DcdActive:MgslEvent_DcdInactive) +
3040 ((s & SerialSignal_CTS) ? MgslEvent_CtsActive:MgslEvent_CtsInactive) +
3041 ((s & SerialSignal_RI) ? MgslEvent_RiActive :MgslEvent_RiInactive) );
3042 if (events) {
3043 spin_unlock_irqrestore(&info->lock,flags);
3044 goto exit;
3045 }
3046
3047 /* save current irq counts */
3048 cprev = info->icount;
3049 oldsigs = info->input_signal_events;
3050
3051 /* enable hunt and idle irqs if needed */
3052 if (mask & (MgslEvent_ExitHuntMode+MgslEvent_IdleReceived)) {
3053 unsigned char oldval = info->ie1_value;
3054 unsigned char newval = oldval +
3055 (mask & MgslEvent_ExitHuntMode ? FLGD:0) +
3056 (mask & MgslEvent_IdleReceived ? IDLD:0);
3057 if ( oldval != newval ) {
3058 info->ie1_value = newval;
3059 write_reg(info, IE1, info->ie1_value);
3060 }
3061 }
3062
3063 set_current_state(TASK_INTERRUPTIBLE);
3064 add_wait_queue(&info->event_wait_q, &wait);
3065
3066 spin_unlock_irqrestore(&info->lock,flags);
3067
3068 for(;;) {
3069 schedule();
3070 if (signal_pending(current)) {
3071 rc = -ERESTARTSYS;
3072 break;
3073 }
3074
3075 /* get current irq counts */
3076 spin_lock_irqsave(&info->lock,flags);
3077 cnow = info->icount;
3078 newsigs = info->input_signal_events;
3079 set_current_state(TASK_INTERRUPTIBLE);
3080 spin_unlock_irqrestore(&info->lock,flags);
3081
3082 /* if no change, wait aborted for some reason */
3083 if (newsigs.dsr_up == oldsigs.dsr_up &&
3084 newsigs.dsr_down == oldsigs.dsr_down &&
3085 newsigs.dcd_up == oldsigs.dcd_up &&
3086 newsigs.dcd_down == oldsigs.dcd_down &&
3087 newsigs.cts_up == oldsigs.cts_up &&
3088 newsigs.cts_down == oldsigs.cts_down &&
3089 newsigs.ri_up == oldsigs.ri_up &&
3090 newsigs.ri_down == oldsigs.ri_down &&
3091 cnow.exithunt == cprev.exithunt &&
3092 cnow.rxidle == cprev.rxidle) {
3093 rc = -EIO;
3094 break;
3095 }
3096
3097 events = mask &
3098 ( (newsigs.dsr_up != oldsigs.dsr_up ? MgslEvent_DsrActive:0) +
3099 (newsigs.dsr_down != oldsigs.dsr_down ? MgslEvent_DsrInactive:0) +
3100 (newsigs.dcd_up != oldsigs.dcd_up ? MgslEvent_DcdActive:0) +
3101 (newsigs.dcd_down != oldsigs.dcd_down ? MgslEvent_DcdInactive:0) +
3102 (newsigs.cts_up != oldsigs.cts_up ? MgslEvent_CtsActive:0) +
3103 (newsigs.cts_down != oldsigs.cts_down ? MgslEvent_CtsInactive:0) +
3104 (newsigs.ri_up != oldsigs.ri_up ? MgslEvent_RiActive:0) +
3105 (newsigs.ri_down != oldsigs.ri_down ? MgslEvent_RiInactive:0) +
3106 (cnow.exithunt != cprev.exithunt ? MgslEvent_ExitHuntMode:0) +
3107 (cnow.rxidle != cprev.rxidle ? MgslEvent_IdleReceived:0) );
3108 if (events)
3109 break;
3110
3111 cprev = cnow;
3112 oldsigs = newsigs;
3113 }
3114
3115 remove_wait_queue(&info->event_wait_q, &wait);
3116 set_current_state(TASK_RUNNING);
3117
3118
3119 if (mask & (MgslEvent_ExitHuntMode + MgslEvent_IdleReceived)) {
3120 spin_lock_irqsave(&info->lock,flags);
3121 if (!waitqueue_active(&info->event_wait_q)) {
3122 /* disable enable exit hunt mode/idle rcvd IRQs */
3123 info->ie1_value &= ~(FLGD|IDLD);
3124 write_reg(info, IE1, info->ie1_value);
3125 }
3126 spin_unlock_irqrestore(&info->lock,flags);
3127 }
3128 exit:
3129 if ( rc == 0 )
3130 PUT_USER(rc, events, mask_ptr);
3131
3132 return rc;
3133 }
3134
3135 static int modem_input_wait(SLMP_INFO *info,int arg)
3136 {
3137 unsigned long flags;
3138 int rc;
3139 struct mgsl_icount cprev, cnow;
3140 DECLARE_WAITQUEUE(wait, current);
3141
3142 /* save current irq counts */
3143 spin_lock_irqsave(&info->lock,flags);
3144 cprev = info->icount;
3145 add_wait_queue(&info->status_event_wait_q, &wait);
3146 set_current_state(TASK_INTERRUPTIBLE);
3147 spin_unlock_irqrestore(&info->lock,flags);
3148
3149 for(;;) {
3150 schedule();
3151 if (signal_pending(current)) {
3152 rc = -ERESTARTSYS;
3153 break;
3154 }
3155
3156 /* get new irq counts */
3157 spin_lock_irqsave(&info->lock,flags);
3158 cnow = info->icount;
3159 set_current_state(TASK_INTERRUPTIBLE);
3160 spin_unlock_irqrestore(&info->lock,flags);
3161
3162 /* if no change, wait aborted for some reason */
3163 if (cnow.rng == cprev.rng && cnow.dsr == cprev.dsr &&
3164 cnow.dcd == cprev.dcd && cnow.cts == cprev.cts) {
3165 rc = -EIO;
3166 break;
3167 }
3168
3169 /* check for change in caller specified modem input */
3170 if ((arg & TIOCM_RNG && cnow.rng != cprev.rng) ||
3171 (arg & TIOCM_DSR && cnow.dsr != cprev.dsr) ||
3172 (arg & TIOCM_CD && cnow.dcd != cprev.dcd) ||
3173 (arg & TIOCM_CTS && cnow.cts != cprev.cts)) {
3174 rc = 0;
3175 break;
3176 }
3177
3178 cprev = cnow;
3179 }
3180 remove_wait_queue(&info->status_event_wait_q, &wait);
3181 set_current_state(TASK_RUNNING);
3182 return rc;
3183 }
3184
3185 /* return the state of the serial control and status signals
3186 */
3187 static int tiocmget(struct tty_struct *tty)
3188 {
3189 SLMP_INFO *info = tty->driver_data;
3190 unsigned int result;
3191 unsigned long flags;
3192
3193 spin_lock_irqsave(&info->lock,flags);
3194 get_signals(info);
3195 spin_unlock_irqrestore(&info->lock,flags);
3196
3197 result = ((info->serial_signals & SerialSignal_RTS) ? TIOCM_RTS : 0) |
3198 ((info->serial_signals & SerialSignal_DTR) ? TIOCM_DTR : 0) |
3199 ((info->serial_signals & SerialSignal_DCD) ? TIOCM_CAR : 0) |
3200 ((info->serial_signals & SerialSignal_RI) ? TIOCM_RNG : 0) |
3201 ((info->serial_signals & SerialSignal_DSR) ? TIOCM_DSR : 0) |
3202 ((info->serial_signals & SerialSignal_CTS) ? TIOCM_CTS : 0);
3203
3204 if (debug_level >= DEBUG_LEVEL_INFO)
3205 printk("%s(%d):%s tiocmget() value=%08X\n",
3206 __FILE__,__LINE__, info->device_name, result );
3207 return result;
3208 }
3209
3210 /* set modem control signals (DTR/RTS)
3211 */
3212 static int tiocmset(struct tty_struct *tty,
3213 unsigned int set, unsigned int clear)
3214 {
3215 SLMP_INFO *info = tty->driver_data;
3216 unsigned long flags;
3217
3218 if (debug_level >= DEBUG_LEVEL_INFO)
3219 printk("%s(%d):%s tiocmset(%x,%x)\n",
3220 __FILE__,__LINE__,info->device_name, set, clear);
3221
3222 if (set & TIOCM_RTS)
3223 info->serial_signals |= SerialSignal_RTS;
3224 if (set & TIOCM_DTR)
3225 info->serial_signals |= SerialSignal_DTR;
3226 if (clear & TIOCM_RTS)
3227 info->serial_signals &= ~SerialSignal_RTS;
3228 if (clear & TIOCM_DTR)
3229 info->serial_signals &= ~SerialSignal_DTR;
3230
3231 spin_lock_irqsave(&info->lock,flags);
3232 set_signals(info);
3233 spin_unlock_irqrestore(&info->lock,flags);
3234
3235 return 0;
3236 }
3237
3238 static int carrier_raised(struct tty_port *port)
3239 {
3240 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3241 unsigned long flags;
3242
3243 spin_lock_irqsave(&info->lock,flags);
3244 get_signals(info);
3245 spin_unlock_irqrestore(&info->lock,flags);
3246
3247 return (info->serial_signals & SerialSignal_DCD) ? 1 : 0;
3248 }
3249
3250 static void dtr_rts(struct tty_port *port, int on)
3251 {
3252 SLMP_INFO *info = container_of(port, SLMP_INFO, port);
3253 unsigned long flags;
3254
3255 spin_lock_irqsave(&info->lock,flags);
3256 if (on)
3257 info->serial_signals |= SerialSignal_RTS | SerialSignal_DTR;
3258 else
3259 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
3260 set_signals(info);
3261 spin_unlock_irqrestore(&info->lock,flags);
3262 }
3263
3264 /* Block the current process until the specified port is ready to open.
3265 */
3266 static int block_til_ready(struct tty_struct *tty, struct file *filp,
3267 SLMP_INFO *info)
3268 {
3269 DECLARE_WAITQUEUE(wait, current);
3270 int retval;
3271 bool do_clocal = false;
3272 unsigned long flags;
3273 int cd;
3274 struct tty_port *port = &info->port;
3275
3276 if (debug_level >= DEBUG_LEVEL_INFO)
3277 printk("%s(%d):%s block_til_ready()\n",
3278 __FILE__,__LINE__, tty->driver->name );
3279
3280 if (filp->f_flags & O_NONBLOCK || tty_io_error(tty)) {
3281 /* nonblock mode is set or port is not enabled */
3282 /* just verify that callout device is not active */
3283 tty_port_set_active(port, 1);
3284 return 0;
3285 }
3286
3287 if (C_CLOCAL(tty))
3288 do_clocal = true;
3289
3290 /* Wait for carrier detect and the line to become
3291 * free (i.e., not in use by the callout). While we are in
3292 * this loop, port->count is dropped by one, so that
3293 * close() knows when to free things. We restore it upon
3294 * exit, either normal or abnormal.
3295 */
3296
3297 retval = 0;
3298 add_wait_queue(&port->open_wait, &wait);
3299
3300 if (debug_level >= DEBUG_LEVEL_INFO)
3301 printk("%s(%d):%s block_til_ready() before block, count=%d\n",
3302 __FILE__,__LINE__, tty->driver->name, port->count );
3303
3304 spin_lock_irqsave(&info->lock, flags);
3305 port->count--;
3306 spin_unlock_irqrestore(&info->lock, flags);
3307 port->blocked_open++;
3308
3309 while (1) {
3310 if (C_BAUD(tty) && tty_port_initialized(port))
3311 tty_port_raise_dtr_rts(port);
3312
3313 set_current_state(TASK_INTERRUPTIBLE);
3314
3315 if (tty_hung_up_p(filp) || !tty_port_initialized(port)) {
3316 retval = (port->flags & ASYNC_HUP_NOTIFY) ?
3317 -EAGAIN : -ERESTARTSYS;
3318 break;
3319 }
3320
3321 cd = tty_port_carrier_raised(port);
3322 if (do_clocal || cd)
3323 break;
3324
3325 if (signal_pending(current)) {
3326 retval = -ERESTARTSYS;
3327 break;
3328 }
3329
3330 if (debug_level >= DEBUG_LEVEL_INFO)
3331 printk("%s(%d):%s block_til_ready() count=%d\n",
3332 __FILE__,__LINE__, tty->driver->name, port->count );
3333
3334 tty_unlock(tty);
3335 schedule();
3336 tty_lock(tty);
3337 }
3338
3339 set_current_state(TASK_RUNNING);
3340 remove_wait_queue(&port->open_wait, &wait);
3341 if (!tty_hung_up_p(filp))
3342 port->count++;
3343 port->blocked_open--;
3344
3345 if (debug_level >= DEBUG_LEVEL_INFO)
3346 printk("%s(%d):%s block_til_ready() after, count=%d\n",
3347 __FILE__,__LINE__, tty->driver->name, port->count );
3348
3349 if (!retval)
3350 tty_port_set_active(port, 1);
3351
3352 return retval;
3353 }
3354
3355 static int alloc_dma_bufs(SLMP_INFO *info)
3356 {
3357 unsigned short BuffersPerFrame;
3358 unsigned short BufferCount;
3359
3360 // Force allocation to start at 64K boundary for each port.
3361 // This is necessary because *all* buffer descriptors for a port
3362 // *must* be in the same 64K block. All descriptors on a port
3363 // share a common 'base' address (upper 8 bits of 24 bits) programmed
3364 // into the CBP register.
3365 info->port_array[0]->last_mem_alloc = (SCA_MEM_SIZE/4) * info->port_num;
3366
3367 /* Calculate the number of DMA buffers necessary to hold the */
3368 /* largest allowable frame size. Note: If the max frame size is */
3369 /* not an even multiple of the DMA buffer size then we need to */
3370 /* round the buffer count per frame up one. */
3371
3372 BuffersPerFrame = (unsigned short)(info->max_frame_size/SCABUFSIZE);
3373 if ( info->max_frame_size % SCABUFSIZE )
3374 BuffersPerFrame++;
3375
3376 /* calculate total number of data buffers (SCABUFSIZE) possible
3377 * in one ports memory (SCA_MEM_SIZE/4) after allocating memory
3378 * for the descriptor list (BUFFERLISTSIZE).
3379 */
3380 BufferCount = (SCA_MEM_SIZE/4 - BUFFERLISTSIZE)/SCABUFSIZE;
3381
3382 /* limit number of buffers to maximum amount of descriptors */
3383 if (BufferCount > BUFFERLISTSIZE/sizeof(SCADESC))
3384 BufferCount = BUFFERLISTSIZE/sizeof(SCADESC);
3385
3386 /* use enough buffers to transmit one max size frame */
3387 info->tx_buf_count = BuffersPerFrame + 1;
3388
3389 /* never use more than half the available buffers for transmit */
3390 if (info->tx_buf_count > (BufferCount/2))
3391 info->tx_buf_count = BufferCount/2;
3392
3393 if (info->tx_buf_count > SCAMAXDESC)
3394 info->tx_buf_count = SCAMAXDESC;
3395
3396 /* use remaining buffers for receive */
3397 info->rx_buf_count = BufferCount - info->tx_buf_count;
3398
3399 if (info->rx_buf_count > SCAMAXDESC)
3400 info->rx_buf_count = SCAMAXDESC;
3401
3402 if ( debug_level >= DEBUG_LEVEL_INFO )
3403 printk("%s(%d):%s Allocating %d TX and %d RX DMA buffers.\n",
3404 __FILE__,__LINE__, info->device_name,
3405 info->tx_buf_count,info->rx_buf_count);
3406
3407 if ( alloc_buf_list( info ) < 0 ||
3408 alloc_frame_bufs(info,
3409 info->rx_buf_list,
3410 info->rx_buf_list_ex,
3411 info->rx_buf_count) < 0 ||
3412 alloc_frame_bufs(info,
3413 info->tx_buf_list,
3414 info->tx_buf_list_ex,
3415 info->tx_buf_count) < 0 ||
3416 alloc_tmp_rx_buf(info) < 0 ) {
3417 printk("%s(%d):%s Can't allocate DMA buffer memory\n",
3418 __FILE__,__LINE__, info->device_name);
3419 return -ENOMEM;
3420 }
3421
3422 rx_reset_buffers( info );
3423
3424 return 0;
3425 }
3426
3427 /* Allocate DMA buffers for the transmit and receive descriptor lists.
3428 */
3429 static int alloc_buf_list(SLMP_INFO *info)
3430 {
3431 unsigned int i;
3432
3433 /* build list in adapter shared memory */
3434 info->buffer_list = info->memory_base + info->port_array[0]->last_mem_alloc;
3435 info->buffer_list_phys = info->port_array[0]->last_mem_alloc;
3436 info->port_array[0]->last_mem_alloc += BUFFERLISTSIZE;
3437
3438 memset(info->buffer_list, 0, BUFFERLISTSIZE);
3439
3440 /* Save virtual address pointers to the receive and */
3441 /* transmit buffer lists. (Receive 1st). These pointers will */
3442 /* be used by the processor to access the lists. */
3443 info->rx_buf_list = (SCADESC *)info->buffer_list;
3444
3445 info->tx_buf_list = (SCADESC *)info->buffer_list;
3446 info->tx_buf_list += info->rx_buf_count;
3447
3448 /* Build links for circular buffer entry lists (tx and rx)
3449 *
3450 * Note: links are physical addresses read by the SCA device
3451 * to determine the next buffer entry to use.
3452 */
3453
3454 for ( i = 0; i < info->rx_buf_count; i++ ) {
3455 /* calculate and store physical address of this buffer entry */
3456 info->rx_buf_list_ex[i].phys_entry =
3457 info->buffer_list_phys + (i * SCABUFSIZE);
3458
3459 /* calculate and store physical address of */
3460 /* next entry in cirular list of entries */
3461 info->rx_buf_list[i].next = info->buffer_list_phys;
3462 if ( i < info->rx_buf_count - 1 )
3463 info->rx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3464
3465 info->rx_buf_list[i].length = SCABUFSIZE;
3466 }
3467
3468 for ( i = 0; i < info->tx_buf_count; i++ ) {
3469 /* calculate and store physical address of this buffer entry */
3470 info->tx_buf_list_ex[i].phys_entry = info->buffer_list_phys +
3471 ((info->rx_buf_count + i) * sizeof(SCADESC));
3472
3473 /* calculate and store physical address of */
3474 /* next entry in cirular list of entries */
3475
3476 info->tx_buf_list[i].next = info->buffer_list_phys +
3477 info->rx_buf_count * sizeof(SCADESC);
3478
3479 if ( i < info->tx_buf_count - 1 )
3480 info->tx_buf_list[i].next += (i + 1) * sizeof(SCADESC);
3481 }
3482
3483 return 0;
3484 }
3485
3486 /* Allocate the frame DMA buffers used by the specified buffer list.
3487 */
3488 static int alloc_frame_bufs(SLMP_INFO *info, SCADESC *buf_list,SCADESC_EX *buf_list_ex,int count)
3489 {
3490 int i;
3491 unsigned long phys_addr;
3492
3493 for ( i = 0; i < count; i++ ) {
3494 buf_list_ex[i].virt_addr = info->memory_base + info->port_array[0]->last_mem_alloc;
3495 phys_addr = info->port_array[0]->last_mem_alloc;
3496 info->port_array[0]->last_mem_alloc += SCABUFSIZE;
3497
3498 buf_list[i].buf_ptr = (unsigned short)phys_addr;
3499 buf_list[i].buf_base = (unsigned char)(phys_addr >> 16);
3500 }
3501
3502 return 0;
3503 }
3504
3505 static void free_dma_bufs(SLMP_INFO *info)
3506 {
3507 info->buffer_list = NULL;
3508 info->rx_buf_list = NULL;
3509 info->tx_buf_list = NULL;
3510 }
3511
3512 /* allocate buffer large enough to hold max_frame_size.
3513 * This buffer is used to pass an assembled frame to the line discipline.
3514 */
3515 static int alloc_tmp_rx_buf(SLMP_INFO *info)
3516 {
3517 info->tmp_rx_buf = kmalloc(info->max_frame_size, GFP_KERNEL);
3518 if (info->tmp_rx_buf == NULL)
3519 return -ENOMEM;
3520 /* unused flag buffer to satisfy receive_buf calling interface */
3521 info->flag_buf = kzalloc(info->max_frame_size, GFP_KERNEL);
3522 if (!info->flag_buf) {
3523 kfree(info->tmp_rx_buf);
3524 info->tmp_rx_buf = NULL;
3525 return -ENOMEM;
3526 }
3527 return 0;
3528 }
3529
3530 static void free_tmp_rx_buf(SLMP_INFO *info)
3531 {
3532 kfree(info->tmp_rx_buf);
3533 info->tmp_rx_buf = NULL;
3534 kfree(info->flag_buf);
3535 info->flag_buf = NULL;
3536 }
3537
3538 static int claim_resources(SLMP_INFO *info)
3539 {
3540 if (request_mem_region(info->phys_memory_base,SCA_MEM_SIZE,"synclinkmp") == NULL) {
3541 printk( "%s(%d):%s mem addr conflict, Addr=%08X\n",
3542 __FILE__,__LINE__,info->device_name, info->phys_memory_base);
3543 info->init_error = DiagStatus_AddressConflict;
3544 goto errout;
3545 }
3546 else
3547 info->shared_mem_requested = true;
3548
3549 if (request_mem_region(info->phys_lcr_base + info->lcr_offset,128,"synclinkmp") == NULL) {
3550 printk( "%s(%d):%s lcr mem addr conflict, Addr=%08X\n",
3551 __FILE__,__LINE__,info->device_name, info->phys_lcr_base);
3552 info->init_error = DiagStatus_AddressConflict;
3553 goto errout;
3554 }
3555 else
3556 info->lcr_mem_requested = true;
3557
3558 if (request_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE,"synclinkmp") == NULL) {
3559 printk( "%s(%d):%s sca mem addr conflict, Addr=%08X\n",
3560 __FILE__,__LINE__,info->device_name, info->phys_sca_base);
3561 info->init_error = DiagStatus_AddressConflict;
3562 goto errout;
3563 }
3564 else
3565 info->sca_base_requested = true;
3566
3567 if (request_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE,"synclinkmp") == NULL) {
3568 printk( "%s(%d):%s stat/ctrl mem addr conflict, Addr=%08X\n",
3569 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base);
3570 info->init_error = DiagStatus_AddressConflict;
3571 goto errout;
3572 }
3573 else
3574 info->sca_statctrl_requested = true;
3575
3576 info->memory_base = ioremap_nocache(info->phys_memory_base,
3577 SCA_MEM_SIZE);
3578 if (!info->memory_base) {
3579 printk( "%s(%d):%s Can't map shared memory, MemAddr=%08X\n",
3580 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3581 info->init_error = DiagStatus_CantAssignPciResources;
3582 goto errout;
3583 }
3584
3585 info->lcr_base = ioremap_nocache(info->phys_lcr_base, PAGE_SIZE);
3586 if (!info->lcr_base) {
3587 printk( "%s(%d):%s Can't map LCR memory, MemAddr=%08X\n",
3588 __FILE__,__LINE__,info->device_name, info->phys_lcr_base );
3589 info->init_error = DiagStatus_CantAssignPciResources;
3590 goto errout;
3591 }
3592 info->lcr_base += info->lcr_offset;
3593
3594 info->sca_base = ioremap_nocache(info->phys_sca_base, PAGE_SIZE);
3595 if (!info->sca_base) {
3596 printk( "%s(%d):%s Can't map SCA memory, MemAddr=%08X\n",
3597 __FILE__,__LINE__,info->device_name, info->phys_sca_base );
3598 info->init_error = DiagStatus_CantAssignPciResources;
3599 goto errout;
3600 }
3601 info->sca_base += info->sca_offset;
3602
3603 info->statctrl_base = ioremap_nocache(info->phys_statctrl_base,
3604 PAGE_SIZE);
3605 if (!info->statctrl_base) {
3606 printk( "%s(%d):%s Can't map SCA Status/Control memory, MemAddr=%08X\n",
3607 __FILE__,__LINE__,info->device_name, info->phys_statctrl_base );
3608 info->init_error = DiagStatus_CantAssignPciResources;
3609 goto errout;
3610 }
3611 info->statctrl_base += info->statctrl_offset;
3612
3613 if ( !memory_test(info) ) {
3614 printk( "%s(%d):Shared Memory Test failed for device %s MemAddr=%08X\n",
3615 __FILE__,__LINE__,info->device_name, info->phys_memory_base );
3616 info->init_error = DiagStatus_MemoryError;
3617 goto errout;
3618 }
3619
3620 return 0;
3621
3622 errout:
3623 release_resources( info );
3624 return -ENODEV;
3625 }
3626
3627 static void release_resources(SLMP_INFO *info)
3628 {
3629 if ( debug_level >= DEBUG_LEVEL_INFO )
3630 printk( "%s(%d):%s release_resources() entry\n",
3631 __FILE__,__LINE__,info->device_name );
3632
3633 if ( info->irq_requested ) {
3634 free_irq(info->irq_level, info);
3635 info->irq_requested = false;
3636 }
3637
3638 if ( info->shared_mem_requested ) {
3639 release_mem_region(info->phys_memory_base,SCA_MEM_SIZE);
3640 info->shared_mem_requested = false;
3641 }
3642 if ( info->lcr_mem_requested ) {
3643 release_mem_region(info->phys_lcr_base + info->lcr_offset,128);
3644 info->lcr_mem_requested = false;
3645 }
3646 if ( info->sca_base_requested ) {
3647 release_mem_region(info->phys_sca_base + info->sca_offset,SCA_BASE_SIZE);
3648 info->sca_base_requested = false;
3649 }
3650 if ( info->sca_statctrl_requested ) {
3651 release_mem_region(info->phys_statctrl_base + info->statctrl_offset,SCA_REG_SIZE);
3652 info->sca_statctrl_requested = false;
3653 }
3654
3655 if (info->memory_base){
3656 iounmap(info->memory_base);
3657 info->memory_base = NULL;
3658 }
3659
3660 if (info->sca_base) {
3661 iounmap(info->sca_base - info->sca_offset);
3662 info->sca_base=NULL;
3663 }
3664
3665 if (info->statctrl_base) {
3666 iounmap(info->statctrl_base - info->statctrl_offset);
3667 info->statctrl_base=NULL;
3668 }
3669
3670 if (info->lcr_base){
3671 iounmap(info->lcr_base - info->lcr_offset);
3672 info->lcr_base = NULL;
3673 }
3674
3675 if ( debug_level >= DEBUG_LEVEL_INFO )
3676 printk( "%s(%d):%s release_resources() exit\n",
3677 __FILE__,__LINE__,info->device_name );
3678 }
3679
3680 /* Add the specified device instance data structure to the
3681 * global linked list of devices and increment the device count.
3682 */
3683 static int add_device(SLMP_INFO *info)
3684 {
3685 info->next_device = NULL;
3686 info->line = synclinkmp_device_count;
3687 sprintf(info->device_name,"ttySLM%dp%d",info->adapter_num,info->port_num);
3688
3689 if (info->line < MAX_DEVICES) {
3690 if (maxframe[info->line])
3691 info->max_frame_size = maxframe[info->line];
3692 }
3693
3694 synclinkmp_device_count++;
3695
3696 if ( !synclinkmp_device_list )
3697 synclinkmp_device_list = info;
3698 else {
3699 SLMP_INFO *current_dev = synclinkmp_device_list;
3700 while( current_dev->next_device )
3701 current_dev = current_dev->next_device;
3702 current_dev->next_device = info;
3703 }
3704
3705 if ( info->max_frame_size < 4096 )
3706 info->max_frame_size = 4096;
3707 else if ( info->max_frame_size > 65535 )
3708 info->max_frame_size = 65535;
3709
3710 printk( "SyncLink MultiPort %s: "
3711 "Mem=(%08x %08X %08x %08X) IRQ=%d MaxFrameSize=%u\n",
3712 info->device_name,
3713 info->phys_sca_base,
3714 info->phys_memory_base,
3715 info->phys_statctrl_base,
3716 info->phys_lcr_base,
3717 info->irq_level,
3718 info->max_frame_size );
3719
3720 #if SYNCLINK_GENERIC_HDLC
3721 return hdlcdev_init(info);
3722 #else
3723 return 0;
3724 #endif
3725 }
3726
3727 static const struct tty_port_operations port_ops = {
3728 .carrier_raised = carrier_raised,
3729 .dtr_rts = dtr_rts,
3730 };
3731
3732 /* Allocate and initialize a device instance structure
3733 *
3734 * Return Value: pointer to SLMP_INFO if success, otherwise NULL
3735 */
3736 static SLMP_INFO *alloc_dev(int adapter_num, int port_num, struct pci_dev *pdev)
3737 {
3738 SLMP_INFO *info;
3739
3740 info = kzalloc(sizeof(SLMP_INFO),
3741 GFP_KERNEL);
3742
3743 if (!info) {
3744 printk("%s(%d) Error can't allocate device instance data for adapter %d, port %d\n",
3745 __FILE__,__LINE__, adapter_num, port_num);
3746 } else {
3747 tty_port_init(&info->port);
3748 info->port.ops = &port_ops;
3749 info->magic = MGSL_MAGIC;
3750 INIT_WORK(&info->task, bh_handler);
3751 info->max_frame_size = 4096;
3752 info->port.close_delay = 5*HZ/10;
3753 info->port.closing_wait = 30*HZ;
3754 init_waitqueue_head(&info->status_event_wait_q);
3755 init_waitqueue_head(&info->event_wait_q);
3756 spin_lock_init(&info->netlock);
3757 memcpy(&info->params,&default_params,sizeof(MGSL_PARAMS));
3758 info->idle_mode = HDLC_TXIDLE_FLAGS;
3759 info->adapter_num = adapter_num;
3760 info->port_num = port_num;
3761
3762 /* Copy configuration info to device instance data */
3763 info->irq_level = pdev->irq;
3764 info->phys_lcr_base = pci_resource_start(pdev,0);
3765 info->phys_sca_base = pci_resource_start(pdev,2);
3766 info->phys_memory_base = pci_resource_start(pdev,3);
3767 info->phys_statctrl_base = pci_resource_start(pdev,4);
3768
3769 /* Because veremap only works on page boundaries we must map
3770 * a larger area than is actually implemented for the LCR
3771 * memory range. We map a full page starting at the page boundary.
3772 */
3773 info->lcr_offset = info->phys_lcr_base & (PAGE_SIZE-1);
3774 info->phys_lcr_base &= ~(PAGE_SIZE-1);
3775
3776 info->sca_offset = info->phys_sca_base & (PAGE_SIZE-1);
3777 info->phys_sca_base &= ~(PAGE_SIZE-1);
3778
3779 info->statctrl_offset = info->phys_statctrl_base & (PAGE_SIZE-1);
3780 info->phys_statctrl_base &= ~(PAGE_SIZE-1);
3781
3782 info->bus_type = MGSL_BUS_TYPE_PCI;
3783 info->irq_flags = IRQF_SHARED;
3784
3785 setup_timer(&info->tx_timer, tx_timeout, (unsigned long)info);
3786 setup_timer(&info->status_timer, status_timeout,
3787 (unsigned long)info);
3788
3789 /* Store the PCI9050 misc control register value because a flaw
3790 * in the PCI9050 prevents LCR registers from being read if
3791 * BIOS assigns an LCR base address with bit 7 set.
3792 *
3793 * Only the misc control register is accessed for which only
3794 * write access is needed, so set an initial value and change
3795 * bits to the device instance data as we write the value
3796 * to the actual misc control register.
3797 */
3798 info->misc_ctrl_value = 0x087e4546;
3799
3800 /* initial port state is unknown - if startup errors
3801 * occur, init_error will be set to indicate the
3802 * problem. Once the port is fully initialized,
3803 * this value will be set to 0 to indicate the
3804 * port is available.
3805 */
3806 info->init_error = -1;
3807 }
3808
3809 return info;
3810 }
3811
3812 static int device_init(int adapter_num, struct pci_dev *pdev)
3813 {
3814 SLMP_INFO *port_array[SCA_MAX_PORTS];
3815 int port, rc;
3816
3817 /* allocate device instances for up to SCA_MAX_PORTS devices */
3818 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3819 port_array[port] = alloc_dev(adapter_num,port,pdev);
3820 if( port_array[port] == NULL ) {
3821 for (--port; port >= 0; --port) {
3822 tty_port_destroy(&port_array[port]->port);
3823 kfree(port_array[port]);
3824 }
3825 return -ENOMEM;
3826 }
3827 }
3828
3829 /* give copy of port_array to all ports and add to device list */
3830 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3831 memcpy(port_array[port]->port_array,port_array,sizeof(port_array));
3832 rc = add_device( port_array[port] );
3833 if (rc)
3834 goto err_add;
3835 spin_lock_init(&port_array[port]->lock);
3836 }
3837
3838 /* Allocate and claim adapter resources */
3839 if ( !claim_resources(port_array[0]) ) {
3840
3841 alloc_dma_bufs(port_array[0]);
3842
3843 /* copy resource information from first port to others */
3844 for ( port = 1; port < SCA_MAX_PORTS; ++port ) {
3845 port_array[port]->lock = port_array[0]->lock;
3846 port_array[port]->irq_level = port_array[0]->irq_level;
3847 port_array[port]->memory_base = port_array[0]->memory_base;
3848 port_array[port]->sca_base = port_array[0]->sca_base;
3849 port_array[port]->statctrl_base = port_array[0]->statctrl_base;
3850 port_array[port]->lcr_base = port_array[0]->lcr_base;
3851 alloc_dma_bufs(port_array[port]);
3852 }
3853
3854 rc = request_irq(port_array[0]->irq_level,
3855 synclinkmp_interrupt,
3856 port_array[0]->irq_flags,
3857 port_array[0]->device_name,
3858 port_array[0]);
3859 if ( rc ) {
3860 printk( "%s(%d):%s Can't request interrupt, IRQ=%d\n",
3861 __FILE__,__LINE__,
3862 port_array[0]->device_name,
3863 port_array[0]->irq_level );
3864 goto err_irq;
3865 }
3866 port_array[0]->irq_requested = true;
3867 adapter_test(port_array[0]);
3868 }
3869 return 0;
3870 err_irq:
3871 release_resources( port_array[0] );
3872 err_add:
3873 for ( port = 0; port < SCA_MAX_PORTS; ++port ) {
3874 tty_port_destroy(&port_array[port]->port);
3875 kfree(port_array[port]);
3876 }
3877 return rc;
3878 }
3879
3880 static const struct tty_operations ops = {
3881 .install = install,
3882 .open = open,
3883 .close = close,
3884 .write = write,
3885 .put_char = put_char,
3886 .flush_chars = flush_chars,
3887 .write_room = write_room,
3888 .chars_in_buffer = chars_in_buffer,
3889 .flush_buffer = flush_buffer,
3890 .ioctl = ioctl,
3891 .throttle = throttle,
3892 .unthrottle = unthrottle,
3893 .send_xchar = send_xchar,
3894 .break_ctl = set_break,
3895 .wait_until_sent = wait_until_sent,
3896 .set_termios = set_termios,
3897 .stop = tx_hold,
3898 .start = tx_release,
3899 .hangup = hangup,
3900 .tiocmget = tiocmget,
3901 .tiocmset = tiocmset,
3902 .get_icount = get_icount,
3903 .proc_fops = &synclinkmp_proc_fops,
3904 };
3905
3906
3907 static void synclinkmp_cleanup(void)
3908 {
3909 int rc;
3910 SLMP_INFO *info;
3911 SLMP_INFO *tmp;
3912
3913 printk("Unloading %s %s\n", driver_name, driver_version);
3914
3915 if (serial_driver) {
3916 rc = tty_unregister_driver(serial_driver);
3917 if (rc)
3918 printk("%s(%d) failed to unregister tty driver err=%d\n",
3919 __FILE__,__LINE__,rc);
3920 put_tty_driver(serial_driver);
3921 }
3922
3923 /* reset devices */
3924 info = synclinkmp_device_list;
3925 while(info) {
3926 reset_port(info);
3927 info = info->next_device;
3928 }
3929
3930 /* release devices */
3931 info = synclinkmp_device_list;
3932 while(info) {
3933 #if SYNCLINK_GENERIC_HDLC
3934 hdlcdev_exit(info);
3935 #endif
3936 free_dma_bufs(info);
3937 free_tmp_rx_buf(info);
3938 if ( info->port_num == 0 ) {
3939 if (info->sca_base)
3940 write_reg(info, LPR, 1); /* set low power mode */
3941 release_resources(info);
3942 }
3943 tmp = info;
3944 info = info->next_device;
3945 tty_port_destroy(&tmp->port);
3946 kfree(tmp);
3947 }
3948
3949 pci_unregister_driver(&synclinkmp_pci_driver);
3950 }
3951
3952 /* Driver initialization entry point.
3953 */
3954
3955 static int __init synclinkmp_init(void)
3956 {
3957 int rc;
3958
3959 if (break_on_load) {
3960 synclinkmp_get_text_ptr();
3961 BREAKPOINT();
3962 }
3963
3964 printk("%s %s\n", driver_name, driver_version);
3965
3966 if ((rc = pci_register_driver(&synclinkmp_pci_driver)) < 0) {
3967 printk("%s:failed to register PCI driver, error=%d\n",__FILE__,rc);
3968 return rc;
3969 }
3970
3971 serial_driver = alloc_tty_driver(128);
3972 if (!serial_driver) {
3973 rc = -ENOMEM;
3974 goto error;
3975 }
3976
3977 /* Initialize the tty_driver structure */
3978
3979 serial_driver->driver_name = "synclinkmp";
3980 serial_driver->name = "ttySLM";
3981 serial_driver->major = ttymajor;
3982 serial_driver->minor_start = 64;
3983 serial_driver->type = TTY_DRIVER_TYPE_SERIAL;
3984 serial_driver->subtype = SERIAL_TYPE_NORMAL;
3985 serial_driver->init_termios = tty_std_termios;
3986 serial_driver->init_termios.c_cflag =
3987 B9600 | CS8 | CREAD | HUPCL | CLOCAL;
3988 serial_driver->init_termios.c_ispeed = 9600;
3989 serial_driver->init_termios.c_ospeed = 9600;
3990 serial_driver->flags = TTY_DRIVER_REAL_RAW;
3991 tty_set_operations(serial_driver, &ops);
3992 if ((rc = tty_register_driver(serial_driver)) < 0) {
3993 printk("%s(%d):Couldn't register serial driver\n",
3994 __FILE__,__LINE__);
3995 put_tty_driver(serial_driver);
3996 serial_driver = NULL;
3997 goto error;
3998 }
3999
4000 printk("%s %s, tty major#%d\n",
4001 driver_name, driver_version,
4002 serial_driver->major);
4003
4004 return 0;
4005
4006 error:
4007 synclinkmp_cleanup();
4008 return rc;
4009 }
4010
4011 static void __exit synclinkmp_exit(void)
4012 {
4013 synclinkmp_cleanup();
4014 }
4015
4016 module_init(synclinkmp_init);
4017 module_exit(synclinkmp_exit);
4018
4019 /* Set the port for internal loopback mode.
4020 * The TxCLK and RxCLK signals are generated from the BRG and
4021 * the TxD is looped back to the RxD internally.
4022 */
4023 static void enable_loopback(SLMP_INFO *info, int enable)
4024 {
4025 if (enable) {
4026 /* MD2 (Mode Register 2)
4027 * 01..00 CNCT<1..0> Channel Connection 11=Local Loopback
4028 */
4029 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) | (BIT1 + BIT0)));
4030
4031 /* degate external TxC clock source */
4032 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4033 write_control_reg(info);
4034
4035 /* RXS/TXS (Rx/Tx clock source)
4036 * 07 Reserved, must be 0
4037 * 06..04 Clock Source, 100=BRG
4038 * 03..00 Clock Divisor, 0000=1
4039 */
4040 write_reg(info, RXS, 0x40);
4041 write_reg(info, TXS, 0x40);
4042
4043 } else {
4044 /* MD2 (Mode Register 2)
4045 * 01..00 CNCT<1..0> Channel connection, 0=normal
4046 */
4047 write_reg(info, MD2, (unsigned char)(read_reg(info, MD2) & ~(BIT1 + BIT0)));
4048
4049 /* RXS/TXS (Rx/Tx clock source)
4050 * 07 Reserved, must be 0
4051 * 06..04 Clock Source, 000=RxC/TxC Pin
4052 * 03..00 Clock Divisor, 0000=1
4053 */
4054 write_reg(info, RXS, 0x00);
4055 write_reg(info, TXS, 0x00);
4056 }
4057
4058 /* set LinkSpeed if available, otherwise default to 2Mbps */
4059 if (info->params.clock_speed)
4060 set_rate(info, info->params.clock_speed);
4061 else
4062 set_rate(info, 3686400);
4063 }
4064
4065 /* Set the baud rate register to the desired speed
4066 *
4067 * data_rate data rate of clock in bits per second
4068 * A data rate of 0 disables the AUX clock.
4069 */
4070 static void set_rate( SLMP_INFO *info, u32 data_rate )
4071 {
4072 u32 TMCValue;
4073 unsigned char BRValue;
4074 u32 Divisor=0;
4075
4076 /* fBRG = fCLK/(TMC * 2^BR)
4077 */
4078 if (data_rate != 0) {
4079 Divisor = 14745600/data_rate;
4080 if (!Divisor)
4081 Divisor = 1;
4082
4083 TMCValue = Divisor;
4084
4085 BRValue = 0;
4086 if (TMCValue != 1 && TMCValue != 2) {
4087 /* BRValue of 0 provides 50/50 duty cycle *only* when
4088 * TMCValue is 1 or 2. BRValue of 1 to 9 always provides
4089 * 50/50 duty cycle.
4090 */
4091 BRValue = 1;
4092 TMCValue >>= 1;
4093 }
4094
4095 /* while TMCValue is too big for TMC register, divide
4096 * by 2 and increment BR exponent.
4097 */
4098 for(; TMCValue > 256 && BRValue < 10; BRValue++)
4099 TMCValue >>= 1;
4100
4101 write_reg(info, TXS,
4102 (unsigned char)((read_reg(info, TXS) & 0xf0) | BRValue));
4103 write_reg(info, RXS,
4104 (unsigned char)((read_reg(info, RXS) & 0xf0) | BRValue));
4105 write_reg(info, TMC, (unsigned char)TMCValue);
4106 }
4107 else {
4108 write_reg(info, TXS,0);
4109 write_reg(info, RXS,0);
4110 write_reg(info, TMC, 0);
4111 }
4112 }
4113
4114 /* Disable receiver
4115 */
4116 static void rx_stop(SLMP_INFO *info)
4117 {
4118 if (debug_level >= DEBUG_LEVEL_ISR)
4119 printk("%s(%d):%s rx_stop()\n",
4120 __FILE__,__LINE__, info->device_name );
4121
4122 write_reg(info, CMD, RXRESET);
4123
4124 info->ie0_value &= ~RXRDYE;
4125 write_reg(info, IE0, info->ie0_value); /* disable Rx data interrupts */
4126
4127 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4128 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4129 write_reg(info, RXDMA + DIR, 0); /* disable Rx DMA interrupts */
4130
4131 info->rx_enabled = false;
4132 info->rx_overflow = false;
4133 }
4134
4135 /* enable the receiver
4136 */
4137 static void rx_start(SLMP_INFO *info)
4138 {
4139 int i;
4140
4141 if (debug_level >= DEBUG_LEVEL_ISR)
4142 printk("%s(%d):%s rx_start()\n",
4143 __FILE__,__LINE__, info->device_name );
4144
4145 write_reg(info, CMD, RXRESET);
4146
4147 if ( info->params.mode == MGSL_MODE_HDLC ) {
4148 /* HDLC, disabe IRQ on rxdata */
4149 info->ie0_value &= ~RXRDYE;
4150 write_reg(info, IE0, info->ie0_value);
4151
4152 /* Reset all Rx DMA buffers and program rx dma */
4153 write_reg(info, RXDMA + DSR, 0); /* disable Rx DMA */
4154 write_reg(info, RXDMA + DCMD, SWABORT); /* reset/init Rx DMA */
4155
4156 for (i = 0; i < info->rx_buf_count; i++) {
4157 info->rx_buf_list[i].status = 0xff;
4158
4159 // throttle to 4 shared memory writes at a time to prevent
4160 // hogging local bus (keep latency time for DMA requests low).
4161 if (!(i % 4))
4162 read_status_reg(info);
4163 }
4164 info->current_rx_buf = 0;
4165
4166 /* set current/1st descriptor address */
4167 write_reg16(info, RXDMA + CDA,
4168 info->rx_buf_list_ex[0].phys_entry);
4169
4170 /* set new last rx descriptor address */
4171 write_reg16(info, RXDMA + EDA,
4172 info->rx_buf_list_ex[info->rx_buf_count - 1].phys_entry);
4173
4174 /* set buffer length (shared by all rx dma data buffers) */
4175 write_reg16(info, RXDMA + BFL, SCABUFSIZE);
4176
4177 write_reg(info, RXDMA + DIR, 0x60); /* enable Rx DMA interrupts (EOM/BOF) */
4178 write_reg(info, RXDMA + DSR, 0xf2); /* clear Rx DMA IRQs, enable Rx DMA */
4179 } else {
4180 /* async, enable IRQ on rxdata */
4181 info->ie0_value |= RXRDYE;
4182 write_reg(info, IE0, info->ie0_value);
4183 }
4184
4185 write_reg(info, CMD, RXENABLE);
4186
4187 info->rx_overflow = false;
4188 info->rx_enabled = true;
4189 }
4190
4191 /* Enable the transmitter and send a transmit frame if
4192 * one is loaded in the DMA buffers.
4193 */
4194 static void tx_start(SLMP_INFO *info)
4195 {
4196 if (debug_level >= DEBUG_LEVEL_ISR)
4197 printk("%s(%d):%s tx_start() tx_count=%d\n",
4198 __FILE__,__LINE__, info->device_name,info->tx_count );
4199
4200 if (!info->tx_enabled ) {
4201 write_reg(info, CMD, TXRESET);
4202 write_reg(info, CMD, TXENABLE);
4203 info->tx_enabled = true;
4204 }
4205
4206 if ( info->tx_count ) {
4207
4208 /* If auto RTS enabled and RTS is inactive, then assert */
4209 /* RTS and set a flag indicating that the driver should */
4210 /* negate RTS when the transmission completes. */
4211
4212 info->drop_rts_on_tx_done = false;
4213
4214 if (info->params.mode != MGSL_MODE_ASYNC) {
4215
4216 if ( info->params.flags & HDLC_FLAG_AUTO_RTS ) {
4217 get_signals( info );
4218 if ( !(info->serial_signals & SerialSignal_RTS) ) {
4219 info->serial_signals |= SerialSignal_RTS;
4220 set_signals( info );
4221 info->drop_rts_on_tx_done = true;
4222 }
4223 }
4224
4225 write_reg16(info, TRC0,
4226 (unsigned short)(((tx_negate_fifo_level-1)<<8) + tx_active_fifo_level));
4227
4228 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4229 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4230
4231 /* set TX CDA (current descriptor address) */
4232 write_reg16(info, TXDMA + CDA,
4233 info->tx_buf_list_ex[0].phys_entry);
4234
4235 /* set TX EDA (last descriptor address) */
4236 write_reg16(info, TXDMA + EDA,
4237 info->tx_buf_list_ex[info->last_tx_buf].phys_entry);
4238
4239 /* enable underrun IRQ */
4240 info->ie1_value &= ~IDLE;
4241 info->ie1_value |= UDRN;
4242 write_reg(info, IE1, info->ie1_value);
4243 write_reg(info, SR1, (unsigned char)(IDLE + UDRN));
4244
4245 write_reg(info, TXDMA + DIR, 0x40); /* enable Tx DMA interrupts (EOM) */
4246 write_reg(info, TXDMA + DSR, 0xf2); /* clear Tx DMA IRQs, enable Tx DMA */
4247
4248 mod_timer(&info->tx_timer, jiffies +
4249 msecs_to_jiffies(5000));
4250 }
4251 else {
4252 tx_load_fifo(info);
4253 /* async, enable IRQ on txdata */
4254 info->ie0_value |= TXRDYE;
4255 write_reg(info, IE0, info->ie0_value);
4256 }
4257
4258 info->tx_active = true;
4259 }
4260 }
4261
4262 /* stop the transmitter and DMA
4263 */
4264 static void tx_stop( SLMP_INFO *info )
4265 {
4266 if (debug_level >= DEBUG_LEVEL_ISR)
4267 printk("%s(%d):%s tx_stop()\n",
4268 __FILE__,__LINE__, info->device_name );
4269
4270 del_timer(&info->tx_timer);
4271
4272 write_reg(info, TXDMA + DSR, 0); /* disable DMA channel */
4273 write_reg(info, TXDMA + DCMD, SWABORT); /* reset/init DMA channel */
4274
4275 write_reg(info, CMD, TXRESET);
4276
4277 info->ie1_value &= ~(UDRN + IDLE);
4278 write_reg(info, IE1, info->ie1_value); /* disable tx status interrupts */
4279 write_reg(info, SR1, (unsigned char)(IDLE + UDRN)); /* clear pending */
4280
4281 info->ie0_value &= ~TXRDYE;
4282 write_reg(info, IE0, info->ie0_value); /* disable tx data interrupts */
4283
4284 info->tx_enabled = false;
4285 info->tx_active = false;
4286 }
4287
4288 /* Fill the transmit FIFO until the FIFO is full or
4289 * there is no more data to load.
4290 */
4291 static void tx_load_fifo(SLMP_INFO *info)
4292 {
4293 u8 TwoBytes[2];
4294
4295 /* do nothing is now tx data available and no XON/XOFF pending */
4296
4297 if ( !info->tx_count && !info->x_char )
4298 return;
4299
4300 /* load the Transmit FIFO until FIFOs full or all data sent */
4301
4302 while( info->tx_count && (read_reg(info,SR0) & BIT1) ) {
4303
4304 /* there is more space in the transmit FIFO and */
4305 /* there is more data in transmit buffer */
4306
4307 if ( (info->tx_count > 1) && !info->x_char ) {
4308 /* write 16-bits */
4309 TwoBytes[0] = info->tx_buf[info->tx_get++];
4310 if (info->tx_get >= info->max_frame_size)
4311 info->tx_get -= info->max_frame_size;
4312 TwoBytes[1] = info->tx_buf[info->tx_get++];
4313 if (info->tx_get >= info->max_frame_size)
4314 info->tx_get -= info->max_frame_size;
4315
4316 write_reg16(info, TRB, *((u16 *)TwoBytes));
4317
4318 info->tx_count -= 2;
4319 info->icount.tx += 2;
4320 } else {
4321 /* only 1 byte left to transmit or 1 FIFO slot left */
4322
4323 if (info->x_char) {
4324 /* transmit pending high priority char */
4325 write_reg(info, TRB, info->x_char);
4326 info->x_char = 0;
4327 } else {
4328 write_reg(info, TRB, info->tx_buf[info->tx_get++]);
4329 if (info->tx_get >= info->max_frame_size)
4330 info->tx_get -= info->max_frame_size;
4331 info->tx_count--;
4332 }
4333 info->icount.tx++;
4334 }
4335 }
4336 }
4337
4338 /* Reset a port to a known state
4339 */
4340 static void reset_port(SLMP_INFO *info)
4341 {
4342 if (info->sca_base) {
4343
4344 tx_stop(info);
4345 rx_stop(info);
4346
4347 info->serial_signals &= ~(SerialSignal_RTS | SerialSignal_DTR);
4348 set_signals(info);
4349
4350 /* disable all port interrupts */
4351 info->ie0_value = 0;
4352 info->ie1_value = 0;
4353 info->ie2_value = 0;
4354 write_reg(info, IE0, info->ie0_value);
4355 write_reg(info, IE1, info->ie1_value);
4356 write_reg(info, IE2, info->ie2_value);
4357
4358 write_reg(info, CMD, CHRESET);
4359 }
4360 }
4361
4362 /* Reset all the ports to a known state.
4363 */
4364 static void reset_adapter(SLMP_INFO *info)
4365 {
4366 int i;
4367
4368 for ( i=0; i < SCA_MAX_PORTS; ++i) {
4369 if (info->port_array[i])
4370 reset_port(info->port_array[i]);
4371 }
4372 }
4373
4374 /* Program port for asynchronous communications.
4375 */
4376 static void async_mode(SLMP_INFO *info)
4377 {
4378
4379 unsigned char RegValue;
4380
4381 tx_stop(info);
4382 rx_stop(info);
4383
4384 /* MD0, Mode Register 0
4385 *
4386 * 07..05 PRCTL<2..0>, Protocol Mode, 000=async
4387 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4388 * 03 Reserved, must be 0
4389 * 02 CRCCC, CRC Calculation, 0=disabled
4390 * 01..00 STOP<1..0> Stop bits (00=1,10=2)
4391 *
4392 * 0000 0000
4393 */
4394 RegValue = 0x00;
4395 if (info->params.stop_bits != 1)
4396 RegValue |= BIT1;
4397 write_reg(info, MD0, RegValue);
4398
4399 /* MD1, Mode Register 1
4400 *
4401 * 07..06 BRATE<1..0>, bit rate, 00=1/1 01=1/16 10=1/32 11=1/64
4402 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits,01=7,10=6,11=5
4403 * 03..02 RXCHR<1..0>, rx char size
4404 * 01..00 PMPM<1..0>, Parity mode, 00=none 10=even 11=odd
4405 *
4406 * 0100 0000
4407 */
4408 RegValue = 0x40;
4409 switch (info->params.data_bits) {
4410 case 7: RegValue |= BIT4 + BIT2; break;
4411 case 6: RegValue |= BIT5 + BIT3; break;
4412 case 5: RegValue |= BIT5 + BIT4 + BIT3 + BIT2; break;
4413 }
4414 if (info->params.parity != ASYNC_PARITY_NONE) {
4415 RegValue |= BIT1;
4416 if (info->params.parity == ASYNC_PARITY_ODD)
4417 RegValue |= BIT0;
4418 }
4419 write_reg(info, MD1, RegValue);
4420
4421 /* MD2, Mode Register 2
4422 *
4423 * 07..02 Reserved, must be 0
4424 * 01..00 CNCT<1..0> Channel connection, 00=normal 11=local loopback
4425 *
4426 * 0000 0000
4427 */
4428 RegValue = 0x00;
4429 if (info->params.loopback)
4430 RegValue |= (BIT1 + BIT0);
4431 write_reg(info, MD2, RegValue);
4432
4433 /* RXS, Receive clock source
4434 *
4435 * 07 Reserved, must be 0
4436 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4437 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4438 */
4439 RegValue=BIT6;
4440 write_reg(info, RXS, RegValue);
4441
4442 /* TXS, Transmit clock source
4443 *
4444 * 07 Reserved, must be 0
4445 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4446 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4447 */
4448 RegValue=BIT6;
4449 write_reg(info, TXS, RegValue);
4450
4451 /* Control Register
4452 *
4453 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4454 */
4455 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4456 write_control_reg(info);
4457
4458 tx_set_idle(info);
4459
4460 /* RRC Receive Ready Control 0
4461 *
4462 * 07..05 Reserved, must be 0
4463 * 04..00 RRC<4..0> Rx FIFO trigger active 0x00 = 1 byte
4464 */
4465 write_reg(info, RRC, 0x00);
4466
4467 /* TRC0 Transmit Ready Control 0
4468 *
4469 * 07..05 Reserved, must be 0
4470 * 04..00 TRC<4..0> Tx FIFO trigger active 0x10 = 16 bytes
4471 */
4472 write_reg(info, TRC0, 0x10);
4473
4474 /* TRC1 Transmit Ready Control 1
4475 *
4476 * 07..05 Reserved, must be 0
4477 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1e = 31 bytes (full-1)
4478 */
4479 write_reg(info, TRC1, 0x1e);
4480
4481 /* CTL, MSCI control register
4482 *
4483 * 07..06 Reserved, set to 0
4484 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4485 * 04 IDLC, idle control, 0=mark 1=idle register
4486 * 03 BRK, break, 0=off 1 =on (async)
4487 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4488 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4489 * 00 RTS, RTS output control, 0=active 1=inactive
4490 *
4491 * 0001 0001
4492 */
4493 RegValue = 0x10;
4494 if (!(info->serial_signals & SerialSignal_RTS))
4495 RegValue |= 0x01;
4496 write_reg(info, CTL, RegValue);
4497
4498 /* enable status interrupts */
4499 info->ie0_value |= TXINTE + RXINTE;
4500 write_reg(info, IE0, info->ie0_value);
4501
4502 /* enable break detect interrupt */
4503 info->ie1_value = BRKD;
4504 write_reg(info, IE1, info->ie1_value);
4505
4506 /* enable rx overrun interrupt */
4507 info->ie2_value = OVRN;
4508 write_reg(info, IE2, info->ie2_value);
4509
4510 set_rate( info, info->params.data_rate * 16 );
4511 }
4512
4513 /* Program the SCA for HDLC communications.
4514 */
4515 static void hdlc_mode(SLMP_INFO *info)
4516 {
4517 unsigned char RegValue;
4518 u32 DpllDivisor;
4519
4520 // Can't use DPLL because SCA outputs recovered clock on RxC when
4521 // DPLL mode selected. This causes output contention with RxC receiver.
4522 // Use of DPLL would require external hardware to disable RxC receiver
4523 // when DPLL mode selected.
4524 info->params.flags &= ~(HDLC_FLAG_TXC_DPLL + HDLC_FLAG_RXC_DPLL);
4525
4526 /* disable DMA interrupts */
4527 write_reg(info, TXDMA + DIR, 0);
4528 write_reg(info, RXDMA + DIR, 0);
4529
4530 /* MD0, Mode Register 0
4531 *
4532 * 07..05 PRCTL<2..0>, Protocol Mode, 100=HDLC
4533 * 04 AUTO, Auto-enable (RTS/CTS/DCD)
4534 * 03 Reserved, must be 0
4535 * 02 CRCCC, CRC Calculation, 1=enabled
4536 * 01 CRC1, CRC selection, 0=CRC-16,1=CRC-CCITT-16
4537 * 00 CRC0, CRC initial value, 1 = all 1s
4538 *
4539 * 1000 0001
4540 */
4541 RegValue = 0x81;
4542 if (info->params.flags & HDLC_FLAG_AUTO_CTS)
4543 RegValue |= BIT4;
4544 if (info->params.flags & HDLC_FLAG_AUTO_DCD)
4545 RegValue |= BIT4;
4546 if (info->params.crc_type == HDLC_CRC_16_CCITT)
4547 RegValue |= BIT2 + BIT1;
4548 write_reg(info, MD0, RegValue);
4549
4550 /* MD1, Mode Register 1
4551 *
4552 * 07..06 ADDRS<1..0>, Address detect, 00=no addr check
4553 * 05..04 TXCHR<1..0>, tx char size, 00=8 bits
4554 * 03..02 RXCHR<1..0>, rx char size, 00=8 bits
4555 * 01..00 PMPM<1..0>, Parity mode, 00=no parity
4556 *
4557 * 0000 0000
4558 */
4559 RegValue = 0x00;
4560 write_reg(info, MD1, RegValue);
4561
4562 /* MD2, Mode Register 2
4563 *
4564 * 07 NRZFM, 0=NRZ, 1=FM
4565 * 06..05 CODE<1..0> Encoding, 00=NRZ
4566 * 04..03 DRATE<1..0> DPLL Divisor, 00=8
4567 * 02 Reserved, must be 0
4568 * 01..00 CNCT<1..0> Channel connection, 0=normal
4569 *
4570 * 0000 0000
4571 */
4572 RegValue = 0x00;
4573 switch(info->params.encoding) {
4574 case HDLC_ENCODING_NRZI: RegValue |= BIT5; break;
4575 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */
4576 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */
4577 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */
4578 #if 0
4579 case HDLC_ENCODING_NRZB: /* not supported */
4580 case HDLC_ENCODING_NRZI_MARK: /* not supported */
4581 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: /* not supported */
4582 #endif
4583 }
4584 if ( info->params.flags & HDLC_FLAG_DPLL_DIV16 ) {
4585 DpllDivisor = 16;
4586 RegValue |= BIT3;
4587 } else if ( info->params.flags & HDLC_FLAG_DPLL_DIV8 ) {
4588 DpllDivisor = 8;
4589 } else {
4590 DpllDivisor = 32;
4591 RegValue |= BIT4;
4592 }
4593 write_reg(info, MD2, RegValue);
4594
4595
4596 /* RXS, Receive clock source
4597 *
4598 * 07 Reserved, must be 0
4599 * 06..04 RXCS<2..0>, clock source, 000=RxC Pin, 100=BRG, 110=DPLL
4600 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4601 */
4602 RegValue=0;
4603 if (info->params.flags & HDLC_FLAG_RXC_BRG)
4604 RegValue |= BIT6;
4605 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4606 RegValue |= BIT6 + BIT5;
4607 write_reg(info, RXS, RegValue);
4608
4609 /* TXS, Transmit clock source
4610 *
4611 * 07 Reserved, must be 0
4612 * 06..04 RXCS<2..0>, clock source, 000=TxC Pin, 100=BRG, 110=Receive Clock
4613 * 03..00 RXBR<3..0>, rate divisor, 0000=1
4614 */
4615 RegValue=0;
4616 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4617 RegValue |= BIT6;
4618 if (info->params.flags & HDLC_FLAG_TXC_DPLL)
4619 RegValue |= BIT6 + BIT5;
4620 write_reg(info, TXS, RegValue);
4621
4622 if (info->params.flags & HDLC_FLAG_RXC_DPLL)
4623 set_rate(info, info->params.clock_speed * DpllDivisor);
4624 else
4625 set_rate(info, info->params.clock_speed);
4626
4627 /* GPDATA (General Purpose I/O Data Register)
4628 *
4629 * 6,4,2,0 CLKSEL<3..0>, 0 = TcCLK in, 1 = Auxclk out
4630 */
4631 if (info->params.flags & HDLC_FLAG_TXC_BRG)
4632 info->port_array[0]->ctrlreg_value |= (BIT0 << (info->port_num * 2));
4633 else
4634 info->port_array[0]->ctrlreg_value &= ~(BIT0 << (info->port_num * 2));
4635 write_control_reg(info);
4636
4637 /* RRC Receive Ready Control 0
4638 *
4639 * 07..05 Reserved, must be 0
4640 * 04..00 RRC<4..0> Rx FIFO trigger active
4641 */
4642 write_reg(info, RRC, rx_active_fifo_level);
4643
4644 /* TRC0 Transmit Ready Control 0
4645 *
4646 * 07..05 Reserved, must be 0
4647 * 04..00 TRC<4..0> Tx FIFO trigger active
4648 */
4649 write_reg(info, TRC0, tx_active_fifo_level);
4650
4651 /* TRC1 Transmit Ready Control 1
4652 *
4653 * 07..05 Reserved, must be 0
4654 * 04..00 TRC<4..0> Tx FIFO trigger inactive 0x1f = 32 bytes (full)
4655 */
4656 write_reg(info, TRC1, (unsigned char)(tx_negate_fifo_level - 1));
4657
4658 /* DMR, DMA Mode Register
4659 *
4660 * 07..05 Reserved, must be 0
4661 * 04 TMOD, Transfer Mode: 1=chained-block
4662 * 03 Reserved, must be 0
4663 * 02 NF, Number of Frames: 1=multi-frame
4664 * 01 CNTE, Frame End IRQ Counter enable: 0=disabled
4665 * 00 Reserved, must be 0
4666 *
4667 * 0001 0100
4668 */
4669 write_reg(info, TXDMA + DMR, 0x14);
4670 write_reg(info, RXDMA + DMR, 0x14);
4671
4672 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4673 write_reg(info, RXDMA + CPB,
4674 (unsigned char)(info->buffer_list_phys >> 16));
4675
4676 /* Set chain pointer base (upper 8 bits of 24 bit addr) */
4677 write_reg(info, TXDMA + CPB,
4678 (unsigned char)(info->buffer_list_phys >> 16));
4679
4680 /* enable status interrupts. other code enables/disables
4681 * the individual sources for these two interrupt classes.
4682 */
4683 info->ie0_value |= TXINTE + RXINTE;
4684 write_reg(info, IE0, info->ie0_value);
4685
4686 /* CTL, MSCI control register
4687 *
4688 * 07..06 Reserved, set to 0
4689 * 05 UDRNC, underrun control, 0=abort 1=CRC+flag (HDLC/BSC)
4690 * 04 IDLC, idle control, 0=mark 1=idle register
4691 * 03 BRK, break, 0=off 1 =on (async)
4692 * 02 SYNCLD, sync char load enable (BSC) 1=enabled
4693 * 01 GOP, go active on poll (LOOP mode) 1=enabled
4694 * 00 RTS, RTS output control, 0=active 1=inactive
4695 *
4696 * 0001 0001
4697 */
4698 RegValue = 0x10;
4699 if (!(info->serial_signals & SerialSignal_RTS))
4700 RegValue |= 0x01;
4701 write_reg(info, CTL, RegValue);
4702
4703 /* preamble not supported ! */
4704
4705 tx_set_idle(info);
4706 tx_stop(info);
4707 rx_stop(info);
4708
4709 set_rate(info, info->params.clock_speed);
4710
4711 if (info->params.loopback)
4712 enable_loopback(info,1);
4713 }
4714
4715 /* Set the transmit HDLC idle mode
4716 */
4717 static void tx_set_idle(SLMP_INFO *info)
4718 {
4719 unsigned char RegValue = 0xff;
4720
4721 /* Map API idle mode to SCA register bits */
4722 switch(info->idle_mode) {
4723 case HDLC_TXIDLE_FLAGS: RegValue = 0x7e; break;
4724 case HDLC_TXIDLE_ALT_ZEROS_ONES: RegValue = 0xaa; break;
4725 case HDLC_TXIDLE_ZEROS: RegValue = 0x00; break;
4726 case HDLC_TXIDLE_ONES: RegValue = 0xff; break;
4727 case HDLC_TXIDLE_ALT_MARK_SPACE: RegValue = 0xaa; break;
4728 case HDLC_TXIDLE_SPACE: RegValue = 0x00; break;
4729 case HDLC_TXIDLE_MARK: RegValue = 0xff; break;
4730 }
4731
4732 write_reg(info, IDL, RegValue);
4733 }
4734
4735 /* Query the adapter for the state of the V24 status (input) signals.
4736 */
4737 static void get_signals(SLMP_INFO *info)
4738 {
4739 u16 status = read_reg(info, SR3);
4740 u16 gpstatus = read_status_reg(info);
4741 u16 testbit;
4742
4743 /* clear all serial signals except RTS and DTR */
4744 info->serial_signals &= SerialSignal_RTS | SerialSignal_DTR;
4745
4746 /* set serial signal bits to reflect MISR */
4747
4748 if (!(status & BIT3))
4749 info->serial_signals |= SerialSignal_CTS;
4750
4751 if ( !(status & BIT2))
4752 info->serial_signals |= SerialSignal_DCD;
4753
4754 testbit = BIT1 << (info->port_num * 2); // Port 0..3 RI is GPDATA<1,3,5,7>
4755 if (!(gpstatus & testbit))
4756 info->serial_signals |= SerialSignal_RI;
4757
4758 testbit = BIT0 << (info->port_num * 2); // Port 0..3 DSR is GPDATA<0,2,4,6>
4759 if (!(gpstatus & testbit))
4760 info->serial_signals |= SerialSignal_DSR;
4761 }
4762
4763 /* Set the state of RTS and DTR based on contents of
4764 * serial_signals member of device context.
4765 */
4766 static void set_signals(SLMP_INFO *info)
4767 {
4768 unsigned char RegValue;
4769 u16 EnableBit;
4770
4771 RegValue = read_reg(info, CTL);
4772 if (info->serial_signals & SerialSignal_RTS)
4773 RegValue &= ~BIT0;
4774 else
4775 RegValue |= BIT0;
4776 write_reg(info, CTL, RegValue);
4777
4778 // Port 0..3 DTR is ctrl reg <1,3,5,7>
4779 EnableBit = BIT1 << (info->port_num*2);
4780 if (info->serial_signals & SerialSignal_DTR)
4781 info->port_array[0]->ctrlreg_value &= ~EnableBit;
4782 else
4783 info->port_array[0]->ctrlreg_value |= EnableBit;
4784 write_control_reg(info);
4785 }
4786
4787 /*******************/
4788 /* DMA Buffer Code */
4789 /*******************/
4790
4791 /* Set the count for all receive buffers to SCABUFSIZE
4792 * and set the current buffer to the first buffer. This effectively
4793 * makes all buffers free and discards any data in buffers.
4794 */
4795 static void rx_reset_buffers(SLMP_INFO *info)
4796 {
4797 rx_free_frame_buffers(info, 0, info->rx_buf_count - 1);
4798 }
4799
4800 /* Free the buffers used by a received frame
4801 *
4802 * info pointer to device instance data
4803 * first index of 1st receive buffer of frame
4804 * last index of last receive buffer of frame
4805 */
4806 static void rx_free_frame_buffers(SLMP_INFO *info, unsigned int first, unsigned int last)
4807 {
4808 bool done = false;
4809
4810 while(!done) {
4811 /* reset current buffer for reuse */
4812 info->rx_buf_list[first].status = 0xff;
4813
4814 if (first == last) {
4815 done = true;
4816 /* set new last rx descriptor address */
4817 write_reg16(info, RXDMA + EDA, info->rx_buf_list_ex[first].phys_entry);
4818 }
4819
4820 first++;
4821 if (first == info->rx_buf_count)
4822 first = 0;
4823 }
4824
4825 /* set current buffer to next buffer after last buffer of frame */
4826 info->current_rx_buf = first;
4827 }
4828
4829 /* Return a received frame from the receive DMA buffers.
4830 * Only frames received without errors are returned.
4831 *
4832 * Return Value: true if frame returned, otherwise false
4833 */
4834 static bool rx_get_frame(SLMP_INFO *info)
4835 {
4836 unsigned int StartIndex, EndIndex; /* index of 1st and last buffers of Rx frame */
4837 unsigned short status;
4838 unsigned int framesize = 0;
4839 bool ReturnCode = false;
4840 unsigned long flags;
4841 struct tty_struct *tty = info->port.tty;
4842 unsigned char addr_field = 0xff;
4843 SCADESC *desc;
4844 SCADESC_EX *desc_ex;
4845
4846 CheckAgain:
4847 /* assume no frame returned, set zero length */
4848 framesize = 0;
4849 addr_field = 0xff;
4850
4851 /*
4852 * current_rx_buf points to the 1st buffer of the next available
4853 * receive frame. To find the last buffer of the frame look for
4854 * a non-zero status field in the buffer entries. (The status
4855 * field is set by the 16C32 after completing a receive frame.
4856 */
4857 StartIndex = EndIndex = info->current_rx_buf;
4858
4859 for ( ;; ) {
4860 desc = &info->rx_buf_list[EndIndex];
4861 desc_ex = &info->rx_buf_list_ex[EndIndex];
4862
4863 if (desc->status == 0xff)
4864 goto Cleanup; /* current desc still in use, no frames available */
4865
4866 if (framesize == 0 && info->params.addr_filter != 0xff)
4867 addr_field = desc_ex->virt_addr[0];
4868
4869 framesize += desc->length;
4870
4871 /* Status != 0 means last buffer of frame */
4872 if (desc->status)
4873 break;
4874
4875 EndIndex++;
4876 if (EndIndex == info->rx_buf_count)
4877 EndIndex = 0;
4878
4879 if (EndIndex == info->current_rx_buf) {
4880 /* all buffers have been 'used' but none mark */
4881 /* the end of a frame. Reset buffers and receiver. */
4882 if ( info->rx_enabled ){
4883 spin_lock_irqsave(&info->lock,flags);
4884 rx_start(info);
4885 spin_unlock_irqrestore(&info->lock,flags);
4886 }
4887 goto Cleanup;
4888 }
4889
4890 }
4891
4892 /* check status of receive frame */
4893
4894 /* frame status is byte stored after frame data
4895 *
4896 * 7 EOM (end of msg), 1 = last buffer of frame
4897 * 6 Short Frame, 1 = short frame
4898 * 5 Abort, 1 = frame aborted
4899 * 4 Residue, 1 = last byte is partial
4900 * 3 Overrun, 1 = overrun occurred during frame reception
4901 * 2 CRC, 1 = CRC error detected
4902 *
4903 */
4904 status = desc->status;
4905
4906 /* ignore CRC bit if not using CRC (bit is undefined) */
4907 /* Note:CRC is not save to data buffer */
4908 if (info->params.crc_type == HDLC_CRC_NONE)
4909 status &= ~BIT2;
4910
4911 if (framesize == 0 ||
4912 (addr_field != 0xff && addr_field != info->params.addr_filter)) {
4913 /* discard 0 byte frames, this seems to occur sometime
4914 * when remote is idling flags.
4915 */
4916 rx_free_frame_buffers(info, StartIndex, EndIndex);
4917 goto CheckAgain;
4918 }
4919
4920 if (framesize < 2)
4921 status |= BIT6;
4922
4923 if (status & (BIT6+BIT5+BIT3+BIT2)) {
4924 /* received frame has errors,
4925 * update counts and mark frame size as 0
4926 */
4927 if (status & BIT6)
4928 info->icount.rxshort++;
4929 else if (status & BIT5)
4930 info->icount.rxabort++;
4931 else if (status & BIT3)
4932 info->icount.rxover++;
4933 else
4934 info->icount.rxcrc++;
4935
4936 framesize = 0;
4937 #if SYNCLINK_GENERIC_HDLC
4938 {
4939 info->netdev->stats.rx_errors++;
4940 info->netdev->stats.rx_frame_errors++;
4941 }
4942 #endif
4943 }
4944
4945 if ( debug_level >= DEBUG_LEVEL_BH )
4946 printk("%s(%d):%s rx_get_frame() status=%04X size=%d\n",
4947 __FILE__,__LINE__,info->device_name,status,framesize);
4948
4949 if ( debug_level >= DEBUG_LEVEL_DATA )
4950 trace_block(info,info->rx_buf_list_ex[StartIndex].virt_addr,
4951 min_t(unsigned int, framesize, SCABUFSIZE), 0);
4952
4953 if (framesize) {
4954 if (framesize > info->max_frame_size)
4955 info->icount.rxlong++;
4956 else {
4957 /* copy dma buffer(s) to contiguous intermediate buffer */
4958 int copy_count = framesize;
4959 int index = StartIndex;
4960 unsigned char *ptmp = info->tmp_rx_buf;
4961 info->tmp_rx_buf_count = framesize;
4962
4963 info->icount.rxok++;
4964
4965 while(copy_count) {
4966 int partial_count = min(copy_count,SCABUFSIZE);
4967 memcpy( ptmp,
4968 info->rx_buf_list_ex[index].virt_addr,
4969 partial_count );
4970 ptmp += partial_count;
4971 copy_count -= partial_count;
4972
4973 if ( ++index == info->rx_buf_count )
4974 index = 0;
4975 }
4976
4977 #if SYNCLINK_GENERIC_HDLC
4978 if (info->netcount)
4979 hdlcdev_rx(info,info->tmp_rx_buf,framesize);
4980 else
4981 #endif
4982 ldisc_receive_buf(tty,info->tmp_rx_buf,
4983 info->flag_buf, framesize);
4984 }
4985 }
4986 /* Free the buffers used by this frame. */
4987 rx_free_frame_buffers( info, StartIndex, EndIndex );
4988
4989 ReturnCode = true;
4990
4991 Cleanup:
4992 if ( info->rx_enabled && info->rx_overflow ) {
4993 /* Receiver is enabled, but needs to restarted due to
4994 * rx buffer overflow. If buffers are empty, restart receiver.
4995 */
4996 if (info->rx_buf_list[EndIndex].status == 0xff) {
4997 spin_lock_irqsave(&info->lock,flags);
4998 rx_start(info);
4999 spin_unlock_irqrestore(&info->lock,flags);
5000 }
5001 }
5002
5003 return ReturnCode;
5004 }
5005
5006 /* load the transmit DMA buffer with data
5007 */
5008 static void tx_load_dma_buffer(SLMP_INFO *info, const char *buf, unsigned int count)
5009 {
5010 unsigned short copy_count;
5011 unsigned int i = 0;
5012 SCADESC *desc;
5013 SCADESC_EX *desc_ex;
5014
5015 if ( debug_level >= DEBUG_LEVEL_DATA )
5016 trace_block(info, buf, min_t(unsigned int, count, SCABUFSIZE), 1);
5017
5018 /* Copy source buffer to one or more DMA buffers, starting with
5019 * the first transmit dma buffer.
5020 */
5021 for(i=0;;)
5022 {
5023 copy_count = min_t(unsigned int, count, SCABUFSIZE);
5024
5025 desc = &info->tx_buf_list[i];
5026 desc_ex = &info->tx_buf_list_ex[i];
5027
5028 load_pci_memory(info, desc_ex->virt_addr,buf,copy_count);
5029
5030 desc->length = copy_count;
5031 desc->status = 0;
5032
5033 buf += copy_count;
5034 count -= copy_count;
5035
5036 if (!count)
5037 break;
5038
5039 i++;
5040 if (i >= info->tx_buf_count)
5041 i = 0;
5042 }
5043
5044 info->tx_buf_list[i].status = 0x81; /* set EOM and EOT status */
5045 info->last_tx_buf = ++i;
5046 }
5047
5048 static bool register_test(SLMP_INFO *info)
5049 {
5050 static unsigned char testval[] = {0x00, 0xff, 0xaa, 0x55, 0x69, 0x96};
5051 static unsigned int count = ARRAY_SIZE(testval);
5052 unsigned int i;
5053 bool rc = true;
5054 unsigned long flags;
5055
5056 spin_lock_irqsave(&info->lock,flags);
5057 reset_port(info);
5058
5059 /* assume failure */
5060 info->init_error = DiagStatus_AddressFailure;
5061
5062 /* Write bit patterns to various registers but do it out of */
5063 /* sync, then read back and verify values. */
5064
5065 for (i = 0 ; i < count ; i++) {
5066 write_reg(info, TMC, testval[i]);
5067 write_reg(info, IDL, testval[(i+1)%count]);
5068 write_reg(info, SA0, testval[(i+2)%count]);
5069 write_reg(info, SA1, testval[(i+3)%count]);
5070
5071 if ( (read_reg(info, TMC) != testval[i]) ||
5072 (read_reg(info, IDL) != testval[(i+1)%count]) ||
5073 (read_reg(info, SA0) != testval[(i+2)%count]) ||
5074 (read_reg(info, SA1) != testval[(i+3)%count]) )
5075 {
5076 rc = false;
5077 break;
5078 }
5079 }
5080
5081 reset_port(info);
5082 spin_unlock_irqrestore(&info->lock,flags);
5083
5084 return rc;
5085 }
5086
5087 static bool irq_test(SLMP_INFO *info)
5088 {
5089 unsigned long timeout;
5090 unsigned long flags;
5091
5092 unsigned char timer = (info->port_num & 1) ? TIMER2 : TIMER0;
5093
5094 spin_lock_irqsave(&info->lock,flags);
5095 reset_port(info);
5096
5097 /* assume failure */
5098 info->init_error = DiagStatus_IrqFailure;
5099 info->irq_occurred = false;
5100
5101 /* setup timer0 on SCA0 to interrupt */
5102
5103 /* IER2<7..4> = timer<3..0> interrupt enables (1=enabled) */
5104 write_reg(info, IER2, (unsigned char)((info->port_num & 1) ? BIT6 : BIT4));
5105
5106 write_reg(info, (unsigned char)(timer + TEPR), 0); /* timer expand prescale */
5107 write_reg16(info, (unsigned char)(timer + TCONR), 1); /* timer constant */
5108
5109
5110 /* TMCS, Timer Control/Status Register
5111 *
5112 * 07 CMF, Compare match flag (read only) 1=match
5113 * 06 ECMI, CMF Interrupt Enable: 1=enabled
5114 * 05 Reserved, must be 0
5115 * 04 TME, Timer Enable
5116 * 03..00 Reserved, must be 0
5117 *
5118 * 0101 0000
5119 */
5120 write_reg(info, (unsigned char)(timer + TMCS), 0x50);
5121
5122 spin_unlock_irqrestore(&info->lock,flags);
5123
5124 timeout=100;
5125 while( timeout-- && !info->irq_occurred ) {
5126 msleep_interruptible(10);
5127 }
5128
5129 spin_lock_irqsave(&info->lock,flags);
5130 reset_port(info);
5131 spin_unlock_irqrestore(&info->lock,flags);
5132
5133 return info->irq_occurred;
5134 }
5135
5136 /* initialize individual SCA device (2 ports)
5137 */
5138 static bool sca_init(SLMP_INFO *info)
5139 {
5140 /* set wait controller to single mem partition (low), no wait states */
5141 write_reg(info, PABR0, 0); /* wait controller addr boundary 0 */
5142 write_reg(info, PABR1, 0); /* wait controller addr boundary 1 */
5143 write_reg(info, WCRL, 0); /* wait controller low range */
5144 write_reg(info, WCRM, 0); /* wait controller mid range */
5145 write_reg(info, WCRH, 0); /* wait controller high range */
5146
5147 /* DPCR, DMA Priority Control
5148 *
5149 * 07..05 Not used, must be 0
5150 * 04 BRC, bus release condition: 0=all transfers complete
5151 * 03 CCC, channel change condition: 0=every cycle
5152 * 02..00 PR<2..0>, priority 100=round robin
5153 *
5154 * 00000100 = 0x04
5155 */
5156 write_reg(info, DPCR, dma_priority);
5157
5158 /* DMA Master Enable, BIT7: 1=enable all channels */
5159 write_reg(info, DMER, 0x80);
5160
5161 /* enable all interrupt classes */
5162 write_reg(info, IER0, 0xff); /* TxRDY,RxRDY,TxINT,RxINT (ports 0-1) */
5163 write_reg(info, IER1, 0xff); /* DMIB,DMIA (channels 0-3) */
5164 write_reg(info, IER2, 0xf0); /* TIRQ (timers 0-3) */
5165
5166 /* ITCR, interrupt control register
5167 * 07 IPC, interrupt priority, 0=MSCI->DMA
5168 * 06..05 IAK<1..0>, Acknowledge cycle, 00=non-ack cycle
5169 * 04 VOS, Vector Output, 0=unmodified vector
5170 * 03..00 Reserved, must be 0
5171 */
5172 write_reg(info, ITCR, 0);
5173
5174 return true;
5175 }
5176
5177 /* initialize adapter hardware
5178 */
5179 static bool init_adapter(SLMP_INFO *info)
5180 {
5181 int i;
5182
5183 /* Set BIT30 of Local Control Reg 0x50 to reset SCA */
5184 volatile u32 *MiscCtrl = (u32 *)(info->lcr_base + 0x50);
5185 u32 readval;
5186
5187 info->misc_ctrl_value |= BIT30;
5188 *MiscCtrl = info->misc_ctrl_value;
5189
5190 /*
5191 * Force at least 170ns delay before clearing
5192 * reset bit. Each read from LCR takes at least
5193 * 30ns so 10 times for 300ns to be safe.
5194 */
5195 for(i=0;i<10;i++)
5196 readval = *MiscCtrl;
5197
5198 info->misc_ctrl_value &= ~BIT30;
5199 *MiscCtrl = info->misc_ctrl_value;
5200
5201 /* init control reg (all DTRs off, all clksel=input) */
5202 info->ctrlreg_value = 0xaa;
5203 write_control_reg(info);
5204
5205 {
5206 volatile u32 *LCR1BRDR = (u32 *)(info->lcr_base + 0x2c);
5207 lcr1_brdr_value &= ~(BIT5 + BIT4 + BIT3);
5208
5209 switch(read_ahead_count)
5210 {
5211 case 16:
5212 lcr1_brdr_value |= BIT5 + BIT4 + BIT3;
5213 break;
5214 case 8:
5215 lcr1_brdr_value |= BIT5 + BIT4;
5216 break;
5217 case 4:
5218 lcr1_brdr_value |= BIT5 + BIT3;
5219 break;
5220 case 0:
5221 lcr1_brdr_value |= BIT5;
5222 break;
5223 }
5224
5225 *LCR1BRDR = lcr1_brdr_value;
5226 *MiscCtrl = misc_ctrl_value;
5227 }
5228
5229 sca_init(info->port_array[0]);
5230 sca_init(info->port_array[2]);
5231
5232 return true;
5233 }
5234
5235 /* Loopback an HDLC frame to test the hardware
5236 * interrupt and DMA functions.
5237 */
5238 static bool loopback_test(SLMP_INFO *info)
5239 {
5240 #define TESTFRAMESIZE 20
5241
5242 unsigned long timeout;
5243 u16 count = TESTFRAMESIZE;
5244 unsigned char buf[TESTFRAMESIZE];
5245 bool rc = false;
5246 unsigned long flags;
5247
5248 struct tty_struct *oldtty = info->port.tty;
5249 u32 speed = info->params.clock_speed;
5250
5251 info->params.clock_speed = 3686400;
5252 info->port.tty = NULL;
5253
5254 /* assume failure */
5255 info->init_error = DiagStatus_DmaFailure;
5256
5257 /* build and send transmit frame */
5258 for (count = 0; count < TESTFRAMESIZE;++count)
5259 buf[count] = (unsigned char)count;
5260
5261 memset(info->tmp_rx_buf,0,TESTFRAMESIZE);
5262
5263 /* program hardware for HDLC and enabled receiver */
5264 spin_lock_irqsave(&info->lock,flags);
5265 hdlc_mode(info);
5266 enable_loopback(info,1);
5267 rx_start(info);
5268 info->tx_count = count;
5269 tx_load_dma_buffer(info,buf,count);
5270 tx_start(info);
5271 spin_unlock_irqrestore(&info->lock,flags);
5272
5273 /* wait for receive complete */
5274 /* Set a timeout for waiting for interrupt. */
5275 for ( timeout = 100; timeout; --timeout ) {
5276 msleep_interruptible(10);
5277
5278 if (rx_get_frame(info)) {
5279 rc = true;
5280 break;
5281 }
5282 }
5283
5284 /* verify received frame length and contents */
5285 if (rc &&
5286 ( info->tmp_rx_buf_count != count ||
5287 memcmp(buf, info->tmp_rx_buf,count))) {
5288 rc = false;
5289 }
5290
5291 spin_lock_irqsave(&info->lock,flags);
5292 reset_adapter(info);
5293 spin_unlock_irqrestore(&info->lock,flags);
5294
5295 info->params.clock_speed = speed;
5296 info->port.tty = oldtty;
5297
5298 return rc;
5299 }
5300
5301 /* Perform diagnostics on hardware
5302 */
5303 static int adapter_test( SLMP_INFO *info )
5304 {
5305 unsigned long flags;
5306 if ( debug_level >= DEBUG_LEVEL_INFO )
5307 printk( "%s(%d):Testing device %s\n",
5308 __FILE__,__LINE__,info->device_name );
5309
5310 spin_lock_irqsave(&info->lock,flags);
5311 init_adapter(info);
5312 spin_unlock_irqrestore(&info->lock,flags);
5313
5314 info->port_array[0]->port_count = 0;
5315
5316 if ( register_test(info->port_array[0]) &&
5317 register_test(info->port_array[1])) {
5318
5319 info->port_array[0]->port_count = 2;
5320
5321 if ( register_test(info->port_array[2]) &&
5322 register_test(info->port_array[3]) )
5323 info->port_array[0]->port_count += 2;
5324 }
5325 else {
5326 printk( "%s(%d):Register test failure for device %s Addr=%08lX\n",
5327 __FILE__,__LINE__,info->device_name, (unsigned long)(info->phys_sca_base));
5328 return -ENODEV;
5329 }
5330
5331 if ( !irq_test(info->port_array[0]) ||
5332 !irq_test(info->port_array[1]) ||
5333 (info->port_count == 4 && !irq_test(info->port_array[2])) ||
5334 (info->port_count == 4 && !irq_test(info->port_array[3]))) {
5335 printk( "%s(%d):Interrupt test failure for device %s IRQ=%d\n",
5336 __FILE__,__LINE__,info->device_name, (unsigned short)(info->irq_level) );
5337 return -ENODEV;
5338 }
5339
5340 if (!loopback_test(info->port_array[0]) ||
5341 !loopback_test(info->port_array[1]) ||
5342 (info->port_count == 4 && !loopback_test(info->port_array[2])) ||
5343 (info->port_count == 4 && !loopback_test(info->port_array[3]))) {
5344 printk( "%s(%d):DMA test failure for device %s\n",
5345 __FILE__,__LINE__,info->device_name);
5346 return -ENODEV;
5347 }
5348
5349 if ( debug_level >= DEBUG_LEVEL_INFO )
5350 printk( "%s(%d):device %s passed diagnostics\n",
5351 __FILE__,__LINE__,info->device_name );
5352
5353 info->port_array[0]->init_error = 0;
5354 info->port_array[1]->init_error = 0;
5355 if ( info->port_count > 2 ) {
5356 info->port_array[2]->init_error = 0;
5357 info->port_array[3]->init_error = 0;
5358 }
5359
5360 return 0;
5361 }
5362
5363 /* Test the shared memory on a PCI adapter.
5364 */
5365 static bool memory_test(SLMP_INFO *info)
5366 {
5367 static unsigned long testval[] = { 0x0, 0x55555555, 0xaaaaaaaa,
5368 0x66666666, 0x99999999, 0xffffffff, 0x12345678 };
5369 unsigned long count = ARRAY_SIZE(testval);
5370 unsigned long i;
5371 unsigned long limit = SCA_MEM_SIZE/sizeof(unsigned long);
5372 unsigned long * addr = (unsigned long *)info->memory_base;
5373
5374 /* Test data lines with test pattern at one location. */
5375
5376 for ( i = 0 ; i < count ; i++ ) {
5377 *addr = testval[i];
5378 if ( *addr != testval[i] )
5379 return false;
5380 }
5381
5382 /* Test address lines with incrementing pattern over */
5383 /* entire address range. */
5384
5385 for ( i = 0 ; i < limit ; i++ ) {
5386 *addr = i * 4;
5387 addr++;
5388 }
5389
5390 addr = (unsigned long *)info->memory_base;
5391
5392 for ( i = 0 ; i < limit ; i++ ) {
5393 if ( *addr != i * 4 )
5394 return false;
5395 addr++;
5396 }
5397
5398 memset( info->memory_base, 0, SCA_MEM_SIZE );
5399 return true;
5400 }
5401
5402 /* Load data into PCI adapter shared memory.
5403 *
5404 * The PCI9050 releases control of the local bus
5405 * after completing the current read or write operation.
5406 *
5407 * While the PCI9050 write FIFO not empty, the
5408 * PCI9050 treats all of the writes as a single transaction
5409 * and does not release the bus. This causes DMA latency problems
5410 * at high speeds when copying large data blocks to the shared memory.
5411 *
5412 * This function breaks a write into multiple transations by
5413 * interleaving a read which flushes the write FIFO and 'completes'
5414 * the write transation. This allows any pending DMA request to gain control
5415 * of the local bus in a timely fasion.
5416 */
5417 static void load_pci_memory(SLMP_INFO *info, char* dest, const char* src, unsigned short count)
5418 {
5419 /* A load interval of 16 allows for 4 32-bit writes at */
5420 /* 136ns each for a maximum latency of 542ns on the local bus.*/
5421
5422 unsigned short interval = count / sca_pci_load_interval;
5423 unsigned short i;
5424
5425 for ( i = 0 ; i < interval ; i++ )
5426 {
5427 memcpy(dest, src, sca_pci_load_interval);
5428 read_status_reg(info);
5429 dest += sca_pci_load_interval;
5430 src += sca_pci_load_interval;
5431 }
5432
5433 memcpy(dest, src, count % sca_pci_load_interval);
5434 }
5435
5436 static void trace_block(SLMP_INFO *info,const char* data, int count, int xmit)
5437 {
5438 int i;
5439 int linecount;
5440 if (xmit)
5441 printk("%s tx data:\n",info->device_name);
5442 else
5443 printk("%s rx data:\n",info->device_name);
5444
5445 while(count) {
5446 if (count > 16)
5447 linecount = 16;
5448 else
5449 linecount = count;
5450
5451 for(i=0;i<linecount;i++)
5452 printk("%02X ",(unsigned char)data[i]);
5453 for(;i<17;i++)
5454 printk(" ");
5455 for(i=0;i<linecount;i++) {
5456 if (data[i]>=040 && data[i]<=0176)
5457 printk("%c",data[i]);
5458 else
5459 printk(".");
5460 }
5461 printk("\n");
5462
5463 data += linecount;
5464 count -= linecount;
5465 }
5466 } /* end of trace_block() */
5467
5468 /* called when HDLC frame times out
5469 * update stats and do tx completion processing
5470 */
5471 static void tx_timeout(unsigned long context)
5472 {
5473 SLMP_INFO *info = (SLMP_INFO*)context;
5474 unsigned long flags;
5475
5476 if ( debug_level >= DEBUG_LEVEL_INFO )
5477 printk( "%s(%d):%s tx_timeout()\n",
5478 __FILE__,__LINE__,info->device_name);
5479 if(info->tx_active && info->params.mode == MGSL_MODE_HDLC) {
5480 info->icount.txtimeout++;
5481 }
5482 spin_lock_irqsave(&info->lock,flags);
5483 info->tx_active = false;
5484 info->tx_count = info->tx_put = info->tx_get = 0;
5485
5486 spin_unlock_irqrestore(&info->lock,flags);
5487
5488 #if SYNCLINK_GENERIC_HDLC
5489 if (info->netcount)
5490 hdlcdev_tx_done(info);
5491 else
5492 #endif
5493 bh_transmit(info);
5494 }
5495
5496 /* called to periodically check the DSR/RI modem signal input status
5497 */
5498 static void status_timeout(unsigned long context)
5499 {
5500 u16 status = 0;
5501 SLMP_INFO *info = (SLMP_INFO*)context;
5502 unsigned long flags;
5503 unsigned char delta;
5504
5505
5506 spin_lock_irqsave(&info->lock,flags);
5507 get_signals(info);
5508 spin_unlock_irqrestore(&info->lock,flags);
5509
5510 /* check for DSR/RI state change */
5511
5512 delta = info->old_signals ^ info->serial_signals;
5513 info->old_signals = info->serial_signals;
5514
5515 if (delta & SerialSignal_DSR)
5516 status |= MISCSTATUS_DSR_LATCHED|(info->serial_signals&SerialSignal_DSR);
5517
5518 if (delta & SerialSignal_RI)
5519 status |= MISCSTATUS_RI_LATCHED|(info->serial_signals&SerialSignal_RI);
5520
5521 if (delta & SerialSignal_DCD)
5522 status |= MISCSTATUS_DCD_LATCHED|(info->serial_signals&SerialSignal_DCD);
5523
5524 if (delta & SerialSignal_CTS)
5525 status |= MISCSTATUS_CTS_LATCHED|(info->serial_signals&SerialSignal_CTS);
5526
5527 if (status)
5528 isr_io_pin(info,status);
5529
5530 mod_timer(&info->status_timer, jiffies + msecs_to_jiffies(10));
5531 }
5532
5533
5534 /* Register Access Routines -
5535 * All registers are memory mapped
5536 */
5537 #define CALC_REGADDR() \
5538 unsigned char * RegAddr = (unsigned char*)(info->sca_base + Addr); \
5539 if (info->port_num > 1) \
5540 RegAddr += 256; /* port 0-1 SCA0, 2-3 SCA1 */ \
5541 if ( info->port_num & 1) { \
5542 if (Addr > 0x7f) \
5543 RegAddr += 0x40; /* DMA access */ \
5544 else if (Addr > 0x1f && Addr < 0x60) \
5545 RegAddr += 0x20; /* MSCI access */ \
5546 }
5547
5548
5549 static unsigned char read_reg(SLMP_INFO * info, unsigned char Addr)
5550 {
5551 CALC_REGADDR();
5552 return *RegAddr;
5553 }
5554 static void write_reg(SLMP_INFO * info, unsigned char Addr, unsigned char Value)
5555 {
5556 CALC_REGADDR();
5557 *RegAddr = Value;
5558 }
5559
5560 static u16 read_reg16(SLMP_INFO * info, unsigned char Addr)
5561 {
5562 CALC_REGADDR();
5563 return *((u16 *)RegAddr);
5564 }
5565
5566 static void write_reg16(SLMP_INFO * info, unsigned char Addr, u16 Value)
5567 {
5568 CALC_REGADDR();
5569 *((u16 *)RegAddr) = Value;
5570 }
5571
5572 static unsigned char read_status_reg(SLMP_INFO * info)
5573 {
5574 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5575 return *RegAddr;
5576 }
5577
5578 static void write_control_reg(SLMP_INFO * info)
5579 {
5580 unsigned char *RegAddr = (unsigned char *)info->statctrl_base;
5581 *RegAddr = info->port_array[0]->ctrlreg_value;
5582 }
5583
5584
5585 static int synclinkmp_init_one (struct pci_dev *dev,
5586 const struct pci_device_id *ent)
5587 {
5588 if (pci_enable_device(dev)) {
5589 printk("error enabling pci device %p\n", dev);
5590 return -EIO;
5591 }
5592 return device_init( ++synclinkmp_adapter_count, dev );
5593 }
5594
5595 static void synclinkmp_remove_one (struct pci_dev *dev)
5596 {
5597 }
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