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git.proxmox.com Git - qemu.git/blob - exec-all.h
2 * internal execution defines for qemu
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
25 #define xglue(x, y) x ## y
26 #define glue(x, y) xglue(x, y)
27 #define stringify(s) tostring(s)
28 #define tostring(s) #s
32 #define __builtin_expect(x, n) (x)
36 #define REGPARM(n) __attribute((regparm(n)))
41 /* is_jmp field values */
42 #define DISAS_NEXT 0 /* next instruction can be analyzed */
43 #define DISAS_JUMP 1 /* only pc was modified dynamically */
44 #define DISAS_UPDATE 2 /* cpu state was modified dynamically */
45 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
47 struct TranslationBlock
;
49 /* XXX: make safe guess about sizes */
50 #define MAX_OP_PER_INSTR 32
51 #define OPC_BUF_SIZE 512
52 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
54 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
56 extern uint16_t gen_opc_buf
[OPC_BUF_SIZE
];
57 extern uint32_t gen_opparam_buf
[OPPARAM_BUF_SIZE
];
58 extern uint32_t gen_opc_pc
[OPC_BUF_SIZE
];
59 extern uint8_t gen_opc_cc_op
[OPC_BUF_SIZE
];
60 extern uint8_t gen_opc_instr_start
[OPC_BUF_SIZE
];
62 #if defined(TARGET_I386)
64 void optimize_flags_init(void);
71 int gen_intermediate_code(CPUState
*env
, struct TranslationBlock
*tb
);
72 int gen_intermediate_code_pc(CPUState
*env
, struct TranslationBlock
*tb
);
73 void dump_ops(const uint16_t *opc_buf
, const uint32_t *opparam_buf
);
74 int cpu_gen_code(CPUState
*env
, struct TranslationBlock
*tb
,
75 int max_code_size
, int *gen_code_size_ptr
);
76 int cpu_restore_state(struct TranslationBlock
*tb
,
77 CPUState
*env
, unsigned long searched_pc
);
78 void cpu_exec_init(void);
79 int page_unprotect(unsigned long address
);
80 void page_unmap(void);
81 void tlb_flush_page(CPUState
*env
, uint32_t addr
);
82 void tlb_flush_page_write(CPUState
*env
, uint32_t addr
);
83 void tlb_flush(CPUState
*env
);
85 #define CODE_GEN_MAX_SIZE 65536
86 #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */
88 #define CODE_GEN_HASH_BITS 15
89 #define CODE_GEN_HASH_SIZE (1 << CODE_GEN_HASH_BITS)
91 /* maximum total translate dcode allocated */
92 #define CODE_GEN_BUFFER_SIZE (2048 * 1024)
93 //#define CODE_GEN_BUFFER_SIZE (128 * 1024)
95 #if defined(__powerpc__)
96 #define USE_DIRECT_JUMP
99 typedef struct TranslationBlock
{
100 unsigned long pc
; /* simulated PC corresponding to this block (EIP + CS base) */
101 unsigned long cs_base
; /* CS base for this block */
102 unsigned int flags
; /* flags defining in which context the code was generated */
103 uint16_t size
; /* size of target code for this block (1 <=
104 size <= TARGET_PAGE_SIZE) */
105 uint8_t *tc_ptr
; /* pointer to the translated code */
106 struct TranslationBlock
*hash_next
; /* next matching block */
107 struct TranslationBlock
*page_next
[2]; /* next blocks in even/odd page */
108 /* the following data are used to directly call another TB from
109 the code of this one. */
110 uint16_t tb_next_offset
[2]; /* offset of original jump target */
111 #ifdef USE_DIRECT_JUMP
112 uint16_t tb_jmp_offset
[4]; /* offset of jump instruction */
114 uint32_t tb_next
[2]; /* address of jump generated code */
116 /* list of TBs jumping to this one. This is a circular list using
117 the two least significant bits of the pointers to tell what is
118 the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
120 struct TranslationBlock
*jmp_next
[2];
121 struct TranslationBlock
*jmp_first
;
124 static inline unsigned int tb_hash_func(unsigned long pc
)
126 return pc
& (CODE_GEN_HASH_SIZE
- 1);
129 TranslationBlock
*tb_alloc(unsigned long pc
);
131 void tb_link(TranslationBlock
*tb
);
133 extern TranslationBlock
*tb_hash
[CODE_GEN_HASH_SIZE
];
135 extern uint8_t code_gen_buffer
[CODE_GEN_BUFFER_SIZE
];
136 extern uint8_t *code_gen_ptr
;
138 /* find a translation block in the translation cache. If not found,
139 return NULL and the pointer to the last element of the list in pptb */
140 static inline TranslationBlock
*tb_find(TranslationBlock
***pptb
,
142 unsigned long cs_base
,
145 TranslationBlock
**ptb
, *tb
;
148 h
= tb_hash_func(pc
);
154 if (tb
->pc
== pc
&& tb
->cs_base
== cs_base
&& tb
->flags
== flags
)
156 ptb
= &tb
->hash_next
;
162 #if defined(__powerpc__)
164 static inline void tb_set_jmp_target1(unsigned long jmp_addr
, unsigned long addr
)
168 /* patch the branch destination */
169 ptr
= (uint32_t *)jmp_addr
;
171 val
= (val
& ~0x03fffffc) | ((addr
- jmp_addr
) & 0x03fffffc);
174 asm volatile ("dcbst 0,%0" : : "r"(ptr
) : "memory");
175 asm volatile ("sync" : : : "memory");
176 asm volatile ("icbi 0,%0" : : "r"(ptr
) : "memory");
177 asm volatile ("sync" : : : "memory");
178 asm volatile ("isync" : : : "memory");
181 static inline void tb_set_jmp_target(TranslationBlock
*tb
,
182 int n
, unsigned long addr
)
184 unsigned long offset
;
186 offset
= tb
->tb_jmp_offset
[n
];
187 tb_set_jmp_target1((unsigned long)(tb
->tc_ptr
+ offset
), addr
);
188 offset
= tb
->tb_jmp_offset
[n
+ 2];
189 if (offset
!= 0xffff)
190 tb_set_jmp_target1((unsigned long)(tb
->tc_ptr
+ offset
), addr
);
195 /* set the jump target */
196 static inline void tb_set_jmp_target(TranslationBlock
*tb
,
197 int n
, unsigned long addr
)
199 tb
->tb_next
[n
] = addr
;
204 static inline void tb_add_jump(TranslationBlock
*tb
, int n
,
205 TranslationBlock
*tb_next
)
207 /* NOTE: this test is only needed for thread safety */
208 if (!tb
->jmp_next
[n
]) {
209 /* patch the native jump address */
210 tb_set_jmp_target(tb
, n
, (unsigned long)tb_next
->tc_ptr
);
212 /* add in TB jmp circular list */
213 tb
->jmp_next
[n
] = tb_next
->jmp_first
;
214 tb_next
->jmp_first
= (TranslationBlock
*)((long)(tb
) | (n
));
218 TranslationBlock
*tb_find_pc(unsigned long pc_ptr
);
221 #define offsetof(type, field) ((size_t) &((type *)0)->field)
224 #if defined(__powerpc__)
226 /* on PowerPC we patch the jump instruction directly */
227 #define JUMP_TB(opname, tbparam, n, eip)\
229 asm volatile (".section \".data\"\n"\
230 "__op_label" #n "." stringify(opname) ":\n"\
233 "b __op_jmp" #n "\n"\
235 T0 = (long)(tbparam) + (n);\
240 #define JUMP_TB2(opname, tbparam, n)\
242 asm volatile ("b __op_jmp%0\n" : : "i" (n + 2));\
247 /* jump to next block operations (more portable code, does not need
248 cache flushing, but slower because of indirect jump) */
249 #define JUMP_TB(opname, tbparam, n, eip)\
251 static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
252 static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
253 goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
255 T0 = (long)(tbparam) + (n);\
261 /* second jump to same destination 'n' */
262 #define JUMP_TB2(opname, tbparam, n)\
264 goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
269 /* physical memory access */
270 #define IO_MEM_NB_ENTRIES 256
271 #define TLB_INVALID_MASK (1 << 3)
272 #define IO_MEM_SHIFT 4
273 #define IO_MEM_UNASSIGNED (1 << IO_MEM_SHIFT)
275 unsigned long physpage_find(unsigned long page
);
277 extern CPUWriteMemoryFunc
*io_mem_write
[IO_MEM_NB_ENTRIES
][4];
278 extern CPUReadMemoryFunc
*io_mem_read
[IO_MEM_NB_ENTRIES
][4];
281 static inline int testandset (int *p
)
284 __asm__
__volatile__ (
292 : "r" (p
), "r" (1), "r" (0)
299 static inline int testandset (int *p
)
304 __asm__
__volatile__ ("lock; cmpxchgl %3, %1; sete %0"
305 : "=q" (ret
), "=m" (*p
), "=a" (readval
)
306 : "r" (1), "m" (*p
), "a" (0)
313 static inline int testandset (int *p
)
317 __asm__
__volatile__ ("0: cs %0,%1,0(%2)\n"
320 : "r" (1), "a" (p
), "0" (*p
)
327 static inline int testandset (int *p
)
332 __asm__
__volatile__ ("0: mov 1,%2\n"
339 : "=r" (ret
), "=m" (*p
), "=r" (one
)
346 static inline int testandset (int *p
)
350 __asm__
__volatile__("ldstub [%1], %0"
355 return (ret
? 1 : 0);
360 static inline int testandset (int *spinlock
)
362 register unsigned int ret
;
363 __asm__
__volatile__("swp %0, %1, [%2]"
365 : "0"(1), "r"(spinlock
));
372 static inline int testandset (int *p
)
375 __asm__
__volatile__("tas %1; sne %0"
383 typedef int spinlock_t
;
385 #define SPIN_LOCK_UNLOCKED 0
388 static inline void spin_lock(spinlock_t
*lock
)
390 while (testandset(lock
));
393 static inline void spin_unlock(spinlock_t
*lock
)
398 static inline int spin_trylock(spinlock_t
*lock
)
400 return !testandset(lock
);
403 static inline void spin_lock(spinlock_t
*lock
)
407 static inline void spin_unlock(spinlock_t
*lock
)
411 static inline int spin_trylock(spinlock_t
*lock
)
417 extern spinlock_t tb_lock
;
420 #if defined(TARGET_I386) && !defined(CONFIG_USER_ONLY)
422 void tlb_fill(unsigned long addr
, int is_write
, int is_user
,
425 #define ACCESS_TYPE 3
426 #define MEMSUFFIX _code
427 #define env cpu_single_env
430 #include "softmmu_header.h"
433 #include "softmmu_header.h"
436 #include "softmmu_header.h"