exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 #ifndef glue
  25 #define xglue(x, y) x ## y
  26 #define glue(x, y) xglue(x, y)
  27 #define stringify(s)    tostring(s)
  28 #define tostring(s)     #s
  29 #endif
  30
  31 #if GCC_MAJOR < 3
  32 #define __builtin_expect(x, n) (x)
  33 #endif
  34
  35 #ifdef __i386__
  36 #define REGPARM(n) __attribute((regparm(n)))
  37 #else
  38 #define REGPARM(n)
  39 #endif
  40
  41 /* is_jmp field values */
  42 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  43 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  44 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  45 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  46
  47 struct TranslationBlock;
  48
  49 /* XXX: make safe guess about sizes */
  50 #define MAX_OP_PER_INSTR 32
  51 #define OPC_BUF_SIZE 512
  52 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  53
  54 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
  55
  56 extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
  57 extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
  58 extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
  59 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  60 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  61
  62 typedef void (GenOpFunc)(void);
  63 typedef void (GenOpFunc1)(long);
  64 typedef void (GenOpFunc2)(long, long);
  65 typedef void (GenOpFunc3)(long, long, long);
  66
  67 #if defined(TARGET_I386)
  68
  69 void optimize_flags_init(void);
  70
  71 #endif
  72
  73 extern FILE *logfile;
  74 extern int loglevel;
  75
  76 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  77 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  78 void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
  79 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  80                  int max_code_size, int *gen_code_size_ptr);
  81 int cpu_restore_state(struct TranslationBlock *tb,
  82                       CPUState *env, unsigned long searched_pc,
  83                       void *puc);
  84 int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
  85                       int max_code_size, int *gen_code_size_ptr);
  86 int cpu_restore_state_copy(struct TranslationBlock *tb,
  87                            CPUState *env, unsigned long searched_pc,
  88                            void *puc);
  89 void cpu_resume_from_signal(CPUState *env1, void *puc);
  90 void cpu_exec_init(void);
  91 int page_unprotect(unsigned long address, unsigned long pc, void *puc);
  92 void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
  93                                    int is_cpu_write_access);
  94 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  95 void tlb_flush_page(CPUState *env, target_ulong addr);
  96 void tlb_flush(CPUState *env, int flush_global);
  97 int tlb_set_page(CPUState *env, target_ulong vaddr,
  98                  target_phys_addr_t paddr, int prot,
  99                  int is_user, int is_softmmu);
 100
 101 #define CODE_GEN_MAX_SIZE        65536
 102 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 103
 104 #define CODE_GEN_HASH_BITS     15
 105 #define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)
 106
 107 #define CODE_GEN_PHYS_HASH_BITS     15
 108 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 109
 110 /* maximum total translate dcode allocated */
 111
 112 /* NOTE: the translated code area cannot be too big because on some
 113    archs the range of "fast" function calls is limited. Here is a
 114    summary of the ranges:
 115
 116    i386  : signed 32 bits
 117    arm   : signed 26 bits
 118    ppc   : signed 24 bits
 119    sparc : signed 32 bits
 120    alpha : signed 23 bits
 121 */
 122
 123 #if defined(__alpha__)
 124 #define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
 125 #elif defined(__powerpc__)
 126 #define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
 127 #else
 128 #define CODE_GEN_BUFFER_SIZE     (8 * 1024 * 1024)
 129 #endif
 130
 131 //#define CODE_GEN_BUFFER_SIZE     (128 * 1024)
 132
 133 /* estimated block size for TB allocation */
 134 /* XXX: use a per code average code fragment size and modulate it
 135    according to the host CPU */
 136 #if defined(CONFIG_SOFTMMU)
 137 #define CODE_GEN_AVG_BLOCK_SIZE 128
 138 #else
 139 #define CODE_GEN_AVG_BLOCK_SIZE 64
 140 #endif
 141
 142 #define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
 143
 144 #if defined(__powerpc__)
 145 #define USE_DIRECT_JUMP
 146 #endif
 147 #if defined(__i386__) && !defined(_WIN32)
 148 #define USE_DIRECT_JUMP
 149 #endif
 150
 151 typedef struct TranslationBlock {
 152     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 153     target_ulong cs_base; /* CS base for this block */
 154     unsigned int flags; /* flags defining in which context the code was generated */
 155     uint16_t size;      /* size of target code for this block (1 <=
 156                            size <= TARGET_PAGE_SIZE) */
 157     uint16_t cflags;    /* compile flags */
 158 #define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
 159 #define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
 160 #define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
 161 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
 162
 163     uint8_t *tc_ptr;    /* pointer to the translated code */
 164     struct TranslationBlock *hash_next; /* next matching tb for virtual address */
 165     /* next matching tb for physical address. */
 166     struct TranslationBlock *phys_hash_next;
 167     /* first and second physical page containing code. The lower bit
 168        of the pointer tells the index in page_next[] */
 169     struct TranslationBlock *page_next[2];
 170     target_ulong page_addr[2];
 171
 172     /* the following data are used to directly call another TB from
 173        the code of this one. */
 174     uint16_t tb_next_offset[2]; /* offset of original jump target */
 175 #ifdef USE_DIRECT_JUMP
 176     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 177 #else
 178     uint32_t tb_next[2]; /* address of jump generated code */
 179 #endif
 180     /* list of TBs jumping to this one. This is a circular list using
 181        the two least significant bits of the pointers to tell what is
 182        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 183        jmp_first */
 184     struct TranslationBlock *jmp_next[2];
 185     struct TranslationBlock *jmp_first;
 186 } TranslationBlock;
 187
 188 static inline unsigned int tb_hash_func(unsigned long pc)
 189 {
 190     return pc & (CODE_GEN_HASH_SIZE - 1);
 191 }
 192
 193 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 194 {
 195     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 196 }
 197
 198 TranslationBlock *tb_alloc(unsigned long pc);
 199 void tb_flush(CPUState *env);
 200 void tb_link(TranslationBlock *tb);
 201 void tb_link_phys(TranslationBlock *tb,
 202                   target_ulong phys_pc, target_ulong phys_page2);
 203
 204 extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
 205 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 206
 207 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 208 extern uint8_t *code_gen_ptr;
 209
 210 /* find a translation block in the translation cache. If not found,
 211    return NULL and the pointer to the last element of the list in pptb */
 212 static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
 213                                         target_ulong pc,
 214                                         target_ulong cs_base,
 215                                         unsigned int flags)
 216 {
 217     TranslationBlock **ptb, *tb;
 218     unsigned int h;
 219
 220     h = tb_hash_func(pc);
 221     ptb = &tb_hash[h];
 222     for(;;) {
 223         tb = *ptb;
 224         if (!tb)
 225             break;
 226         if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
 227             return tb;
 228         ptb = &tb->hash_next;
 229     }
 230     *pptb = ptb;
 231     return NULL;
 232 }
 233
 234
 235 #if defined(USE_DIRECT_JUMP)
 236
 237 #if defined(__powerpc__)
 238 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 239 {
 240     uint32_t val, *ptr;
 241
 242     /* patch the branch destination */
 243     ptr = (uint32_t *)jmp_addr;
 244     val = *ptr;
 245     val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
 246     *ptr = val;
 247     /* flush icache */
 248     asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
 249     asm volatile ("sync" : : : "memory");
 250     asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
 251     asm volatile ("sync" : : : "memory");
 252     asm volatile ("isync" : : : "memory");
 253 }
 254 #elif defined(__i386__)
 255 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 256 {
 257     /* patch the branch destination */
 258     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 259     /* no need to flush icache explicitely */
 260 }
 261 #endif
 262
 263 static inline void tb_set_jmp_target(TranslationBlock *tb,
 264                                      int n, unsigned long addr)
 265 {
 266     unsigned long offset;
 267
 268     offset = tb->tb_jmp_offset[n];
 269     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 270     offset = tb->tb_jmp_offset[n + 2];
 271     if (offset != 0xffff)
 272         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 273 }
 274
 275 #else
 276
 277 /* set the jump target */
 278 static inline void tb_set_jmp_target(TranslationBlock *tb,
 279                                      int n, unsigned long addr)
 280 {
 281     tb->tb_next[n] = addr;
 282 }
 283
 284 #endif
 285
 286 static inline void tb_add_jump(TranslationBlock *tb, int n,
 287                                TranslationBlock *tb_next)
 288 {
 289     /* NOTE: this test is only needed for thread safety */
 290     if (!tb->jmp_next[n]) {
 291         /* patch the native jump address */
 292         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 293
 294         /* add in TB jmp circular list */
 295         tb->jmp_next[n] = tb_next->jmp_first;
 296         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 297     }
 298 }
 299
 300 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 301
 302 #ifndef offsetof
 303 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 304 #endif
 305
 306 #if defined(_WIN32)
 307 #define ASM_DATA_SECTION ".section \".data\"\n"
 308 #define ASM_PREVIOUS_SECTION ".section .text\n"
 309 #elif defined(__APPLE__)
 310 #define ASM_DATA_SECTION ".data\n"
 311 #define ASM_PREVIOUS_SECTION ".text\n"
 312 #define ASM_NAME(x) "_" #x
 313 #else
 314 #define ASM_DATA_SECTION ".section \".data\"\n"
 315 #define ASM_PREVIOUS_SECTION ".previous\n"
 316 #define ASM_NAME(x) stringify(x)
 317 #endif
 318
 319 #if defined(__powerpc__)
 320
 321 /* we patch the jump instruction directly */
 322 #define JUMP_TB(opname, tbparam, n, eip)\
 323 do {\
 324     asm volatile (ASM_DATA_SECTION\
 325                   ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
 326                   ".long 1f\n"\
 327                   ASM_PREVIOUS_SECTION \
 328                   "b " ASM_NAME(__op_jmp) #n "\n"\
 329                   "1:\n");\
 330     T0 = (long)(tbparam) + (n);\
 331     EIP = eip;\
 332     EXIT_TB();\
 333 } while (0)
 334
 335 #define JUMP_TB2(opname, tbparam, n)\
 336 do {\
 337     asm volatile ("b " ASM_NAME(__op_jmp) #n "\n");\
 338 } while (0)
 339
 340 #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
 341
 342 /* we patch the jump instruction directly */
 343 #define JUMP_TB(opname, tbparam, n, eip)\
 344 do {\
 345     asm volatile (".section .data\n"\
 346                   ASM_NAME(__op_label) #n "." ASM_NAME(opname) ":\n"\
 347                   ".long 1f\n"\
 348                   ASM_PREVIOUS_SECTION \
 349                   "jmp " ASM_NAME(__op_jmp) #n "\n"\
 350                   "1:\n");\
 351     T0 = (long)(tbparam) + (n);\
 352     EIP = eip;\
 353     EXIT_TB();\
 354 } while (0)
 355
 356 #define JUMP_TB2(opname, tbparam, n)\
 357 do {\
 358     asm volatile ("jmp " ASM_NAME(__op_jmp) #n "\n");\
 359 } while (0)
 360
 361 #else
 362
 363 /* jump to next block operations (more portable code, does not need
 364    cache flushing, but slower because of indirect jump) */
 365 #define JUMP_TB(opname, tbparam, n, eip)\
 366 do {\
 367     static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
 368     static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
 369     goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
 370 label ## n:\
 371     T0 = (long)(tbparam) + (n);\
 372     EIP = eip;\
 373 dummy_label ## n:\
 374     EXIT_TB();\
 375 } while (0)
 376
 377 /* second jump to same destination 'n' */
 378 #define JUMP_TB2(opname, tbparam, n)\
 379 do {\
 380     goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
 381 } while (0)
 382
 383 #endif
 384
 385 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 386 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 387 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 388
 389 #ifdef __powerpc__
 390 static inline int testandset (int *p)
 391 {
 392     int ret;
 393     __asm__ __volatile__ (
 394                           "0:    lwarx %0,0,%1\n"
 395                           "      xor. %0,%3,%0\n"
 396                           "      bne 1f\n"
 397                           "      stwcx. %2,0,%1\n"
 398                           "      bne- 0b\n"
 399                           "1:    "
 400                           : "=&r" (ret)
 401                           : "r" (p), "r" (1), "r" (0)
 402                           : "cr0", "memory");
 403     return ret;
 404 }
 405 #endif
 406
 407 #ifdef __i386__
 408 static inline int testandset (int *p)
 409 {
 410     char ret;
 411     long int readval;
 412
 413     __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
 414                           : "=q" (ret), "=m" (*p), "=a" (readval)
 415                           : "r" (1), "m" (*p), "a" (0)
 416                           : "memory");
 417     return ret;
 418 }
 419 #endif
 420
 421 #ifdef __x86_64__
 422 static inline int testandset (int *p)
 423 {
 424     char ret;
 425     int readval;
 426
 427     __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
 428                           : "=q" (ret), "=m" (*p), "=a" (readval)
 429                           : "r" (1), "m" (*p), "a" (0)
 430                           : "memory");
 431     return ret;
 432 }
 433 #endif
 434
 435 #ifdef __s390__
 436 static inline int testandset (int *p)
 437 {
 438     int ret;
 439
 440     __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
 441                           "   jl    0b"
 442                           : "=&d" (ret)
 443                           : "r" (1), "a" (p), "0" (*p)
 444                           : "cc", "memory" );
 445     return ret;
 446 }
 447 #endif
 448
 449 #ifdef __alpha__
 450 static inline int testandset (int *p)
 451 {
 452     int ret;
 453     unsigned long one;
 454
 455     __asm__ __volatile__ ("0:   mov 1,%2\n"
 456                           "     ldl_l %0,%1\n"
 457                           "     stl_c %2,%1\n"
 458                           "     beq %2,1f\n"
 459                           ".subsection 2\n"
 460                           "1:   br 0b\n"
 461                           ".previous"
 462                           : "=r" (ret), "=m" (*p), "=r" (one)
 463                           : "m" (*p));
 464     return ret;
 465 }
 466 #endif
 467
 468 #ifdef __sparc__
 469 static inline int testandset (int *p)
 470 {
 471         int ret;
 472
 473         __asm__ __volatile__("ldstub    [%1], %0"
 474                              : "=r" (ret)
 475                              : "r" (p)
 476                              : "memory");
 477
 478         return (ret ? 1 : 0);
 479 }
 480 #endif
 481
 482 #ifdef __arm__
 483 static inline int testandset (int *spinlock)
 484 {
 485     register unsigned int ret;
 486     __asm__ __volatile__("swp %0, %1, [%2]"
 487                          : "=r"(ret)
 488                          : "0"(1), "r"(spinlock));
 489
 490     return ret;
 491 }
 492 #endif
 493
 494 #ifdef __mc68000
 495 static inline int testandset (int *p)
 496 {
 497     char ret;
 498     __asm__ __volatile__("tas %1; sne %0"
 499                          : "=r" (ret)
 500                          : "m" (p)
 501                          : "cc","memory");
 502     return ret == 0;
 503 }
 504 #endif
 505
 506 typedef int spinlock_t;
 507
 508 #define SPIN_LOCK_UNLOCKED 0
 509
 510 #if defined(CONFIG_USER_ONLY)
 511 static inline void spin_lock(spinlock_t *lock)
 512 {
 513     while (testandset(lock));
 514 }
 515
 516 static inline void spin_unlock(spinlock_t *lock)
 517 {
 518     *lock = 0;
 519 }
 520
 521 static inline int spin_trylock(spinlock_t *lock)
 522 {
 523     return !testandset(lock);
 524 }
 525 #else
 526 static inline void spin_lock(spinlock_t *lock)
 527 {
 528 }
 529
 530 static inline void spin_unlock(spinlock_t *lock)
 531 {
 532 }
 533
 534 static inline int spin_trylock(spinlock_t *lock)
 535 {
 536     return 1;
 537 }
 538 #endif
 539
 540 extern spinlock_t tb_lock;
 541
 542 extern int tb_invalidated_flag;
 543
 544 #if (defined(TARGET_I386) || defined(TARGET_PPC)) && \
 545     !defined(CONFIG_USER_ONLY)
 546
 547 void tlb_fill(unsigned long addr, int is_write, int is_user,
 548               void *retaddr);
 549
 550 #define ACCESS_TYPE 3
 551 #define MEMSUFFIX _code
 552 #define env cpu_single_env
 553
 554 #define DATA_SIZE 1
 555 #include "softmmu_header.h"
 556
 557 #define DATA_SIZE 2
 558 #include "softmmu_header.h"
 559
 560 #define DATA_SIZE 4
 561 #include "softmmu_header.h"
 562
 563 #undef ACCESS_TYPE
 564 #undef MEMSUFFIX
 565 #undef env
 566
 567 #endif
 568
 569 #if defined(CONFIG_USER_ONLY)
 570 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 571 {
 572     return addr;
 573 }
 574 #else
 575 /* NOTE: this function can trigger an exception */
 576 /* NOTE2: the returned address is not exactly the physical address: it
 577    is the offset relative to phys_ram_base */
 578 /* XXX: i386 target specific */
 579 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 580 {
 581     int is_user, index;
 582
 583     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 584 #if defined(TARGET_I386)
 585     is_user = ((env->hflags & HF_CPL_MASK) == 3);
 586 #elif defined (TARGET_PPC)
 587     is_user = msr_pr;
 588 #else
 589 #error "Unimplemented !"
 590 #endif
 591     if (__builtin_expect(env->tlb_read[is_user][index].address !=
 592                          (addr & TARGET_PAGE_MASK), 0)) {
 593 #if defined (TARGET_PPC)
 594         env->access_type = ACCESS_CODE;
 595         ldub_code((void *)addr);
 596         env->access_type = ACCESS_INT;
 597 #else
 598         ldub_code((void *)addr);
 599 #endif
 600     }
 601     return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
 602 }
 603 #endif