exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 /* is_jmp field values */
  25 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  26 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  27 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  28 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  29
  30 struct TranslationBlock;
  31
  32 /* XXX: make safe guess about sizes */
  33 #define MAX_OP_PER_INSTR 32
  34 /* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
  35 #define MAX_OPC_PARAM 10
  36 #define OPC_BUF_SIZE 512
  37 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  38
  39 /* Maximum size a TCG op can expand to.  This is complicated because a
  40    single op may require several host instructions and regirster reloads.
  41    For now take a wild guess at 128 bytes, which should allow at least
  42    a couple of fixup instructions per argument.  */
  43 #define TCG_MAX_OP_SIZE 128
  44
  45 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  46
  47 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  48 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  49 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  50 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  51 extern target_ulong gen_opc_jump_pc[2];
  52 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
  53
  54 typedef void (GenOpFunc)(void);
  55 typedef void (GenOpFunc1)(long);
  56 typedef void (GenOpFunc2)(long, long);
  57 typedef void (GenOpFunc3)(long, long, long);
  58
  59 #if defined(TARGET_I386)
  60
  61 void optimize_flags_init(void);
  62
  63 #endif
  64
  65 extern FILE *logfile;
  66 extern int loglevel;
  67
  68 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  69 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  70 unsigned long code_gen_max_block_size(void);
  71 void cpu_gen_init(void);
  72 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  73                  int *gen_code_size_ptr);
  74 int cpu_restore_state(struct TranslationBlock *tb,
  75                       CPUState *env, unsigned long searched_pc,
  76                       void *puc);
  77 int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
  78                       int max_code_size, int *gen_code_size_ptr);
  79 int cpu_restore_state_copy(struct TranslationBlock *tb,
  80                            CPUState *env, unsigned long searched_pc,
  81                            void *puc);
  82 void cpu_resume_from_signal(CPUState *env1, void *puc);
  83 void cpu_exec_init(CPUState *env);
  84 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  85 void tb_invalidate_phys_page_range(target_phys_addr_t start, target_phys_addr_t end,
  86                                    int is_cpu_write_access);
  87 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  88 void tlb_flush_page(CPUState *env, target_ulong addr);
  89 void tlb_flush(CPUState *env, int flush_global);
  90 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
  91                       target_phys_addr_t paddr, int prot,
  92                       int mmu_idx, int is_softmmu);
  93 static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
  94                                target_phys_addr_t paddr, int prot,
  95                                int mmu_idx, int is_softmmu)
  96 {
  97     if (prot & PAGE_READ)
  98         prot |= PAGE_EXEC;
  99     return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
 100 }
 101
 102 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 103
 104 #define CODE_GEN_PHYS_HASH_BITS     15
 105 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 106
 107 /* maximum total translate dcode allocated */
 108
 109 /* NOTE: the translated code area cannot be too big because on some
 110    archs the range of "fast" function calls is limited. Here is a
 111    summary of the ranges:
 112
 113    i386  : signed 32 bits
 114    arm   : signed 26 bits
 115    ppc   : signed 24 bits
 116    sparc : signed 32 bits
 117    alpha : signed 23 bits
 118 */
 119
 120 #if defined(__alpha__)
 121 #define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
 122 #elif defined(__ia64)
 123 #define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)      /* range of addl */
 124 #elif defined(__powerpc__)
 125 #define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
 126 #else
 127 /* XXX: make it dynamic on x86 */
 128 #define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
 129 #endif
 130
 131 //#define CODE_GEN_BUFFER_SIZE     (128 * 1024)
 132
 133 /* estimated block size for TB allocation */
 134 /* XXX: use a per code average code fragment size and modulate it
 135    according to the host CPU */
 136 #if defined(CONFIG_SOFTMMU)
 137 #define CODE_GEN_AVG_BLOCK_SIZE 128
 138 #else
 139 #define CODE_GEN_AVG_BLOCK_SIZE 64
 140 #endif
 141
 142 #define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
 143
 144 #if defined(__powerpc__) || defined(__x86_64__)
 145 #define USE_DIRECT_JUMP
 146 #endif
 147 #if defined(__i386__) && !defined(_WIN32)
 148 #define USE_DIRECT_JUMP
 149 #endif
 150
 151 typedef struct TranslationBlock {
 152     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 153     target_ulong cs_base; /* CS base for this block */
 154     uint64_t flags; /* flags defining in which context the code was generated */
 155     uint16_t size;      /* size of target code for this block (1 <=
 156                            size <= TARGET_PAGE_SIZE) */
 157     uint16_t cflags;    /* compile flags */
 158 #define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
 159 #define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
 160 #define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
 161 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
 162
 163     uint8_t *tc_ptr;    /* pointer to the translated code */
 164     /* next matching tb for physical address. */
 165     struct TranslationBlock *phys_hash_next;
 166     /* first and second physical page containing code. The lower bit
 167        of the pointer tells the index in page_next[] */
 168     struct TranslationBlock *page_next[2];
 169     target_ulong page_addr[2];
 170
 171     /* the following data are used to directly call another TB from
 172        the code of this one. */
 173     uint16_t tb_next_offset[2]; /* offset of original jump target */
 174 #ifdef USE_DIRECT_JUMP
 175     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 176 #else
 177     unsigned long tb_next[2]; /* address of jump generated code */
 178 #endif
 179     /* list of TBs jumping to this one. This is a circular list using
 180        the two least significant bits of the pointers to tell what is
 181        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 182        jmp_first */
 183     struct TranslationBlock *jmp_next[2];
 184     struct TranslationBlock *jmp_first;
 185 } TranslationBlock;
 186
 187 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 188 {
 189     target_ulong tmp;
 190     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 191     return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
 192 }
 193
 194 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 195 {
 196     target_ulong tmp;
 197     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 198     return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
 199             (tmp & TB_JMP_ADDR_MASK));
 200 }
 201
 202 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 203 {
 204     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 205 }
 206
 207 TranslationBlock *tb_alloc(target_ulong pc);
 208 void tb_flush(CPUState *env);
 209 void tb_link_phys(TranslationBlock *tb,
 210                   target_ulong phys_pc, target_ulong phys_page2);
 211
 212 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 213
 214 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 215 extern uint8_t *code_gen_ptr;
 216
 217 #if defined(USE_DIRECT_JUMP)
 218
 219 #if defined(__powerpc__)
 220 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 221 {
 222     uint32_t val, *ptr;
 223
 224     /* patch the branch destination */
 225     ptr = (uint32_t *)jmp_addr;
 226     val = *ptr;
 227     val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
 228     *ptr = val;
 229     /* flush icache */
 230     asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
 231     asm volatile ("sync" : : : "memory");
 232     asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
 233     asm volatile ("sync" : : : "memory");
 234     asm volatile ("isync" : : : "memory");
 235 }
 236 #elif defined(__i386__) || defined(__x86_64__)
 237 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 238 {
 239     /* patch the branch destination */
 240     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 241     /* no need to flush icache explicitely */
 242 }
 243 #endif
 244
 245 static inline void tb_set_jmp_target(TranslationBlock *tb,
 246                                      int n, unsigned long addr)
 247 {
 248     unsigned long offset;
 249
 250     offset = tb->tb_jmp_offset[n];
 251     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 252     offset = tb->tb_jmp_offset[n + 2];
 253     if (offset != 0xffff)
 254         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 255 }
 256
 257 #else
 258
 259 /* set the jump target */
 260 static inline void tb_set_jmp_target(TranslationBlock *tb,
 261                                      int n, unsigned long addr)
 262 {
 263     tb->tb_next[n] = addr;
 264 }
 265
 266 #endif
 267
 268 static inline void tb_add_jump(TranslationBlock *tb, int n,
 269                                TranslationBlock *tb_next)
 270 {
 271     /* NOTE: this test is only needed for thread safety */
 272     if (!tb->jmp_next[n]) {
 273         /* patch the native jump address */
 274         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 275
 276         /* add in TB jmp circular list */
 277         tb->jmp_next[n] = tb_next->jmp_first;
 278         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 279     }
 280 }
 281
 282 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 283
 284 #ifndef offsetof
 285 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 286 #endif
 287
 288 #if defined(_WIN32)
 289 #define ASM_DATA_SECTION ".section \".data\"\n"
 290 #define ASM_PREVIOUS_SECTION ".section .text\n"
 291 #elif defined(__APPLE__)
 292 #define ASM_DATA_SECTION ".data\n"
 293 #define ASM_PREVIOUS_SECTION ".text\n"
 294 #else
 295 #define ASM_DATA_SECTION ".section \".data\"\n"
 296 #define ASM_PREVIOUS_SECTION ".previous\n"
 297 #endif
 298
 299 #define ASM_OP_LABEL_NAME(n, opname) \
 300     ASM_NAME(__op_label) #n "." ASM_NAME(opname)
 301
 302 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 303 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 304 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 305
 306 #if defined(__hppa__)
 307
 308 typedef int spinlock_t[4];
 309
 310 #define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 }
 311
 312 static inline void resetlock (spinlock_t *p)
 313 {
 314     (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1;
 315 }
 316
 317 #else
 318
 319 typedef int spinlock_t;
 320
 321 #define SPIN_LOCK_UNLOCKED 0
 322
 323 static inline void resetlock (spinlock_t *p)
 324 {
 325     *p = SPIN_LOCK_UNLOCKED;
 326 }
 327
 328 #endif
 329
 330 #if defined(__powerpc__)
 331 static inline int testandset (int *p)
 332 {
 333     int ret;
 334     __asm__ __volatile__ (
 335                           "0:    lwarx %0,0,%1\n"
 336                           "      xor. %0,%3,%0\n"
 337                           "      bne 1f\n"
 338                           "      stwcx. %2,0,%1\n"
 339                           "      bne- 0b\n"
 340                           "1:    "
 341                           : "=&r" (ret)
 342                           : "r" (p), "r" (1), "r" (0)
 343                           : "cr0", "memory");
 344     return ret;
 345 }
 346 #elif defined(__i386__)
 347 static inline int testandset (int *p)
 348 {
 349     long int readval = 0;
 350
 351     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 352                           : "+m" (*p), "+a" (readval)
 353                           : "r" (1)
 354                           : "cc");
 355     return readval;
 356 }
 357 #elif defined(__x86_64__)
 358 static inline int testandset (int *p)
 359 {
 360     long int readval = 0;
 361
 362     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 363                           : "+m" (*p), "+a" (readval)
 364                           : "r" (1)
 365                           : "cc");
 366     return readval;
 367 }
 368 #elif defined(__s390__)
 369 static inline int testandset (int *p)
 370 {
 371     int ret;
 372
 373     __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
 374                           "   jl    0b"
 375                           : "=&d" (ret)
 376                           : "r" (1), "a" (p), "0" (*p)
 377                           : "cc", "memory" );
 378     return ret;
 379 }
 380 #elif defined(__alpha__)
 381 static inline int testandset (int *p)
 382 {
 383     int ret;
 384     unsigned long one;
 385
 386     __asm__ __volatile__ ("0:   mov 1,%2\n"
 387                           "     ldl_l %0,%1\n"
 388                           "     stl_c %2,%1\n"
 389                           "     beq %2,1f\n"
 390                           ".subsection 2\n"
 391                           "1:   br 0b\n"
 392                           ".previous"
 393                           : "=r" (ret), "=m" (*p), "=r" (one)
 394                           : "m" (*p));
 395     return ret;
 396 }
 397 #elif defined(__sparc__)
 398 static inline int testandset (int *p)
 399 {
 400         int ret;
 401
 402         __asm__ __volatile__("ldstub    [%1], %0"
 403                              : "=r" (ret)
 404                              : "r" (p)
 405                              : "memory");
 406
 407         return (ret ? 1 : 0);
 408 }
 409 #elif defined(__arm__)
 410 static inline int testandset (int *spinlock)
 411 {
 412     register unsigned int ret;
 413     __asm__ __volatile__("swp %0, %1, [%2]"
 414                          : "=r"(ret)
 415                          : "0"(1), "r"(spinlock));
 416
 417     return ret;
 418 }
 419 #elif defined(__mc68000)
 420 static inline int testandset (int *p)
 421 {
 422     char ret;
 423     __asm__ __volatile__("tas %1; sne %0"
 424                          : "=r" (ret)
 425                          : "m" (p)
 426                          : "cc","memory");
 427     return ret;
 428 }
 429 #elif defined(__hppa__)
 430
 431 /* Because malloc only guarantees 8-byte alignment for malloc'd data,
 432    and GCC only guarantees 8-byte alignment for stack locals, we can't
 433    be assured of 16-byte alignment for atomic lock data even if we
 434    specify "__attribute ((aligned(16)))" in the type declaration.  So,
 435    we use a struct containing an array of four ints for the atomic lock
 436    type and dynamically select the 16-byte aligned int from the array
 437    for the semaphore.  */
 438 #define __PA_LDCW_ALIGNMENT 16
 439 static inline void *ldcw_align (void *p) {
 440     unsigned long a = (unsigned long)p;
 441     a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1);
 442     return (void *)a;
 443 }
 444
 445 static inline int testandset (spinlock_t *p)
 446 {
 447     unsigned int ret;
 448     p = ldcw_align(p);
 449     __asm__ __volatile__("ldcw 0(%1),%0"
 450                          : "=r" (ret)
 451                          : "r" (p)
 452                          : "memory" );
 453     return !ret;
 454 }
 455
 456 #elif defined(__ia64)
 457
 458 #include <ia64intrin.h>
 459
 460 static inline int testandset (int *p)
 461 {
 462     return __sync_lock_test_and_set (p, 1);
 463 }
 464 #elif defined(__mips__)
 465 static inline int testandset (int *p)
 466 {
 467     int ret;
 468
 469     __asm__ __volatile__ (
 470         "       .set push               \n"
 471         "       .set noat               \n"
 472         "       .set mips2              \n"
 473         "1:     li      $1, 1           \n"
 474         "       ll      %0, %1          \n"
 475         "       sc      $1, %1          \n"
 476         "       beqz    $1, 1b          \n"
 477         "       .set pop                "
 478         : "=r" (ret), "+R" (*p)
 479         :
 480         : "memory");
 481
 482     return ret;
 483 }
 484 #else
 485 #error unimplemented CPU support
 486 #endif
 487
 488 #if defined(CONFIG_USER_ONLY)
 489 static inline void spin_lock(spinlock_t *lock)
 490 {
 491     while (testandset(lock));
 492 }
 493
 494 static inline void spin_unlock(spinlock_t *lock)
 495 {
 496     resetlock(lock);
 497 }
 498
 499 static inline int spin_trylock(spinlock_t *lock)
 500 {
 501     return !testandset(lock);
 502 }
 503 #else
 504 static inline void spin_lock(spinlock_t *lock)
 505 {
 506 }
 507
 508 static inline void spin_unlock(spinlock_t *lock)
 509 {
 510 }
 511
 512 static inline int spin_trylock(spinlock_t *lock)
 513 {
 514     return 1;
 515 }
 516 #endif
 517
 518 extern spinlock_t tb_lock;
 519
 520 extern int tb_invalidated_flag;
 521
 522 #if !defined(CONFIG_USER_ONLY)
 523
 524 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 525               void *retaddr);
 526
 527 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 528 #define MEMSUFFIX _code
 529 #define env cpu_single_env
 530
 531 #define DATA_SIZE 1
 532 #include "softmmu_header.h"
 533
 534 #define DATA_SIZE 2
 535 #include "softmmu_header.h"
 536
 537 #define DATA_SIZE 4
 538 #include "softmmu_header.h"
 539
 540 #define DATA_SIZE 8
 541 #include "softmmu_header.h"
 542
 543 #undef ACCESS_TYPE
 544 #undef MEMSUFFIX
 545 #undef env
 546
 547 #endif
 548
 549 #if defined(CONFIG_USER_ONLY)
 550 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 551 {
 552     return addr;
 553 }
 554 #else
 555 /* NOTE: this function can trigger an exception */
 556 /* NOTE2: the returned address is not exactly the physical address: it
 557    is the offset relative to phys_ram_base */
 558 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 559 {
 560     int mmu_idx, index, pd;
 561
 562     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 563     mmu_idx = cpu_mmu_index(env);
 564     if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
 565                          (addr & TARGET_PAGE_MASK), 0)) {
 566         ldub_code(addr);
 567     }
 568     pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
 569     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 570 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 571         do_unassigned_access(addr, 0, 1, 0);
 572 #else
 573         cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 574 #endif
 575     }
 576     return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
 577 }
 578 #endif
 579
 580 #ifdef USE_KQEMU
 581 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
 582
 583 int kqemu_init(CPUState *env);
 584 int kqemu_cpu_exec(CPUState *env);
 585 void kqemu_flush_page(CPUState *env, target_ulong addr);
 586 void kqemu_flush(CPUState *env, int global);
 587 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
 588 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
 589 void kqemu_cpu_interrupt(CPUState *env);
 590 void kqemu_record_dump(void);
 591
 592 static inline int kqemu_is_ok(CPUState *env)
 593 {
 594     return(env->kqemu_enabled &&
 595            (env->cr[0] & CR0_PE_MASK) &&
 596            !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
 597            (env->eflags & IF_MASK) &&
 598            !(env->eflags & VM_MASK) &&
 599            (env->kqemu_enabled == 2 ||
 600             ((env->hflags & HF_CPL_MASK) == 3 &&
 601              (env->eflags & IOPL_MASK) != IOPL_MASK)));
 602 }
 603
 604 #endif