exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 /* is_jmp field values */
  25 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  26 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  27 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  28 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  29
  30 struct TranslationBlock;
  31
  32 /* XXX: make safe guess about sizes */
  33 #define MAX_OP_PER_INSTR 32
  34 /* A Call op needs up to 6 + 2N parameters (N = number of arguments).  */
  35 #define MAX_OPC_PARAM 10
  36 #define OPC_BUF_SIZE 512
  37 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  38
  39 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  40
  41 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  42 extern target_ulong gen_opc_npc[OPC_BUF_SIZE];
  43 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  44 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  45 extern target_ulong gen_opc_jump_pc[2];
  46 extern uint32_t gen_opc_hflags[OPC_BUF_SIZE];
  47
  48 typedef void (GenOpFunc)(void);
  49 typedef void (GenOpFunc1)(long);
  50 typedef void (GenOpFunc2)(long, long);
  51 typedef void (GenOpFunc3)(long, long, long);
  52
  53 #if defined(TARGET_I386)
  54
  55 void optimize_flags_init(void);
  56
  57 #endif
  58
  59 extern FILE *logfile;
  60 extern int loglevel;
  61
  62 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  63 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  64 unsigned long code_gen_max_block_size(void);
  65 void cpu_gen_init(void);
  66 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  67                  int *gen_code_size_ptr);
  68 int cpu_restore_state(struct TranslationBlock *tb,
  69                       CPUState *env, unsigned long searched_pc,
  70                       void *puc);
  71 int cpu_gen_code_copy(CPUState *env, struct TranslationBlock *tb,
  72                       int max_code_size, int *gen_code_size_ptr);
  73 int cpu_restore_state_copy(struct TranslationBlock *tb,
  74                            CPUState *env, unsigned long searched_pc,
  75                            void *puc);
  76 void cpu_resume_from_signal(CPUState *env1, void *puc);
  77 void cpu_exec_init(CPUState *env);
  78 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
  79 void tb_invalidate_phys_page_range(target_ulong start, target_ulong end,
  80                                    int is_cpu_write_access);
  81 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  82 void tlb_flush_page(CPUState *env, target_ulong addr);
  83 void tlb_flush(CPUState *env, int flush_global);
  84 int tlb_set_page_exec(CPUState *env, target_ulong vaddr,
  85                       target_phys_addr_t paddr, int prot,
  86                       int mmu_idx, int is_softmmu);
  87 static inline int tlb_set_page(CPUState *env, target_ulong vaddr,
  88                                target_phys_addr_t paddr, int prot,
  89                                int mmu_idx, int is_softmmu)
  90 {
  91     if (prot & PAGE_READ)
  92         prot |= PAGE_EXEC;
  93     return tlb_set_page_exec(env, vaddr, paddr, prot, mmu_idx, is_softmmu);
  94 }
  95
  96 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
  97
  98 #define CODE_GEN_PHYS_HASH_BITS     15
  99 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 100
 101 /* maximum total translate dcode allocated */
 102
 103 /* NOTE: the translated code area cannot be too big because on some
 104    archs the range of "fast" function calls is limited. Here is a
 105    summary of the ranges:
 106
 107    i386  : signed 32 bits
 108    arm   : signed 26 bits
 109    ppc   : signed 24 bits
 110    sparc : signed 32 bits
 111    alpha : signed 23 bits
 112 */
 113
 114 #if defined(__alpha__)
 115 #define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
 116 #elif defined(__ia64)
 117 #define CODE_GEN_BUFFER_SIZE     (4 * 1024 * 1024)      /* range of addl */
 118 #elif defined(__powerpc__)
 119 #define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
 120 #else
 121 /* XXX: make it dynamic on x86 */
 122 #define CODE_GEN_BUFFER_SIZE     (16 * 1024 * 1024)
 123 #endif
 124
 125 //#define CODE_GEN_BUFFER_SIZE     (128 * 1024)
 126
 127 /* estimated block size for TB allocation */
 128 /* XXX: use a per code average code fragment size and modulate it
 129    according to the host CPU */
 130 #if defined(CONFIG_SOFTMMU)
 131 #define CODE_GEN_AVG_BLOCK_SIZE 128
 132 #else
 133 #define CODE_GEN_AVG_BLOCK_SIZE 64
 134 #endif
 135
 136 #define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
 137
 138 #if defined(__powerpc__) || defined(__x86_64__)
 139 #define USE_DIRECT_JUMP
 140 #endif
 141 #if defined(__i386__) && !defined(_WIN32)
 142 #define USE_DIRECT_JUMP
 143 #endif
 144
 145 typedef struct TranslationBlock {
 146     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 147     target_ulong cs_base; /* CS base for this block */
 148     uint64_t flags; /* flags defining in which context the code was generated */
 149     uint16_t size;      /* size of target code for this block (1 <=
 150                            size <= TARGET_PAGE_SIZE) */
 151     uint16_t cflags;    /* compile flags */
 152 #define CF_CODE_COPY   0x0001 /* block was generated in code copy mode */
 153 #define CF_TB_FP_USED  0x0002 /* fp ops are used in the TB */
 154 #define CF_FP_USED     0x0004 /* fp ops are used in the TB or in a chained TB */
 155 #define CF_SINGLE_INSN 0x0008 /* compile only a single instruction */
 156
 157     uint8_t *tc_ptr;    /* pointer to the translated code */
 158     /* next matching tb for physical address. */
 159     struct TranslationBlock *phys_hash_next;
 160     /* first and second physical page containing code. The lower bit
 161        of the pointer tells the index in page_next[] */
 162     struct TranslationBlock *page_next[2];
 163     target_ulong page_addr[2];
 164
 165     /* the following data are used to directly call another TB from
 166        the code of this one. */
 167     uint16_t tb_next_offset[2]; /* offset of original jump target */
 168 #ifdef USE_DIRECT_JUMP
 169     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 170 #else
 171     unsigned long tb_next[2]; /* address of jump generated code */
 172 #endif
 173     /* list of TBs jumping to this one. This is a circular list using
 174        the two least significant bits of the pointers to tell what is
 175        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 176        jmp_first */
 177     struct TranslationBlock *jmp_next[2];
 178     struct TranslationBlock *jmp_first;
 179 } TranslationBlock;
 180
 181 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 182 {
 183     target_ulong tmp;
 184     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 185     return (tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK;
 186 }
 187
 188 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 189 {
 190     target_ulong tmp;
 191     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 192     return (((tmp >> TB_JMP_PAGE_BITS) & TB_JMP_PAGE_MASK) |
 193             (tmp & TB_JMP_ADDR_MASK));
 194 }
 195
 196 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 197 {
 198     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 199 }
 200
 201 TranslationBlock *tb_alloc(target_ulong pc);
 202 void tb_flush(CPUState *env);
 203 void tb_link_phys(TranslationBlock *tb,
 204                   target_ulong phys_pc, target_ulong phys_page2);
 205
 206 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 207
 208 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 209 extern uint8_t *code_gen_ptr;
 210
 211 #if defined(USE_DIRECT_JUMP)
 212
 213 #if defined(__powerpc__)
 214 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 215 {
 216     uint32_t val, *ptr;
 217
 218     /* patch the branch destination */
 219     ptr = (uint32_t *)jmp_addr;
 220     val = *ptr;
 221     val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
 222     *ptr = val;
 223     /* flush icache */
 224     asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
 225     asm volatile ("sync" : : : "memory");
 226     asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
 227     asm volatile ("sync" : : : "memory");
 228     asm volatile ("isync" : : : "memory");
 229 }
 230 #elif defined(__i386__) || defined(__x86_64__)
 231 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 232 {
 233     /* patch the branch destination */
 234     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 235     /* no need to flush icache explicitely */
 236 }
 237 #endif
 238
 239 static inline void tb_set_jmp_target(TranslationBlock *tb,
 240                                      int n, unsigned long addr)
 241 {
 242     unsigned long offset;
 243
 244     offset = tb->tb_jmp_offset[n];
 245     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 246     offset = tb->tb_jmp_offset[n + 2];
 247     if (offset != 0xffff)
 248         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 249 }
 250
 251 #else
 252
 253 /* set the jump target */
 254 static inline void tb_set_jmp_target(TranslationBlock *tb,
 255                                      int n, unsigned long addr)
 256 {
 257     tb->tb_next[n] = addr;
 258 }
 259
 260 #endif
 261
 262 static inline void tb_add_jump(TranslationBlock *tb, int n,
 263                                TranslationBlock *tb_next)
 264 {
 265     /* NOTE: this test is only needed for thread safety */
 266     if (!tb->jmp_next[n]) {
 267         /* patch the native jump address */
 268         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 269
 270         /* add in TB jmp circular list */
 271         tb->jmp_next[n] = tb_next->jmp_first;
 272         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 273     }
 274 }
 275
 276 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 277
 278 #ifndef offsetof
 279 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 280 #endif
 281
 282 #if defined(_WIN32)
 283 #define ASM_DATA_SECTION ".section \".data\"\n"
 284 #define ASM_PREVIOUS_SECTION ".section .text\n"
 285 #elif defined(__APPLE__)
 286 #define ASM_DATA_SECTION ".data\n"
 287 #define ASM_PREVIOUS_SECTION ".text\n"
 288 #else
 289 #define ASM_DATA_SECTION ".section \".data\"\n"
 290 #define ASM_PREVIOUS_SECTION ".previous\n"
 291 #endif
 292
 293 #define ASM_OP_LABEL_NAME(n, opname) \
 294     ASM_NAME(__op_label) #n "." ASM_NAME(opname)
 295
 296 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 297 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 298 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 299
 300 #if defined(__hppa__)
 301
 302 typedef int spinlock_t[4];
 303
 304 #define SPIN_LOCK_UNLOCKED { 1, 1, 1, 1 }
 305
 306 static inline void resetlock (spinlock_t *p)
 307 {
 308     (*p)[0] = (*p)[1] = (*p)[2] = (*p)[3] = 1;
 309 }
 310
 311 #else
 312
 313 typedef int spinlock_t;
 314
 315 #define SPIN_LOCK_UNLOCKED 0
 316
 317 static inline void resetlock (spinlock_t *p)
 318 {
 319     *p = SPIN_LOCK_UNLOCKED;
 320 }
 321
 322 #endif
 323
 324 #if defined(__powerpc__)
 325 static inline int testandset (int *p)
 326 {
 327     int ret;
 328     __asm__ __volatile__ (
 329                           "0:    lwarx %0,0,%1\n"
 330                           "      xor. %0,%3,%0\n"
 331                           "      bne 1f\n"
 332                           "      stwcx. %2,0,%1\n"
 333                           "      bne- 0b\n"
 334                           "1:    "
 335                           : "=&r" (ret)
 336                           : "r" (p), "r" (1), "r" (0)
 337                           : "cr0", "memory");
 338     return ret;
 339 }
 340 #elif defined(__i386__)
 341 static inline int testandset (int *p)
 342 {
 343     long int readval = 0;
 344
 345     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 346                           : "+m" (*p), "+a" (readval)
 347                           : "r" (1)
 348                           : "cc");
 349     return readval;
 350 }
 351 #elif defined(__x86_64__)
 352 static inline int testandset (int *p)
 353 {
 354     long int readval = 0;
 355
 356     __asm__ __volatile__ ("lock; cmpxchgl %2, %0"
 357                           : "+m" (*p), "+a" (readval)
 358                           : "r" (1)
 359                           : "cc");
 360     return readval;
 361 }
 362 #elif defined(__s390__)
 363 static inline int testandset (int *p)
 364 {
 365     int ret;
 366
 367     __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
 368                           "   jl    0b"
 369                           : "=&d" (ret)
 370                           : "r" (1), "a" (p), "0" (*p)
 371                           : "cc", "memory" );
 372     return ret;
 373 }
 374 #elif defined(__alpha__)
 375 static inline int testandset (int *p)
 376 {
 377     int ret;
 378     unsigned long one;
 379
 380     __asm__ __volatile__ ("0:   mov 1,%2\n"
 381                           "     ldl_l %0,%1\n"
 382                           "     stl_c %2,%1\n"
 383                           "     beq %2,1f\n"
 384                           ".subsection 2\n"
 385                           "1:   br 0b\n"
 386                           ".previous"
 387                           : "=r" (ret), "=m" (*p), "=r" (one)
 388                           : "m" (*p));
 389     return ret;
 390 }
 391 #elif defined(__sparc__)
 392 static inline int testandset (int *p)
 393 {
 394         int ret;
 395
 396         __asm__ __volatile__("ldstub    [%1], %0"
 397                              : "=r" (ret)
 398                              : "r" (p)
 399                              : "memory");
 400
 401         return (ret ? 1 : 0);
 402 }
 403 #elif defined(__arm__)
 404 static inline int testandset (int *spinlock)
 405 {
 406     register unsigned int ret;
 407     __asm__ __volatile__("swp %0, %1, [%2]"
 408                          : "=r"(ret)
 409                          : "0"(1), "r"(spinlock));
 410
 411     return ret;
 412 }
 413 #elif defined(__mc68000)
 414 static inline int testandset (int *p)
 415 {
 416     char ret;
 417     __asm__ __volatile__("tas %1; sne %0"
 418                          : "=r" (ret)
 419                          : "m" (p)
 420                          : "cc","memory");
 421     return ret;
 422 }
 423 #elif defined(__hppa__)
 424
 425 /* Because malloc only guarantees 8-byte alignment for malloc'd data,
 426    and GCC only guarantees 8-byte alignment for stack locals, we can't
 427    be assured of 16-byte alignment for atomic lock data even if we
 428    specify "__attribute ((aligned(16)))" in the type declaration.  So,
 429    we use a struct containing an array of four ints for the atomic lock
 430    type and dynamically select the 16-byte aligned int from the array
 431    for the semaphore.  */
 432 #define __PA_LDCW_ALIGNMENT 16
 433 static inline void *ldcw_align (void *p) {
 434     unsigned long a = (unsigned long)p;
 435     a = (a + __PA_LDCW_ALIGNMENT - 1) & ~(__PA_LDCW_ALIGNMENT - 1);
 436     return (void *)a;
 437 }
 438
 439 static inline int testandset (spinlock_t *p)
 440 {
 441     unsigned int ret;
 442     p = ldcw_align(p);
 443     __asm__ __volatile__("ldcw 0(%1),%0"
 444                          : "=r" (ret)
 445                          : "r" (p)
 446                          : "memory" );
 447     return !ret;
 448 }
 449
 450 #elif defined(__ia64)
 451
 452 #include <ia64intrin.h>
 453
 454 static inline int testandset (int *p)
 455 {
 456     return __sync_lock_test_and_set (p, 1);
 457 }
 458 #elif defined(__mips__)
 459 static inline int testandset (int *p)
 460 {
 461     int ret;
 462
 463     __asm__ __volatile__ (
 464         "       .set push               \n"
 465         "       .set noat               \n"
 466         "       .set mips2              \n"
 467         "1:     li      $1, 1           \n"
 468         "       ll      %0, %1          \n"
 469         "       sc      $1, %1          \n"
 470         "       beqz    $1, 1b          \n"
 471         "       .set pop                "
 472         : "=r" (ret), "+R" (*p)
 473         :
 474         : "memory");
 475
 476     return ret;
 477 }
 478 #else
 479 #error unimplemented CPU support
 480 #endif
 481
 482 #if defined(CONFIG_USER_ONLY)
 483 static inline void spin_lock(spinlock_t *lock)
 484 {
 485     while (testandset(lock));
 486 }
 487
 488 static inline void spin_unlock(spinlock_t *lock)
 489 {
 490     resetlock(lock);
 491 }
 492
 493 static inline int spin_trylock(spinlock_t *lock)
 494 {
 495     return !testandset(lock);
 496 }
 497 #else
 498 static inline void spin_lock(spinlock_t *lock)
 499 {
 500 }
 501
 502 static inline void spin_unlock(spinlock_t *lock)
 503 {
 504 }
 505
 506 static inline int spin_trylock(spinlock_t *lock)
 507 {
 508     return 1;
 509 }
 510 #endif
 511
 512 extern spinlock_t tb_lock;
 513
 514 extern int tb_invalidated_flag;
 515
 516 #if !defined(CONFIG_USER_ONLY)
 517
 518 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 519               void *retaddr);
 520
 521 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 522 #define MEMSUFFIX _code
 523 #define env cpu_single_env
 524
 525 #define DATA_SIZE 1
 526 #include "softmmu_header.h"
 527
 528 #define DATA_SIZE 2
 529 #include "softmmu_header.h"
 530
 531 #define DATA_SIZE 4
 532 #include "softmmu_header.h"
 533
 534 #define DATA_SIZE 8
 535 #include "softmmu_header.h"
 536
 537 #undef ACCESS_TYPE
 538 #undef MEMSUFFIX
 539 #undef env
 540
 541 #endif
 542
 543 #if defined(CONFIG_USER_ONLY)
 544 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 545 {
 546     return addr;
 547 }
 548 #else
 549 /* NOTE: this function can trigger an exception */
 550 /* NOTE2: the returned address is not exactly the physical address: it
 551    is the offset relative to phys_ram_base */
 552 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 553 {
 554     int mmu_idx, index, pd;
 555
 556     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 557     mmu_idx = cpu_mmu_index(env);
 558     if (__builtin_expect(env->tlb_table[mmu_idx][index].addr_code !=
 559                          (addr & TARGET_PAGE_MASK), 0)) {
 560         ldub_code(addr);
 561     }
 562     pd = env->tlb_table[mmu_idx][index].addr_code & ~TARGET_PAGE_MASK;
 563     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 564 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 565         do_unassigned_access(addr, 0, 1, 0);
 566 #else
 567         cpu_abort(env, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 568 #endif
 569     }
 570     return addr + env->tlb_table[mmu_idx][index].addend - (unsigned long)phys_ram_base;
 571 }
 572 #endif
 573
 574 #ifdef USE_KQEMU
 575 #define KQEMU_MODIFY_PAGE_MASK (0xff & ~(VGA_DIRTY_FLAG | CODE_DIRTY_FLAG))
 576
 577 int kqemu_init(CPUState *env);
 578 int kqemu_cpu_exec(CPUState *env);
 579 void kqemu_flush_page(CPUState *env, target_ulong addr);
 580 void kqemu_flush(CPUState *env, int global);
 581 void kqemu_set_notdirty(CPUState *env, ram_addr_t ram_addr);
 582 void kqemu_modify_page(CPUState *env, ram_addr_t ram_addr);
 583 void kqemu_cpu_interrupt(CPUState *env);
 584 void kqemu_record_dump(void);
 585
 586 static inline int kqemu_is_ok(CPUState *env)
 587 {
 588     return(env->kqemu_enabled &&
 589            (env->cr[0] & CR0_PE_MASK) &&
 590            !(env->hflags & HF_INHIBIT_IRQ_MASK) &&
 591            (env->eflags & IF_MASK) &&
 592            !(env->eflags & VM_MASK) &&
 593            (env->kqemu_enabled == 2 ||
 594             ((env->hflags & HF_CPL_MASK) == 3 &&
 595              (env->eflags & IOPL_MASK) != IOPL_MASK)));
 596 }
 597
 598 #endif