exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  */
  20
  21 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  22 #define DEBUG_DISAS
  23
  24 #ifndef glue
  25 #define xglue(x, y) x ## y
  26 #define glue(x, y) xglue(x, y)
  27 #define stringify(s)    tostring(s)
  28 #define tostring(s)     #s
  29 #endif
  30
  31 #if GCC_MAJOR < 3
  32 #define __builtin_expect(x, n) (x)
  33 #endif
  34
  35 #ifdef __i386__
  36 #define REGPARM(n) __attribute((regparm(n)))
  37 #else
  38 #define REGPARM(n)
  39 #endif
  40
  41 /* is_jmp field values */
  42 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  43 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  44 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  45 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  46
  47 struct TranslationBlock;
  48
  49 /* XXX: make safe guess about sizes */
  50 #define MAX_OP_PER_INSTR 32
  51 #define OPC_BUF_SIZE 512
  52 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  53
  54 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * 3)
  55
  56 extern uint16_t gen_opc_buf[OPC_BUF_SIZE];
  57 extern uint32_t gen_opparam_buf[OPPARAM_BUF_SIZE];
  58 extern uint32_t gen_opc_pc[OPC_BUF_SIZE];
  59 extern uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
  60 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  61
  62 typedef void (GenOpFunc)(void);
  63 typedef void (GenOpFunc1)(long);
  64 typedef void (GenOpFunc2)(long, long);
  65 typedef void (GenOpFunc3)(long, long, long);
  66
  67 #if defined(TARGET_I386)
  68
  69 void optimize_flags_init(void);
  70
  71 #endif
  72
  73 extern FILE *logfile;
  74 extern int loglevel;
  75
  76 int gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  77 int gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  78 void dump_ops(const uint16_t *opc_buf, const uint32_t *opparam_buf);
  79 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  80                  int max_code_size, int *gen_code_size_ptr);
  81 int cpu_restore_state(struct TranslationBlock *tb,
  82                       CPUState *env, unsigned long searched_pc);
  83 void cpu_exec_init(void);
  84 int page_unprotect(unsigned long address);
  85 void tb_invalidate_page_range(target_ulong start, target_ulong end);
  86 void tlb_flush_page(CPUState *env, uint32_t addr);
  87 void tlb_flush_page_write(CPUState *env, uint32_t addr);
  88 void tlb_flush(CPUState *env, int flush_global);
  89 int tlb_set_page(CPUState *env, uint32_t vaddr, uint32_t paddr, int prot,
  90                  int is_user, int is_softmmu);
  91
  92 #define CODE_GEN_MAX_SIZE        65536
  93 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
  94
  95 #define CODE_GEN_HASH_BITS     15
  96 #define CODE_GEN_HASH_SIZE     (1 << CODE_GEN_HASH_BITS)
  97
  98 #define CODE_GEN_PHYS_HASH_BITS     15
  99 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 100
 101 /* maximum total translate dcode allocated */
 102
 103 /* NOTE: the translated code area cannot be too big because on some
 104    archs the range of "fast" function calls is limited. Here is a
 105    summary of the ranges:
 106
 107    i386  : signed 32 bits
 108    arm   : signed 26 bits
 109    ppc   : signed 24 bits
 110    sparc : signed 32 bits
 111    alpha : signed 23 bits
 112 */
 113
 114 #if defined(__alpha__)
 115 #define CODE_GEN_BUFFER_SIZE     (2 * 1024 * 1024)
 116 #elif defined(__powerpc__)
 117 #define CODE_GEN_BUFFER_SIZE     (6 * 1024 * 1024)
 118 #else
 119 #define CODE_GEN_BUFFER_SIZE     (8 * 1024 * 1024)
 120 #endif
 121
 122 //#define CODE_GEN_BUFFER_SIZE     (128 * 1024)
 123
 124 /* estimated block size for TB allocation */
 125 /* XXX: use a per code average code fragment size and modulate it
 126    according to the host CPU */
 127 #if defined(CONFIG_SOFTMMU)
 128 #define CODE_GEN_AVG_BLOCK_SIZE 128
 129 #else
 130 #define CODE_GEN_AVG_BLOCK_SIZE 64
 131 #endif
 132
 133 #define CODE_GEN_MAX_BLOCKS    (CODE_GEN_BUFFER_SIZE / CODE_GEN_AVG_BLOCK_SIZE)
 134
 135 #if defined(__powerpc__)
 136 #define USE_DIRECT_JUMP
 137 #endif
 138 #if defined(__i386__)
 139 #define USE_DIRECT_JUMP
 140 #endif
 141
 142 typedef struct TranslationBlock {
 143     unsigned long pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 144     unsigned long cs_base; /* CS base for this block */
 145     unsigned int flags; /* flags defining in which context the code was generated */
 146     uint16_t size;      /* size of target code for this block (1 <=
 147                            size <= TARGET_PAGE_SIZE) */
 148     uint8_t *tc_ptr;    /* pointer to the translated code */
 149     struct TranslationBlock *hash_next; /* next matching tb for virtual address */
 150     /* next matching tb for physical address. */
 151     struct TranslationBlock *phys_hash_next;
 152     /* first and second physical page containing code. The lower bit
 153        of the pointer tells the index in page_next[] */
 154     struct TranslationBlock *page_next[2];
 155     target_ulong page_addr[2];
 156
 157     /* the following data are used to directly call another TB from
 158        the code of this one. */
 159     uint16_t tb_next_offset[2]; /* offset of original jump target */
 160 #ifdef USE_DIRECT_JUMP
 161     uint16_t tb_jmp_offset[4]; /* offset of jump instruction */
 162 #else
 163     uint32_t tb_next[2]; /* address of jump generated code */
 164 #endif
 165     /* list of TBs jumping to this one. This is a circular list using
 166        the two least significant bits of the pointers to tell what is
 167        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 168        jmp_first */
 169     struct TranslationBlock *jmp_next[2];
 170     struct TranslationBlock *jmp_first;
 171 } TranslationBlock;
 172
 173 static inline unsigned int tb_hash_func(unsigned long pc)
 174 {
 175     return pc & (CODE_GEN_HASH_SIZE - 1);
 176 }
 177
 178 static inline unsigned int tb_phys_hash_func(unsigned long pc)
 179 {
 180     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 181 }
 182
 183 TranslationBlock *tb_alloc(unsigned long pc);
 184 void tb_flush(CPUState *env);
 185 void tb_link(TranslationBlock *tb);
 186 void tb_link_phys(TranslationBlock *tb,
 187                   target_ulong phys_pc, target_ulong phys_page2);
 188
 189 extern TranslationBlock *tb_hash[CODE_GEN_HASH_SIZE];
 190 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 191
 192 extern uint8_t code_gen_buffer[CODE_GEN_BUFFER_SIZE];
 193 extern uint8_t *code_gen_ptr;
 194
 195 /* find a translation block in the translation cache. If not found,
 196    return NULL and the pointer to the last element of the list in pptb */
 197 static inline TranslationBlock *tb_find(TranslationBlock ***pptb,
 198                                         unsigned long pc,
 199                                         unsigned long cs_base,
 200                                         unsigned int flags)
 201 {
 202     TranslationBlock **ptb, *tb;
 203     unsigned int h;
 204
 205     h = tb_hash_func(pc);
 206     ptb = &tb_hash[h];
 207     for(;;) {
 208         tb = *ptb;
 209         if (!tb)
 210             break;
 211         if (tb->pc == pc && tb->cs_base == cs_base && tb->flags == flags)
 212             return tb;
 213         ptb = &tb->hash_next;
 214     }
 215     *pptb = ptb;
 216     return NULL;
 217 }
 218
 219
 220 #if defined(USE_DIRECT_JUMP)
 221
 222 #if defined(__powerpc__)
 223 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 224 {
 225     uint32_t val, *ptr;
 226
 227     /* patch the branch destination */
 228     ptr = (uint32_t *)jmp_addr;
 229     val = *ptr;
 230     val = (val & ~0x03fffffc) | ((addr - jmp_addr) & 0x03fffffc);
 231     *ptr = val;
 232     /* flush icache */
 233     asm volatile ("dcbst 0,%0" : : "r"(ptr) : "memory");
 234     asm volatile ("sync" : : : "memory");
 235     asm volatile ("icbi 0,%0" : : "r"(ptr) : "memory");
 236     asm volatile ("sync" : : : "memory");
 237     asm volatile ("isync" : : : "memory");
 238 }
 239 #elif defined(__i386__)
 240 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 241 {
 242     /* patch the branch destination */
 243     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 244     /* no need to flush icache explicitely */
 245 }
 246 #endif
 247
 248 static inline void tb_set_jmp_target(TranslationBlock *tb,
 249                                      int n, unsigned long addr)
 250 {
 251     unsigned long offset;
 252
 253     offset = tb->tb_jmp_offset[n];
 254     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 255     offset = tb->tb_jmp_offset[n + 2];
 256     if (offset != 0xffff)
 257         tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 258 }
 259
 260 #else
 261
 262 /* set the jump target */
 263 static inline void tb_set_jmp_target(TranslationBlock *tb,
 264                                      int n, unsigned long addr)
 265 {
 266     tb->tb_next[n] = addr;
 267 }
 268
 269 #endif
 270
 271 static inline void tb_add_jump(TranslationBlock *tb, int n,
 272                                TranslationBlock *tb_next)
 273 {
 274     /* NOTE: this test is only needed for thread safety */
 275     if (!tb->jmp_next[n]) {
 276         /* patch the native jump address */
 277         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 278
 279         /* add in TB jmp circular list */
 280         tb->jmp_next[n] = tb_next->jmp_first;
 281         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 282     }
 283 }
 284
 285 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 286
 287 #ifndef offsetof
 288 #define offsetof(type, field) ((size_t) &((type *)0)->field)
 289 #endif
 290
 291 #if defined(__powerpc__)
 292
 293 /* we patch the jump instruction directly */
 294 #define JUMP_TB(opname, tbparam, n, eip)\
 295 do {\
 296     asm volatile (".section \".data\"\n"\
 297                   "__op_label" #n "." stringify(opname) ":\n"\
 298                   ".long 1f\n"\
 299                   ".previous\n"\
 300                   "b __op_jmp" #n "\n"\
 301                   "1:\n");\
 302     T0 = (long)(tbparam) + (n);\
 303     EIP = eip;\
 304     EXIT_TB();\
 305 } while (0)
 306
 307 #define JUMP_TB2(opname, tbparam, n)\
 308 do {\
 309     asm volatile ("b __op_jmp" #n "\n");\
 310 } while (0)
 311
 312 #elif defined(__i386__) && defined(USE_DIRECT_JUMP)
 313
 314 /* we patch the jump instruction directly */
 315 #define JUMP_TB(opname, tbparam, n, eip)\
 316 do {\
 317     asm volatile (".section \".data\"\n"\
 318                   "__op_label" #n "." stringify(opname) ":\n"\
 319                   ".long 1f\n"\
 320                   ".previous\n"\
 321                   "jmp __op_jmp" #n "\n"\
 322                   "1:\n");\
 323     T0 = (long)(tbparam) + (n);\
 324     EIP = eip;\
 325     EXIT_TB();\
 326 } while (0)
 327
 328 #define JUMP_TB2(opname, tbparam, n)\
 329 do {\
 330     asm volatile ("jmp __op_jmp" #n "\n");\
 331 } while (0)
 332
 333 #else
 334
 335 /* jump to next block operations (more portable code, does not need
 336    cache flushing, but slower because of indirect jump) */
 337 #define JUMP_TB(opname, tbparam, n, eip)\
 338 do {\
 339     static void __attribute__((unused)) *__op_label ## n = &&label ## n;\
 340     static void __attribute__((unused)) *dummy ## n = &&dummy_label ## n;\
 341     goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n]);\
 342 label ## n:\
 343     T0 = (long)(tbparam) + (n);\
 344     EIP = eip;\
 345 dummy_label ## n:\
 346     EXIT_TB();\
 347 } while (0)
 348
 349 /* second jump to same destination 'n' */
 350 #define JUMP_TB2(opname, tbparam, n)\
 351 do {\
 352     goto *(void *)(((TranslationBlock *)tbparam)->tb_next[n - 2]);\
 353 } while (0)
 354
 355 #endif
 356
 357 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 358 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 359
 360 #ifdef __powerpc__
 361 static inline int testandset (int *p)
 362 {
 363     int ret;
 364     __asm__ __volatile__ (
 365                           "0:    lwarx %0,0,%1 ;"
 366                           "      xor. %0,%3,%0;"
 367                           "      bne 1f;"
 368                           "      stwcx. %2,0,%1;"
 369                           "      bne- 0b;"
 370                           "1:    "
 371                           : "=&r" (ret)
 372                           : "r" (p), "r" (1), "r" (0)
 373                           : "cr0", "memory");
 374     return ret;
 375 }
 376 #endif
 377
 378 #ifdef __i386__
 379 static inline int testandset (int *p)
 380 {
 381     char ret;
 382     long int readval;
 383
 384     __asm__ __volatile__ ("lock; cmpxchgl %3, %1; sete %0"
 385                           : "=q" (ret), "=m" (*p), "=a" (readval)
 386                           : "r" (1), "m" (*p), "a" (0)
 387                           : "memory");
 388     return ret;
 389 }
 390 #endif
 391
 392 #ifdef __s390__
 393 static inline int testandset (int *p)
 394 {
 395     int ret;
 396
 397     __asm__ __volatile__ ("0: cs    %0,%1,0(%2)\n"
 398                           "   jl    0b"
 399                           : "=&d" (ret)
 400                           : "r" (1), "a" (p), "0" (*p)
 401                           : "cc", "memory" );
 402     return ret;
 403 }
 404 #endif
 405
 406 #ifdef __alpha__
 407 static inline int testandset (int *p)
 408 {
 409     int ret;
 410     unsigned long one;
 411
 412     __asm__ __volatile__ ("0:   mov 1,%2\n"
 413                           "     ldl_l %0,%1\n"
 414                           "     stl_c %2,%1\n"
 415                           "     beq %2,1f\n"
 416                           ".subsection 2\n"
 417                           "1:   br 0b\n"
 418                           ".previous"
 419                           : "=r" (ret), "=m" (*p), "=r" (one)
 420                           : "m" (*p));
 421     return ret;
 422 }
 423 #endif
 424
 425 #ifdef __sparc__
 426 static inline int testandset (int *p)
 427 {
 428         int ret;
 429
 430         __asm__ __volatile__("ldstub    [%1], %0"
 431                              : "=r" (ret)
 432                              : "r" (p)
 433                              : "memory");
 434
 435         return (ret ? 1 : 0);
 436 }
 437 #endif
 438
 439 #ifdef __arm__
 440 static inline int testandset (int *spinlock)
 441 {
 442     register unsigned int ret;
 443     __asm__ __volatile__("swp %0, %1, [%2]"
 444                          : "=r"(ret)
 445                          : "0"(1), "r"(spinlock));
 446
 447     return ret;
 448 }
 449 #endif
 450
 451 #ifdef __mc68000
 452 static inline int testandset (int *p)
 453 {
 454     char ret;
 455     __asm__ __volatile__("tas %1; sne %0"
 456                          : "=r" (ret)
 457                          : "m" (p)
 458                          : "cc","memory");
 459     return ret == 0;
 460 }
 461 #endif
 462
 463 typedef int spinlock_t;
 464
 465 #define SPIN_LOCK_UNLOCKED 0
 466
 467 #if defined(CONFIG_USER_ONLY)
 468 static inline void spin_lock(spinlock_t *lock)
 469 {
 470     while (testandset(lock));
 471 }
 472
 473 static inline void spin_unlock(spinlock_t *lock)
 474 {
 475     *lock = 0;
 476 }
 477
 478 static inline int spin_trylock(spinlock_t *lock)
 479 {
 480     return !testandset(lock);
 481 }
 482 #else
 483 static inline void spin_lock(spinlock_t *lock)
 484 {
 485 }
 486
 487 static inline void spin_unlock(spinlock_t *lock)
 488 {
 489 }
 490
 491 static inline int spin_trylock(spinlock_t *lock)
 492 {
 493     return 1;
 494 }
 495 #endif
 496
 497 extern spinlock_t tb_lock;
 498
 499 extern int tb_invalidated_flag;
 500
 501 #if (defined(TARGET_I386) || defined(TARGET_PPC)) && \
 502     !defined(CONFIG_USER_ONLY)
 503
 504 void tlb_fill(unsigned long addr, int is_write, int is_user,
 505               void *retaddr);
 506
 507 #define ACCESS_TYPE 3
 508 #define MEMSUFFIX _code
 509 #define env cpu_single_env
 510
 511 #define DATA_SIZE 1
 512 #include "softmmu_header.h"
 513
 514 #define DATA_SIZE 2
 515 #include "softmmu_header.h"
 516
 517 #define DATA_SIZE 4
 518 #include "softmmu_header.h"
 519
 520 #undef ACCESS_TYPE
 521 #undef MEMSUFFIX
 522 #undef env
 523
 524 #endif
 525
 526 #if defined(CONFIG_USER_ONLY)
 527 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 528 {
 529     return addr;
 530 }
 531 #else
 532 /* NOTE: this function can trigger an exception */
 533 /* NOTE2: the returned address is not exactly the physical address: it
 534    is the offset relative to phys_ram_base */
 535 /* XXX: i386 target specific */
 536 static inline target_ulong get_phys_addr_code(CPUState *env, target_ulong addr)
 537 {
 538     int is_user, index;
 539
 540     index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 541 #if defined(TARGET_I386)
 542     is_user = ((env->hflags & HF_CPL_MASK) == 3);
 543 #elif defined (TARGET_PPC)
 544     is_user = msr_pr;
 545 #else
 546 #error "Unimplemented !"
 547 #endif
 548     if (__builtin_expect(env->tlb_read[is_user][index].address !=
 549                          (addr & TARGET_PAGE_MASK), 0)) {
 550         ldub_code((void *)addr);
 551     }
 552     return addr + env->tlb_read[is_user][index].addend - (unsigned long)phys_ram_base;
 553 }
 554 #endif
 555